2 * drivers/mb862xx/mb862xxfb.c
4 * Fujitsu Carmine/Coral-P(A)/Lime framebuffer driver
6 * (C) 2008 Anatolij Gustschin <agust@denx.de>
7 * DENX Software Engineering
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
18 #include <linux/delay.h>
19 #include <linux/init.h>
20 #include <linux/interrupt.h>
21 #include <linux/pci.h>
22 #if defined(CONFIG_OF)
23 #include <linux/of_platform.h>
25 #include "mb862xxfb.h"
26 #include "mb862xx_reg.h"
28 #define NR_PALETTE 256
29 #define MB862XX_MEM_SIZE 0x1000000
30 #define CORALP_MEM_SIZE 0x4000000
31 #define CARMINE_MEM_SIZE 0x8000000
32 #define DRV_NAME "mb862xxfb"
34 #if defined(CONFIG_LWMON5)
35 static struct mb862xx_gc_mode lwmon5_gc_mode = {
36 /* Mode for Sharp LQ104V1DG61 TFT LCD Panel */
37 { "640x480", 60, 640, 480, 40000, 48, 16, 32, 11, 96, 2, 0, 0, 0 },
38 /* 16 bits/pixel, 32MB, 100MHz, SDRAM memory mode value */
39 16, 0x2000000, GC_CCF_COT_100, 0x414fb7f2
43 #if defined(CONFIG_SOCRATES)
44 static struct mb862xx_gc_mode socrates_gc_mode = {
45 /* Mode for Prime View PM070WL4 TFT LCD Panel */
46 { "800x480", 45, 800, 480, 40000, 86, 42, 33, 10, 128, 2, 0, 0, 0 },
47 /* 16 bits/pixel, 16MB, 133MHz, SDRAM memory mode value */
48 16, 0x1000000, GC_CCF_COT_133, 0x4157ba63
53 static inline int h_total(struct fb_var_screeninfo *var)
55 return var->xres + var->left_margin +
56 var->right_margin + var->hsync_len;
59 static inline int v_total(struct fb_var_screeninfo *var)
61 return var->yres + var->upper_margin +
62 var->lower_margin + var->vsync_len;
65 static inline int hsp(struct fb_var_screeninfo *var)
67 return var->xres + var->right_margin - 1;
70 static inline int vsp(struct fb_var_screeninfo *var)
72 return var->yres + var->lower_margin - 1;
75 static inline int d_pitch(struct fb_var_screeninfo *var)
77 return var->xres * var->bits_per_pixel / 8;
80 static inline unsigned int chan_to_field(unsigned int chan,
81 struct fb_bitfield *bf)
84 chan >>= 16 - bf->length;
85 return chan << bf->offset;
88 static int mb862xxfb_setcolreg(unsigned regno,
89 unsigned red, unsigned green, unsigned blue,
90 unsigned transp, struct fb_info *info)
92 struct mb862xxfb_par *par = info->par;
95 switch (info->fix.visual) {
96 case FB_VISUAL_TRUECOLOR:
98 val = chan_to_field(red, &info->var.red);
99 val |= chan_to_field(green, &info->var.green);
100 val |= chan_to_field(blue, &info->var.blue);
101 par->pseudo_palette[regno] = val;
104 case FB_VISUAL_PSEUDOCOLOR:
106 val = (red >> 8) << 16;
107 val |= (green >> 8) << 8;
109 outreg(disp, GC_L0PAL0 + (regno * 4), val);
113 return 1; /* unsupported type */
118 static int mb862xxfb_check_var(struct fb_var_screeninfo *var,
124 dev_dbg(fbi->dev, "%s\n", __func__);
126 /* check if these values fit into the registers */
127 if (var->hsync_len > 255 || var->vsync_len > 255)
130 if ((var->xres + var->right_margin) >= 4096)
133 if ((var->yres + var->lower_margin) > 4096)
136 if (h_total(var) > 4096 || v_total(var) > 4096)
139 if (var->xres_virtual > 4096 || var->yres_virtual > 4096)
142 if (var->bits_per_pixel <= 8)
143 var->bits_per_pixel = 8;
144 else if (var->bits_per_pixel <= 16)
145 var->bits_per_pixel = 16;
146 else if (var->bits_per_pixel <= 32)
147 var->bits_per_pixel = 32;
150 * can cope with 8,16 or 24/32bpp if resulting
151 * pitch is divisible by 64 without remainder
153 if (d_pitch(&fbi->var) % GC_L0M_L0W_UNIT) {
156 var->bits_per_pixel = 0;
158 var->bits_per_pixel += 8;
159 r = d_pitch(&fbi->var) % GC_L0M_L0W_UNIT;
160 } while (r && var->bits_per_pixel <= 32);
162 if (d_pitch(&fbi->var) % GC_L0M_L0W_UNIT)
166 /* line length is going to be 128 bit aligned */
167 tmp = (var->xres * var->bits_per_pixel) / 8;
171 /* set r/g/b positions and validate bpp */
172 switch (var->bits_per_pixel) {
174 var->red.length = var->bits_per_pixel;
175 var->green.length = var->bits_per_pixel;
176 var->blue.length = var->bits_per_pixel;
178 var->green.offset = 0;
179 var->blue.offset = 0;
180 var->transp.length = 0;
184 var->green.length = 5;
185 var->blue.length = 5;
186 var->red.offset = 10;
187 var->green.offset = 5;
188 var->blue.offset = 0;
189 var->transp.length = 0;
193 var->transp.length = 8;
195 var->green.length = 8;
196 var->blue.length = 8;
197 var->transp.offset = 24;
198 var->red.offset = 16;
199 var->green.offset = 8;
200 var->blue.offset = 0;
209 * set display parameters
211 static int mb862xxfb_set_par(struct fb_info *fbi)
213 struct mb862xxfb_par *par = fbi->par;
214 unsigned long reg, sc;
216 dev_dbg(par->dev, "%s\n", __func__);
217 if (par->type == BT_CORALP)
218 mb862xxfb_init_accel(fbi, fbi->var.xres);
224 reg = inreg(disp, GC_DCM1);
225 reg &= ~GC_DCM01_DEN;
226 outreg(disp, GC_DCM1, reg);
228 /* set display reference clock div. */
229 sc = par->refclk / (1000000 / fbi->var.pixclock) - 1;
230 reg = inreg(disp, GC_DCM1);
231 reg &= ~(GC_DCM01_CKS | GC_DCM01_RESV | GC_DCM01_SC);
233 outreg(disp, GC_DCM1, reg);
234 dev_dbg(par->dev, "SC 0x%lx\n", sc);
236 /* disp dimension, format */
237 reg = pack(d_pitch(&fbi->var) / GC_L0M_L0W_UNIT,
238 (fbi->var.yres - 1));
239 if (fbi->var.bits_per_pixel == 16)
240 reg |= GC_L0M_L0C_16;
241 outreg(disp, GC_L0M, reg);
243 if (fbi->var.bits_per_pixel == 32) {
244 reg = inreg(disp, GC_L0EM);
245 outreg(disp, GC_L0EM, reg | GC_L0EM_L0EC_24);
247 outreg(disp, GC_WY_WX, 0);
248 reg = pack(fbi->var.yres - 1, fbi->var.xres);
249 outreg(disp, GC_WH_WW, reg);
250 outreg(disp, GC_L0OA0, 0);
251 outreg(disp, GC_L0DA0, 0);
252 outreg(disp, GC_L0DY_L0DX, 0);
253 outreg(disp, GC_L0WY_L0WX, 0);
254 outreg(disp, GC_L0WH_L0WW, reg);
256 /* both HW-cursors off */
257 reg = inreg(disp, GC_CPM_CUTC);
258 reg &= ~(GC_CPM_CEN0 | GC_CPM_CEN1);
259 outreg(disp, GC_CPM_CUTC, reg);
262 reg = pack(fbi->var.xres - 1, fbi->var.xres - 1);
263 outreg(disp, GC_HDB_HDP, reg);
264 reg = pack((fbi->var.yres - 1), vsp(&fbi->var));
265 outreg(disp, GC_VDP_VSP, reg);
266 reg = ((fbi->var.vsync_len - 1) << 24) |
267 pack((fbi->var.hsync_len - 1), hsp(&fbi->var));
268 outreg(disp, GC_VSW_HSW_HSP, reg);
269 outreg(disp, GC_HTP, pack(h_total(&fbi->var) - 1, 0));
270 outreg(disp, GC_VTR, pack(v_total(&fbi->var) - 1, 0));
273 reg = inreg(disp, GC_DCM1);
274 reg |= GC_DCM01_DEN | GC_DCM01_L0E;
275 reg &= ~GC_DCM01_ESY;
276 outreg(disp, GC_DCM1, reg);
280 static int mb862xxfb_pan(struct fb_var_screeninfo *var,
281 struct fb_info *info)
283 struct mb862xxfb_par *par = info->par;
286 reg = pack(var->yoffset, var->xoffset);
287 outreg(disp, GC_L0WY_L0WX, reg);
289 reg = pack(var->yres_virtual, var->xres_virtual);
290 outreg(disp, GC_L0WH_L0WW, reg);
294 static int mb862xxfb_blank(int mode, struct fb_info *fbi)
296 struct mb862xxfb_par *par = fbi->par;
299 dev_dbg(fbi->dev, "blank mode=%d\n", mode);
302 case FB_BLANK_POWERDOWN:
303 reg = inreg(disp, GC_DCM1);
304 reg &= ~GC_DCM01_DEN;
305 outreg(disp, GC_DCM1, reg);
307 case FB_BLANK_UNBLANK:
308 reg = inreg(disp, GC_DCM1);
310 outreg(disp, GC_DCM1, reg);
312 case FB_BLANK_NORMAL:
313 case FB_BLANK_VSYNC_SUSPEND:
314 case FB_BLANK_HSYNC_SUSPEND:
321 /* framebuffer ops */
322 static struct fb_ops mb862xxfb_ops = {
323 .owner = THIS_MODULE,
324 .fb_check_var = mb862xxfb_check_var,
325 .fb_set_par = mb862xxfb_set_par,
326 .fb_setcolreg = mb862xxfb_setcolreg,
327 .fb_blank = mb862xxfb_blank,
328 .fb_pan_display = mb862xxfb_pan,
329 .fb_fillrect = cfb_fillrect,
330 .fb_copyarea = cfb_copyarea,
331 .fb_imageblit = cfb_imageblit,
334 /* initialize fb_info data */
335 static int mb862xxfb_init_fbinfo(struct fb_info *fbi)
337 struct mb862xxfb_par *par = fbi->par;
338 struct mb862xx_gc_mode *mode = par->gc_mode;
341 fbi->fbops = &mb862xxfb_ops;
342 fbi->pseudo_palette = par->pseudo_palette;
343 fbi->screen_base = par->fb_base;
344 fbi->screen_size = par->mapped_vram;
346 strcpy(fbi->fix.id, DRV_NAME);
347 fbi->fix.smem_start = (unsigned long)par->fb_base_phys;
348 fbi->fix.smem_len = par->mapped_vram;
349 fbi->fix.mmio_start = (unsigned long)par->mmio_base_phys;
350 fbi->fix.mmio_len = par->mmio_len;
351 fbi->fix.accel = FB_ACCEL_NONE;
352 fbi->fix.type = FB_TYPE_PACKED_PIXELS;
353 fbi->fix.type_aux = 0;
354 fbi->fix.xpanstep = 1;
355 fbi->fix.ypanstep = 1;
356 fbi->fix.ywrapstep = 0;
358 reg = inreg(disp, GC_DCM1);
359 if (reg & GC_DCM01_DEN && reg & GC_DCM01_L0E) {
360 /* get the disp mode from active display cfg */
361 unsigned long sc = ((reg & GC_DCM01_SC) >> 8) + 1;
362 unsigned long hsp, vsp, ht, vt;
364 dev_dbg(par->dev, "using bootloader's disp. mode\n");
365 fbi->var.pixclock = (sc * 1000000) / par->refclk;
366 fbi->var.xres = (inreg(disp, GC_HDB_HDP) & 0x0fff) + 1;
367 reg = inreg(disp, GC_VDP_VSP);
368 fbi->var.yres = ((reg >> 16) & 0x0fff) + 1;
369 vsp = (reg & 0x0fff) + 1;
370 fbi->var.xres_virtual = fbi->var.xres;
371 fbi->var.yres_virtual = fbi->var.yres;
372 reg = inreg(disp, GC_L0EM);
373 if (reg & GC_L0EM_L0EC_24) {
374 fbi->var.bits_per_pixel = 32;
376 reg = inreg(disp, GC_L0M);
377 if (reg & GC_L0M_L0C_16)
378 fbi->var.bits_per_pixel = 16;
380 fbi->var.bits_per_pixel = 8;
382 reg = inreg(disp, GC_VSW_HSW_HSP);
383 fbi->var.hsync_len = ((reg & 0xff0000) >> 16) + 1;
384 fbi->var.vsync_len = ((reg & 0x3f000000) >> 24) + 1;
385 hsp = (reg & 0xffff) + 1;
386 ht = ((inreg(disp, GC_HTP) & 0xfff0000) >> 16) + 1;
387 fbi->var.right_margin = hsp - fbi->var.xres;
388 fbi->var.left_margin = ht - hsp - fbi->var.hsync_len;
389 vt = ((inreg(disp, GC_VTR) & 0xfff0000) >> 16) + 1;
390 fbi->var.lower_margin = vsp - fbi->var.yres;
391 fbi->var.upper_margin = vt - vsp - fbi->var.vsync_len;
393 dev_dbg(par->dev, "using supplied mode\n");
394 fb_videomode_to_var(&fbi->var, (struct fb_videomode *)mode);
395 fbi->var.bits_per_pixel = mode->def_bpp ? mode->def_bpp : 8;
399 ret = fb_find_mode(&fbi->var, fbi, "640x480-16@60",
401 if (ret == 0 || ret == 4) {
403 "failed to get initial mode\n");
408 fbi->var.xoffset = 0;
409 fbi->var.yoffset = 0;
410 fbi->var.grayscale = 0;
412 fbi->var.height = -1;
414 fbi->var.accel_flags = 0;
415 fbi->var.vmode = FB_VMODE_NONINTERLACED;
416 fbi->var.activate = FB_ACTIVATE_NOW;
417 fbi->flags = FBINFO_DEFAULT |
419 FBINFO_FOREIGN_ENDIAN |
421 FBINFO_HWACCEL_XPAN |
424 /* check and possibly fix bpp */
425 if ((fbi->fbops->fb_check_var)(&fbi->var, fbi))
426 dev_err(par->dev, "check_var() failed on initial setup?\n");
428 fbi->fix.visual = fbi->var.bits_per_pixel == 8 ?
429 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
430 fbi->fix.line_length = (fbi->var.xres_virtual *
431 fbi->var.bits_per_pixel) / 8;
436 * show some display controller and cursor registers
438 static ssize_t mb862xxfb_show_dispregs(struct device *dev,
439 struct device_attribute *attr, char *buf)
441 struct fb_info *fbi = dev_get_drvdata(dev);
442 struct mb862xxfb_par *par = fbi->par;
446 for (reg = GC_DCM0; reg <= GC_L0DY_L0DX; reg += 4)
447 ptr += sprintf(ptr, "%08x = %08x\n",
448 reg, inreg(disp, reg));
450 for (reg = GC_CPM_CUTC; reg <= GC_CUY1_CUX1; reg += 4)
451 ptr += sprintf(ptr, "%08x = %08x\n",
452 reg, inreg(disp, reg));
454 for (reg = GC_DCM1; reg <= GC_L0WH_L0WW; reg += 4)
455 ptr += sprintf(ptr, "%08x = %08x\n",
456 reg, inreg(disp, reg));
458 for (reg = 0x400; reg <= 0x410; reg += 4)
459 ptr += sprintf(ptr, "geo %08x = %08x\n",
460 reg, inreg(geo, reg));
462 for (reg = 0x400; reg <= 0x410; reg += 4)
463 ptr += sprintf(ptr, "draw %08x = %08x\n",
464 reg, inreg(draw, reg));
466 for (reg = 0x440; reg <= 0x450; reg += 4)
467 ptr += sprintf(ptr, "draw %08x = %08x\n",
468 reg, inreg(draw, reg));
473 static DEVICE_ATTR(dispregs, 0444, mb862xxfb_show_dispregs, NULL);
475 irqreturn_t mb862xx_intr(int irq, void *dev_id)
477 struct mb862xxfb_par *par = (struct mb862xxfb_par *) dev_id;
478 unsigned long reg_ist, mask;
483 if (par->type == BT_CARMINE) {
484 /* Get Interrupt Status */
485 reg_ist = inreg(ctrl, GC_CTRL_STATUS);
486 mask = inreg(ctrl, GC_CTRL_INT_MASK);
494 /* Clear interrupt status */
495 outreg(ctrl, 0x0, reg_ist);
498 reg_ist = inreg(host, GC_IST);
499 mask = inreg(host, GC_IMASK);
506 outreg(host, GC_IST, ~reg_ist);
511 #if defined(CONFIG_FB_MB862XX_LIME)
513 * GDC (Lime, Coral(B/Q), Mint, ...) on host bus
515 static int mb862xx_gdc_init(struct mb862xxfb_par *par)
517 unsigned long ccf, mmr;
518 unsigned long ver, rev;
523 #if defined(CONFIG_FB_PRE_INIT_FB)
526 par->host = par->mmio_base;
527 par->i2c = par->mmio_base + MB862XX_I2C_BASE;
528 par->disp = par->mmio_base + MB862XX_DISP_BASE;
529 par->cap = par->mmio_base + MB862XX_CAP_BASE;
530 par->draw = par->mmio_base + MB862XX_DRAW_BASE;
531 par->geo = par->mmio_base + MB862XX_GEO_BASE;
532 par->pio = par->mmio_base + MB862XX_PIO_BASE;
534 par->refclk = GC_DISP_REFCLK_400;
536 ver = inreg(host, GC_CID);
537 rev = inreg(pio, GC_REVISION);
538 if ((ver == 0x303) && (rev & 0xffffff00) == 0x20050100) {
539 dev_info(par->dev, "Fujitsu Lime v1.%d found\n",
542 ccf = par->gc_mode ? par->gc_mode->ccf : GC_CCF_COT_100;
543 mmr = par->gc_mode ? par->gc_mode->mmr : 0x414fb7f2;
545 dev_info(par->dev, "? GDC, CID/Rev.: 0x%lx/0x%lx \n", ver, rev);
549 if (!par->pre_init) {
550 outreg(host, GC_CCF, ccf);
552 outreg(host, GC_MMR, mmr);
556 /* interrupt status */
557 outreg(host, GC_IST, 0);
558 outreg(host, GC_IMASK, GC_INT_EN);
562 static int __devinit of_platform_mb862xx_probe(struct of_device *ofdev,
563 const struct of_device_id *id)
565 struct device_node *np = ofdev->node;
566 struct device *dev = &ofdev->dev;
567 struct mb862xxfb_par *par;
568 struct fb_info *info;
570 resource_size_t res_size;
571 unsigned long ret = -ENODEV;
573 if (of_address_to_resource(np, 0, &res)) {
574 dev_err(dev, "Invalid address\n");
578 info = framebuffer_alloc(sizeof(struct mb862xxfb_par), dev);
580 dev_err(dev, "cannot allocate framebuffer\n");
588 par->irq = irq_of_parse_and_map(np, 0);
589 if (par->irq == NO_IRQ) {
590 dev_err(dev, "failed to map irq\n");
595 res_size = 1 + res.end - res.start;
596 par->res = request_mem_region(res.start, res_size, DRV_NAME);
597 if (par->res == NULL) {
598 dev_err(dev, "Cannot claim framebuffer/mmio\n");
603 #if defined(CONFIG_LWMON5)
604 par->gc_mode = &lwmon5_gc_mode;
607 #if defined(CONFIG_SOCRATES)
608 par->gc_mode = &socrates_gc_mode;
611 par->fb_base_phys = res.start;
612 par->mmio_base_phys = res.start + MB862XX_MMIO_BASE;
613 par->mmio_len = MB862XX_MMIO_SIZE;
615 par->mapped_vram = par->gc_mode->max_vram;
617 par->mapped_vram = MB862XX_MEM_SIZE;
619 par->fb_base = ioremap(par->fb_base_phys, par->mapped_vram);
620 if (par->fb_base == NULL) {
621 dev_err(dev, "Cannot map framebuffer\n");
625 par->mmio_base = ioremap(par->mmio_base_phys, par->mmio_len);
626 if (par->mmio_base == NULL) {
627 dev_err(dev, "Cannot map registers\n");
631 dev_dbg(dev, "fb phys 0x%llx 0x%lx\n",
632 (u64)par->fb_base_phys, (ulong)par->mapped_vram);
633 dev_dbg(dev, "mmio phys 0x%llx 0x%lx, (irq = %d)\n",
634 (u64)par->mmio_base_phys, (ulong)par->mmio_len, par->irq);
636 if (mb862xx_gdc_init(par))
639 if (request_irq(par->irq, mb862xx_intr, IRQF_DISABLED,
640 DRV_NAME, (void *)par)) {
641 dev_err(dev, "Cannot request irq\n");
645 mb862xxfb_init_fbinfo(info);
647 if (fb_alloc_cmap(&info->cmap, NR_PALETTE, 0) < 0) {
648 dev_err(dev, "Could not allocate cmap for fb_info.\n");
652 if ((info->fbops->fb_set_par)(info))
653 dev_err(dev, "set_var() failed on initial setup?\n");
655 if (register_framebuffer(info)) {
656 dev_err(dev, "failed to register framebuffer\n");
660 dev_set_drvdata(dev, info);
662 if (device_create_file(dev, &dev_attr_dispregs))
663 dev_err(dev, "Can't create sysfs regdump file\n");
667 fb_dealloc_cmap(&info->cmap);
669 outreg(host, GC_IMASK, 0);
670 free_irq(par->irq, (void *)par);
672 iounmap(par->mmio_base);
674 iounmap(par->fb_base);
676 release_mem_region(res.start, res_size);
678 irq_dispose_mapping(par->irq);
680 dev_set_drvdata(dev, NULL);
681 framebuffer_release(info);
685 static int __devexit of_platform_mb862xx_remove(struct of_device *ofdev)
687 struct fb_info *fbi = dev_get_drvdata(&ofdev->dev);
688 struct mb862xxfb_par *par = fbi->par;
689 resource_size_t res_size = 1 + par->res->end - par->res->start;
692 dev_dbg(fbi->dev, "%s release\n", fbi->fix.id);
695 reg = inreg(disp, GC_DCM1);
696 reg &= ~(GC_DCM01_DEN | GC_DCM01_L0E);
697 outreg(disp, GC_DCM1, reg);
699 /* disable interrupts */
700 outreg(host, GC_IMASK, 0);
702 free_irq(par->irq, (void *)par);
703 irq_dispose_mapping(par->irq);
705 device_remove_file(&ofdev->dev, &dev_attr_dispregs);
707 unregister_framebuffer(fbi);
708 fb_dealloc_cmap(&fbi->cmap);
710 iounmap(par->mmio_base);
711 iounmap(par->fb_base);
713 dev_set_drvdata(&ofdev->dev, NULL);
714 release_mem_region(par->res->start, res_size);
715 framebuffer_release(fbi);
722 static struct of_device_id __devinitdata of_platform_mb862xx_tbl[] = {
723 { .compatible = "fujitsu,MB86276", },
724 { .compatible = "fujitsu,lime", },
725 { .compatible = "fujitsu,MB86277", },
726 { .compatible = "fujitsu,mint", },
727 { .compatible = "fujitsu,MB86293", },
728 { .compatible = "fujitsu,MB86294", },
729 { .compatible = "fujitsu,coral", },
733 static struct of_platform_driver of_platform_mb862xxfb_driver = {
734 .owner = THIS_MODULE,
736 .match_table = of_platform_mb862xx_tbl,
737 .probe = of_platform_mb862xx_probe,
738 .remove = __devexit_p(of_platform_mb862xx_remove),
742 #if defined(CONFIG_FB_MB862XX_PCI_GDC)
743 static int coralp_init(struct mb862xxfb_par *par)
747 par->host = par->mmio_base;
748 par->i2c = par->mmio_base + MB862XX_I2C_BASE;
749 par->disp = par->mmio_base + MB862XX_DISP_BASE;
750 par->cap = par->mmio_base + MB862XX_CAP_BASE;
751 par->draw = par->mmio_base + MB862XX_DRAW_BASE;
752 par->geo = par->mmio_base + MB862XX_GEO_BASE;
753 par->pio = par->mmio_base + MB862XX_PIO_BASE;
755 par->refclk = GC_DISP_REFCLK_400;
757 ver = inreg(host, GC_CID);
758 cn = (ver & GC_CID_CNAME_MSK) >> 8;
759 ver = ver & GC_CID_VERSION_MSK;
761 dev_info(par->dev, "Fujitsu Coral-%s GDC Rev.%d found\n",\
762 (ver == 6) ? "P" : (ver == 8) ? "PA" : "?",
763 par->pdev->revision);
764 outreg(host, GC_CCF, GC_CCF_CGE_166 | GC_CCF_COT_133);
766 outreg(host, GC_MMR, GC_MMR_CORALP_EVB_VAL);
768 /* Clear interrupt status */
769 outreg(host, GC_IST, 0);
776 static int init_dram_ctrl(struct mb862xxfb_par *par)
781 * Set io mode first! Spec. says IC may be destroyed
782 * if not set to SSTL2/LVCMOS before init.
784 outreg(dram_ctrl, GC_DCTL_IOCONT1_IOCONT0, GC_EVB_DCTL_IOCONT1_IOCONT0);
787 outreg(dram_ctrl, GC_DCTL_MODE_ADD, GC_EVB_DCTL_MODE_ADD);
788 outreg(dram_ctrl, GC_DCTL_SETTIME1_EMODE, GC_EVB_DCTL_SETTIME1_EMODE);
789 outreg(dram_ctrl, GC_DCTL_REFRESH_SETTIME2,
790 GC_EVB_DCTL_REFRESH_SETTIME2);
791 outreg(dram_ctrl, GC_DCTL_RSV2_RSV1, GC_EVB_DCTL_RSV2_RSV1);
792 outreg(dram_ctrl, GC_DCTL_DDRIF2_DDRIF1, GC_EVB_DCTL_DDRIF2_DDRIF1);
793 outreg(dram_ctrl, GC_DCTL_RSV0_STATES, GC_EVB_DCTL_RSV0_STATES);
795 /* DLL reset done? */
796 while ((inreg(dram_ctrl, GC_DCTL_RSV0_STATES) & GC_DCTL_STATES_MSK)) {
797 udelay(GC_DCTL_INIT_WAIT_INTERVAL);
798 if (i++ > GC_DCTL_INIT_WAIT_CNT) {
799 dev_err(par->dev, "VRAM init failed.\n");
803 outreg(dram_ctrl, GC_DCTL_MODE_ADD, GC_EVB_DCTL_MODE_ADD_AFT_RST);
804 outreg(dram_ctrl, GC_DCTL_RSV0_STATES, GC_EVB_DCTL_RSV0_STATES_AFT_RST);
808 static int carmine_init(struct mb862xxfb_par *par)
812 par->ctrl = par->mmio_base + MB86297_CTRL_BASE;
813 par->i2c = par->mmio_base + MB86297_I2C_BASE;
814 par->disp = par->mmio_base + MB86297_DISP0_BASE;
815 par->disp1 = par->mmio_base + MB86297_DISP1_BASE;
816 par->cap = par->mmio_base + MB86297_CAP0_BASE;
817 par->cap1 = par->mmio_base + MB86297_CAP1_BASE;
818 par->draw = par->mmio_base + MB86297_DRAW_BASE;
819 par->dram_ctrl = par->mmio_base + MB86297_DRAMCTRL_BASE;
820 par->wrback = par->mmio_base + MB86297_WRBACK_BASE;
822 par->refclk = GC_DISP_REFCLK_533;
825 reg = GC_CTRL_CLK_EN_DRAM | GC_CTRL_CLK_EN_2D3D | GC_CTRL_CLK_EN_DISP0;
826 outreg(ctrl, GC_CTRL_CLK_ENABLE, reg);
828 /* check for engine module revision */
829 if (inreg(draw, GC_2D3D_REV) == GC_RE_REVISION)
830 dev_info(par->dev, "Fujitsu Carmine GDC Rev.%d found\n",
831 par->pdev->revision);
835 reg &= ~GC_CTRL_CLK_EN_2D3D;
836 outreg(ctrl, GC_CTRL_CLK_ENABLE, reg);
839 if (init_dram_ctrl(par) < 0)
842 outreg(ctrl, GC_CTRL_INT_MASK, 0);
846 outreg(ctrl, GC_CTRL_CLK_ENABLE, 0);
850 static inline int mb862xx_pci_gdc_init(struct mb862xxfb_par *par)
854 return coralp_init(par);
856 return carmine_init(par);
862 #define CHIP_ID(id) \
863 { PCI_DEVICE(PCI_VENDOR_ID_FUJITSU_LIMITED, id) }
865 static struct pci_device_id mb862xx_pci_tbl[] __devinitdata = {
866 /* MB86295/MB86296 */
867 CHIP_ID(PCI_DEVICE_ID_FUJITSU_CORALP),
868 CHIP_ID(PCI_DEVICE_ID_FUJITSU_CORALPA),
870 CHIP_ID(PCI_DEVICE_ID_FUJITSU_CARMINE),
874 MODULE_DEVICE_TABLE(pci, mb862xx_pci_tbl);
876 static int __devinit mb862xx_pci_probe(struct pci_dev *pdev,
877 const struct pci_device_id *ent)
879 struct mb862xxfb_par *par;
880 struct fb_info *info;
881 struct device *dev = &pdev->dev;
884 ret = pci_enable_device(pdev);
886 dev_err(dev, "Cannot enable PCI device\n");
890 info = framebuffer_alloc(sizeof(struct mb862xxfb_par), dev);
892 dev_err(dev, "framebuffer alloc failed\n");
901 par->irq = pdev->irq;
903 ret = pci_request_regions(pdev, DRV_NAME);
905 dev_err(dev, "Cannot reserve region(s) for PCI device\n");
909 switch (pdev->device) {
910 case PCI_DEVICE_ID_FUJITSU_CORALP:
911 case PCI_DEVICE_ID_FUJITSU_CORALPA:
912 par->fb_base_phys = pci_resource_start(par->pdev, 0);
913 par->mapped_vram = CORALP_MEM_SIZE;
914 par->mmio_base_phys = par->fb_base_phys + MB862XX_MMIO_BASE;
915 par->mmio_len = MB862XX_MMIO_SIZE;
916 par->type = BT_CORALP;
918 case PCI_DEVICE_ID_FUJITSU_CARMINE:
919 par->fb_base_phys = pci_resource_start(par->pdev, 2);
920 par->mmio_base_phys = pci_resource_start(par->pdev, 3);
921 par->mmio_len = pci_resource_len(par->pdev, 3);
922 par->mapped_vram = CARMINE_MEM_SIZE;
923 par->type = BT_CARMINE;
926 /* should never occur */
930 par->fb_base = ioremap(par->fb_base_phys, par->mapped_vram);
931 if (par->fb_base == NULL) {
932 dev_err(dev, "Cannot map framebuffer\n");
936 par->mmio_base = ioremap(par->mmio_base_phys, par->mmio_len);
937 if (par->mmio_base == NULL) {
938 dev_err(dev, "Cannot map registers\n");
943 dev_dbg(dev, "fb phys 0x%llx 0x%lx\n",
944 (unsigned long long)par->fb_base_phys, (ulong)par->mapped_vram);
945 dev_dbg(dev, "mmio phys 0x%llx 0x%lx\n",
946 (unsigned long long)par->mmio_base_phys, (ulong)par->mmio_len);
948 if (mb862xx_pci_gdc_init(par))
951 if (request_irq(par->irq, mb862xx_intr, IRQF_DISABLED | IRQF_SHARED,
952 DRV_NAME, (void *)par)) {
953 dev_err(dev, "Cannot request irq\n");
957 mb862xxfb_init_fbinfo(info);
959 if (fb_alloc_cmap(&info->cmap, NR_PALETTE, 0) < 0) {
960 dev_err(dev, "Could not allocate cmap for fb_info.\n");
965 if ((info->fbops->fb_set_par)(info))
966 dev_err(dev, "set_var() failed on initial setup?\n");
968 ret = register_framebuffer(info);
970 dev_err(dev, "failed to register framebuffer\n");
974 pci_set_drvdata(pdev, info);
976 if (device_create_file(dev, &dev_attr_dispregs))
977 dev_err(dev, "Can't create sysfs regdump file\n");
979 if (par->type == BT_CARMINE)
980 outreg(ctrl, GC_CTRL_INT_MASK, GC_CARMINE_INT_EN);
982 outreg(host, GC_IMASK, GC_INT_EN);
987 fb_dealloc_cmap(&info->cmap);
989 free_irq(par->irq, (void *)par);
991 iounmap(par->mmio_base);
993 iounmap(par->fb_base);
995 pci_release_regions(pdev);
997 framebuffer_release(info);
999 pci_disable_device(pdev);
1004 static void __devexit mb862xx_pci_remove(struct pci_dev *pdev)
1006 struct fb_info *fbi = pci_get_drvdata(pdev);
1007 struct mb862xxfb_par *par = fbi->par;
1010 dev_dbg(fbi->dev, "%s release\n", fbi->fix.id);
1013 reg = inreg(disp, GC_DCM1);
1014 reg &= ~(GC_DCM01_DEN | GC_DCM01_L0E);
1015 outreg(disp, GC_DCM1, reg);
1017 if (par->type == BT_CARMINE) {
1018 outreg(ctrl, GC_CTRL_INT_MASK, 0);
1019 outreg(ctrl, GC_CTRL_CLK_ENABLE, 0);
1021 outreg(host, GC_IMASK, 0);
1024 device_remove_file(&pdev->dev, &dev_attr_dispregs);
1026 pci_set_drvdata(pdev, NULL);
1027 unregister_framebuffer(fbi);
1028 fb_dealloc_cmap(&fbi->cmap);
1030 free_irq(par->irq, (void *)par);
1031 iounmap(par->mmio_base);
1032 iounmap(par->fb_base);
1034 pci_release_regions(pdev);
1035 framebuffer_release(fbi);
1036 pci_disable_device(pdev);
1039 static struct pci_driver mb862xxfb_pci_driver = {
1041 .id_table = mb862xx_pci_tbl,
1042 .probe = mb862xx_pci_probe,
1043 .remove = __devexit_p(mb862xx_pci_remove),
1047 static int __devinit mb862xxfb_init(void)
1051 #if defined(CONFIG_FB_MB862XX_LIME)
1052 ret = of_register_platform_driver(&of_platform_mb862xxfb_driver);
1054 #if defined(CONFIG_FB_MB862XX_PCI_GDC)
1055 ret = pci_register_driver(&mb862xxfb_pci_driver);
1060 static void __exit mb862xxfb_exit(void)
1062 #if defined(CONFIG_FB_MB862XX_LIME)
1063 of_unregister_platform_driver(&of_platform_mb862xxfb_driver);
1065 #if defined(CONFIG_FB_MB862XX_PCI_GDC)
1066 pci_unregister_driver(&mb862xxfb_pci_driver);
1070 module_init(mb862xxfb_init);
1071 module_exit(mb862xxfb_exit);
1073 MODULE_DESCRIPTION("Fujitsu MB862xx Framebuffer driver");
1074 MODULE_AUTHOR("Anatolij Gustschin <agust@denx.de>");
1075 MODULE_LICENSE("GPL v2");