2 * Freescale i.MX23/i.MX28 LCDIF driver
4 * Copyright (C) 2011-2013 Marek Vasut <marex@denx.de>
6 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/sys_proto.h>
16 #include <asm/errno.h>
19 #include <asm/imx-common/dma.h>
21 #include "videomodes.h"
23 #define PS2KHZ(ps) (1000000000UL / (ps))
25 DECLARE_GLOBAL_DATA_PTR;
27 static GraphicDevice panel;
28 struct mxs_dma_desc desc;
31 * mxsfb_system_setup() - Fine-tune LCDIF configuration
33 * This function is used to adjust the LCDIF configuration. This is usually
34 * needed when driving the controller in System-Mode to operate an 8080 or
35 * 6800 connected SmartLCD.
37 __weak void mxsfb_system_setup(void)
44 * video=ctfb:x:800,y:480,depth:18,mode:0,pclk:30066,
45 * le:0,ri:256,up:0,lo:45,hs:1,vs:1,sync:100663296,vmode:0
47 * Freescale mx23evk/mx28evk with a Seiko 4.3'' WVGA panel:
49 * video=ctfb:x:800,y:480,depth:24,mode:0,pclk:29851,
50 * le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0
53 static void mxs_lcd_init(GraphicDevice *panel,
54 struct ctfb_res_modes *mode, int bpp)
56 struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
57 uint32_t word_len, bus_width;
61 /* Kick in the LCDIF clock */
62 mxs_set_lcdclk(PS2KHZ(mode->pixclock));
64 /* Restart the LCDIF block */
65 mxs_reset_block(®s->hw_lcdif_ctrl_reg);
69 word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
70 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT;
74 word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
75 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT;
79 word_len = LCDIF_CTRL_WORD_LENGTH_16BIT;
80 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT;
84 word_len = LCDIF_CTRL_WORD_LENGTH_8BIT;
85 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT;
89 printf("Invalid color depth: %d\n", bpp);
93 writel(bus_width | word_len | LCDIF_CTRL_DOTCLK_MODE |
94 LCDIF_CTRL_BYPASS_COUNT | LCDIF_CTRL_LCDIF_MASTER,
95 ®s->hw_lcdif_ctrl);
97 writel(valid_data << LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET,
98 ®s->hw_lcdif_ctrl1);
100 mxsfb_system_setup();
102 writel((mode->yres << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) | mode->xres,
103 ®s->hw_lcdif_transfer_count);
105 if (!(mode->sync & FB_SYNC_OE_LOW_ACT))
106 vctrl0 |= LCDIF_VDCTRL0_ENABLE_POL;
108 if (mode->sync & FB_SYNC_CLK_LAT_FALL)
109 vctrl0 |= LCDIF_VDCTRL0_DOTCLK_POL;
111 if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
112 vctrl0 |= LCDIF_VDCTRL0_HSYNC_POL;
114 if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
115 vctrl0 |= LCDIF_VDCTRL0_VSYNC_POL;
117 writel(vctrl0 | LCDIF_VDCTRL0_ENABLE_PRESENT |
118 LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT |
119 LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
120 mode->vsync_len, ®s->hw_lcdif_vdctrl0);
121 writel(mode->upper_margin + mode->lower_margin +
122 mode->vsync_len + mode->yres,
123 ®s->hw_lcdif_vdctrl1);
124 writel((mode->hsync_len << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET) |
125 (mode->left_margin + mode->right_margin +
126 mode->hsync_len + mode->xres),
127 ®s->hw_lcdif_vdctrl2);
128 writel(((mode->left_margin + mode->hsync_len) <<
129 LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET) |
130 (mode->upper_margin + mode->vsync_len),
131 ®s->hw_lcdif_vdctrl3);
132 writel((0 << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET) | mode->xres,
133 ®s->hw_lcdif_vdctrl4);
135 writel(panel->frameAdrs, ®s->hw_lcdif_cur_buf);
136 writel(panel->frameAdrs, ®s->hw_lcdif_next_buf);
138 /* Flush FIFO first */
139 writel(LCDIF_CTRL1_FIFO_CLEAR, ®s->hw_lcdif_ctrl1_set);
141 #ifndef CONFIG_VIDEO_MXS_MODE_SYSTEM
142 /* Sync signals ON */
143 setbits_le32(®s->hw_lcdif_vdctrl4, LCDIF_VDCTRL4_SYNC_SIGNALS_ON);
147 writel(LCDIF_CTRL1_FIFO_CLEAR, ®s->hw_lcdif_ctrl1_clr);
150 writel(LCDIF_CTRL_RUN, ®s->hw_lcdif_ctrl_set);
153 void *video_hw_init(void)
157 struct ctfb_res_modes mode;
161 /* Suck display configuration from "videomode" variable */
162 penv = getenv("videomode");
164 puts("MXSFB: 'videomode' variable not set!\n");
168 bpp = video_get_params(&mode, penv);
170 /* fill in Graphic device struct */
171 sprintf(panel.modeIdent, "%dx%dx%d",
172 mode.xres, mode.yres, bpp);
174 panel.winSizeX = mode.xres;
175 panel.winSizeY = mode.yres;
176 panel.plnSizeX = mode.xres;
177 panel.plnSizeY = mode.yres;
182 panel.gdfBytesPP = 4;
183 panel.gdfIndex = GDF_32BIT_X888RGB;
186 panel.gdfBytesPP = 2;
187 panel.gdfIndex = GDF_16BIT_565RGB;
190 panel.gdfBytesPP = 1;
191 panel.gdfIndex = GDF__8BIT_INDEX;
194 printf("MXSFB: Invalid BPP specified! (bpp = %i)\n", bpp);
198 panel.memSize = mode.xres * mode.yres * panel.gdfBytesPP;
200 panel.frameAdrs = gd->fb_base;
202 printf("%s\n", panel.modeIdent);
204 /* Start framebuffer */
205 mxs_lcd_init(&panel, &mode, bpp);
207 #ifdef CONFIG_VIDEO_MXS_MODE_SYSTEM
209 * If the LCD runs in system mode, the LCD refresh has to be triggered
210 * manually by setting the RUN bit in HW_LCDIF_CTRL register. To avoid
211 * having to set this bit manually after every single change in the
212 * framebuffer memory, we set up specially crafted circular DMA, which
213 * sets the RUN bit, then waits until it gets cleared and repeats this
214 * infinitelly. This way, we get smooth continuous updates of the LCD.
216 struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
218 memset(&desc, 0, sizeof(struct mxs_dma_desc));
219 desc.address = (dma_addr_t)&desc;
220 desc.cmd.data = MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
221 MXS_DMA_DESC_WAIT4END |
222 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
223 desc.cmd.pio_words[0] = readl(®s->hw_lcdif_ctrl) | LCDIF_CTRL_RUN;
224 desc.cmd.next = (uint32_t)&desc.cmd;
226 /* Execute the DMA chain. */
227 mxs_dma_circ_start(MXS_DMA_CHANNEL_AHB_APBH_LCDIF, &desc);
230 return (void *)&panel;