1 /***************************************************************************\
3 |* Copyright 2003 NVIDIA, Corporation. All rights reserved. *|
5 |* NOTICE TO USER: The source code is copyrighted under U.S. and *|
6 |* international laws. Users and possessors of this source code are *|
7 |* hereby granted a nonexclusive, royalty-free copyright license to *|
8 |* use this code in individual and commercial software. *|
10 |* Any use of this source code must include, in the user documenta- *|
11 |* tion and internal comments to the code, notices to the end user *|
14 |* Copyright 2003 NVIDIA, Corporation. All rights reserved. *|
16 |* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
17 |* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
18 |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
19 |* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
20 |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
21 |* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
22 |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
23 |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
24 |* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
25 |* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
26 |* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
28 |* U.S. Government End Users. This source code is a "commercial *|
29 |* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
30 |* consisting of "commercial computer software" and "commercial *|
31 |* computer software documentation," as such terms are used in *|
32 |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
33 |* ment only as a commercial end item. Consistent with 48 C.F.R. *|
34 |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
35 |* all U.S. Government End Users acquire the source code with only *|
36 |* those rights set forth herein. *|
38 \***************************************************************************/
41 * GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/
42 * XFree86 'nv' driver, this source code is provided under MIT-style licensing
43 * where the source code is provided "as is" without warranty of any kind.
44 * The only usage restriction is for the copyright notices to be retained
45 * whenever code is used.
47 * Antonino Daplas <adaplas@pol.net> 2005-03-11
50 #include <video/vga.h>
51 #include <linux/delay.h>
52 #include <linux/pci.h>
53 #include <linux/slab.h>
58 * Override VGA I/O routines.
60 void NVWriteCrtc(struct nvidia_par *par, u8 index, u8 value)
62 VGA_WR08(par->PCIO, par->IOBase + 0x04, index);
63 VGA_WR08(par->PCIO, par->IOBase + 0x05, value);
65 u8 NVReadCrtc(struct nvidia_par *par, u8 index)
67 VGA_WR08(par->PCIO, par->IOBase + 0x04, index);
68 return (VGA_RD08(par->PCIO, par->IOBase + 0x05));
70 void NVWriteGr(struct nvidia_par *par, u8 index, u8 value)
72 VGA_WR08(par->PVIO, VGA_GFX_I, index);
73 VGA_WR08(par->PVIO, VGA_GFX_D, value);
75 u8 NVReadGr(struct nvidia_par *par, u8 index)
77 VGA_WR08(par->PVIO, VGA_GFX_I, index);
78 return (VGA_RD08(par->PVIO, VGA_GFX_D));
80 void NVWriteSeq(struct nvidia_par *par, u8 index, u8 value)
82 VGA_WR08(par->PVIO, VGA_SEQ_I, index);
83 VGA_WR08(par->PVIO, VGA_SEQ_D, value);
85 u8 NVReadSeq(struct nvidia_par *par, u8 index)
87 VGA_WR08(par->PVIO, VGA_SEQ_I, index);
88 return (VGA_RD08(par->PVIO, VGA_SEQ_D));
90 void NVWriteAttr(struct nvidia_par *par, u8 index, u8 value)
94 tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a);
95 if (par->paletteEnabled)
99 VGA_WR08(par->PCIO, VGA_ATT_IW, index);
100 VGA_WR08(par->PCIO, VGA_ATT_W, value);
102 u8 NVReadAttr(struct nvidia_par *par, u8 index)
106 tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a);
107 if (par->paletteEnabled)
111 VGA_WR08(par->PCIO, VGA_ATT_IW, index);
112 return (VGA_RD08(par->PCIO, VGA_ATT_R));
114 void NVWriteMiscOut(struct nvidia_par *par, u8 value)
116 VGA_WR08(par->PVIO, VGA_MIS_W, value);
118 u8 NVReadMiscOut(struct nvidia_par *par)
120 return (VGA_RD08(par->PVIO, VGA_MIS_R));
123 void NVEnablePalette(struct nvidia_par *par)
127 tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a);
128 VGA_WR08(par->PCIO, VGA_ATT_IW, 0x00);
129 par->paletteEnabled = 1;
131 void NVDisablePalette(struct nvidia_par *par)
135 tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a);
136 VGA_WR08(par->PCIO, VGA_ATT_IW, 0x20);
137 par->paletteEnabled = 0;
140 void NVWriteDacMask(struct nvidia_par *par, u8 value)
142 VGA_WR08(par->PDIO, VGA_PEL_MSK, value);
145 u8 NVReadDacMask(struct nvidia_par *par)
147 return (VGA_RD08(par->PDIO, VGA_PEL_MSK));
150 void NVWriteDacReadAddr(struct nvidia_par *par, u8 value)
152 VGA_WR08(par->PDIO, VGA_PEL_IR, value);
154 void NVWriteDacWriteAddr(struct nvidia_par *par, u8 value)
156 VGA_WR08(par->PDIO, VGA_PEL_IW, value);
158 void NVWriteDacData(struct nvidia_par *par, u8 value)
160 VGA_WR08(par->PDIO, VGA_PEL_D, value);
162 u8 NVReadDacData(struct nvidia_par *par)
164 return (VGA_RD08(par->PDIO, VGA_PEL_D));
167 static int NVIsConnected(struct nvidia_par *par, int output)
169 volatile u32 __iomem *PRAMDAC = par->PRAMDAC0;
170 u32 reg52C, reg608, dac0_reg608 = 0;
174 dac0_reg608 = NV_RD32(PRAMDAC, 0x0608);
178 reg52C = NV_RD32(PRAMDAC, 0x052C);
179 reg608 = NV_RD32(PRAMDAC, 0x0608);
181 NV_WR32(PRAMDAC, 0x0608, reg608 & ~0x00010000);
183 NV_WR32(PRAMDAC, 0x052C, reg52C & 0x0000FEEE);
185 NV_WR32(PRAMDAC, 0x052C, NV_RD32(PRAMDAC, 0x052C) | 1);
187 NV_WR32(par->PRAMDAC0, 0x0610, 0x94050140);
188 NV_WR32(par->PRAMDAC0, 0x0608, NV_RD32(par->PRAMDAC0, 0x0608) |
193 present = (NV_RD32(PRAMDAC, 0x0608) & (1 << 28)) ? 1 : 0;
196 printk("nvidiafb: CRTC%i analog found\n", output);
198 printk("nvidiafb: CRTC%i analog not found\n", output);
201 NV_WR32(par->PRAMDAC0, 0x0608, dac0_reg608);
203 NV_WR32(PRAMDAC, 0x052C, reg52C);
204 NV_WR32(PRAMDAC, 0x0608, reg608);
209 static void NVSelectHeadRegisters(struct nvidia_par *par, int head)
212 par->PCIO = par->PCIO0 + 0x2000;
213 par->PCRTC = par->PCRTC0 + 0x800;
214 par->PRAMDAC = par->PRAMDAC0 + 0x800;
215 par->PDIO = par->PDIO0 + 0x2000;
217 par->PCIO = par->PCIO0;
218 par->PCRTC = par->PCRTC0;
219 par->PRAMDAC = par->PRAMDAC0;
220 par->PDIO = par->PDIO0;
224 static void nv4GetConfig(struct nvidia_par *par)
226 if (NV_RD32(par->PFB, 0x0000) & 0x00000100) {
227 par->RamAmountKBytes =
228 ((NV_RD32(par->PFB, 0x0000) >> 12) & 0x0F) * 1024 * 2 +
231 switch (NV_RD32(par->PFB, 0x0000) & 0x00000003) {
233 par->RamAmountKBytes = 1024 * 32;
236 par->RamAmountKBytes = 1024 * 4;
239 par->RamAmountKBytes = 1024 * 8;
243 par->RamAmountKBytes = 1024 * 16;
247 par->CrystalFreqKHz = (NV_RD32(par->PEXTDEV, 0x0000) & 0x00000040) ?
249 par->CURSOR = &par->PRAMIN[0x1E00];
250 par->MinVClockFreqKHz = 12000;
251 par->MaxVClockFreqKHz = 350000;
254 static void nv10GetConfig(struct nvidia_par *par)
257 u32 implementation = par->Chipset & 0x0ff0;
260 /* turn on big endian register access */
261 if (!(NV_RD32(par->PMC, 0x0004) & 0x01000001)) {
262 NV_WR32(par->PMC, 0x0004, 0x01000001);
267 dev = pci_get_bus_and_slot(0, 1);
268 if ((par->Chipset & 0xffff) == 0x01a0) {
271 pci_read_config_dword(dev, 0x7c, &amt);
272 par->RamAmountKBytes = (((amt >> 6) & 31) + 1) * 1024;
273 } else if ((par->Chipset & 0xffff) == 0x01f0) {
276 pci_read_config_dword(dev, 0x84, &amt);
277 par->RamAmountKBytes = (((amt >> 4) & 127) + 1) * 1024;
279 par->RamAmountKBytes =
280 (NV_RD32(par->PFB, 0x020C) & 0xFFF00000) >> 10;
284 par->CrystalFreqKHz = (NV_RD32(par->PEXTDEV, 0x0000) & (1 << 6)) ?
287 if (par->twoHeads && (implementation != 0x0110)) {
288 if (NV_RD32(par->PEXTDEV, 0x0000) & (1 << 22))
289 par->CrystalFreqKHz = 27000;
292 par->CURSOR = NULL; /* can't set this here */
293 par->MinVClockFreqKHz = 12000;
294 par->MaxVClockFreqKHz = par->twoStagePLL ? 400000 : 350000;
297 int NVCommonSetup(struct fb_info *info)
299 struct nvidia_par *par = info->par;
300 struct fb_var_screeninfo *var;
301 u16 implementation = par->Chipset & 0x0ff0;
302 u8 *edidA = NULL, *edidB = NULL;
303 struct fb_monspecs *monitorA, *monitorB;
304 struct fb_monspecs *monA = NULL, *monB = NULL;
308 int FlatPanel = -1; /* really means the CRTC is slaved */
312 var = kzalloc(sizeof(struct fb_var_screeninfo), GFP_KERNEL);
313 monitorA = kzalloc(sizeof(struct fb_monspecs), GFP_KERNEL);
314 monitorB = kzalloc(sizeof(struct fb_monspecs), GFP_KERNEL);
316 if (!var || !monitorA || !monitorB) {
321 par->PRAMIN = par->REGS + (0x00710000 / 4);
322 par->PCRTC0 = par->REGS + (0x00600000 / 4);
323 par->PRAMDAC0 = par->REGS + (0x00680000 / 4);
324 par->PFB = par->REGS + (0x00100000 / 4);
325 par->PFIFO = par->REGS + (0x00002000 / 4);
326 par->PGRAPH = par->REGS + (0x00400000 / 4);
327 par->PEXTDEV = par->REGS + (0x00101000 / 4);
328 par->PTIMER = par->REGS + (0x00009000 / 4);
329 par->PMC = par->REGS + (0x00000000 / 4);
330 par->FIFO = par->REGS + (0x00800000 / 4);
332 /* 8 bit registers */
333 par->PCIO0 = (u8 __iomem *) par->REGS + 0x00601000;
334 par->PDIO0 = (u8 __iomem *) par->REGS + 0x00681000;
335 par->PVIO = (u8 __iomem *) par->REGS + 0x000C0000;
337 par->twoHeads = (par->Architecture >= NV_ARCH_10) &&
338 (implementation != 0x0100) &&
339 (implementation != 0x0150) &&
340 (implementation != 0x01A0) && (implementation != 0x0200);
342 par->fpScaler = (par->FpScale && par->twoHeads &&
343 (implementation != 0x0110));
345 par->twoStagePLL = (implementation == 0x0310) ||
346 (implementation == 0x0340) || (par->Architecture >= NV_ARCH_40);
348 par->WaitVSyncPossible = (par->Architecture >= NV_ARCH_10) &&
349 (implementation != 0x0100);
351 par->BlendingPossible = ((par->Chipset & 0xffff) != 0x0020);
353 /* look for known laptop chips */
354 switch (par->Chipset & 0xffff) {
409 if (par->Architecture == NV_ARCH_04)
414 NVSelectHeadRegisters(par, 0);
416 NVLockUnlock(par, 0);
418 par->IOBase = (NVReadMiscOut(par) & 0x01) ? 0x3d0 : 0x3b0;
422 nvidia_create_i2c_busses(par);
423 if (!par->twoHeads) {
425 if (nvidia_probe_i2c_connector(info, 1, &edidA))
426 nvidia_probe_of_connector(info, 1, &edidA);
427 if (edidA && !fb_parse_edid(edidA, var)) {
428 printk("nvidiafb: EDID found from BUS1\n");
430 fb_edid_to_monspecs(edidA, monA);
431 FlatPanel = (monA->input & FB_DISP_DDI) ? 1 : 0;
433 /* NV4 doesn't support FlatPanels */
434 if ((par->Chipset & 0x0fff) <= 0x0020)
437 VGA_WR08(par->PCIO, 0x03D4, 0x28);
438 if (VGA_RD08(par->PCIO, 0x03D5) & 0x80) {
439 VGA_WR08(par->PCIO, 0x03D4, 0x33);
440 if (!(VGA_RD08(par->PCIO, 0x03D5) & 0x01))
446 printk("nvidiafb: HW is currently programmed for %s\n",
447 FlatPanel ? (Television ? "TV" : "DFP") :
451 if (par->FlatPanel == -1) {
452 par->FlatPanel = FlatPanel;
453 par->Television = Television;
455 printk("nvidiafb: Forcing display type to %s as "
456 "specified\n", par->FlatPanel ? "DFP" : "CRT");
459 u8 outputAfromCRTC, outputBfromCRTC;
461 u8 slaved_on_A, slaved_on_B;
462 int analog_on_A, analog_on_B;
466 if (implementation != 0x0110) {
467 if (NV_RD32(par->PRAMDAC0, 0x0000052C) & 0x100)
471 if (NV_RD32(par->PRAMDAC0, 0x0000252C) & 0x100)
475 analog_on_A = NVIsConnected(par, 0);
476 analog_on_B = NVIsConnected(par, 1);
484 VGA_WR08(par->PCIO, 0x03D4, 0x44);
485 cr44 = VGA_RD08(par->PCIO, 0x03D5);
487 VGA_WR08(par->PCIO, 0x03D5, 3);
488 NVSelectHeadRegisters(par, 1);
489 NVLockUnlock(par, 0);
491 VGA_WR08(par->PCIO, 0x03D4, 0x28);
492 slaved_on_B = VGA_RD08(par->PCIO, 0x03D5) & 0x80;
494 VGA_WR08(par->PCIO, 0x03D4, 0x33);
495 tvB = !(VGA_RD08(par->PCIO, 0x03D5) & 0x01);
498 VGA_WR08(par->PCIO, 0x03D4, 0x44);
499 VGA_WR08(par->PCIO, 0x03D5, 0);
500 NVSelectHeadRegisters(par, 0);
501 NVLockUnlock(par, 0);
503 VGA_WR08(par->PCIO, 0x03D4, 0x28);
504 slaved_on_A = VGA_RD08(par->PCIO, 0x03D5) & 0x80;
506 VGA_WR08(par->PCIO, 0x03D4, 0x33);
507 tvA = !(VGA_RD08(par->PCIO, 0x03D5) & 0x01);
510 oldhead = NV_RD32(par->PCRTC0, 0x00000860);
511 NV_WR32(par->PCRTC0, 0x00000860, oldhead | 0x00000010);
513 if (nvidia_probe_i2c_connector(info, 1, &edidA))
514 nvidia_probe_of_connector(info, 1, &edidA);
515 if (edidA && !fb_parse_edid(edidA, var)) {
516 printk("nvidiafb: EDID found from BUS1\n");
518 fb_edid_to_monspecs(edidA, monA);
521 if (nvidia_probe_i2c_connector(info, 2, &edidB))
522 nvidia_probe_of_connector(info, 2, &edidB);
523 if (edidB && !fb_parse_edid(edidB, var)) {
524 printk("nvidiafb: EDID found from BUS2\n");
526 fb_edid_to_monspecs(edidB, monB);
529 if (slaved_on_A && !tvA) {
532 printk("nvidiafb: CRTC 0 is currently programmed for "
534 } else if (slaved_on_B && !tvB) {
537 printk("nvidiafb: CRTC 1 is currently programmed "
539 } else if (analog_on_A) {
540 CRTCnumber = outputAfromCRTC;
542 printk("nvidiafb: CRTC %i appears to have a "
543 "CRT attached\n", CRTCnumber);
544 } else if (analog_on_B) {
545 CRTCnumber = outputBfromCRTC;
547 printk("nvidiafb: CRTC %i appears to have a "
548 "CRT attached\n", CRTCnumber);
549 } else if (slaved_on_A) {
553 printk("nvidiafb: CRTC 0 is currently programmed "
555 } else if (slaved_on_B) {
559 printk("nvidiafb: CRTC 1 is currently programmed for "
562 FlatPanel = (monA->input & FB_DISP_DDI) ? 1 : 0;
564 FlatPanel = (monB->input & FB_DISP_DDI) ? 1 : 0;
567 if (par->FlatPanel == -1) {
568 if (FlatPanel != -1) {
569 par->FlatPanel = FlatPanel;
570 par->Television = Television;
572 printk("nvidiafb: Unable to detect display "
575 printk("...On a laptop, assuming "
579 printk("...Using default of CRT\n");
584 printk("nvidiafb: Forcing display type to %s as "
585 "specified\n", par->FlatPanel ? "DFP" : "CRT");
588 if (par->CRTCnumber == -1) {
589 if (CRTCnumber != -1)
590 par->CRTCnumber = CRTCnumber;
592 printk("nvidiafb: Unable to detect which "
598 printk("...Defaulting to CRTCNumber %i\n",
602 printk("nvidiafb: Forcing CRTCNumber %i as "
603 "specified\n", par->CRTCnumber);
607 if (((monA->input & FB_DISP_DDI) &&
609 ((!(monA->input & FB_DISP_DDI)) &&
612 fb_destroy_modedb(monB->modedb);
616 fb_destroy_modedb(monA->modedb);
622 if (((monB->input & FB_DISP_DDI) &&
624 ((!(monB->input & FB_DISP_DDI)) &&
626 fb_destroy_modedb(monB->modedb);
632 if (implementation == 0x0110)
633 cr44 = par->CRTCnumber * 0x3;
635 NV_WR32(par->PCRTC0, 0x00000860, oldhead);
637 VGA_WR08(par->PCIO, 0x03D4, 0x44);
638 VGA_WR08(par->PCIO, 0x03D5, cr44);
639 NVSelectHeadRegisters(par, par->CRTCnumber);
642 printk("nvidiafb: Using %s on CRTC %i\n",
643 par->FlatPanel ? (par->Television ? "TV" : "DFP") : "CRT",
646 if (par->FlatPanel && !par->Television) {
647 par->fpWidth = NV_RD32(par->PRAMDAC, 0x0820) + 1;
648 par->fpHeight = NV_RD32(par->PRAMDAC, 0x0800) + 1;
649 par->fpSyncs = NV_RD32(par->PRAMDAC, 0x0848) & 0x30000033;
651 printk("nvidiafb: Panel size is %i x %i\n", par->fpWidth, par->fpHeight);
655 info->monspecs = *monA;
657 if (!par->FlatPanel || !par->twoHeads)
661 if (par->FlatPanel && par->twoHeads) {
662 NV_WR32(par->PRAMDAC0, 0x08B0, 0x00010004);
663 if (NV_RD32(par->PRAMDAC0, 0x08b4) & 1)
665 printk("nvidiafb: Panel is %s\n", par->LVDS ? "LVDS" : "TMDS");