2 * linux/drivers/video/nvidia/nvidia.c - nVidia fb driver
4 * Copyright 2004 Antonino Daplas <adaplas@pol.net>
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/errno.h>
15 #include <linux/string.h>
17 #include <linux/slab.h>
18 #include <linux/delay.h>
20 #include <linux/init.h>
21 #include <linux/pci.h>
22 #include <linux/console.h>
23 #include <linux/backlight.h>
29 #include <asm/pci-bridge.h>
37 #ifndef CONFIG_PCI /* sanity check */
38 #error This driver requires PCI support.
41 #undef CONFIG_FB_NVIDIA_DEBUG
42 #ifdef CONFIG_FB_NVIDIA_DEBUG
43 #define NVTRACE printk
45 #define NVTRACE if (0) printk
48 #define NVTRACE_ENTER(...) NVTRACE("%s START\n", __FUNCTION__)
49 #define NVTRACE_LEAVE(...) NVTRACE("%s END\n", __FUNCTION__)
51 #ifdef CONFIG_FB_NVIDIA_DEBUG
52 #define assert(expr) \
54 printk( "Assertion failed! %s,%s,%s,line=%d\n",\
55 #expr,__FILE__,__FUNCTION__,__LINE__); \
62 #define PFX "nvidiafb: "
64 /* HW cursor parameters */
67 static struct pci_device_id nvidiafb_pci_tbl[] = {
68 {PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
69 PCI_BASE_CLASS_DISPLAY << 16, 0xff0000, 0},
72 MODULE_DEVICE_TABLE(pci, nvidiafb_pci_tbl);
74 /* command line data, set in nvidiafb_setup() */
75 static int flatpanel __devinitdata = -1; /* Autodetect later */
76 static int fpdither __devinitdata = -1;
77 static int forceCRTC __devinitdata = -1;
78 static int hwcur __devinitdata = 0;
79 static int noaccel __devinitdata = 0;
80 static int noscale __devinitdata = 0;
81 static int paneltweak __devinitdata = 0;
82 static int vram __devinitdata = 0;
83 static int bpp __devinitdata = 8;
85 static int nomtrr __devinitdata = 0;
88 static char *mode_option __devinitdata = NULL;
90 static struct fb_fix_screeninfo __devinitdata nvidiafb_fix = {
91 .type = FB_TYPE_PACKED_PIXELS,
96 static struct fb_var_screeninfo __devinitdata nvidiafb_default_var = {
106 .activate = FB_ACTIVATE_NOW,
116 .vmode = FB_VMODE_NONINTERLACED
119 static void nvidiafb_load_cursor_image(struct nvidia_par *par, u8 * data8,
120 u16 bg, u16 fg, u32 w, u32 h)
122 u32 *data = (u32 *) data8;
128 for (i = 0; i < h; i++) {
132 for (j = 0; j < w / 2; j++) {
134 #if defined (__BIG_ENDIAN)
135 tmp = (b & (1 << 31)) ? fg << 16 : bg << 16;
137 tmp |= (b & (1 << 31)) ? fg : bg;
140 tmp = (b & 1) ? fg : bg;
142 tmp |= (b & 1) ? fg << 16 : bg << 16;
145 NV_WR32(&par->CURSOR[k++], 0, tmp);
147 k += (MAX_CURS - w) / 2;
151 static void nvidia_write_clut(struct nvidia_par *par,
152 u8 regnum, u8 red, u8 green, u8 blue)
154 NVWriteDacMask(par, 0xff);
155 NVWriteDacWriteAddr(par, regnum);
156 NVWriteDacData(par, red);
157 NVWriteDacData(par, green);
158 NVWriteDacData(par, blue);
161 static void nvidia_read_clut(struct nvidia_par *par,
162 u8 regnum, u8 * red, u8 * green, u8 * blue)
164 NVWriteDacMask(par, 0xff);
165 NVWriteDacReadAddr(par, regnum);
166 *red = NVReadDacData(par);
167 *green = NVReadDacData(par);
168 *blue = NVReadDacData(par);
171 static int nvidia_panel_tweak(struct nvidia_par *par,
172 struct _riva_hw_state *state)
176 if (par->paneltweak) {
177 tweak = par->paneltweak;
179 /* begin flat panel hacks */
180 /* This is unfortunate, but some chips need this register
181 tweaked or else you get artifacts where adjacent pixels are
182 swapped. There are no hard rules for what to set here so all
183 we can do is experiment and apply hacks. */
185 if(((par->Chipset & 0xffff) == 0x0328) && (state->bpp == 32)) {
186 /* At least one NV34 laptop needs this workaround. */
190 if((par->Chipset & 0xfff0) == 0x0310) {
193 /* end flat panel hacks */
199 static void nvidia_vga_protect(struct nvidia_par *par, int on)
205 * Turn off screen and disable sequencer.
207 tmp = NVReadSeq(par, 0x01);
209 NVWriteSeq(par, 0x00, 0x01); /* Synchronous Reset */
210 NVWriteSeq(par, 0x01, tmp | 0x20); /* disable the display */
213 * Reenable sequencer, then turn on screen.
216 tmp = NVReadSeq(par, 0x01);
218 NVWriteSeq(par, 0x01, tmp & ~0x20); /* reenable display */
219 NVWriteSeq(par, 0x00, 0x03); /* End Reset */
223 static void nvidia_save_vga(struct nvidia_par *par,
224 struct _riva_hw_state *state)
229 NVLockUnlock(par, 0);
231 NVUnloadStateExt(par, state);
233 state->misc_output = NVReadMiscOut(par);
235 for (i = 0; i < NUM_CRT_REGS; i++)
236 state->crtc[i] = NVReadCrtc(par, i);
238 for (i = 0; i < NUM_ATC_REGS; i++)
239 state->attr[i] = NVReadAttr(par, i);
241 for (i = 0; i < NUM_GRC_REGS; i++)
242 state->gra[i] = NVReadGr(par, i);
244 for (i = 0; i < NUM_SEQ_REGS; i++)
245 state->seq[i] = NVReadSeq(par, i);
251 static void nvidia_write_regs(struct nvidia_par *par,
252 struct _riva_hw_state *state)
258 NVLoadStateExt(par, state);
260 NVWriteMiscOut(par, state->misc_output);
262 for (i = 1; i < NUM_SEQ_REGS; i++) {
264 printk(" SEQ[%02x] = %08x\n", i, state->seq[i]);
266 NVWriteSeq(par, i, state->seq[i]);
269 /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */
270 NVWriteCrtc(par, 0x11, state->crtc[0x11] & ~0x80);
272 for (i = 0; i < NUM_CRT_REGS; i++) {
279 printk("CRTC[%02x] = %08x\n", i, state->crtc[i]);
281 NVWriteCrtc(par, i, state->crtc[i]);
285 for (i = 0; i < NUM_GRC_REGS; i++) {
287 printk(" GRA[%02x] = %08x\n", i, state->gra[i]);
289 NVWriteGr(par, i, state->gra[i]);
292 for (i = 0; i < NUM_ATC_REGS; i++) {
294 printk("ATTR[%02x] = %08x\n", i, state->attr[i]);
296 NVWriteAttr(par, i, state->attr[i]);
302 static int nvidia_calc_regs(struct fb_info *info)
304 struct nvidia_par *par = info->par;
305 struct _riva_hw_state *state = &par->ModeReg;
306 int i, depth = fb_get_color_depth(&info->var, &info->fix);
307 int h_display = info->var.xres / 8 - 1;
308 int h_start = (info->var.xres + info->var.right_margin) / 8 - 1;
309 int h_end = (info->var.xres + info->var.right_margin +
310 info->var.hsync_len) / 8 - 1;
311 int h_total = (info->var.xres + info->var.right_margin +
312 info->var.hsync_len + info->var.left_margin) / 8 - 5;
313 int h_blank_s = h_display;
314 int h_blank_e = h_total + 4;
315 int v_display = info->var.yres - 1;
316 int v_start = info->var.yres + info->var.lower_margin - 1;
317 int v_end = (info->var.yres + info->var.lower_margin +
318 info->var.vsync_len) - 1;
319 int v_total = (info->var.yres + info->var.lower_margin +
320 info->var.vsync_len + info->var.upper_margin) - 2;
321 int v_blank_s = v_display;
322 int v_blank_e = v_total + 1;
325 * Set all CRTC values.
328 if (info->var.vmode & FB_VMODE_INTERLACED)
331 if (par->FlatPanel == 1) {
332 v_start = v_total - 3;
335 h_start = h_total - 5;
337 h_blank_e = h_total + 4;
340 state->crtc[0x0] = Set8Bits(h_total);
341 state->crtc[0x1] = Set8Bits(h_display);
342 state->crtc[0x2] = Set8Bits(h_blank_s);
343 state->crtc[0x3] = SetBitField(h_blank_e, 4: 0, 4:0)
345 state->crtc[0x4] = Set8Bits(h_start);
346 state->crtc[0x5] = SetBitField(h_blank_e, 5: 5, 7:7)
347 | SetBitField(h_end, 4: 0, 4:0);
348 state->crtc[0x6] = SetBitField(v_total, 7: 0, 7:0);
349 state->crtc[0x7] = SetBitField(v_total, 8: 8, 0:0)
350 | SetBitField(v_display, 8: 8, 1:1)
351 | SetBitField(v_start, 8: 8, 2:2)
352 | SetBitField(v_blank_s, 8: 8, 3:3)
354 | SetBitField(v_total, 9: 9, 5:5)
355 | SetBitField(v_display, 9: 9, 6:6)
356 | SetBitField(v_start, 9: 9, 7:7);
357 state->crtc[0x9] = SetBitField(v_blank_s, 9: 9, 5:5)
359 | ((info->var.vmode & FB_VMODE_DOUBLE) ? 0x80 : 0x00);
360 state->crtc[0x10] = Set8Bits(v_start);
361 state->crtc[0x11] = SetBitField(v_end, 3: 0, 3:0) | SetBit(5);
362 state->crtc[0x12] = Set8Bits(v_display);
363 state->crtc[0x13] = ((info->var.xres_virtual / 8) *
364 (info->var.bits_per_pixel / 8));
365 state->crtc[0x15] = Set8Bits(v_blank_s);
366 state->crtc[0x16] = Set8Bits(v_blank_e);
368 state->attr[0x10] = 0x01;
371 state->attr[0x11] = 0x00;
373 state->screen = SetBitField(h_blank_e, 6: 6, 4:4)
374 | SetBitField(v_blank_s, 10: 10, 3:3)
375 | SetBitField(v_start, 10: 10, 2:2)
376 | SetBitField(v_display, 10: 10, 1:1)
377 | SetBitField(v_total, 10: 10, 0:0);
379 state->horiz = SetBitField(h_total, 8: 8, 0:0)
380 | SetBitField(h_display, 8: 8, 1:1)
381 | SetBitField(h_blank_s, 8: 8, 2:2)
382 | SetBitField(h_start, 8: 8, 3:3);
384 state->extra = SetBitField(v_total, 11: 11, 0:0)
385 | SetBitField(v_display, 11: 11, 2:2)
386 | SetBitField(v_start, 11: 11, 4:4)
387 | SetBitField(v_blank_s, 11: 11, 6:6);
389 if (info->var.vmode & FB_VMODE_INTERLACED) {
390 h_total = (h_total >> 1) & ~1;
391 state->interlace = Set8Bits(h_total);
392 state->horiz |= SetBitField(h_total, 8: 8, 4:4);
394 state->interlace = 0xff; /* interlace off */
398 * Calculate the extended registers.
406 if (par->Architecture >= NV_ARCH_10)
407 par->CURSOR = (volatile u32 __iomem *)(info->screen_base +
410 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
411 state->misc_output &= ~0x40;
413 state->misc_output |= 0x40;
414 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
415 state->misc_output &= ~0x80;
417 state->misc_output |= 0x80;
419 NVCalcStateExt(par, state, i, info->var.xres_virtual,
420 info->var.xres, info->var.yres_virtual,
421 1000000000 / info->var.pixclock, info->var.vmode);
423 state->scale = NV_RD32(par->PRAMDAC, 0x00000848) & 0xfff000ff;
424 if (par->FlatPanel == 1) {
425 state->pixel |= (1 << 7);
427 if (!par->fpScaler || (par->fpWidth <= info->var.xres)
428 || (par->fpHeight <= info->var.yres)) {
429 state->scale |= (1 << 8);
432 if (!par->crtcSync_read) {
433 state->crtcSync = NV_RD32(par->PRAMDAC, 0x0828);
434 par->crtcSync_read = 1;
437 par->PanelTweak = nvidia_panel_tweak(par, state);
440 state->vpll = state->pll;
441 state->vpll2 = state->pll;
442 state->vpllB = state->pllB;
443 state->vpll2B = state->pllB;
445 VGA_WR08(par->PCIO, 0x03D4, 0x1C);
446 state->fifo = VGA_RD08(par->PCIO, 0x03D5) & ~(1<<5);
448 if (par->CRTCnumber) {
449 state->head = NV_RD32(par->PCRTC0, 0x00000860) & ~0x00001000;
450 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) | 0x00001000;
451 state->crtcOwner = 3;
452 state->pllsel |= 0x20000800;
453 state->vpll = NV_RD32(par->PRAMDAC0, 0x00000508);
454 if (par->twoStagePLL)
455 state->vpllB = NV_RD32(par->PRAMDAC0, 0x00000578);
456 } else if (par->twoHeads) {
457 state->head = NV_RD32(par->PCRTC0, 0x00000860) | 0x00001000;
458 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) & ~0x00001000;
459 state->crtcOwner = 0;
460 state->vpll2 = NV_RD32(par->PRAMDAC0, 0x0520);
461 if (par->twoStagePLL)
462 state->vpll2B = NV_RD32(par->PRAMDAC0, 0x057C);
465 state->cursorConfig = 0x00000100;
467 if (info->var.vmode & FB_VMODE_DOUBLE)
468 state->cursorConfig |= (1 << 4);
470 if (par->alphaCursor) {
471 if ((par->Chipset & 0x0ff0) != 0x0110)
472 state->cursorConfig |= 0x04011000;
474 state->cursorConfig |= 0x14011000;
475 state->general |= (1 << 29);
477 state->cursorConfig |= 0x02000000;
480 if ((par->Chipset & 0x0ff0) == 0x0110) {
481 state->dither = NV_RD32(par->PRAMDAC, 0x0528) &
484 state->dither |= 0x00010000;
486 state->dither = NV_RD32(par->PRAMDAC, 0x083C) & ~1;
494 state->displayV = info->var.xres;
499 static void nvidia_init_vga(struct fb_info *info)
501 struct nvidia_par *par = info->par;
502 struct _riva_hw_state *state = &par->ModeReg;
505 for (i = 0; i < 0x10; i++)
507 state->attr[0x10] = 0x41;
508 state->attr[0x11] = 0xff;
509 state->attr[0x12] = 0x0f;
510 state->attr[0x13] = 0x00;
511 state->attr[0x14] = 0x00;
513 memset(state->crtc, 0x00, NUM_CRT_REGS);
514 state->crtc[0x0a] = 0x20;
515 state->crtc[0x17] = 0xe3;
516 state->crtc[0x18] = 0xff;
517 state->crtc[0x28] = 0x40;
519 memset(state->gra, 0x00, NUM_GRC_REGS);
520 state->gra[0x05] = 0x40;
521 state->gra[0x06] = 0x05;
522 state->gra[0x07] = 0x0f;
523 state->gra[0x08] = 0xff;
525 state->seq[0x00] = 0x03;
526 state->seq[0x01] = 0x01;
527 state->seq[0x02] = 0x0f;
528 state->seq[0x03] = 0x00;
529 state->seq[0x04] = 0x0e;
531 state->misc_output = 0xeb;
534 static int nvidiafb_cursor(struct fb_info *info, struct fb_cursor *cursor)
536 struct nvidia_par *par = info->par;
537 u8 data[MAX_CURS * MAX_CURS / 8];
538 int i, set = cursor->set;
541 if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS)
544 NVShowHideCursor(par, 0);
546 if (par->cursor_reset) {
548 par->cursor_reset = 0;
551 if (set & FB_CUR_SETSIZE)
552 memset_io(par->CURSOR, 0, MAX_CURS * MAX_CURS * 2);
554 if (set & FB_CUR_SETPOS) {
557 yy = cursor->image.dy - info->var.yoffset;
558 xx = cursor->image.dx - info->var.xoffset;
562 NV_WR32(par->PRAMDAC, 0x0000300, temp);
565 if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) {
566 u32 bg_idx = cursor->image.bg_color;
567 u32 fg_idx = cursor->image.fg_color;
568 u32 s_pitch = (cursor->image.width + 7) >> 3;
569 u32 d_pitch = MAX_CURS / 8;
570 u8 *dat = (u8 *) cursor->image.data;
571 u8 *msk = (u8 *) cursor->mask;
574 src = kmalloc(s_pitch * cursor->image.height, GFP_ATOMIC);
577 switch (cursor->rop) {
579 for (i = 0; i < s_pitch * cursor->image.height; i++)
580 src[i] = dat[i] ^ msk[i];
584 for (i = 0; i < s_pitch * cursor->image.height; i++)
585 src[i] = dat[i] & msk[i];
589 fb_pad_aligned_buffer(data, d_pitch, src, s_pitch,
590 cursor->image.height);
592 bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) |
593 ((info->cmap.green[bg_idx] & 0xf8) << 2) |
594 ((info->cmap.blue[bg_idx] & 0xf8) >> 3) | 1 << 15;
596 fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
597 ((info->cmap.green[fg_idx] & 0xf8) << 2) |
598 ((info->cmap.blue[fg_idx] & 0xf8) >> 3) | 1 << 15;
600 NVLockUnlock(par, 0);
602 nvidiafb_load_cursor_image(par, data, bg, fg,
604 cursor->image.height);
610 NVShowHideCursor(par, 1);
615 static int nvidiafb_set_par(struct fb_info *info)
617 struct nvidia_par *par = info->par;
621 NVLockUnlock(par, 1);
622 if (!par->FlatPanel || !par->twoHeads)
625 if (par->FPDither < 0) {
626 if ((par->Chipset & 0x0ff0) == 0x0110)
627 par->FPDither = !!(NV_RD32(par->PRAMDAC, 0x0528)
630 par->FPDither = !!(NV_RD32(par->PRAMDAC, 0x083C) & 1);
631 printk(KERN_INFO PFX "Flat panel dithering %s\n",
632 par->FPDither ? "enabled" : "disabled");
635 info->fix.visual = (info->var.bits_per_pixel == 8) ?
636 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
638 nvidia_init_vga(info);
639 nvidia_calc_regs(info);
641 NVLockUnlock(par, 0);
643 VGA_WR08(par->PCIO, 0x03D4, 0x44);
644 VGA_WR08(par->PCIO, 0x03D5, par->ModeReg.crtcOwner);
645 NVLockUnlock(par, 0);
648 nvidia_vga_protect(par, 1);
650 nvidia_write_regs(par, &par->ModeReg);
651 NVSetStartAddress(par, 0);
653 #if defined (__BIG_ENDIAN)
654 /* turn on LFB swapping */
658 VGA_WR08(par->PCIO, 0x3d4, 0x46);
659 tmp = VGA_RD08(par->PCIO, 0x3d5);
661 VGA_WR08(par->PCIO, 0x3d5, tmp);
665 info->fix.line_length = (info->var.xres_virtual *
666 info->var.bits_per_pixel) >> 3;
667 if (info->var.accel_flags) {
668 info->fbops->fb_imageblit = nvidiafb_imageblit;
669 info->fbops->fb_fillrect = nvidiafb_fillrect;
670 info->fbops->fb_copyarea = nvidiafb_copyarea;
671 info->fbops->fb_sync = nvidiafb_sync;
672 info->pixmap.scan_align = 4;
673 info->flags &= ~FBINFO_HWACCEL_DISABLED;
674 NVResetGraphics(info);
676 info->fbops->fb_imageblit = cfb_imageblit;
677 info->fbops->fb_fillrect = cfb_fillrect;
678 info->fbops->fb_copyarea = cfb_copyarea;
679 info->fbops->fb_sync = NULL;
680 info->pixmap.scan_align = 1;
681 info->flags |= FBINFO_HWACCEL_DISABLED;
684 par->cursor_reset = 1;
686 nvidia_vga_protect(par, 0);
692 static int nvidiafb_setcolreg(unsigned regno, unsigned red, unsigned green,
693 unsigned blue, unsigned transp,
694 struct fb_info *info)
696 struct nvidia_par *par = info->par;
700 if (regno >= (1 << info->var.green.length))
703 if (info->var.grayscale) {
704 /* gray = 0.30*R + 0.59*G + 0.11*B */
705 red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
708 if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
709 ((u32 *) info->pseudo_palette)[regno] =
710 (regno << info->var.red.offset) |
711 (regno << info->var.green.offset) |
712 (regno << info->var.blue.offset);
715 switch (info->var.bits_per_pixel) {
717 /* "transparent" stuff is completely ignored. */
718 nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8);
721 if (info->var.green.length == 5) {
722 for (i = 0; i < 8; i++) {
723 nvidia_write_clut(par, regno * 8 + i, red >> 8,
724 green >> 8, blue >> 8);
730 for (i = 0; i < 8; i++) {
731 nvidia_write_clut(par, regno * 8 + i,
732 red >> 8, green >> 8,
737 nvidia_read_clut(par, regno * 4, &r, &g, &b);
739 for (i = 0; i < 4; i++)
740 nvidia_write_clut(par, regno * 4 + i, r,
745 nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8);
756 static int nvidiafb_check_var(struct fb_var_screeninfo *var,
757 struct fb_info *info)
759 struct nvidia_par *par = info->par;
760 int memlen, vramlen, mode_valid = 0;
765 var->transp.offset = 0;
766 var->transp.length = 0;
770 if (var->bits_per_pixel <= 8)
771 var->bits_per_pixel = 8;
772 else if (var->bits_per_pixel <= 16)
773 var->bits_per_pixel = 16;
775 var->bits_per_pixel = 32;
777 switch (var->bits_per_pixel) {
781 var->green.offset = 0;
782 var->green.length = 8;
783 var->blue.offset = 0;
784 var->blue.length = 8;
785 var->transp.offset = 0;
786 var->transp.length = 0;
789 var->green.length = (var->green.length < 6) ? 5 : 6;
791 var->blue.length = 5;
792 var->transp.length = 6 - var->green.length;
793 var->blue.offset = 0;
794 var->green.offset = 5;
795 var->red.offset = 5 + var->green.length;
796 var->transp.offset = (5 + var->red.offset) & 15;
798 case 32: /* RGBA 8888 */
799 var->red.offset = 16;
801 var->green.offset = 8;
802 var->green.length = 8;
803 var->blue.offset = 0;
804 var->blue.length = 8;
805 var->transp.length = 8;
806 var->transp.offset = 24;
810 var->red.msb_right = 0;
811 var->green.msb_right = 0;
812 var->blue.msb_right = 0;
813 var->transp.msb_right = 0;
815 if (!info->monspecs.hfmax || !info->monspecs.vfmax ||
816 !info->monspecs.dclkmax || !fb_validate_mode(var, info))
819 /* calculate modeline if supported by monitor */
820 if (!mode_valid && info->monspecs.gtf) {
821 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
826 struct fb_videomode *mode;
828 mode = fb_find_best_mode(var, &info->modelist);
830 fb_videomode_to_var(var, mode);
835 if (!mode_valid && info->monspecs.modedb_len)
838 if (par->fpWidth && par->fpHeight && (par->fpWidth < var->xres ||
839 par->fpHeight < var->yres))
842 if (var->yres_virtual < var->yres)
843 var->yres_virtual = var->yres;
845 if (var->xres_virtual < var->xres)
846 var->xres_virtual = var->xres;
848 var->xres_virtual = (var->xres_virtual + 63) & ~63;
850 vramlen = info->screen_size;
851 pitch = ((var->xres_virtual * var->bits_per_pixel) + 7) / 8;
852 memlen = pitch * var->yres_virtual;
854 if (memlen > vramlen) {
855 var->yres_virtual = vramlen / pitch;
857 if (var->yres_virtual < var->yres) {
858 var->yres_virtual = var->yres;
859 var->xres_virtual = vramlen / var->yres_virtual;
860 var->xres_virtual /= var->bits_per_pixel / 8;
861 var->xres_virtual &= ~63;
862 pitch = (var->xres_virtual *
863 var->bits_per_pixel + 7) / 8;
864 memlen = pitch * var->yres;
866 if (var->xres_virtual < var->xres) {
867 printk("nvidiafb: required video memory, "
868 "%d bytes, for %dx%d-%d (virtual) "
870 memlen, var->xres_virtual,
871 var->yres_virtual, var->bits_per_pixel);
877 if (var->accel_flags) {
878 if (var->yres_virtual > 0x7fff)
879 var->yres_virtual = 0x7fff;
880 if (var->xres_virtual > 0x7fff)
881 var->xres_virtual = 0x7fff;
884 var->xres_virtual &= ~63;
891 static int nvidiafb_pan_display(struct fb_var_screeninfo *var,
892 struct fb_info *info)
894 struct nvidia_par *par = info->par;
897 total = var->yoffset * info->fix.line_length + var->xoffset;
899 NVSetStartAddress(par, total);
904 static int nvidiafb_blank(int blank, struct fb_info *info)
906 struct nvidia_par *par = info->par;
907 unsigned char tmp, vesa;
909 tmp = NVReadSeq(par, 0x01) & ~0x20; /* screen on/off */
910 vesa = NVReadCrtc(par, 0x1a) & ~0xc0; /* sync on/off */
918 case FB_BLANK_UNBLANK:
919 case FB_BLANK_NORMAL:
921 case FB_BLANK_VSYNC_SUSPEND:
924 case FB_BLANK_HSYNC_SUSPEND:
927 case FB_BLANK_POWERDOWN:
932 NVWriteSeq(par, 0x01, tmp);
933 NVWriteCrtc(par, 0x1a, vesa);
935 #ifdef CONFIG_FB_NVIDIA_BACKLIGHT
936 mutex_lock(&info->bl_mutex);
938 down(&info->bl_dev->sem);
939 info->bl_dev->props->power = blank;
940 info->bl_dev->props->update_status(info->bl_dev);
941 up(&info->bl_dev->sem);
943 mutex_unlock(&info->bl_mutex);
951 static struct fb_ops nvidia_fb_ops = {
952 .owner = THIS_MODULE,
953 .fb_check_var = nvidiafb_check_var,
954 .fb_set_par = nvidiafb_set_par,
955 .fb_setcolreg = nvidiafb_setcolreg,
956 .fb_pan_display = nvidiafb_pan_display,
957 .fb_blank = nvidiafb_blank,
958 .fb_fillrect = nvidiafb_fillrect,
959 .fb_copyarea = nvidiafb_copyarea,
960 .fb_imageblit = nvidiafb_imageblit,
961 .fb_cursor = nvidiafb_cursor,
962 .fb_sync = nvidiafb_sync,
966 static int nvidiafb_suspend(struct pci_dev *dev, pm_message_t state)
968 struct fb_info *info = pci_get_drvdata(dev);
969 struct nvidia_par *par = info->par;
971 acquire_console_sem();
972 par->pm_state = state.event;
974 if (state.event == PM_EVENT_FREEZE) {
975 dev->dev.power.power_state = state;
977 fb_set_suspend(info, 1);
978 nvidiafb_blank(FB_BLANK_POWERDOWN, info);
979 nvidia_write_regs(par, &par->SavedReg);
981 pci_disable_device(dev);
982 pci_set_power_state(dev, pci_choose_state(dev, state));
985 release_console_sem();
989 static int nvidiafb_resume(struct pci_dev *dev)
991 struct fb_info *info = pci_get_drvdata(dev);
992 struct nvidia_par *par = info->par;
994 acquire_console_sem();
995 pci_set_power_state(dev, PCI_D0);
997 if (par->pm_state != PM_EVENT_FREEZE) {
998 pci_restore_state(dev);
999 pci_enable_device(dev);
1000 pci_set_master(dev);
1003 par->pm_state = PM_EVENT_ON;
1004 nvidiafb_set_par(info);
1005 fb_set_suspend (info, 0);
1006 nvidiafb_blank(FB_BLANK_UNBLANK, info);
1008 release_console_sem();
1012 #define nvidiafb_suspend NULL
1013 #define nvidiafb_resume NULL
1016 static int __devinit nvidia_set_fbinfo(struct fb_info *info)
1018 struct fb_monspecs *specs = &info->monspecs;
1019 struct fb_videomode modedb;
1020 struct nvidia_par *par = info->par;
1024 info->flags = FBINFO_DEFAULT
1025 | FBINFO_HWACCEL_IMAGEBLIT
1026 | FBINFO_HWACCEL_FILLRECT
1027 | FBINFO_HWACCEL_COPYAREA
1028 | FBINFO_HWACCEL_YPAN;
1030 fb_videomode_to_modelist(info->monspecs.modedb,
1031 info->monspecs.modedb_len, &info->modelist);
1032 fb_var_to_videomode(&modedb, &nvidiafb_default_var);
1046 if (specs->modedb != NULL) {
1047 struct fb_videomode *modedb;
1049 modedb = fb_find_best_display(specs, &info->modelist);
1050 fb_videomode_to_var(&nvidiafb_default_var, modedb);
1051 nvidiafb_default_var.bits_per_pixel = bpp;
1052 } else if (par->fpWidth && par->fpHeight) {
1056 snprintf(buf, 15, "%dx%dMR", par->fpWidth, par->fpHeight);
1057 fb_find_mode(&nvidiafb_default_var, info, buf, specs->modedb,
1058 specs->modedb_len, &modedb, bpp);
1062 fb_find_mode(&nvidiafb_default_var, info, mode_option,
1063 specs->modedb, specs->modedb_len, &modedb, bpp);
1065 info->var = nvidiafb_default_var;
1066 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1067 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1068 info->pseudo_palette = par->pseudo_palette;
1069 fb_alloc_cmap(&info->cmap, 256, 0);
1070 fb_destroy_modedb(info->monspecs.modedb);
1071 info->monspecs.modedb = NULL;
1073 /* maximize virtual vertical length */
1074 lpitch = info->var.xres_virtual *
1075 ((info->var.bits_per_pixel + 7) >> 3);
1076 info->var.yres_virtual = info->screen_size / lpitch;
1078 info->pixmap.scan_align = 4;
1079 info->pixmap.buf_align = 4;
1080 info->pixmap.access_align = 32;
1081 info->pixmap.size = 8 * 1024;
1082 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1085 info->fbops->fb_cursor = NULL;
1087 info->var.accel_flags = (!noaccel);
1089 switch (par->Architecture) {
1091 info->fix.accel = FB_ACCEL_NV4;
1094 info->fix.accel = FB_ACCEL_NV_10;
1097 info->fix.accel = FB_ACCEL_NV_20;
1100 info->fix.accel = FB_ACCEL_NV_30;
1103 info->fix.accel = FB_ACCEL_NV_40;
1109 return nvidiafb_check_var(&info->var, info);
1112 static u32 __devinit nvidia_get_chipset(struct fb_info *info)
1114 struct nvidia_par *par = info->par;
1115 u32 id = (par->pci_dev->vendor << 16) | par->pci_dev->device;
1117 printk(KERN_INFO PFX "Device ID: %x \n", id);
1119 if ((id & 0xfff0) == 0x00f0) {
1121 id = NV_RD32(par->REGS, 0x1800);
1123 if ((id & 0x0000ffff) == 0x000010DE)
1124 id = 0x10DE0000 | (id >> 16);
1125 else if ((id & 0xffff0000) == 0xDE100000) /* wrong endian */
1126 id = 0x10DE0000 | ((id << 8) & 0x0000ff00) |
1127 ((id >> 8) & 0x000000ff);
1128 printk(KERN_INFO PFX "Subsystem ID: %x \n", id);
1134 static u32 __devinit nvidia_get_arch(struct fb_info *info)
1136 struct nvidia_par *par = info->par;
1139 switch (par->Chipset & 0x0ff0) {
1140 case 0x0100: /* GeForce 256 */
1141 case 0x0110: /* GeForce2 MX */
1142 case 0x0150: /* GeForce2 */
1143 case 0x0170: /* GeForce4 MX */
1144 case 0x0180: /* GeForce4 MX (8x AGP) */
1145 case 0x01A0: /* nForce */
1146 case 0x01F0: /* nForce2 */
1149 case 0x0200: /* GeForce3 */
1150 case 0x0250: /* GeForce4 Ti */
1151 case 0x0280: /* GeForce4 Ti (8x AGP) */
1154 case 0x0300: /* GeForceFX 5800 */
1155 case 0x0310: /* GeForceFX 5600 */
1156 case 0x0320: /* GeForceFX 5200 */
1157 case 0x0330: /* GeForceFX 5900 */
1158 case 0x0340: /* GeForceFX 5700 */
1177 case 0x0020: /* TNT, TNT2 */
1180 default: /* unknown architecture */
1187 static int __devinit nvidiafb_probe(struct pci_dev *pd,
1188 const struct pci_device_id *ent)
1190 struct nvidia_par *par;
1191 struct fb_info *info;
1198 info = framebuffer_alloc(sizeof(struct nvidia_par), &pd->dev);
1206 info->pixmap.addr = kmalloc(8 * 1024, GFP_KERNEL);
1208 if (info->pixmap.addr == NULL)
1211 memset(info->pixmap.addr, 0, 8 * 1024);
1213 if (pci_enable_device(pd)) {
1214 printk(KERN_ERR PFX "cannot enable PCI device\n");
1215 goto err_out_enable;
1218 if (pci_request_regions(pd, "nvidiafb")) {
1219 printk(KERN_ERR PFX "cannot request PCI regions\n");
1220 goto err_out_enable;
1223 par->FlatPanel = flatpanel;
1225 printk(KERN_INFO PFX "flatpanel support enabled\n");
1226 par->FPDither = fpdither;
1228 par->CRTCnumber = forceCRTC;
1229 par->FpScale = (!noscale);
1230 par->paneltweak = paneltweak;
1232 /* enable IO and mem if not already done */
1233 pci_read_config_word(pd, PCI_COMMAND, &cmd);
1234 cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
1235 pci_write_config_word(pd, PCI_COMMAND, cmd);
1237 nvidiafb_fix.mmio_start = pci_resource_start(pd, 0);
1238 nvidiafb_fix.smem_start = pci_resource_start(pd, 1);
1239 nvidiafb_fix.mmio_len = pci_resource_len(pd, 0);
1241 par->REGS = ioremap(nvidiafb_fix.mmio_start, nvidiafb_fix.mmio_len);
1244 printk(KERN_ERR PFX "cannot ioremap MMIO base\n");
1245 goto err_out_free_base0;
1248 par->Chipset = nvidia_get_chipset(info);
1249 par->Architecture = nvidia_get_arch(info);
1251 if (par->Architecture == 0) {
1252 printk(KERN_ERR PFX "unknown NV_ARCH\n");
1256 sprintf(nvidiafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4);
1258 if (NVCommonSetup(info))
1261 par->FbAddress = nvidiafb_fix.smem_start;
1262 par->FbMapSize = par->RamAmountKBytes * 1024;
1263 if (vram && vram * 1024 * 1024 < par->FbMapSize)
1264 par->FbMapSize = vram * 1024 * 1024;
1266 /* Limit amount of vram to 64 MB */
1267 if (par->FbMapSize > 64 * 1024 * 1024)
1268 par->FbMapSize = 64 * 1024 * 1024;
1270 if(par->Architecture >= NV_ARCH_40)
1271 par->FbUsableSize = par->FbMapSize - (560 * 1024);
1273 par->FbUsableSize = par->FbMapSize - (128 * 1024);
1274 par->ScratchBufferSize = (par->Architecture < NV_ARCH_10) ? 8 * 1024 :
1276 par->ScratchBufferStart = par->FbUsableSize - par->ScratchBufferSize;
1277 par->CursorStart = par->FbUsableSize + (32 * 1024);
1279 info->screen_base = ioremap(nvidiafb_fix.smem_start, par->FbMapSize);
1280 info->screen_size = par->FbUsableSize;
1281 nvidiafb_fix.smem_len = par->RamAmountKBytes * 1024;
1283 if (!info->screen_base) {
1284 printk(KERN_ERR PFX "cannot ioremap FB base\n");
1285 goto err_out_free_base1;
1288 par->FbStart = info->screen_base;
1292 par->mtrr.vram = mtrr_add(nvidiafb_fix.smem_start,
1293 par->RamAmountKBytes * 1024,
1294 MTRR_TYPE_WRCOMB, 1);
1295 if (par->mtrr.vram < 0) {
1296 printk(KERN_ERR PFX "unable to setup MTRR\n");
1298 par->mtrr.vram_valid = 1;
1299 /* let there be speed */
1300 printk(KERN_INFO PFX "MTRR set to ON\n");
1303 #endif /* CONFIG_MTRR */
1305 info->fbops = &nvidia_fb_ops;
1306 info->fix = nvidiafb_fix;
1308 if (nvidia_set_fbinfo(info) < 0) {
1309 printk(KERN_ERR PFX "error setting initial video mode\n");
1310 goto err_out_iounmap_fb;
1313 nvidia_save_vga(par, &par->SavedReg);
1315 if (register_framebuffer(info) < 0) {
1316 printk(KERN_ERR PFX "error registering nVidia framebuffer\n");
1317 goto err_out_iounmap_fb;
1320 pci_set_drvdata(pd, info);
1322 printk(KERN_INFO PFX
1323 "PCI nVidia %s framebuffer (%dMB @ 0x%lX)\n",
1325 par->FbMapSize / (1024 * 1024), info->fix.smem_start);
1327 nvidia_bl_init(par);
1333 iounmap(info->screen_base);
1335 fb_destroy_modedb(info->monspecs.modedb);
1336 nvidia_delete_i2c_busses(par);
1340 pci_release_regions(pd);
1342 kfree(info->pixmap.addr);
1344 framebuffer_release(info);
1349 static void __exit nvidiafb_remove(struct pci_dev *pd)
1351 struct fb_info *info = pci_get_drvdata(pd);
1352 struct nvidia_par *par = info->par;
1356 nvidia_bl_exit(par);
1358 unregister_framebuffer(info);
1360 if (par->mtrr.vram_valid)
1361 mtrr_del(par->mtrr.vram, info->fix.smem_start,
1362 info->fix.smem_len);
1363 #endif /* CONFIG_MTRR */
1365 iounmap(info->screen_base);
1366 fb_destroy_modedb(info->monspecs.modedb);
1367 nvidia_delete_i2c_busses(par);
1369 pci_release_regions(pd);
1370 kfree(info->pixmap.addr);
1371 framebuffer_release(info);
1372 pci_set_drvdata(pd, NULL);
1376 /* ------------------------------------------------------------------------- *
1380 * ------------------------------------------------------------------------- */
1383 static int __devinit nvidiafb_setup(char *options)
1388 if (!options || !*options)
1391 while ((this_opt = strsep(&options, ",")) != NULL) {
1392 if (!strncmp(this_opt, "forceCRTC", 9)) {
1398 forceCRTC = *p - '0';
1399 if (forceCRTC < 0 || forceCRTC > 1)
1401 } else if (!strncmp(this_opt, "flatpanel", 9)) {
1403 } else if (!strncmp(this_opt, "hwcur", 5)) {
1405 } else if (!strncmp(this_opt, "noaccel", 6)) {
1407 } else if (!strncmp(this_opt, "noscale", 7)) {
1409 } else if (!strncmp(this_opt, "paneltweak:", 11)) {
1410 paneltweak = simple_strtoul(this_opt+11, NULL, 0);
1411 } else if (!strncmp(this_opt, "vram:", 5)) {
1412 vram = simple_strtoul(this_opt+5, NULL, 0);
1414 } else if (!strncmp(this_opt, "nomtrr", 6)) {
1417 } else if (!strncmp(this_opt, "fpdither:", 9)) {
1418 fpdither = simple_strtol(this_opt+9, NULL, 0);
1419 } else if (!strncmp(this_opt, "bpp:", 4)) {
1420 bpp = simple_strtoul(this_opt+4, NULL, 0);
1422 mode_option = this_opt;
1427 #endif /* !MODULE */
1429 static struct pci_driver nvidiafb_driver = {
1431 .id_table = nvidiafb_pci_tbl,
1432 .probe = nvidiafb_probe,
1433 .suspend = nvidiafb_suspend,
1434 .resume = nvidiafb_resume,
1435 .remove = __exit_p(nvidiafb_remove),
1438 /* ------------------------------------------------------------------------- *
1442 * ------------------------------------------------------------------------- */
1444 static int __devinit nvidiafb_init(void)
1447 char *option = NULL;
1449 if (fb_get_options("nvidiafb", &option))
1451 nvidiafb_setup(option);
1453 return pci_register_driver(&nvidiafb_driver);
1456 module_init(nvidiafb_init);
1459 static void __exit nvidiafb_exit(void)
1461 pci_unregister_driver(&nvidiafb_driver);
1464 module_exit(nvidiafb_exit);
1466 module_param(flatpanel, int, 0);
1467 MODULE_PARM_DESC(flatpanel,
1468 "Enables experimental flat panel support for some chipsets. "
1469 "(0=disabled, 1=enabled, -1=autodetect) (default=-1)");
1470 module_param(fpdither, int, 0);
1471 MODULE_PARM_DESC(fpdither,
1472 "Enables dithering of flat panel for 6 bits panels. "
1473 "(0=disabled, 1=enabled, -1=autodetect) (default=-1)");
1474 module_param(hwcur, int, 0);
1475 MODULE_PARM_DESC(hwcur,
1476 "Enables hardware cursor implementation. (0 or 1=enabled) "
1478 module_param(noaccel, int, 0);
1479 MODULE_PARM_DESC(noaccel,
1480 "Disables hardware acceleration. (0 or 1=disable) "
1482 module_param(noscale, int, 0);
1483 MODULE_PARM_DESC(noscale,
1484 "Disables screen scaleing. (0 or 1=disable) "
1485 "(default=0, do scaling)");
1486 module_param(paneltweak, int, 0);
1487 MODULE_PARM_DESC(paneltweak,
1488 "Tweak display settings for flatpanels. "
1489 "(default=0, no tweaks)");
1490 module_param(forceCRTC, int, 0);
1491 MODULE_PARM_DESC(forceCRTC,
1492 "Forces usage of a particular CRTC in case autodetection "
1493 "fails. (0 or 1) (default=autodetect)");
1494 module_param(vram, int, 0);
1495 MODULE_PARM_DESC(vram,
1496 "amount of framebuffer memory to remap in MiB"
1497 "(default=0 - remap entire memory)");
1498 module_param(mode_option, charp, 0);
1499 MODULE_PARM_DESC(mode_option, "Specify initial video mode");
1500 module_param(bpp, int, 0);
1501 MODULE_PARM_DESC(bpp, "pixel width in bits"
1504 module_param(nomtrr, bool, 0);
1505 MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) "
1509 MODULE_AUTHOR("Antonino Daplas");
1510 MODULE_DESCRIPTION("Framebuffer driver for nVidia graphics chipset");
1511 MODULE_LICENSE("GPL");