drivers/video/omap2/dss/dispc.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dispc.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #define DSS_SUBSYS_NAME "DISPC"
  24
  25 #include <linux/kernel.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/vmalloc.h>
  28 #include <linux/export.h>
  29 #include <linux/clk.h>
  30 #include <linux/io.h>
  31 #include <linux/jiffies.h>
  32 #include <linux/seq_file.h>
  33 #include <linux/delay.h>
  34 #include <linux/workqueue.h>
  35 #include <linux/hardirq.h>
  36 #include <linux/platform_device.h>
  37 #include <linux/pm_runtime.h>
  38 #include <linux/sizes.h>
  39
  40 #include <video/omapdss.h>
  41
  42 #include "dss.h"
  43 #include "dss_features.h"
  44 #include "dispc.h"
  45
  46 /* DISPC */
  47 #define DISPC_SZ_REGS                   SZ_4K
  48
  49 enum omap_burst_size {
  50         BURST_SIZE_X2 = 0,
  51         BURST_SIZE_X4 = 1,
  52         BURST_SIZE_X8 = 2,
  53 };
  54
  55 #define REG_GET(idx, start, end) \
  56         FLD_GET(dispc_read_reg(idx), start, end)
  57
  58 #define REG_FLD_MOD(idx, val, start, end)                               \
  59         dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
  60
  61 struct dispc_features {
  62         u8 sw_start;
  63         u8 fp_start;
  64         u8 bp_start;
  65         u16 sw_max;
  66         u16 vp_max;
  67         u16 hp_max;
  68         u8 mgr_width_start;
  69         u8 mgr_height_start;
  70         u16 mgr_width_max;
  71         u16 mgr_height_max;
  72         int (*calc_scaling) (unsigned long pclk, unsigned long lclk,
  73                 const struct omap_video_timings *mgr_timings,
  74                 u16 width, u16 height, u16 out_width, u16 out_height,
  75                 enum omap_color_mode color_mode, bool *five_taps,
  76                 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
  77                 u16 pos_x, unsigned long *core_clk, bool mem_to_mem);
  78         unsigned long (*calc_core_clk) (unsigned long pclk,
  79                 u16 width, u16 height, u16 out_width, u16 out_height,
  80                 bool mem_to_mem);
  81         u8 num_fifos;
  82
  83         /* swap GFX & WB fifos */
  84         bool gfx_fifo_workaround:1;
  85
  86         /* no DISPC_IRQ_FRAMEDONETV on this SoC */
  87         bool no_framedone_tv:1;
  88 };
  89
  90 #define DISPC_MAX_NR_FIFOS 5
  91
  92 static struct {
  93         struct platform_device *pdev;
  94         void __iomem    *base;
  95
  96         int             ctx_loss_cnt;
  97
  98         int irq;
  99
 100         u32 fifo_size[DISPC_MAX_NR_FIFOS];
 101         /* maps which plane is using a fifo. fifo-id -> plane-id */
 102         int fifo_assignment[DISPC_MAX_NR_FIFOS];
 103
 104         bool            ctx_valid;
 105         u32             ctx[DISPC_SZ_REGS / sizeof(u32)];
 106
 107         const struct dispc_features *feat;
 108 } dispc;
 109
 110 enum omap_color_component {
 111         /* used for all color formats for OMAP3 and earlier
 112          * and for RGB and Y color component on OMAP4
 113          */
 114         DISPC_COLOR_COMPONENT_RGB_Y             = 1 << 0,
 115         /* used for UV component for
 116          * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
 117          * color formats on OMAP4
 118          */
 119         DISPC_COLOR_COMPONENT_UV                = 1 << 1,
 120 };
 121
 122 enum mgr_reg_fields {
 123         DISPC_MGR_FLD_ENABLE,
 124         DISPC_MGR_FLD_STNTFT,
 125         DISPC_MGR_FLD_GO,
 126         DISPC_MGR_FLD_TFTDATALINES,
 127         DISPC_MGR_FLD_STALLMODE,
 128         DISPC_MGR_FLD_TCKENABLE,
 129         DISPC_MGR_FLD_TCKSELECTION,
 130         DISPC_MGR_FLD_CPR,
 131         DISPC_MGR_FLD_FIFOHANDCHECK,
 132         /* used to maintain a count of the above fields */
 133         DISPC_MGR_FLD_NUM,
 134 };
 135
 136 static const struct {
 137         const char *name;
 138         u32 vsync_irq;
 139         u32 framedone_irq;
 140         u32 sync_lost_irq;
 141         struct reg_field reg_desc[DISPC_MGR_FLD_NUM];
 142 } mgr_desc[] = {
 143         [OMAP_DSS_CHANNEL_LCD] = {
 144                 .name           = "LCD",
 145                 .vsync_irq      = DISPC_IRQ_VSYNC,
 146                 .framedone_irq  = DISPC_IRQ_FRAMEDONE,
 147                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST,
 148                 .reg_desc       = {
 149                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL,  0,  0 },
 150                         [DISPC_MGR_FLD_STNTFT]          = { DISPC_CONTROL,  3,  3 },
 151                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL,  5,  5 },
 152                         [DISPC_MGR_FLD_TFTDATALINES]    = { DISPC_CONTROL,  9,  8 },
 153                         [DISPC_MGR_FLD_STALLMODE]       = { DISPC_CONTROL, 11, 11 },
 154                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG,  10, 10 },
 155                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG,  11, 11 },
 156                         [DISPC_MGR_FLD_CPR]             = { DISPC_CONFIG,  15, 15 },
 157                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG,  16, 16 },
 158                 },
 159         },
 160         [OMAP_DSS_CHANNEL_DIGIT] = {
 161                 .name           = "DIGIT",
 162                 .vsync_irq      = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
 163                 .framedone_irq  = DISPC_IRQ_FRAMEDONETV,
 164                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST_DIGIT,
 165                 .reg_desc       = {
 166                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL,  1,  1 },
 167                         [DISPC_MGR_FLD_STNTFT]          = { },
 168                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL,  6,  6 },
 169                         [DISPC_MGR_FLD_TFTDATALINES]    = { },
 170                         [DISPC_MGR_FLD_STALLMODE]       = { },
 171                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG,  12, 12 },
 172                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG,  13, 13 },
 173                         [DISPC_MGR_FLD_CPR]             = { },
 174                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG,  16, 16 },
 175                 },
 176         },
 177         [OMAP_DSS_CHANNEL_LCD2] = {
 178                 .name           = "LCD2",
 179                 .vsync_irq      = DISPC_IRQ_VSYNC2,
 180                 .framedone_irq  = DISPC_IRQ_FRAMEDONE2,
 181                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST2,
 182                 .reg_desc       = {
 183                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL2,  0,  0 },
 184                         [DISPC_MGR_FLD_STNTFT]          = { DISPC_CONTROL2,  3,  3 },
 185                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL2,  5,  5 },
 186                         [DISPC_MGR_FLD_TFTDATALINES]    = { DISPC_CONTROL2,  9,  8 },
 187                         [DISPC_MGR_FLD_STALLMODE]       = { DISPC_CONTROL2, 11, 11 },
 188                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG2,  10, 10 },
 189                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG2,  11, 11 },
 190                         [DISPC_MGR_FLD_CPR]             = { DISPC_CONFIG2,  15, 15 },
 191                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG2,  16, 16 },
 192                 },
 193         },
 194         [OMAP_DSS_CHANNEL_LCD3] = {
 195                 .name           = "LCD3",
 196                 .vsync_irq      = DISPC_IRQ_VSYNC3,
 197                 .framedone_irq  = DISPC_IRQ_FRAMEDONE3,
 198                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST3,
 199                 .reg_desc       = {
 200                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL3,  0,  0 },
 201                         [DISPC_MGR_FLD_STNTFT]          = { DISPC_CONTROL3,  3,  3 },
 202                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL3,  5,  5 },
 203                         [DISPC_MGR_FLD_TFTDATALINES]    = { DISPC_CONTROL3,  9,  8 },
 204                         [DISPC_MGR_FLD_STALLMODE]       = { DISPC_CONTROL3, 11, 11 },
 205                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG3,  10, 10 },
 206                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG3,  11, 11 },
 207                         [DISPC_MGR_FLD_CPR]             = { DISPC_CONFIG3,  15, 15 },
 208                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG3,  16, 16 },
 209                 },
 210         },
 211 };
 212
 213 struct color_conv_coef {
 214         int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
 215         int full_range;
 216 };
 217
 218 static unsigned long dispc_plane_pclk_rate(enum omap_plane plane);
 219 static unsigned long dispc_plane_lclk_rate(enum omap_plane plane);
 220
 221 static inline void dispc_write_reg(const u16 idx, u32 val)
 222 {
 223         __raw_writel(val, dispc.base + idx);
 224 }
 225
 226 static inline u32 dispc_read_reg(const u16 idx)
 227 {
 228         return __raw_readl(dispc.base + idx);
 229 }
 230
 231 static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)
 232 {
 233         const struct reg_field rfld = mgr_desc[channel].reg_desc[regfld];
 234         return REG_GET(rfld.reg, rfld.high, rfld.low);
 235 }
 236
 237 static void mgr_fld_write(enum omap_channel channel,
 238                                         enum mgr_reg_fields regfld, int val) {
 239         const struct reg_field rfld = mgr_desc[channel].reg_desc[regfld];
 240         REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
 241 }
 242
 243 #define SR(reg) \
 244         dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
 245 #define RR(reg) \
 246         dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
 247
 248 static void dispc_save_context(void)
 249 {
 250         int i, j;
 251
 252         DSSDBG("dispc_save_context\n");
 253
 254         SR(IRQENABLE);
 255         SR(CONTROL);
 256         SR(CONFIG);
 257         SR(LINE_NUMBER);
 258         if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
 259                         dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
 260                 SR(GLOBAL_ALPHA);
 261         if (dss_has_feature(FEAT_MGR_LCD2)) {
 262                 SR(CONTROL2);
 263                 SR(CONFIG2);
 264         }
 265         if (dss_has_feature(FEAT_MGR_LCD3)) {
 266                 SR(CONTROL3);
 267                 SR(CONFIG3);
 268         }
 269
 270         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
 271                 SR(DEFAULT_COLOR(i));
 272                 SR(TRANS_COLOR(i));
 273                 SR(SIZE_MGR(i));
 274                 if (i == OMAP_DSS_CHANNEL_DIGIT)
 275                         continue;
 276                 SR(TIMING_H(i));
 277                 SR(TIMING_V(i));
 278                 SR(POL_FREQ(i));
 279                 SR(DIVISORo(i));
 280
 281                 SR(DATA_CYCLE1(i));
 282                 SR(DATA_CYCLE2(i));
 283                 SR(DATA_CYCLE3(i));
 284
 285                 if (dss_has_feature(FEAT_CPR)) {
 286                         SR(CPR_COEF_R(i));
 287                         SR(CPR_COEF_G(i));
 288                         SR(CPR_COEF_B(i));
 289                 }
 290         }
 291
 292         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
 293                 SR(OVL_BA0(i));
 294                 SR(OVL_BA1(i));
 295                 SR(OVL_POSITION(i));
 296                 SR(OVL_SIZE(i));
 297                 SR(OVL_ATTRIBUTES(i));
 298                 SR(OVL_FIFO_THRESHOLD(i));
 299                 SR(OVL_ROW_INC(i));
 300                 SR(OVL_PIXEL_INC(i));
 301                 if (dss_has_feature(FEAT_PRELOAD))
 302                         SR(OVL_PRELOAD(i));
 303                 if (i == OMAP_DSS_GFX) {
 304                         SR(OVL_WINDOW_SKIP(i));
 305                         SR(OVL_TABLE_BA(i));
 306                         continue;
 307                 }
 308                 SR(OVL_FIR(i));
 309                 SR(OVL_PICTURE_SIZE(i));
 310                 SR(OVL_ACCU0(i));
 311                 SR(OVL_ACCU1(i));
 312
 313                 for (j = 0; j < 8; j++)
 314                         SR(OVL_FIR_COEF_H(i, j));
 315
 316                 for (j = 0; j < 8; j++)
 317                         SR(OVL_FIR_COEF_HV(i, j));
 318
 319                 for (j = 0; j < 5; j++)
 320                         SR(OVL_CONV_COEF(i, j));
 321
 322                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
 323                         for (j = 0; j < 8; j++)
 324                                 SR(OVL_FIR_COEF_V(i, j));
 325                 }
 326
 327                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
 328                         SR(OVL_BA0_UV(i));
 329                         SR(OVL_BA1_UV(i));
 330                         SR(OVL_FIR2(i));
 331                         SR(OVL_ACCU2_0(i));
 332                         SR(OVL_ACCU2_1(i));
 333
 334                         for (j = 0; j < 8; j++)
 335                                 SR(OVL_FIR_COEF_H2(i, j));
 336
 337                         for (j = 0; j < 8; j++)
 338                                 SR(OVL_FIR_COEF_HV2(i, j));
 339
 340                         for (j = 0; j < 8; j++)
 341                                 SR(OVL_FIR_COEF_V2(i, j));
 342                 }
 343                 if (dss_has_feature(FEAT_ATTR2))
 344                         SR(OVL_ATTRIBUTES2(i));
 345         }
 346
 347         if (dss_has_feature(FEAT_CORE_CLK_DIV))
 348                 SR(DIVISOR);
 349
 350         dispc.ctx_loss_cnt = dss_get_ctx_loss_count();
 351         dispc.ctx_valid = true;
 352
 353         DSSDBG("context saved, ctx_loss_count %d\n", dispc.ctx_loss_cnt);
 354 }
 355
 356 static void dispc_restore_context(void)
 357 {
 358         int i, j, ctx;
 359
 360         DSSDBG("dispc_restore_context\n");
 361
 362         if (!dispc.ctx_valid)
 363                 return;
 364
 365         ctx = dss_get_ctx_loss_count();
 366
 367         if (ctx >= 0 && ctx == dispc.ctx_loss_cnt)
 368                 return;
 369
 370         DSSDBG("ctx_loss_count: saved %d, current %d\n",
 371                         dispc.ctx_loss_cnt, ctx);
 372
 373         /*RR(IRQENABLE);*/
 374         /*RR(CONTROL);*/
 375         RR(CONFIG);
 376         RR(LINE_NUMBER);
 377         if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
 378                         dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
 379                 RR(GLOBAL_ALPHA);
 380         if (dss_has_feature(FEAT_MGR_LCD2))
 381                 RR(CONFIG2);
 382         if (dss_has_feature(FEAT_MGR_LCD3))
 383                 RR(CONFIG3);
 384
 385         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
 386                 RR(DEFAULT_COLOR(i));
 387                 RR(TRANS_COLOR(i));
 388                 RR(SIZE_MGR(i));
 389                 if (i == OMAP_DSS_CHANNEL_DIGIT)
 390                         continue;
 391                 RR(TIMING_H(i));
 392                 RR(TIMING_V(i));
 393                 RR(POL_FREQ(i));
 394                 RR(DIVISORo(i));
 395
 396                 RR(DATA_CYCLE1(i));
 397                 RR(DATA_CYCLE2(i));
 398                 RR(DATA_CYCLE3(i));
 399
 400                 if (dss_has_feature(FEAT_CPR)) {
 401                         RR(CPR_COEF_R(i));
 402                         RR(CPR_COEF_G(i));
 403                         RR(CPR_COEF_B(i));
 404                 }
 405         }
 406
 407         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
 408                 RR(OVL_BA0(i));
 409                 RR(OVL_BA1(i));
 410                 RR(OVL_POSITION(i));
 411                 RR(OVL_SIZE(i));
 412                 RR(OVL_ATTRIBUTES(i));
 413                 RR(OVL_FIFO_THRESHOLD(i));
 414                 RR(OVL_ROW_INC(i));
 415                 RR(OVL_PIXEL_INC(i));
 416                 if (dss_has_feature(FEAT_PRELOAD))
 417                         RR(OVL_PRELOAD(i));
 418                 if (i == OMAP_DSS_GFX) {
 419                         RR(OVL_WINDOW_SKIP(i));
 420                         RR(OVL_TABLE_BA(i));
 421                         continue;
 422                 }
 423                 RR(OVL_FIR(i));
 424                 RR(OVL_PICTURE_SIZE(i));
 425                 RR(OVL_ACCU0(i));
 426                 RR(OVL_ACCU1(i));
 427
 428                 for (j = 0; j < 8; j++)
 429                         RR(OVL_FIR_COEF_H(i, j));
 430
 431                 for (j = 0; j < 8; j++)
 432                         RR(OVL_FIR_COEF_HV(i, j));
 433
 434                 for (j = 0; j < 5; j++)
 435                         RR(OVL_CONV_COEF(i, j));
 436
 437                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
 438                         for (j = 0; j < 8; j++)
 439                                 RR(OVL_FIR_COEF_V(i, j));
 440                 }
 441
 442                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
 443                         RR(OVL_BA0_UV(i));
 444                         RR(OVL_BA1_UV(i));
 445                         RR(OVL_FIR2(i));
 446                         RR(OVL_ACCU2_0(i));
 447                         RR(OVL_ACCU2_1(i));
 448
 449                         for (j = 0; j < 8; j++)
 450                                 RR(OVL_FIR_COEF_H2(i, j));
 451
 452                         for (j = 0; j < 8; j++)
 453                                 RR(OVL_FIR_COEF_HV2(i, j));
 454
 455                         for (j = 0; j < 8; j++)
 456                                 RR(OVL_FIR_COEF_V2(i, j));
 457                 }
 458                 if (dss_has_feature(FEAT_ATTR2))
 459                         RR(OVL_ATTRIBUTES2(i));
 460         }
 461
 462         if (dss_has_feature(FEAT_CORE_CLK_DIV))
 463                 RR(DIVISOR);
 464
 465         /* enable last, because LCD & DIGIT enable are here */
 466         RR(CONTROL);
 467         if (dss_has_feature(FEAT_MGR_LCD2))
 468                 RR(CONTROL2);
 469         if (dss_has_feature(FEAT_MGR_LCD3))
 470                 RR(CONTROL3);
 471         /* clear spurious SYNC_LOST_DIGIT interrupts */
 472         dispc_clear_irqstatus(DISPC_IRQ_SYNC_LOST_DIGIT);
 473
 474         /*
 475          * enable last so IRQs won't trigger before
 476          * the context is fully restored
 477          */
 478         RR(IRQENABLE);
 479
 480         DSSDBG("context restored\n");
 481 }
 482
 483 #undef SR
 484 #undef RR
 485
 486 int dispc_runtime_get(void)
 487 {
 488         int r;
 489
 490         DSSDBG("dispc_runtime_get\n");
 491
 492         r = pm_runtime_get_sync(&dispc.pdev->dev);
 493         WARN_ON(r < 0);
 494         return r < 0 ? r : 0;
 495 }
 496 EXPORT_SYMBOL(dispc_runtime_get);
 497
 498 void dispc_runtime_put(void)
 499 {
 500         int r;
 501
 502         DSSDBG("dispc_runtime_put\n");
 503
 504         r = pm_runtime_put_sync(&dispc.pdev->dev);
 505         WARN_ON(r < 0 && r != -ENOSYS);
 506 }
 507 EXPORT_SYMBOL(dispc_runtime_put);
 508
 509 u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
 510 {
 511         return mgr_desc[channel].vsync_irq;
 512 }
 513 EXPORT_SYMBOL(dispc_mgr_get_vsync_irq);
 514
 515 u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
 516 {
 517         if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv)
 518                 return 0;
 519
 520         return mgr_desc[channel].framedone_irq;
 521 }
 522 EXPORT_SYMBOL(dispc_mgr_get_framedone_irq);
 523
 524 u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel)
 525 {
 526         return mgr_desc[channel].sync_lost_irq;
 527 }
 528 EXPORT_SYMBOL(dispc_mgr_get_sync_lost_irq);
 529
 530 u32 dispc_wb_get_framedone_irq(void)
 531 {
 532         return DISPC_IRQ_FRAMEDONEWB;
 533 }
 534
 535 bool dispc_mgr_go_busy(enum omap_channel channel)
 536 {
 537         return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
 538 }
 539 EXPORT_SYMBOL(dispc_mgr_go_busy);
 540
 541 void dispc_mgr_go(enum omap_channel channel)
 542 {
 543         WARN_ON(dispc_mgr_is_enabled(channel) == false);
 544         WARN_ON(dispc_mgr_go_busy(channel));
 545
 546         DSSDBG("GO %s\n", mgr_desc[channel].name);
 547
 548         mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
 549 }
 550 EXPORT_SYMBOL(dispc_mgr_go);
 551
 552 bool dispc_wb_go_busy(void)
 553 {
 554         return REG_GET(DISPC_CONTROL2, 6, 6) == 1;
 555 }
 556
 557 void dispc_wb_go(void)
 558 {
 559         enum omap_plane plane = OMAP_DSS_WB;
 560         bool enable, go;
 561
 562         enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1;
 563
 564         if (!enable)
 565                 return;
 566
 567         go = REG_GET(DISPC_CONTROL2, 6, 6) == 1;
 568         if (go) {
 569                 DSSERR("GO bit not down for WB\n");
 570                 return;
 571         }
 572
 573         REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6);
 574 }
 575
 576 static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
 577 {
 578         dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
 579 }
 580
 581 static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
 582 {
 583         dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
 584 }
 585
 586 static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
 587 {
 588         dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
 589 }
 590
 591 static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
 592 {
 593         BUG_ON(plane == OMAP_DSS_GFX);
 594
 595         dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
 596 }
 597
 598 static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
 599                 u32 value)
 600 {
 601         BUG_ON(plane == OMAP_DSS_GFX);
 602
 603         dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
 604 }
 605
 606 static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
 607 {
 608         BUG_ON(plane == OMAP_DSS_GFX);
 609
 610         dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
 611 }
 612
 613 static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
 614                                 int fir_vinc, int five_taps,
 615                                 enum omap_color_component color_comp)
 616 {
 617         const struct dispc_coef *h_coef, *v_coef;
 618         int i;
 619
 620         h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
 621         v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
 622
 623         for (i = 0; i < 8; i++) {
 624                 u32 h, hv;
 625
 626                 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
 627                         | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
 628                         | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
 629                         | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
 630                 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
 631                         | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
 632                         | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
 633                         | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
 634
 635                 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
 636                         dispc_ovl_write_firh_reg(plane, i, h);
 637                         dispc_ovl_write_firhv_reg(plane, i, hv);
 638                 } else {
 639                         dispc_ovl_write_firh2_reg(plane, i, h);
 640                         dispc_ovl_write_firhv2_reg(plane, i, hv);
 641                 }
 642
 643         }
 644
 645         if (five_taps) {
 646                 for (i = 0; i < 8; i++) {
 647                         u32 v;
 648                         v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
 649                                 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
 650                         if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
 651                                 dispc_ovl_write_firv_reg(plane, i, v);
 652                         else
 653                                 dispc_ovl_write_firv2_reg(plane, i, v);
 654                 }
 655         }
 656 }
 657
 658
 659 static void dispc_ovl_write_color_conv_coef(enum omap_plane plane,
 660                 const struct color_conv_coef *ct)
 661 {
 662 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
 663
 664         dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry));
 665         dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy,  ct->rcb));
 666         dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr));
 667         dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by));
 668         dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb));
 669
 670         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);
 671
 672 #undef CVAL
 673 }
 674
 675 static void dispc_setup_color_conv_coef(void)
 676 {
 677         int i;
 678         int num_ovl = dss_feat_get_num_ovls();
 679         int num_wb = dss_feat_get_num_wbs();
 680         const struct color_conv_coef ctbl_bt601_5_ovl = {
 681                 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
 682         };
 683         const struct color_conv_coef ctbl_bt601_5_wb = {
 684                 66, 112, -38, 129, -94, -74, 25, -18, 112, 0,
 685         };
 686
 687         for (i = 1; i < num_ovl; i++)
 688                 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_ovl);
 689
 690         for (; i < num_wb; i++)
 691                 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_wb);
 692 }
 693
 694 static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
 695 {
 696         dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
 697 }
 698
 699 static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
 700 {
 701         dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
 702 }
 703
 704 static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
 705 {
 706         dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
 707 }
 708
 709 static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
 710 {
 711         dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
 712 }
 713
 714 static void dispc_ovl_set_pos(enum omap_plane plane,
 715                 enum omap_overlay_caps caps, int x, int y)
 716 {
 717         u32 val;
 718
 719         if ((caps & OMAP_DSS_OVL_CAP_POS) == 0)
 720                 return;
 721
 722         val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
 723
 724         dispc_write_reg(DISPC_OVL_POSITION(plane), val);
 725 }
 726
 727 static void dispc_ovl_set_input_size(enum omap_plane plane, int width,
 728                 int height)
 729 {
 730         u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 731
 732         if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB)
 733                 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
 734         else
 735                 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
 736 }
 737
 738 static void dispc_ovl_set_output_size(enum omap_plane plane, int width,
 739                 int height)
 740 {
 741         u32 val;
 742
 743         BUG_ON(plane == OMAP_DSS_GFX);
 744
 745         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 746
 747         if (plane == OMAP_DSS_WB)
 748                 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
 749         else
 750                 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
 751 }
 752
 753 static void dispc_ovl_set_zorder(enum omap_plane plane,
 754                 enum omap_overlay_caps caps, u8 zorder)
 755 {
 756         if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
 757                 return;
 758
 759         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
 760 }
 761
 762 static void dispc_ovl_enable_zorder_planes(void)
 763 {
 764         int i;
 765
 766         if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
 767                 return;
 768
 769         for (i = 0; i < dss_feat_get_num_ovls(); i++)
 770                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
 771 }
 772
 773 static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane,
 774                 enum omap_overlay_caps caps, bool enable)
 775 {
 776         if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
 777                 return;
 778
 779         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
 780 }
 781
 782 static void dispc_ovl_setup_global_alpha(enum omap_plane plane,
 783                 enum omap_overlay_caps caps, u8 global_alpha)
 784 {
 785         static const unsigned shifts[] = { 0, 8, 16, 24, };
 786         int shift;
 787
 788         if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
 789                 return;
 790
 791         shift = shifts[plane];
 792         REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
 793 }
 794
 795 static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
 796 {
 797         dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
 798 }
 799
 800 static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
 801 {
 802         dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
 803 }
 804
 805 static void dispc_ovl_set_color_mode(enum omap_plane plane,
 806                 enum omap_color_mode color_mode)
 807 {
 808         u32 m = 0;
 809         if (plane != OMAP_DSS_GFX) {
 810                 switch (color_mode) {
 811                 case OMAP_DSS_COLOR_NV12:
 812                         m = 0x0; break;
 813                 case OMAP_DSS_COLOR_RGBX16:
 814                         m = 0x1; break;
 815                 case OMAP_DSS_COLOR_RGBA16:
 816                         m = 0x2; break;
 817                 case OMAP_DSS_COLOR_RGB12U:
 818                         m = 0x4; break;
 819                 case OMAP_DSS_COLOR_ARGB16:
 820                         m = 0x5; break;
 821                 case OMAP_DSS_COLOR_RGB16:
 822                         m = 0x6; break;
 823                 case OMAP_DSS_COLOR_ARGB16_1555:
 824                         m = 0x7; break;
 825                 case OMAP_DSS_COLOR_RGB24U:
 826                         m = 0x8; break;
 827                 case OMAP_DSS_COLOR_RGB24P:
 828                         m = 0x9; break;
 829                 case OMAP_DSS_COLOR_YUV2:
 830                         m = 0xa; break;
 831                 case OMAP_DSS_COLOR_UYVY:
 832                         m = 0xb; break;
 833                 case OMAP_DSS_COLOR_ARGB32:
 834                         m = 0xc; break;
 835                 case OMAP_DSS_COLOR_RGBA32:
 836                         m = 0xd; break;
 837                 case OMAP_DSS_COLOR_RGBX32:
 838                         m = 0xe; break;
 839                 case OMAP_DSS_COLOR_XRGB16_1555:
 840                         m = 0xf; break;
 841                 default:
 842                         BUG(); return;
 843                 }
 844         } else {
 845                 switch (color_mode) {
 846                 case OMAP_DSS_COLOR_CLUT1:
 847                         m = 0x0; break;
 848                 case OMAP_DSS_COLOR_CLUT2:
 849                         m = 0x1; break;
 850                 case OMAP_DSS_COLOR_CLUT4:
 851                         m = 0x2; break;
 852                 case OMAP_DSS_COLOR_CLUT8:
 853                         m = 0x3; break;
 854                 case OMAP_DSS_COLOR_RGB12U:
 855                         m = 0x4; break;
 856                 case OMAP_DSS_COLOR_ARGB16:
 857                         m = 0x5; break;
 858                 case OMAP_DSS_COLOR_RGB16:
 859                         m = 0x6; break;
 860                 case OMAP_DSS_COLOR_ARGB16_1555:
 861                         m = 0x7; break;
 862                 case OMAP_DSS_COLOR_RGB24U:
 863                         m = 0x8; break;
 864                 case OMAP_DSS_COLOR_RGB24P:
 865                         m = 0x9; break;
 866                 case OMAP_DSS_COLOR_RGBX16:
 867                         m = 0xa; break;
 868                 case OMAP_DSS_COLOR_RGBA16:
 869                         m = 0xb; break;
 870                 case OMAP_DSS_COLOR_ARGB32:
 871                         m = 0xc; break;
 872                 case OMAP_DSS_COLOR_RGBA32:
 873                         m = 0xd; break;
 874                 case OMAP_DSS_COLOR_RGBX32:
 875                         m = 0xe; break;
 876                 case OMAP_DSS_COLOR_XRGB16_1555:
 877                         m = 0xf; break;
 878                 default:
 879                         BUG(); return;
 880                 }
 881         }
 882
 883         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
 884 }
 885
 886 static void dispc_ovl_configure_burst_type(enum omap_plane plane,
 887                 enum omap_dss_rotation_type rotation_type)
 888 {
 889         if (dss_has_feature(FEAT_BURST_2D) == 0)
 890                 return;
 891
 892         if (rotation_type == OMAP_DSS_ROT_TILER)
 893                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
 894         else
 895                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
 896 }
 897
 898 void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
 899 {
 900         int shift;
 901         u32 val;
 902         int chan = 0, chan2 = 0;
 903
 904         switch (plane) {
 905         case OMAP_DSS_GFX:
 906                 shift = 8;
 907                 break;
 908         case OMAP_DSS_VIDEO1:
 909         case OMAP_DSS_VIDEO2:
 910         case OMAP_DSS_VIDEO3:
 911                 shift = 16;
 912                 break;
 913         default:
 914                 BUG();
 915                 return;
 916         }
 917
 918         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
 919         if (dss_has_feature(FEAT_MGR_LCD2)) {
 920                 switch (channel) {
 921                 case OMAP_DSS_CHANNEL_LCD:
 922                         chan = 0;
 923                         chan2 = 0;
 924                         break;
 925                 case OMAP_DSS_CHANNEL_DIGIT:
 926                         chan = 1;
 927                         chan2 = 0;
 928                         break;
 929                 case OMAP_DSS_CHANNEL_LCD2:
 930                         chan = 0;
 931                         chan2 = 1;
 932                         break;
 933                 case OMAP_DSS_CHANNEL_LCD3:
 934                         if (dss_has_feature(FEAT_MGR_LCD3)) {
 935                                 chan = 0;
 936                                 chan2 = 2;
 937                         } else {
 938                                 BUG();
 939                                 return;
 940                         }
 941                         break;
 942                 default:
 943                         BUG();
 944                         return;
 945                 }
 946
 947                 val = FLD_MOD(val, chan, shift, shift);
 948                 val = FLD_MOD(val, chan2, 31, 30);
 949         } else {
 950                 val = FLD_MOD(val, channel, shift, shift);
 951         }
 952         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
 953 }
 954 EXPORT_SYMBOL(dispc_ovl_set_channel_out);
 955
 956 static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
 957 {
 958         int shift;
 959         u32 val;
 960         enum omap_channel channel;
 961
 962         switch (plane) {
 963         case OMAP_DSS_GFX:
 964                 shift = 8;
 965                 break;
 966         case OMAP_DSS_VIDEO1:
 967         case OMAP_DSS_VIDEO2:
 968         case OMAP_DSS_VIDEO3:
 969                 shift = 16;
 970                 break;
 971         default:
 972                 BUG();
 973                 return 0;
 974         }
 975
 976         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
 977
 978         if (dss_has_feature(FEAT_MGR_LCD3)) {
 979                 if (FLD_GET(val, 31, 30) == 0)
 980                         channel = FLD_GET(val, shift, shift);
 981                 else if (FLD_GET(val, 31, 30) == 1)
 982                         channel = OMAP_DSS_CHANNEL_LCD2;
 983                 else
 984                         channel = OMAP_DSS_CHANNEL_LCD3;
 985         } else if (dss_has_feature(FEAT_MGR_LCD2)) {
 986                 if (FLD_GET(val, 31, 30) == 0)
 987                         channel = FLD_GET(val, shift, shift);
 988                 else
 989                         channel = OMAP_DSS_CHANNEL_LCD2;
 990         } else {
 991                 channel = FLD_GET(val, shift, shift);
 992         }
 993
 994         return channel;
 995 }
 996
 997 void dispc_wb_set_channel_in(enum dss_writeback_channel channel)
 998 {
 999         enum omap_plane plane = OMAP_DSS_WB;
1000
1001         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), channel, 18, 16);
1002 }
1003
1004 static void dispc_ovl_set_burst_size(enum omap_plane plane,
1005                 enum omap_burst_size burst_size)
1006 {
1007         static const unsigned shifts[] = { 6, 14, 14, 14, 14, };
1008         int shift;
1009
1010         shift = shifts[plane];
1011         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
1012 }
1013
1014 static void dispc_configure_burst_sizes(void)
1015 {
1016         int i;
1017         const int burst_size = BURST_SIZE_X8;
1018
1019         /* Configure burst size always to maximum size */
1020         for (i = 0; i < dss_feat_get_num_ovls(); ++i)
1021                 dispc_ovl_set_burst_size(i, burst_size);
1022 }
1023
1024 static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
1025 {
1026         unsigned unit = dss_feat_get_burst_size_unit();
1027         /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
1028         return unit * 8;
1029 }
1030
1031 void dispc_enable_gamma_table(bool enable)
1032 {
1033         /*
1034          * This is partially implemented to support only disabling of
1035          * the gamma table.
1036          */
1037         if (enable) {
1038                 DSSWARN("Gamma table enabling for TV not yet supported");
1039                 return;
1040         }
1041
1042         REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
1043 }
1044
1045 static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
1046 {
1047         if (channel == OMAP_DSS_CHANNEL_DIGIT)
1048                 return;
1049
1050         mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);
1051 }
1052
1053 static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
1054                 const struct omap_dss_cpr_coefs *coefs)
1055 {
1056         u32 coef_r, coef_g, coef_b;
1057
1058         if (!dss_mgr_is_lcd(channel))
1059                 return;
1060
1061         coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1062                 FLD_VAL(coefs->rb, 9, 0);
1063         coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1064                 FLD_VAL(coefs->gb, 9, 0);
1065         coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1066                 FLD_VAL(coefs->bb, 9, 0);
1067
1068         dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1069         dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1070         dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1071 }
1072
1073 static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
1074 {
1075         u32 val;
1076
1077         BUG_ON(plane == OMAP_DSS_GFX);
1078
1079         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1080         val = FLD_MOD(val, enable, 9, 9);
1081         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
1082 }
1083
1084 static void dispc_ovl_enable_replication(enum omap_plane plane,
1085                 enum omap_overlay_caps caps, bool enable)
1086 {
1087         static const unsigned shifts[] = { 5, 10, 10, 10 };
1088         int shift;
1089
1090         if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0)
1091                 return;
1092
1093         shift = shifts[plane];
1094         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
1095 }
1096
1097 static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
1098                 u16 height)
1099 {
1100         u32 val;
1101
1102         val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) |
1103                 FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0);
1104
1105         dispc_write_reg(DISPC_SIZE_MGR(channel), val);
1106 }
1107
1108 static void dispc_init_fifos(void)
1109 {
1110         u32 size;
1111         int fifo;
1112         u8 start, end;
1113         u32 unit;
1114
1115         unit = dss_feat_get_buffer_size_unit();
1116
1117         dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
1118
1119         for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1120                 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end);
1121                 size *= unit;
1122                 dispc.fifo_size[fifo] = size;
1123
1124                 /*
1125                  * By default fifos are mapped directly to overlays, fifo 0 to
1126                  * ovl 0, fifo 1 to ovl 1, etc.
1127                  */
1128                 dispc.fifo_assignment[fifo] = fifo;
1129         }
1130
1131         /*
1132          * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo
1133          * causes problems with certain use cases, like using the tiler in 2D
1134          * mode. The below hack swaps the fifos of GFX and WB planes, thus
1135          * giving GFX plane a larger fifo. WB but should work fine with a
1136          * smaller fifo.
1137          */
1138         if (dispc.feat->gfx_fifo_workaround) {
1139                 u32 v;
1140
1141                 v = dispc_read_reg(DISPC_GLOBAL_BUFFER);
1142
1143                 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */
1144                 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */
1145                 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */
1146                 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */
1147
1148                 dispc_write_reg(DISPC_GLOBAL_BUFFER, v);
1149
1150                 dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB;
1151                 dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX;
1152         }
1153 }
1154
1155 static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
1156 {
1157         int fifo;
1158         u32 size = 0;
1159
1160         for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1161                 if (dispc.fifo_assignment[fifo] == plane)
1162                         size += dispc.fifo_size[fifo];
1163         }
1164
1165         return size;
1166 }
1167
1168 void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
1169 {
1170         u8 hi_start, hi_end, lo_start, lo_end;
1171         u32 unit;
1172
1173         unit = dss_feat_get_buffer_size_unit();
1174
1175         WARN_ON(low % unit != 0);
1176         WARN_ON(high % unit != 0);
1177
1178         low /= unit;
1179         high /= unit;
1180
1181         dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1182         dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1183
1184         DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
1185                         plane,
1186                         REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1187                                 lo_start, lo_end) * unit,
1188                         REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1189                                 hi_start, hi_end) * unit,
1190                         low * unit, high * unit);
1191
1192         dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
1193                         FLD_VAL(high, hi_start, hi_end) |
1194                         FLD_VAL(low, lo_start, lo_end));
1195 }
1196
1197 void dispc_enable_fifomerge(bool enable)
1198 {
1199         if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1200                 WARN_ON(enable);
1201                 return;
1202         }
1203
1204         DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1205         REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1206 }
1207
1208 void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
1209                 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
1210                 bool manual_update)
1211 {
1212         /*
1213          * All sizes are in bytes. Both the buffer and burst are made of
1214          * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1215          */
1216
1217         unsigned buf_unit = dss_feat_get_buffer_size_unit();
1218         unsigned ovl_fifo_size, total_fifo_size, burst_size;
1219         int i;
1220
1221         burst_size = dispc_ovl_get_burst_size(plane);
1222         ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
1223
1224         if (use_fifomerge) {
1225                 total_fifo_size = 0;
1226                 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
1227                         total_fifo_size += dispc_ovl_get_fifo_size(i);
1228         } else {
1229                 total_fifo_size = ovl_fifo_size;
1230         }
1231
1232         /*
1233          * We use the same low threshold for both fifomerge and non-fifomerge
1234          * cases, but for fifomerge we calculate the high threshold using the
1235          * combined fifo size
1236          */
1237
1238         if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
1239                 *fifo_low = ovl_fifo_size - burst_size * 2;
1240                 *fifo_high = total_fifo_size - burst_size;
1241         } else if (plane == OMAP_DSS_WB) {
1242                 /*
1243                  * Most optimal configuration for writeback is to push out data
1244                  * to the interconnect the moment writeback pushes enough pixels
1245                  * in the FIFO to form a burst
1246                  */
1247                 *fifo_low = 0;
1248                 *fifo_high = burst_size;
1249         } else {
1250                 *fifo_low = ovl_fifo_size - burst_size;
1251                 *fifo_high = total_fifo_size - buf_unit;
1252         }
1253 }
1254
1255 static void dispc_ovl_set_fir(enum omap_plane plane,
1256                                 int hinc, int vinc,
1257                                 enum omap_color_component color_comp)
1258 {
1259         u32 val;
1260
1261         if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1262                 u8 hinc_start, hinc_end, vinc_start, vinc_end;
1263
1264                 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1265                                         &hinc_start, &hinc_end);
1266                 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1267                                         &vinc_start, &vinc_end);
1268                 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1269                                 FLD_VAL(hinc, hinc_start, hinc_end);
1270
1271                 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1272         } else {
1273                 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1274                 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1275         }
1276 }
1277
1278 static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1279 {
1280         u32 val;
1281         u8 hor_start, hor_end, vert_start, vert_end;
1282
1283         dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1284         dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1285
1286         val = FLD_VAL(vaccu, vert_start, vert_end) |
1287                         FLD_VAL(haccu, hor_start, hor_end);
1288
1289         dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
1290 }
1291
1292 static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1293 {
1294         u32 val;
1295         u8 hor_start, hor_end, vert_start, vert_end;
1296
1297         dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1298         dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1299
1300         val = FLD_VAL(vaccu, vert_start, vert_end) |
1301                         FLD_VAL(haccu, hor_start, hor_end);
1302
1303         dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
1304 }
1305
1306 static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1307                 int vaccu)
1308 {
1309         u32 val;
1310
1311         val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1312         dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1313 }
1314
1315 static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1316                 int vaccu)
1317 {
1318         u32 val;
1319
1320         val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1321         dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1322 }
1323
1324 static void dispc_ovl_set_scale_param(enum omap_plane plane,
1325                 u16 orig_width, u16 orig_height,
1326                 u16 out_width, u16 out_height,
1327                 bool five_taps, u8 rotation,
1328                 enum omap_color_component color_comp)
1329 {
1330         int fir_hinc, fir_vinc;
1331
1332         fir_hinc = 1024 * orig_width / out_width;
1333         fir_vinc = 1024 * orig_height / out_height;
1334
1335         dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1336                                 color_comp);
1337         dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
1338 }
1339
1340 static void dispc_ovl_set_accu_uv(enum omap_plane plane,
1341                 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
1342                 bool ilace, enum omap_color_mode color_mode, u8 rotation)
1343 {
1344         int h_accu2_0, h_accu2_1;
1345         int v_accu2_0, v_accu2_1;
1346         int chroma_hinc, chroma_vinc;
1347         int idx;
1348
1349         struct accu {
1350                 s8 h0_m, h0_n;
1351                 s8 h1_m, h1_n;
1352                 s8 v0_m, v0_n;
1353                 s8 v1_m, v1_n;
1354         };
1355
1356         const struct accu *accu_table;
1357         const struct accu *accu_val;
1358
1359         static const struct accu accu_nv12[4] = {
1360                 {  0, 1,  0, 1 , -1, 2, 0, 1 },
1361                 {  1, 2, -3, 4 ,  0, 1, 0, 1 },
1362                 { -1, 1,  0, 1 , -1, 2, 0, 1 },
1363                 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1364         };
1365
1366         static const struct accu accu_nv12_ilace[4] = {
1367                 {  0, 1,  0, 1 , -3, 4, -1, 4 },
1368                 { -1, 4, -3, 4 ,  0, 1,  0, 1 },
1369                 { -1, 1,  0, 1 , -1, 4, -3, 4 },
1370                 { -3, 4, -3, 4 , -1, 1,  0, 1 },
1371         };
1372
1373         static const struct accu accu_yuv[4] = {
1374                 {  0, 1, 0, 1,  0, 1, 0, 1 },
1375                 {  0, 1, 0, 1,  0, 1, 0, 1 },
1376                 { -1, 1, 0, 1,  0, 1, 0, 1 },
1377                 {  0, 1, 0, 1, -1, 1, 0, 1 },
1378         };
1379
1380         switch (rotation) {
1381         case OMAP_DSS_ROT_0:
1382                 idx = 0;
1383                 break;
1384         case OMAP_DSS_ROT_90:
1385                 idx = 1;
1386                 break;
1387         case OMAP_DSS_ROT_180:
1388                 idx = 2;
1389                 break;
1390         case OMAP_DSS_ROT_270:
1391                 idx = 3;
1392                 break;
1393         default:
1394                 BUG();
1395                 return;
1396         }
1397
1398         switch (color_mode) {
1399         case OMAP_DSS_COLOR_NV12:
1400                 if (ilace)
1401                         accu_table = accu_nv12_ilace;
1402                 else
1403                         accu_table = accu_nv12;
1404                 break;
1405         case OMAP_DSS_COLOR_YUV2:
1406         case OMAP_DSS_COLOR_UYVY:
1407                 accu_table = accu_yuv;
1408                 break;
1409         default:
1410                 BUG();
1411                 return;
1412         }
1413
1414         accu_val = &accu_table[idx];
1415
1416         chroma_hinc = 1024 * orig_width / out_width;
1417         chroma_vinc = 1024 * orig_height / out_height;
1418
1419         h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1420         h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1421         v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1422         v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1423
1424         dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
1425         dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
1426 }
1427
1428 static void dispc_ovl_set_scaling_common(enum omap_plane plane,
1429                 u16 orig_width, u16 orig_height,
1430                 u16 out_width, u16 out_height,
1431                 bool ilace, bool five_taps,
1432                 bool fieldmode, enum omap_color_mode color_mode,
1433                 u8 rotation)
1434 {
1435         int accu0 = 0;
1436         int accu1 = 0;
1437         u32 l;
1438
1439         dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1440                                 out_width, out_height, five_taps,
1441                                 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
1442         l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1443
1444         /* RESIZEENABLE and VERTICALTAPS */
1445         l &= ~((0x3 << 5) | (0x1 << 21));
1446         l |= (orig_width != out_width) ? (1 << 5) : 0;
1447         l |= (orig_height != out_height) ? (1 << 6) : 0;
1448         l |= five_taps ? (1 << 21) : 0;
1449
1450         /* VRESIZECONF and HRESIZECONF */
1451         if (dss_has_feature(FEAT_RESIZECONF)) {
1452                 l &= ~(0x3 << 7);
1453                 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1454                 l |= (orig_height <= out_height) ? 0 : (1 << 8);
1455         }
1456
1457         /* LINEBUFFERSPLIT */
1458         if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1459                 l &= ~(0x1 << 22);
1460                 l |= five_taps ? (1 << 22) : 0;
1461         }
1462
1463         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
1464
1465         /*
1466          * field 0 = even field = bottom field
1467          * field 1 = odd field = top field
1468          */
1469         if (ilace && !fieldmode) {
1470                 accu1 = 0;
1471                 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
1472                 if (accu0 >= 1024/2) {
1473                         accu1 = 1024/2;
1474                         accu0 -= accu1;
1475                 }
1476         }
1477
1478         dispc_ovl_set_vid_accu0(plane, 0, accu0);
1479         dispc_ovl_set_vid_accu1(plane, 0, accu1);
1480 }
1481
1482 static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
1483                 u16 orig_width, u16 orig_height,
1484                 u16 out_width, u16 out_height,
1485                 bool ilace, bool five_taps,
1486                 bool fieldmode, enum omap_color_mode color_mode,
1487                 u8 rotation)
1488 {
1489         int scale_x = out_width != orig_width;
1490         int scale_y = out_height != orig_height;
1491         bool chroma_upscale = plane != OMAP_DSS_WB ? true : false;
1492
1493         if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1494                 return;
1495         if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1496                         color_mode != OMAP_DSS_COLOR_UYVY &&
1497                         color_mode != OMAP_DSS_COLOR_NV12)) {
1498                 /* reset chroma resampling for RGB formats  */
1499                 if (plane != OMAP_DSS_WB)
1500                         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1501                 return;
1502         }
1503
1504         dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
1505                         out_height, ilace, color_mode, rotation);
1506
1507         switch (color_mode) {
1508         case OMAP_DSS_COLOR_NV12:
1509                 if (chroma_upscale) {
1510                         /* UV is subsampled by 2 horizontally and vertically */
1511                         orig_height >>= 1;
1512                         orig_width >>= 1;
1513                 } else {
1514                         /* UV is downsampled by 2 horizontally and vertically */
1515                         orig_height <<= 1;
1516                         orig_width <<= 1;
1517                 }
1518
1519                 break;
1520         case OMAP_DSS_COLOR_YUV2:
1521         case OMAP_DSS_COLOR_UYVY:
1522                 /* For YUV422 with 90/270 rotation, we don't upsample chroma */
1523                 if (rotation == OMAP_DSS_ROT_0 ||
1524                                 rotation == OMAP_DSS_ROT_180) {
1525                         if (chroma_upscale)
1526                                 /* UV is subsampled by 2 horizontally */
1527                                 orig_width >>= 1;
1528                         else
1529                                 /* UV is downsampled by 2 horizontally */
1530                                 orig_width <<= 1;
1531                 }
1532
1533                 /* must use FIR for YUV422 if rotated */
1534                 if (rotation != OMAP_DSS_ROT_0)
1535                         scale_x = scale_y = true;
1536
1537                 break;
1538         default:
1539                 BUG();
1540                 return;
1541         }
1542
1543         if (out_width != orig_width)
1544                 scale_x = true;
1545         if (out_height != orig_height)
1546                 scale_y = true;
1547
1548         dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1549                         out_width, out_height, five_taps,
1550                                 rotation, DISPC_COLOR_COMPONENT_UV);
1551
1552         if (plane != OMAP_DSS_WB)
1553                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1554                         (scale_x || scale_y) ? 1 : 0, 8, 8);
1555
1556         /* set H scaling */
1557         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1558         /* set V scaling */
1559         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1560 }
1561
1562 static void dispc_ovl_set_scaling(enum omap_plane plane,
1563                 u16 orig_width, u16 orig_height,
1564                 u16 out_width, u16 out_height,
1565                 bool ilace, bool five_taps,
1566                 bool fieldmode, enum omap_color_mode color_mode,
1567                 u8 rotation)
1568 {
1569         BUG_ON(plane == OMAP_DSS_GFX);
1570
1571         dispc_ovl_set_scaling_common(plane,
1572                         orig_width, orig_height,
1573                         out_width, out_height,
1574                         ilace, five_taps,
1575                         fieldmode, color_mode,
1576                         rotation);
1577
1578         dispc_ovl_set_scaling_uv(plane,
1579                 orig_width, orig_height,
1580                 out_width, out_height,
1581                 ilace, five_taps,
1582                 fieldmode, color_mode,
1583                 rotation);
1584 }
1585
1586 static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1587                 bool mirroring, enum omap_color_mode color_mode)
1588 {
1589         bool row_repeat = false;
1590         int vidrot = 0;
1591
1592         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1593                         color_mode == OMAP_DSS_COLOR_UYVY) {
1594
1595                 if (mirroring) {
1596                         switch (rotation) {
1597                         case OMAP_DSS_ROT_0:
1598                                 vidrot = 2;
1599                                 break;
1600                         case OMAP_DSS_ROT_90:
1601                                 vidrot = 1;
1602                                 break;
1603                         case OMAP_DSS_ROT_180:
1604                                 vidrot = 0;
1605                                 break;
1606                         case OMAP_DSS_ROT_270:
1607                                 vidrot = 3;
1608                                 break;
1609                         }
1610                 } else {
1611                         switch (rotation) {
1612                         case OMAP_DSS_ROT_0:
1613                                 vidrot = 0;
1614                                 break;
1615                         case OMAP_DSS_ROT_90:
1616                                 vidrot = 1;
1617                                 break;
1618                         case OMAP_DSS_ROT_180:
1619                                 vidrot = 2;
1620                                 break;
1621                         case OMAP_DSS_ROT_270:
1622                                 vidrot = 3;
1623                                 break;
1624                         }
1625                 }
1626
1627                 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1628                         row_repeat = true;
1629                 else
1630                         row_repeat = false;
1631         }
1632
1633         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
1634         if (dss_has_feature(FEAT_ROWREPEATENABLE))
1635                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1636                         row_repeat ? 1 : 0, 18, 18);
1637 }
1638
1639 static int color_mode_to_bpp(enum omap_color_mode color_mode)
1640 {
1641         switch (color_mode) {
1642         case OMAP_DSS_COLOR_CLUT1:
1643                 return 1;
1644         case OMAP_DSS_COLOR_CLUT2:
1645                 return 2;
1646         case OMAP_DSS_COLOR_CLUT4:
1647                 return 4;
1648         case OMAP_DSS_COLOR_CLUT8:
1649         case OMAP_DSS_COLOR_NV12:
1650                 return 8;
1651         case OMAP_DSS_COLOR_RGB12U:
1652         case OMAP_DSS_COLOR_RGB16:
1653         case OMAP_DSS_COLOR_ARGB16:
1654         case OMAP_DSS_COLOR_YUV2:
1655         case OMAP_DSS_COLOR_UYVY:
1656         case OMAP_DSS_COLOR_RGBA16:
1657         case OMAP_DSS_COLOR_RGBX16:
1658         case OMAP_DSS_COLOR_ARGB16_1555:
1659         case OMAP_DSS_COLOR_XRGB16_1555:
1660                 return 16;
1661         case OMAP_DSS_COLOR_RGB24P:
1662                 return 24;
1663         case OMAP_DSS_COLOR_RGB24U:
1664         case OMAP_DSS_COLOR_ARGB32:
1665         case OMAP_DSS_COLOR_RGBA32:
1666         case OMAP_DSS_COLOR_RGBX32:
1667                 return 32;
1668         default:
1669                 BUG();
1670                 return 0;
1671         }
1672 }
1673
1674 static s32 pixinc(int pixels, u8 ps)
1675 {
1676         if (pixels == 1)
1677                 return 1;
1678         else if (pixels > 1)
1679                 return 1 + (pixels - 1) * ps;
1680         else if (pixels < 0)
1681                 return 1 - (-pixels + 1) * ps;
1682         else
1683                 BUG();
1684                 return 0;
1685 }
1686
1687 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1688                 u16 screen_width,
1689                 u16 width, u16 height,
1690                 enum omap_color_mode color_mode, bool fieldmode,
1691                 unsigned int field_offset,
1692                 unsigned *offset0, unsigned *offset1,
1693                 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1694 {
1695         u8 ps;
1696
1697         /* FIXME CLUT formats */
1698         switch (color_mode) {
1699         case OMAP_DSS_COLOR_CLUT1:
1700         case OMAP_DSS_COLOR_CLUT2:
1701         case OMAP_DSS_COLOR_CLUT4:
1702         case OMAP_DSS_COLOR_CLUT8:
1703                 BUG();
1704                 return;
1705         case OMAP_DSS_COLOR_YUV2:
1706         case OMAP_DSS_COLOR_UYVY:
1707                 ps = 4;
1708                 break;
1709         default:
1710                 ps = color_mode_to_bpp(color_mode) / 8;
1711                 break;
1712         }
1713
1714         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1715                         width, height);
1716
1717         /*
1718          * field 0 = even field = bottom field
1719          * field 1 = odd field = top field
1720          */
1721         switch (rotation + mirror * 4) {
1722         case OMAP_DSS_ROT_0:
1723         case OMAP_DSS_ROT_180:
1724                 /*
1725                  * If the pixel format is YUV or UYVY divide the width
1726                  * of the image by 2 for 0 and 180 degree rotation.
1727                  */
1728                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1729                         color_mode == OMAP_DSS_COLOR_UYVY)
1730                         width = width >> 1;
1731         case OMAP_DSS_ROT_90:
1732         case OMAP_DSS_ROT_270:
1733                 *offset1 = 0;
1734                 if (field_offset)
1735                         *offset0 = field_offset * screen_width * ps;
1736                 else
1737                         *offset0 = 0;
1738
1739                 *row_inc = pixinc(1 +
1740                         (y_predecim * screen_width - x_predecim * width) +
1741                         (fieldmode ? screen_width : 0), ps);
1742                 *pix_inc = pixinc(x_predecim, ps);
1743                 break;
1744
1745         case OMAP_DSS_ROT_0 + 4:
1746         case OMAP_DSS_ROT_180 + 4:
1747                 /* If the pixel format is YUV or UYVY divide the width
1748                  * of the image by 2  for 0 degree and 180 degree
1749                  */
1750                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1751                         color_mode == OMAP_DSS_COLOR_UYVY)
1752                         width = width >> 1;
1753         case OMAP_DSS_ROT_90 + 4:
1754         case OMAP_DSS_ROT_270 + 4:
1755                 *offset1 = 0;
1756                 if (field_offset)
1757                         *offset0 = field_offset * screen_width * ps;
1758                 else
1759                         *offset0 = 0;
1760                 *row_inc = pixinc(1 -
1761                         (y_predecim * screen_width + x_predecim * width) -
1762                         (fieldmode ? screen_width : 0), ps);
1763                 *pix_inc = pixinc(x_predecim, ps);
1764                 break;
1765
1766         default:
1767                 BUG();
1768                 return;
1769         }
1770 }
1771
1772 static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1773                 u16 screen_width,
1774                 u16 width, u16 height,
1775                 enum omap_color_mode color_mode, bool fieldmode,
1776                 unsigned int field_offset,
1777                 unsigned *offset0, unsigned *offset1,
1778                 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1779 {
1780         u8 ps;
1781         u16 fbw, fbh;
1782
1783         /* FIXME CLUT formats */
1784         switch (color_mode) {
1785         case OMAP_DSS_COLOR_CLUT1:
1786         case OMAP_DSS_COLOR_CLUT2:
1787         case OMAP_DSS_COLOR_CLUT4:
1788         case OMAP_DSS_COLOR_CLUT8:
1789                 BUG();
1790                 return;
1791         default:
1792                 ps = color_mode_to_bpp(color_mode) / 8;
1793                 break;
1794         }
1795
1796         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1797                         width, height);
1798
1799         /* width & height are overlay sizes, convert to fb sizes */
1800
1801         if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1802                 fbw = width;
1803                 fbh = height;
1804         } else {
1805                 fbw = height;
1806                 fbh = width;
1807         }
1808
1809         /*
1810          * field 0 = even field = bottom field
1811          * field 1 = odd field = top field
1812          */
1813         switch (rotation + mirror * 4) {
1814         case OMAP_DSS_ROT_0:
1815                 *offset1 = 0;
1816                 if (field_offset)
1817                         *offset0 = *offset1 + field_offset * screen_width * ps;
1818                 else
1819                         *offset0 = *offset1;
1820                 *row_inc = pixinc(1 +
1821                         (y_predecim * screen_width - fbw * x_predecim) +
1822                         (fieldmode ? screen_width : 0), ps);
1823                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1824                         color_mode == OMAP_DSS_COLOR_UYVY)
1825                         *pix_inc = pixinc(x_predecim, 2 * ps);
1826                 else
1827                         *pix_inc = pixinc(x_predecim, ps);
1828                 break;
1829         case OMAP_DSS_ROT_90:
1830                 *offset1 = screen_width * (fbh - 1) * ps;
1831                 if (field_offset)
1832                         *offset0 = *offset1 + field_offset * ps;
1833                 else
1834                         *offset0 = *offset1;
1835                 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
1836                                 y_predecim + (fieldmode ? 1 : 0), ps);
1837                 *pix_inc = pixinc(-x_predecim * screen_width, ps);
1838                 break;
1839         case OMAP_DSS_ROT_180:
1840                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1841                 if (field_offset)
1842                         *offset0 = *offset1 - field_offset * screen_width * ps;
1843                 else
1844                         *offset0 = *offset1;
1845                 *row_inc = pixinc(-1 -
1846                         (y_predecim * screen_width - fbw * x_predecim) -
1847                         (fieldmode ? screen_width : 0), ps);
1848                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1849                         color_mode == OMAP_DSS_COLOR_UYVY)
1850                         *pix_inc = pixinc(-x_predecim, 2 * ps);
1851                 else
1852                         *pix_inc = pixinc(-x_predecim, ps);
1853                 break;
1854         case OMAP_DSS_ROT_270:
1855                 *offset1 = (fbw - 1) * ps;
1856                 if (field_offset)
1857                         *offset0 = *offset1 - field_offset * ps;
1858                 else
1859                         *offset0 = *offset1;
1860                 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
1861                                 y_predecim - (fieldmode ? 1 : 0), ps);
1862                 *pix_inc = pixinc(x_predecim * screen_width, ps);
1863                 break;
1864
1865         /* mirroring */
1866         case OMAP_DSS_ROT_0 + 4:
1867                 *offset1 = (fbw - 1) * ps;
1868                 if (field_offset)
1869                         *offset0 = *offset1 + field_offset * screen_width * ps;
1870                 else
1871                         *offset0 = *offset1;
1872                 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
1873                                 (fieldmode ? screen_width : 0),
1874                                 ps);
1875                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1876                         color_mode == OMAP_DSS_COLOR_UYVY)
1877                         *pix_inc = pixinc(-x_predecim, 2 * ps);
1878                 else
1879                         *pix_inc = pixinc(-x_predecim, ps);
1880                 break;
1881
1882         case OMAP_DSS_ROT_90 + 4:
1883                 *offset1 = 0;
1884                 if (field_offset)
1885                         *offset0 = *offset1 + field_offset * ps;
1886                 else
1887                         *offset0 = *offset1;
1888                 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
1889                                 y_predecim + (fieldmode ? 1 : 0),
1890                                 ps);
1891                 *pix_inc = pixinc(x_predecim * screen_width, ps);
1892                 break;
1893
1894         case OMAP_DSS_ROT_180 + 4:
1895                 *offset1 = screen_width * (fbh - 1) * ps;
1896                 if (field_offset)
1897                         *offset0 = *offset1 - field_offset * screen_width * ps;
1898                 else
1899                         *offset0 = *offset1;
1900                 *row_inc = pixinc(1 - y_predecim * screen_width * 2 -
1901                                 (fieldmode ? screen_width : 0),
1902                                 ps);
1903                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1904                         color_mode == OMAP_DSS_COLOR_UYVY)
1905                         *pix_inc = pixinc(x_predecim, 2 * ps);
1906                 else
1907                         *pix_inc = pixinc(x_predecim, ps);
1908                 break;
1909
1910         case OMAP_DSS_ROT_270 + 4:
1911                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1912                 if (field_offset)
1913                         *offset0 = *offset1 - field_offset * ps;
1914                 else
1915                         *offset0 = *offset1;
1916                 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
1917                                 y_predecim - (fieldmode ? 1 : 0),
1918                                 ps);
1919                 *pix_inc = pixinc(-x_predecim * screen_width, ps);
1920                 break;
1921
1922         default:
1923                 BUG();
1924                 return;
1925         }
1926 }
1927
1928 static void calc_tiler_rotation_offset(u16 screen_width, u16 width,
1929                 enum omap_color_mode color_mode, bool fieldmode,
1930                 unsigned int field_offset, unsigned *offset0, unsigned *offset1,
1931                 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1932 {
1933         u8 ps;
1934
1935         switch (color_mode) {
1936         case OMAP_DSS_COLOR_CLUT1:
1937         case OMAP_DSS_COLOR_CLUT2:
1938         case OMAP_DSS_COLOR_CLUT4:
1939         case OMAP_DSS_COLOR_CLUT8:
1940                 BUG();
1941                 return;
1942         default:
1943                 ps = color_mode_to_bpp(color_mode) / 8;
1944                 break;
1945         }
1946
1947         DSSDBG("scrw %d, width %d\n", screen_width, width);
1948
1949         /*
1950          * field 0 = even field = bottom field
1951          * field 1 = odd field = top field
1952          */
1953         *offset1 = 0;
1954         if (field_offset)
1955                 *offset0 = *offset1 + field_offset * screen_width * ps;
1956         else
1957                 *offset0 = *offset1;
1958         *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) +
1959                         (fieldmode ? screen_width : 0), ps);
1960         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1961                 color_mode == OMAP_DSS_COLOR_UYVY)
1962                 *pix_inc = pixinc(x_predecim, 2 * ps);
1963         else
1964                 *pix_inc = pixinc(x_predecim, ps);
1965 }
1966
1967 /*
1968  * This function is used to avoid synclosts in OMAP3, because of some
1969  * undocumented horizontal position and timing related limitations.
1970  */
1971 static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk,
1972                 const struct omap_video_timings *t, u16 pos_x,
1973                 u16 width, u16 height, u16 out_width, u16 out_height)
1974 {
1975         const int ds = DIV_ROUND_UP(height, out_height);
1976         unsigned long nonactive;
1977         static const u8 limits[3] = { 8, 10, 20 };
1978         u64 val, blank;
1979         int i;
1980
1981         nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
1982
1983         i = 0;
1984         if (out_height < height)
1985                 i++;
1986         if (out_width < width)
1987                 i++;
1988         blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
1989         DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
1990         if (blank <= limits[i])
1991                 return -EINVAL;
1992
1993         /*
1994          * Pixel data should be prepared before visible display point starts.
1995          * So, atleast DS-2 lines must have already been fetched by DISPC
1996          * during nonactive - pos_x period.
1997          */
1998         val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
1999         DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
2000                 val, max(0, ds - 2) * width);
2001         if (val < max(0, ds - 2) * width)
2002                 return -EINVAL;
2003
2004         /*
2005          * All lines need to be refilled during the nonactive period of which
2006          * only one line can be loaded during the active period. So, atleast
2007          * DS - 1 lines should be loaded during nonactive period.
2008          */
2009         val =  div_u64((u64)nonactive * lclk, pclk);
2010         DSSDBG("nonactive * pcd  = %llu, max(0, DS - 1) * width = %d\n",
2011                 val, max(0, ds - 1) * width);
2012         if (val < max(0, ds - 1) * width)
2013                 return -EINVAL;
2014
2015         return 0;
2016 }
2017
2018 static unsigned long calc_core_clk_five_taps(unsigned long pclk,
2019                 const struct omap_video_timings *mgr_timings, u16 width,
2020                 u16 height, u16 out_width, u16 out_height,
2021                 enum omap_color_mode color_mode)
2022 {
2023         u32 core_clk = 0;
2024         u64 tmp;
2025
2026         if (height <= out_height && width <= out_width)
2027                 return (unsigned long) pclk;
2028
2029         if (height > out_height) {
2030                 unsigned int ppl = mgr_timings->x_res;
2031
2032                 tmp = pclk * height * out_width;
2033                 do_div(tmp, 2 * out_height * ppl);
2034                 core_clk = tmp;
2035
2036                 if (height > 2 * out_height) {
2037                         if (ppl == out_width)
2038                                 return 0;
2039
2040                         tmp = pclk * (height - 2 * out_height) * out_width;
2041                         do_div(tmp, 2 * out_height * (ppl - out_width));
2042                         core_clk = max_t(u32, core_clk, tmp);
2043                 }
2044         }
2045
2046         if (width > out_width) {
2047                 tmp = pclk * width;
2048                 do_div(tmp, out_width);
2049                 core_clk = max_t(u32, core_clk, tmp);
2050
2051                 if (color_mode == OMAP_DSS_COLOR_RGB24U)
2052                         core_clk <<= 1;
2053         }
2054
2055         return core_clk;
2056 }
2057
2058 static unsigned long calc_core_clk_24xx(unsigned long pclk, u16 width,
2059                 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2060 {
2061         if (height > out_height && width > out_width)
2062                 return pclk * 4;
2063         else
2064                 return pclk * 2;
2065 }
2066
2067 static unsigned long calc_core_clk_34xx(unsigned long pclk, u16 width,
2068                 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2069 {
2070         unsigned int hf, vf;
2071
2072         /*
2073          * FIXME how to determine the 'A' factor
2074          * for the no downscaling case ?
2075          */
2076
2077         if (width > 3 * out_width)
2078                 hf = 4;
2079         else if (width > 2 * out_width)
2080                 hf = 3;
2081         else if (width > out_width)
2082                 hf = 2;
2083         else
2084                 hf = 1;
2085         if (height > out_height)
2086                 vf = 2;
2087         else
2088                 vf = 1;
2089
2090         return pclk * vf * hf;
2091 }
2092
2093 static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width,
2094                 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2095 {
2096         /*
2097          * If the overlay/writeback is in mem to mem mode, there are no
2098          * downscaling limitations with respect to pixel clock, return 1 as
2099          * required core clock to represent that we have sufficient enough
2100          * core clock to do maximum downscaling
2101          */
2102         if (mem_to_mem)
2103                 return 1;
2104
2105         if (width > out_width)
2106                 return DIV_ROUND_UP(pclk, out_width) * width;
2107         else
2108                 return pclk;
2109 }
2110
2111 static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk,
2112                 const struct omap_video_timings *mgr_timings,
2113                 u16 width, u16 height, u16 out_width, u16 out_height,
2114                 enum omap_color_mode color_mode, bool *five_taps,
2115                 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2116                 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2117 {
2118         int error;
2119         u16 in_width, in_height;
2120         int min_factor = min(*decim_x, *decim_y);
2121         const int maxsinglelinewidth =
2122                         dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2123
2124         *five_taps = false;
2125
2126         do {
2127                 in_height = DIV_ROUND_UP(height, *decim_y);
2128                 in_width = DIV_ROUND_UP(width, *decim_x);
2129                 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
2130                                 in_height, out_width, out_height, mem_to_mem);
2131                 error = (in_width > maxsinglelinewidth || !*core_clk ||
2132                         *core_clk > dispc_core_clk_rate());
2133                 if (error) {
2134                         if (*decim_x == *decim_y) {
2135                                 *decim_x = min_factor;
2136                                 ++*decim_y;
2137                         } else {
2138                                 swap(*decim_x, *decim_y);
2139                                 if (*decim_x < *decim_y)
2140                                         ++*decim_x;
2141                         }
2142                 }
2143         } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2144
2145         if (in_width > maxsinglelinewidth) {
2146                 DSSERR("Cannot scale max input width exceeded");
2147                 return -EINVAL;
2148         }
2149         return 0;
2150 }
2151
2152 static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk,
2153                 const struct omap_video_timings *mgr_timings,
2154                 u16 width, u16 height, u16 out_width, u16 out_height,
2155                 enum omap_color_mode color_mode, bool *five_taps,
2156                 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2157                 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2158 {
2159         int error;
2160         u16 in_width, in_height;
2161         int min_factor = min(*decim_x, *decim_y);
2162         const int maxsinglelinewidth =
2163                         dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2164
2165         do {
2166                 in_height = DIV_ROUND_UP(height, *decim_y);
2167                 in_width = DIV_ROUND_UP(width, *decim_x);
2168                 *core_clk = calc_core_clk_five_taps(pclk, mgr_timings,
2169                         in_width, in_height, out_width, out_height, color_mode);
2170
2171                 error = check_horiz_timing_omap3(pclk, lclk, mgr_timings,
2172                                 pos_x, in_width, in_height, out_width,
2173                                 out_height);
2174
2175                 if (in_width > maxsinglelinewidth)
2176                         if (in_height > out_height &&
2177                                                 in_height < out_height * 2)
2178                                 *five_taps = false;
2179                 if (!*five_taps)
2180                         *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
2181                                         in_height, out_width, out_height,
2182                                         mem_to_mem);
2183
2184                 error = (error || in_width > maxsinglelinewidth * 2 ||
2185                         (in_width > maxsinglelinewidth && *five_taps) ||
2186                         !*core_clk || *core_clk > dispc_core_clk_rate());
2187                 if (error) {
2188                         if (*decim_x == *decim_y) {
2189                                 *decim_x = min_factor;
2190                                 ++*decim_y;
2191                         } else {
2192                                 swap(*decim_x, *decim_y);
2193                                 if (*decim_x < *decim_y)
2194                                         ++*decim_x;
2195                         }
2196                 }
2197         } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2198
2199         if (check_horiz_timing_omap3(pclk, lclk, mgr_timings, pos_x, width,
2200                                 height, out_width, out_height)){
2201                         DSSERR("horizontal timing too tight\n");
2202                         return -EINVAL;
2203         }
2204
2205         if (in_width > (maxsinglelinewidth * 2)) {
2206                 DSSERR("Cannot setup scaling");
2207                 DSSERR("width exceeds maximum width possible");
2208                 return -EINVAL;
2209         }
2210
2211         if (in_width > maxsinglelinewidth && *five_taps) {
2212                 DSSERR("cannot setup scaling with five taps");
2213                 return -EINVAL;
2214         }
2215         return 0;
2216 }
2217
2218 static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk,
2219                 const struct omap_video_timings *mgr_timings,
2220                 u16 width, u16 height, u16 out_width, u16 out_height,
2221                 enum omap_color_mode color_mode, bool *five_taps,
2222                 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2223                 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2224 {
2225         u16 in_width, in_width_max;
2226         int decim_x_min = *decim_x;
2227         u16 in_height = DIV_ROUND_UP(height, *decim_y);
2228         const int maxsinglelinewidth =
2229                                 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2230         const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
2231
2232         if (mem_to_mem) {
2233                 in_width_max = out_width * maxdownscale;
2234         } else {
2235                 in_width_max = dispc_core_clk_rate() /
2236                                         DIV_ROUND_UP(pclk, out_width);
2237         }
2238
2239         *decim_x = DIV_ROUND_UP(width, in_width_max);
2240
2241         *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min;
2242         if (*decim_x > *x_predecim)
2243                 return -EINVAL;
2244
2245         do {
2246                 in_width = DIV_ROUND_UP(width, *decim_x);
2247         } while (*decim_x <= *x_predecim &&
2248                         in_width > maxsinglelinewidth && ++*decim_x);
2249
2250         if (in_width > maxsinglelinewidth) {
2251                 DSSERR("Cannot scale width exceeds max line width");
2252                 return -EINVAL;
2253         }
2254
2255         *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in_height,
2256                                 out_width, out_height, mem_to_mem);
2257         return 0;
2258 }
2259
2260 static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk,
2261                 enum omap_overlay_caps caps,
2262                 const struct omap_video_timings *mgr_timings,
2263                 u16 width, u16 height, u16 out_width, u16 out_height,
2264                 enum omap_color_mode color_mode, bool *five_taps,
2265                 int *x_predecim, int *y_predecim, u16 pos_x,
2266                 enum omap_dss_rotation_type rotation_type, bool mem_to_mem)
2267 {
2268         const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
2269         const int max_decim_limit = 16;
2270         unsigned long core_clk = 0;
2271         int decim_x, decim_y, ret;
2272
2273         if (width == out_width && height == out_height)
2274                 return 0;
2275
2276         if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
2277                 return -EINVAL;
2278
2279         if (mem_to_mem) {
2280                 *x_predecim = *y_predecim = 1;
2281         } else {
2282                 *x_predecim = max_decim_limit;
2283                 *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER &&
2284                                 dss_has_feature(FEAT_BURST_2D)) ?
2285                                 2 : max_decim_limit;
2286         }
2287
2288         if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
2289             color_mode == OMAP_DSS_COLOR_CLUT2 ||
2290             color_mode == OMAP_DSS_COLOR_CLUT4 ||
2291             color_mode == OMAP_DSS_COLOR_CLUT8) {
2292                 *x_predecim = 1;
2293                 *y_predecim = 1;
2294                 *five_taps = false;
2295                 return 0;
2296         }
2297
2298         decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
2299         decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
2300
2301         if (decim_x > *x_predecim || out_width > width * 8)
2302                 return -EINVAL;
2303
2304         if (decim_y > *y_predecim || out_height > height * 8)
2305                 return -EINVAL;
2306
2307         ret = dispc.feat->calc_scaling(pclk, lclk, mgr_timings, width, height,
2308                 out_width, out_height, color_mode, five_taps,
2309                 x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk,
2310                 mem_to_mem);
2311         if (ret)
2312                 return ret;
2313
2314         DSSDBG("required core clk rate = %lu Hz\n", core_clk);
2315         DSSDBG("current core clk rate = %lu Hz\n", dispc_core_clk_rate());
2316
2317         if (!core_clk || core_clk > dispc_core_clk_rate()) {
2318                 DSSERR("failed to set up scaling, "
2319                         "required core clk rate = %lu Hz, "
2320                         "current core clk rate = %lu Hz\n",
2321                         core_clk, dispc_core_clk_rate());
2322                 return -EINVAL;
2323         }
2324
2325         *x_predecim = decim_x;
2326         *y_predecim = decim_y;
2327         return 0;
2328 }
2329
2330 int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel,
2331                 const struct omap_overlay_info *oi,
2332                 const struct omap_video_timings *timings,
2333                 int *x_predecim, int *y_predecim)
2334 {
2335         enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
2336         bool five_taps = true;
2337         bool fieldmode = 0;
2338         u16 in_height = oi->height;
2339         u16 in_width = oi->width;
2340         bool ilace = timings->interlace;
2341         u16 out_width, out_height;
2342         int pos_x = oi->pos_x;
2343         unsigned long pclk = dispc_mgr_pclk_rate(channel);
2344         unsigned long lclk = dispc_mgr_lclk_rate(channel);
2345
2346         out_width = oi->out_width == 0 ? oi->width : oi->out_width;
2347         out_height = oi->out_height == 0 ? oi->height : oi->out_height;
2348
2349         if (ilace && oi->height == out_height)
2350                 fieldmode = 1;
2351
2352         if (ilace) {
2353                 if (fieldmode)
2354                         in_height /= 2;
2355                 out_height /= 2;
2356
2357                 DSSDBG("adjusting for ilace: height %d, out_height %d\n",
2358                                 in_height, out_height);
2359         }
2360
2361         if (!dss_feat_color_mode_supported(plane, oi->color_mode))
2362                 return -EINVAL;
2363
2364         return dispc_ovl_calc_scaling(pclk, lclk, caps, timings, in_width,
2365                         in_height, out_width, out_height, oi->color_mode,
2366                         &five_taps, x_predecim, y_predecim, pos_x,
2367                         oi->rotation_type, false);
2368 }
2369 EXPORT_SYMBOL(dispc_ovl_check);
2370
2371 static int dispc_ovl_setup_common(enum omap_plane plane,
2372                 enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr,
2373                 u16 screen_width, int pos_x, int pos_y, u16 width, u16 height,
2374                 u16 out_width, u16 out_height, enum omap_color_mode color_mode,
2375                 u8 rotation, bool mirror, u8 zorder, u8 pre_mult_alpha,
2376                 u8 global_alpha, enum omap_dss_rotation_type rotation_type,
2377                 bool replication, const struct omap_video_timings *mgr_timings,
2378                 bool mem_to_mem)
2379 {
2380         bool five_taps = true;
2381         bool fieldmode = 0;
2382         int r, cconv = 0;
2383         unsigned offset0, offset1;
2384         s32 row_inc;
2385         s32 pix_inc;
2386         u16 frame_width, frame_height;
2387         unsigned int field_offset = 0;
2388         u16 in_height = height;
2389         u16 in_width = width;
2390         int x_predecim = 1, y_predecim = 1;
2391         bool ilace = mgr_timings->interlace;
2392         unsigned long pclk = dispc_plane_pclk_rate(plane);
2393         unsigned long lclk = dispc_plane_lclk_rate(plane);
2394
2395         if (paddr == 0)
2396                 return -EINVAL;
2397
2398         out_width = out_width == 0 ? width : out_width;
2399         out_height = out_height == 0 ? height : out_height;
2400
2401         if (ilace && height == out_height)
2402                 fieldmode = 1;
2403
2404         if (ilace) {
2405                 if (fieldmode)
2406                         in_height /= 2;
2407                 pos_y /= 2;
2408                 out_height /= 2;
2409
2410                 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
2411                         "out_height %d\n", in_height, pos_y,
2412                         out_height);
2413         }
2414
2415         if (!dss_feat_color_mode_supported(plane, color_mode))
2416                 return -EINVAL;
2417
2418         r = dispc_ovl_calc_scaling(pclk, lclk, caps, mgr_timings, in_width,
2419                         in_height, out_width, out_height, color_mode,
2420                         &five_taps, &x_predecim, &y_predecim, pos_x,
2421                         rotation_type, mem_to_mem);
2422         if (r)
2423                 return r;
2424
2425         in_width = DIV_ROUND_UP(in_width, x_predecim);
2426         in_height = DIV_ROUND_UP(in_height, y_predecim);
2427
2428         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2429                         color_mode == OMAP_DSS_COLOR_UYVY ||
2430                         color_mode == OMAP_DSS_COLOR_NV12)
2431                 cconv = 1;
2432
2433         if (ilace && !fieldmode) {
2434                 /*
2435                  * when downscaling the bottom field may have to start several
2436                  * source lines below the top field. Unfortunately ACCUI
2437                  * registers will only hold the fractional part of the offset
2438                  * so the integer part must be added to the base address of the
2439                  * bottom field.
2440                  */
2441                 if (!in_height || in_height == out_height)
2442                         field_offset = 0;
2443                 else
2444                         field_offset = in_height / out_height / 2;
2445         }
2446
2447         /* Fields are independent but interleaved in memory. */
2448         if (fieldmode)
2449                 field_offset = 1;
2450
2451         offset0 = 0;
2452         offset1 = 0;
2453         row_inc = 0;
2454         pix_inc = 0;
2455
2456         if (plane == OMAP_DSS_WB) {
2457                 frame_width = out_width;
2458                 frame_height = out_height;
2459         } else {
2460                 frame_width = in_width;
2461                 frame_height = height;
2462         }
2463
2464         if (rotation_type == OMAP_DSS_ROT_TILER)
2465                 calc_tiler_rotation_offset(screen_width, frame_width,
2466                                 color_mode, fieldmode, field_offset,
2467                                 &offset0, &offset1, &row_inc, &pix_inc,
2468                                 x_predecim, y_predecim);
2469         else if (rotation_type == OMAP_DSS_ROT_DMA)
2470                 calc_dma_rotation_offset(rotation, mirror, screen_width,
2471                                 frame_width, frame_height,
2472                                 color_mode, fieldmode, field_offset,
2473                                 &offset0, &offset1, &row_inc, &pix_inc,
2474                                 x_predecim, y_predecim);
2475         else
2476                 calc_vrfb_rotation_offset(rotation, mirror,
2477                                 screen_width, frame_width, frame_height,
2478                                 color_mode, fieldmode, field_offset,
2479                                 &offset0, &offset1, &row_inc, &pix_inc,
2480                                 x_predecim, y_predecim);
2481
2482         DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2483                         offset0, offset1, row_inc, pix_inc);
2484
2485         dispc_ovl_set_color_mode(plane, color_mode);
2486
2487         dispc_ovl_configure_burst_type(plane, rotation_type);
2488
2489         dispc_ovl_set_ba0(plane, paddr + offset0);
2490         dispc_ovl_set_ba1(plane, paddr + offset1);
2491
2492         if (OMAP_DSS_COLOR_NV12 == color_mode) {
2493                 dispc_ovl_set_ba0_uv(plane, p_uv_addr + offset0);
2494                 dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1);
2495         }
2496
2497         dispc_ovl_set_row_inc(plane, row_inc);
2498         dispc_ovl_set_pix_inc(plane, pix_inc);
2499
2500         DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width,
2501                         in_height, out_width, out_height);
2502
2503         dispc_ovl_set_pos(plane, caps, pos_x, pos_y);
2504
2505         dispc_ovl_set_input_size(plane, in_width, in_height);
2506
2507         if (caps & OMAP_DSS_OVL_CAP_SCALE) {
2508                 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2509                                    out_height, ilace, five_taps, fieldmode,
2510                                    color_mode, rotation);
2511                 dispc_ovl_set_output_size(plane, out_width, out_height);
2512                 dispc_ovl_set_vid_color_conv(plane, cconv);
2513         }
2514
2515         dispc_ovl_set_rotation_attrs(plane, rotation, mirror, color_mode);
2516
2517         dispc_ovl_set_zorder(plane, caps, zorder);
2518         dispc_ovl_set_pre_mult_alpha(plane, caps, pre_mult_alpha);
2519         dispc_ovl_setup_global_alpha(plane, caps, global_alpha);
2520
2521         dispc_ovl_enable_replication(plane, caps, replication);
2522
2523         return 0;
2524 }
2525
2526 int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
2527                 bool replication, const struct omap_video_timings *mgr_timings,
2528                 bool mem_to_mem)
2529 {
2530         int r;
2531         enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
2532         enum omap_channel channel;
2533
2534         channel = dispc_ovl_get_channel_out(plane);
2535
2536         DSSDBG("dispc_ovl_setup %d, pa %x, pa_uv %x, sw %d, %d,%d, %dx%d -> "
2537                 "%dx%d, cmode %x, rot %d, mir %d, chan %d repl %d\n",
2538                 plane, oi->paddr, oi->p_uv_addr, oi->screen_width, oi->pos_x,
2539                 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height,
2540                 oi->color_mode, oi->rotation, oi->mirror, channel, replication);
2541
2542         r = dispc_ovl_setup_common(plane, caps, oi->paddr, oi->p_uv_addr,
2543                 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2544                 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
2545                 oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha,
2546                 oi->rotation_type, replication, mgr_timings, mem_to_mem);
2547
2548         return r;
2549 }
2550 EXPORT_SYMBOL(dispc_ovl_setup);
2551
2552 int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
2553                 bool mem_to_mem, const struct omap_video_timings *mgr_timings)
2554 {
2555         int r;
2556         u32 l;
2557         enum omap_plane plane = OMAP_DSS_WB;
2558         const int pos_x = 0, pos_y = 0;
2559         const u8 zorder = 0, global_alpha = 0;
2560         const bool replication = false;
2561         bool truncation;
2562         int in_width = mgr_timings->x_res;
2563         int in_height = mgr_timings->y_res;
2564         enum omap_overlay_caps caps =
2565                 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA;
2566
2567         DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, "
2568                 "rot %d, mir %d\n", wi->paddr, wi->p_uv_addr, in_width,
2569                 in_height, wi->width, wi->height, wi->color_mode, wi->rotation,
2570                 wi->mirror);
2571
2572         r = dispc_ovl_setup_common(plane, caps, wi->paddr, wi->p_uv_addr,
2573                 wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width,
2574                 wi->height, wi->color_mode, wi->rotation, wi->mirror, zorder,
2575                 wi->pre_mult_alpha, global_alpha, wi->rotation_type,
2576                 replication, mgr_timings, mem_to_mem);
2577
2578         switch (wi->color_mode) {
2579         case OMAP_DSS_COLOR_RGB16:
2580         case OMAP_DSS_COLOR_RGB24P:
2581         case OMAP_DSS_COLOR_ARGB16:
2582         case OMAP_DSS_COLOR_RGBA16:
2583         case OMAP_DSS_COLOR_RGB12U:
2584         case OMAP_DSS_COLOR_ARGB16_1555:
2585         case OMAP_DSS_COLOR_XRGB16_1555:
2586         case OMAP_DSS_COLOR_RGBX16:
2587                 truncation = true;
2588                 break;
2589         default:
2590                 truncation = false;
2591                 break;
2592         }
2593
2594         /* setup extra DISPC_WB_ATTRIBUTES */
2595         l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2596         l = FLD_MOD(l, truncation, 10, 10);     /* TRUNCATIONENABLE */
2597         l = FLD_MOD(l, mem_to_mem, 19, 19);     /* WRITEBACKMODE */
2598         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
2599
2600         return r;
2601 }
2602
2603 int dispc_ovl_enable(enum omap_plane plane, bool enable)
2604 {
2605         DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2606
2607         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
2608
2609         return 0;
2610 }
2611 EXPORT_SYMBOL(dispc_ovl_enable);
2612
2613 bool dispc_ovl_enabled(enum omap_plane plane)
2614 {
2615         return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0);
2616 }
2617 EXPORT_SYMBOL(dispc_ovl_enabled);
2618
2619 void dispc_mgr_enable(enum omap_channel channel, bool enable)
2620 {
2621         mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);
2622         /* flush posted write */
2623         mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2624 }
2625 EXPORT_SYMBOL(dispc_mgr_enable);
2626
2627 bool dispc_mgr_is_enabled(enum omap_channel channel)
2628 {
2629         return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2630 }
2631 EXPORT_SYMBOL(dispc_mgr_is_enabled);
2632
2633 void dispc_wb_enable(bool enable)
2634 {
2635         dispc_ovl_enable(OMAP_DSS_WB, enable);
2636 }
2637
2638 bool dispc_wb_is_enabled(void)
2639 {
2640         return dispc_ovl_enabled(OMAP_DSS_WB);
2641 }
2642
2643 static void dispc_lcd_enable_signal_polarity(bool act_high)
2644 {
2645         if (!dss_has_feature(FEAT_LCDENABLEPOL))
2646                 return;
2647
2648         REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
2649 }
2650
2651 void dispc_lcd_enable_signal(bool enable)
2652 {
2653         if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2654                 return;
2655
2656         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
2657 }
2658
2659 void dispc_pck_free_enable(bool enable)
2660 {
2661         if (!dss_has_feature(FEAT_PCKFREEENABLE))
2662                 return;
2663
2664         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
2665 }
2666
2667 static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
2668 {
2669         mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
2670 }
2671
2672
2673 static void dispc_mgr_set_lcd_type_tft(enum omap_channel channel)
2674 {
2675         mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1);
2676 }
2677
2678 void dispc_set_loadmode(enum omap_dss_load_mode mode)
2679 {
2680         REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
2681 }
2682
2683
2684 static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
2685 {
2686         dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
2687 }
2688
2689 static void dispc_mgr_set_trans_key(enum omap_channel ch,
2690                 enum omap_dss_trans_key_type type,
2691                 u32 trans_key)
2692 {
2693         mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type);
2694
2695         dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
2696 }
2697
2698 static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
2699 {
2700         mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable);
2701 }
2702
2703 static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2704                 bool enable)
2705 {
2706         if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
2707                 return;
2708
2709         if (ch == OMAP_DSS_CHANNEL_LCD)
2710                 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2711         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2712                 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2713 }
2714
2715 void dispc_mgr_setup(enum omap_channel channel,
2716                 const struct omap_overlay_manager_info *info)
2717 {
2718         dispc_mgr_set_default_color(channel, info->default_color);
2719         dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
2720         dispc_mgr_enable_trans_key(channel, info->trans_enabled);
2721         dispc_mgr_enable_alpha_fixed_zorder(channel,
2722                         info->partial_alpha_enabled);
2723         if (dss_has_feature(FEAT_CPR)) {
2724                 dispc_mgr_enable_cpr(channel, info->cpr_enable);
2725                 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
2726         }
2727 }
2728 EXPORT_SYMBOL(dispc_mgr_setup);
2729
2730 static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
2731 {
2732         int code;
2733
2734         switch (data_lines) {
2735         case 12:
2736                 code = 0;
2737                 break;
2738         case 16:
2739                 code = 1;
2740                 break;
2741         case 18:
2742                 code = 2;
2743                 break;
2744         case 24:
2745                 code = 3;
2746                 break;
2747         default:
2748                 BUG();
2749                 return;
2750         }
2751
2752         mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code);
2753 }
2754
2755 static void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
2756 {
2757         u32 l;
2758         int gpout0, gpout1;
2759
2760         switch (mode) {
2761         case DSS_IO_PAD_MODE_RESET:
2762                 gpout0 = 0;
2763                 gpout1 = 0;
2764                 break;
2765         case DSS_IO_PAD_MODE_RFBI:
2766                 gpout0 = 1;
2767                 gpout1 = 0;
2768                 break;
2769         case DSS_IO_PAD_MODE_BYPASS:
2770                 gpout0 = 1;
2771                 gpout1 = 1;
2772                 break;
2773         default:
2774                 BUG();
2775                 return;
2776         }
2777
2778         l = dispc_read_reg(DISPC_CONTROL);
2779         l = FLD_MOD(l, gpout0, 15, 15);
2780         l = FLD_MOD(l, gpout1, 16, 16);
2781         dispc_write_reg(DISPC_CONTROL, l);
2782 }
2783
2784 static void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
2785 {
2786         mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);
2787 }
2788
2789 void dispc_mgr_set_lcd_config(enum omap_channel channel,
2790                 const struct dss_lcd_mgr_config *config)
2791 {
2792         dispc_mgr_set_io_pad_mode(config->io_pad_mode);
2793
2794         dispc_mgr_enable_stallmode(channel, config->stallmode);
2795         dispc_mgr_enable_fifohandcheck(channel, config->fifohandcheck);
2796
2797         dispc_mgr_set_clock_div(channel, &config->clock_info);
2798
2799         dispc_mgr_set_tft_data_lines(channel, config->video_port_width);
2800
2801         dispc_lcd_enable_signal_polarity(config->lcden_sig_polarity);
2802
2803         dispc_mgr_set_lcd_type_tft(channel);
2804 }
2805 EXPORT_SYMBOL(dispc_mgr_set_lcd_config);
2806
2807 static bool _dispc_mgr_size_ok(u16 width, u16 height)
2808 {
2809         return width <= dispc.feat->mgr_width_max &&
2810                 height <= dispc.feat->mgr_height_max;
2811 }
2812
2813 static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2814                 int vsw, int vfp, int vbp)
2815 {
2816         if (hsw < 1 || hsw > dispc.feat->sw_max ||
2817                         hfp < 1 || hfp > dispc.feat->hp_max ||
2818                         hbp < 1 || hbp > dispc.feat->hp_max ||
2819                         vsw < 1 || vsw > dispc.feat->sw_max ||
2820                         vfp < 0 || vfp > dispc.feat->vp_max ||
2821                         vbp < 0 || vbp > dispc.feat->vp_max)
2822                 return false;
2823         return true;
2824 }
2825
2826 bool dispc_mgr_timings_ok(enum omap_channel channel,
2827                 const struct omap_video_timings *timings)
2828 {
2829         bool timings_ok;
2830
2831         timings_ok = _dispc_mgr_size_ok(timings->x_res, timings->y_res);
2832
2833         if (dss_mgr_is_lcd(channel))
2834                 timings_ok =  timings_ok && _dispc_lcd_timings_ok(timings->hsw,
2835                                                 timings->hfp, timings->hbp,
2836                                                 timings->vsw, timings->vfp,
2837                                                 timings->vbp);
2838
2839         return timings_ok;
2840 }
2841
2842 static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
2843                 int hfp, int hbp, int vsw, int vfp, int vbp,
2844                 enum omap_dss_signal_level vsync_level,
2845                 enum omap_dss_signal_level hsync_level,
2846                 enum omap_dss_signal_edge data_pclk_edge,
2847                 enum omap_dss_signal_level de_level,
2848                 enum omap_dss_signal_edge sync_pclk_edge)
2849
2850 {
2851         u32 timing_h, timing_v, l;
2852         bool onoff, rf, ipc;
2853
2854         timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) |
2855                         FLD_VAL(hfp-1, dispc.feat->fp_start, 8) |
2856                         FLD_VAL(hbp-1, dispc.feat->bp_start, 20);
2857         timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) |
2858                         FLD_VAL(vfp, dispc.feat->fp_start, 8) |
2859                         FLD_VAL(vbp, dispc.feat->bp_start, 20);
2860
2861         dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2862         dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
2863
2864         switch (data_pclk_edge) {
2865         case OMAPDSS_DRIVE_SIG_RISING_EDGE:
2866                 ipc = false;
2867                 break;
2868         case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
2869                 ipc = true;
2870                 break;
2871         case OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES:
2872         default:
2873                 BUG();
2874         }
2875
2876         switch (sync_pclk_edge) {
2877         case OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES:
2878                 onoff = false;
2879                 rf = false;
2880                 break;
2881         case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
2882                 onoff = true;
2883                 rf = false;
2884                 break;
2885         case OMAPDSS_DRIVE_SIG_RISING_EDGE:
2886                 onoff = true;
2887                 rf = true;
2888                 break;
2889         default:
2890                 BUG();
2891         };
2892
2893         l = dispc_read_reg(DISPC_POL_FREQ(channel));
2894         l |= FLD_VAL(onoff, 17, 17);
2895         l |= FLD_VAL(rf, 16, 16);
2896         l |= FLD_VAL(de_level, 15, 15);
2897         l |= FLD_VAL(ipc, 14, 14);
2898         l |= FLD_VAL(hsync_level, 13, 13);
2899         l |= FLD_VAL(vsync_level, 12, 12);
2900         dispc_write_reg(DISPC_POL_FREQ(channel), l);
2901 }
2902
2903 /* change name to mode? */
2904 void dispc_mgr_set_timings(enum omap_channel channel,
2905                 const struct omap_video_timings *timings)
2906 {
2907         unsigned xtot, ytot;
2908         unsigned long ht, vt;
2909         struct omap_video_timings t = *timings;
2910
2911         DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res);
2912
2913         if (!dispc_mgr_timings_ok(channel, &t)) {
2914                 BUG();
2915                 return;
2916         }
2917
2918         if (dss_mgr_is_lcd(channel)) {
2919                 _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw,
2920                                 t.vfp, t.vbp, t.vsync_level, t.hsync_level,
2921                                 t.data_pclk_edge, t.de_level, t.sync_pclk_edge);
2922
2923                 xtot = t.x_res + t.hfp + t.hsw + t.hbp;
2924                 ytot = t.y_res + t.vfp + t.vsw + t.vbp;
2925
2926                 ht = (timings->pixel_clock * 1000) / xtot;
2927                 vt = (timings->pixel_clock * 1000) / xtot / ytot;
2928
2929                 DSSDBG("pck %u\n", timings->pixel_clock);
2930                 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2931                         t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
2932                 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
2933                         t.vsync_level, t.hsync_level, t.data_pclk_edge,
2934                         t.de_level, t.sync_pclk_edge);
2935
2936                 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2937         } else {
2938                 if (t.interlace == true)
2939                         t.y_res /= 2;
2940         }
2941
2942         dispc_mgr_set_size(channel, t.x_res, t.y_res);
2943 }
2944 EXPORT_SYMBOL(dispc_mgr_set_timings);
2945
2946 static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
2947                 u16 pck_div)
2948 {
2949         BUG_ON(lck_div < 1);
2950         BUG_ON(pck_div < 1);
2951
2952         dispc_write_reg(DISPC_DIVISORo(channel),
2953                         FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
2954 }
2955
2956 static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2957                 int *pck_div)
2958 {
2959         u32 l;
2960         l = dispc_read_reg(DISPC_DIVISORo(channel));
2961         *lck_div = FLD_GET(l, 23, 16);
2962         *pck_div = FLD_GET(l, 7, 0);
2963 }
2964
2965 unsigned long dispc_fclk_rate(void)
2966 {
2967         struct platform_device *dsidev;
2968         unsigned long r = 0;
2969
2970         switch (dss_get_dispc_clk_source()) {
2971         case OMAP_DSS_CLK_SRC_FCK:
2972                 r = dss_get_dispc_clk_rate();
2973                 break;
2974         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
2975                 dsidev = dsi_get_dsidev_from_id(0);
2976                 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2977                 break;
2978         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2979                 dsidev = dsi_get_dsidev_from_id(1);
2980                 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2981                 break;
2982         default:
2983                 BUG();
2984                 return 0;
2985         }
2986
2987         return r;
2988 }
2989
2990 unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
2991 {
2992         struct platform_device *dsidev;
2993         int lcd;
2994         unsigned long r;
2995         u32 l;
2996
2997         if (dss_mgr_is_lcd(channel)) {
2998                 l = dispc_read_reg(DISPC_DIVISORo(channel));
2999
3000                 lcd = FLD_GET(l, 23, 16);
3001
3002                 switch (dss_get_lcd_clk_source(channel)) {
3003                 case OMAP_DSS_CLK_SRC_FCK:
3004                         r = dss_get_dispc_clk_rate();
3005                         break;
3006                 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
3007                         dsidev = dsi_get_dsidev_from_id(0);
3008                         r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
3009                         break;
3010                 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3011                         dsidev = dsi_get_dsidev_from_id(1);
3012                         r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
3013                         break;
3014                 default:
3015                         BUG();
3016                         return 0;
3017                 }
3018
3019                 return r / lcd;
3020         } else {
3021                 return dispc_fclk_rate();
3022         }
3023 }
3024
3025 unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
3026 {
3027         unsigned long r;
3028
3029         if (dss_mgr_is_lcd(channel)) {
3030                 int pcd;
3031                 u32 l;
3032
3033                 l = dispc_read_reg(DISPC_DIVISORo(channel));
3034
3035                 pcd = FLD_GET(l, 7, 0);
3036
3037                 r = dispc_mgr_lclk_rate(channel);
3038
3039                 return r / pcd;
3040         } else {
3041                 enum dss_hdmi_venc_clk_source_select source;
3042
3043                 source = dss_get_hdmi_venc_clk_source();
3044
3045                 switch (source) {
3046                 case DSS_VENC_TV_CLK:
3047                         return venc_get_pixel_clock();
3048                 case DSS_HDMI_M_PCLK:
3049                         return hdmi_get_pixel_clock();
3050                 default:
3051                         BUG();
3052                         return 0;
3053                 }
3054         }
3055 }
3056
3057 unsigned long dispc_core_clk_rate(void)
3058 {
3059         int lcd;
3060         unsigned long fclk = dispc_fclk_rate();
3061
3062         if (dss_has_feature(FEAT_CORE_CLK_DIV))
3063                 lcd = REG_GET(DISPC_DIVISOR, 23, 16);
3064         else
3065                 lcd = REG_GET(DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD), 23, 16);
3066
3067         return fclk / lcd;
3068 }
3069
3070 static unsigned long dispc_plane_pclk_rate(enum omap_plane plane)
3071 {
3072         enum omap_channel channel;
3073
3074         if (plane == OMAP_DSS_WB)
3075                 return 0;
3076
3077         channel = dispc_ovl_get_channel_out(plane);
3078
3079         return dispc_mgr_pclk_rate(channel);
3080 }
3081
3082 static unsigned long dispc_plane_lclk_rate(enum omap_plane plane)
3083 {
3084         enum omap_channel channel;
3085
3086         if (plane == OMAP_DSS_WB)
3087                 return 0;
3088
3089         channel = dispc_ovl_get_channel_out(plane);
3090
3091         return dispc_mgr_lclk_rate(channel);
3092 }
3093
3094 static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel)
3095 {
3096         int lcd, pcd;
3097         enum omap_dss_clk_source lcd_clk_src;
3098
3099         seq_printf(s, "- %s -\n", mgr_desc[channel].name);
3100
3101         lcd_clk_src = dss_get_lcd_clk_source(channel);
3102
3103         seq_printf(s, "%s clk source = %s (%s)\n", mgr_desc[channel].name,
3104                 dss_get_generic_clk_source_name(lcd_clk_src),
3105                 dss_feat_get_clk_source_name(lcd_clk_src));
3106
3107         dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd);
3108
3109         seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3110                 dispc_mgr_lclk_rate(channel), lcd);
3111         seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
3112                 dispc_mgr_pclk_rate(channel), pcd);
3113 }
3114
3115 void dispc_dump_clocks(struct seq_file *s)
3116 {
3117         int lcd;
3118         u32 l;
3119         enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
3120
3121         if (dispc_runtime_get())
3122                 return;
3123
3124         seq_printf(s, "- DISPC -\n");
3125
3126         seq_printf(s, "dispc fclk source = %s (%s)\n",
3127                         dss_get_generic_clk_source_name(dispc_clk_src),
3128                         dss_feat_get_clk_source_name(dispc_clk_src));
3129
3130         seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
3131
3132         if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3133                 seq_printf(s, "- DISPC-CORE-CLK -\n");
3134                 l = dispc_read_reg(DISPC_DIVISOR);
3135                 lcd = FLD_GET(l, 23, 16);
3136
3137                 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3138                                 (dispc_fclk_rate()/lcd), lcd);
3139         }
3140
3141         dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD);
3142
3143         if (dss_has_feature(FEAT_MGR_LCD2))
3144                 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2);
3145         if (dss_has_feature(FEAT_MGR_LCD3))
3146                 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3);
3147
3148         dispc_runtime_put();
3149 }
3150
3151 static void dispc_dump_regs(struct seq_file *s)
3152 {
3153         int i, j;
3154         const char *mgr_names[] = {
3155                 [OMAP_DSS_CHANNEL_LCD]          = "LCD",
3156                 [OMAP_DSS_CHANNEL_DIGIT]        = "TV",
3157                 [OMAP_DSS_CHANNEL_LCD2]         = "LCD2",
3158                 [OMAP_DSS_CHANNEL_LCD3]         = "LCD3",
3159         };
3160         const char *ovl_names[] = {
3161                 [OMAP_DSS_GFX]          = "GFX",
3162                 [OMAP_DSS_VIDEO1]       = "VID1",
3163                 [OMAP_DSS_VIDEO2]       = "VID2",
3164                 [OMAP_DSS_VIDEO3]       = "VID3",
3165         };
3166         const char **p_names;
3167
3168 #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
3169
3170         if (dispc_runtime_get())
3171                 return;
3172
3173         /* DISPC common registers */
3174         DUMPREG(DISPC_REVISION);
3175         DUMPREG(DISPC_SYSCONFIG);
3176         DUMPREG(DISPC_SYSSTATUS);
3177         DUMPREG(DISPC_IRQSTATUS);
3178         DUMPREG(DISPC_IRQENABLE);
3179         DUMPREG(DISPC_CONTROL);
3180         DUMPREG(DISPC_CONFIG);
3181         DUMPREG(DISPC_CAPABLE);
3182         DUMPREG(DISPC_LINE_STATUS);
3183         DUMPREG(DISPC_LINE_NUMBER);
3184         if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
3185                         dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
3186                 DUMPREG(DISPC_GLOBAL_ALPHA);
3187         if (dss_has_feature(FEAT_MGR_LCD2)) {
3188                 DUMPREG(DISPC_CONTROL2);
3189                 DUMPREG(DISPC_CONFIG2);
3190         }
3191         if (dss_has_feature(FEAT_MGR_LCD3)) {
3192                 DUMPREG(DISPC_CONTROL3);
3193                 DUMPREG(DISPC_CONFIG3);
3194         }
3195
3196 #undef DUMPREG
3197
3198 #define DISPC_REG(i, name) name(i)
3199 #define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
3200         (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \
3201         dispc_read_reg(DISPC_REG(i, r)))
3202
3203         p_names = mgr_names;
3204
3205         /* DISPC channel specific registers */
3206         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
3207                 DUMPREG(i, DISPC_DEFAULT_COLOR);
3208                 DUMPREG(i, DISPC_TRANS_COLOR);
3209                 DUMPREG(i, DISPC_SIZE_MGR);
3210
3211                 if (i == OMAP_DSS_CHANNEL_DIGIT)
3212                         continue;
3213
3214                 DUMPREG(i, DISPC_DEFAULT_COLOR);
3215                 DUMPREG(i, DISPC_TRANS_COLOR);
3216                 DUMPREG(i, DISPC_TIMING_H);
3217                 DUMPREG(i, DISPC_TIMING_V);
3218                 DUMPREG(i, DISPC_POL_FREQ);
3219                 DUMPREG(i, DISPC_DIVISORo);
3220                 DUMPREG(i, DISPC_SIZE_MGR);
3221
3222                 DUMPREG(i, DISPC_DATA_CYCLE1);
3223                 DUMPREG(i, DISPC_DATA_CYCLE2);
3224                 DUMPREG(i, DISPC_DATA_CYCLE3);
3225
3226                 if (dss_has_feature(FEAT_CPR)) {
3227                         DUMPREG(i, DISPC_CPR_COEF_R);
3228                         DUMPREG(i, DISPC_CPR_COEF_G);
3229                         DUMPREG(i, DISPC_CPR_COEF_B);
3230                 }
3231         }
3232
3233         p_names = ovl_names;
3234
3235         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
3236                 DUMPREG(i, DISPC_OVL_BA0);
3237                 DUMPREG(i, DISPC_OVL_BA1);
3238                 DUMPREG(i, DISPC_OVL_POSITION);
3239                 DUMPREG(i, DISPC_OVL_SIZE);
3240                 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3241                 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3242                 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3243                 DUMPREG(i, DISPC_OVL_ROW_INC);
3244                 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3245                 if (dss_has_feature(FEAT_PRELOAD))
3246                         DUMPREG(i, DISPC_OVL_PRELOAD);
3247
3248                 if (i == OMAP_DSS_GFX) {
3249                         DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
3250                         DUMPREG(i, DISPC_OVL_TABLE_BA);
3251                         continue;
3252                 }
3253
3254                 DUMPREG(i, DISPC_OVL_FIR);
3255                 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3256                 DUMPREG(i, DISPC_OVL_ACCU0);
3257                 DUMPREG(i, DISPC_OVL_ACCU1);
3258                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3259                         DUMPREG(i, DISPC_OVL_BA0_UV);
3260                         DUMPREG(i, DISPC_OVL_BA1_UV);
3261                         DUMPREG(i, DISPC_OVL_FIR2);
3262                         DUMPREG(i, DISPC_OVL_ACCU2_0);
3263                         DUMPREG(i, DISPC_OVL_ACCU2_1);
3264                 }
3265                 if (dss_has_feature(FEAT_ATTR2))
3266                         DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3267                 if (dss_has_feature(FEAT_PRELOAD))
3268                         DUMPREG(i, DISPC_OVL_PRELOAD);
3269         }
3270
3271 #undef DISPC_REG
3272 #undef DUMPREG
3273
3274 #define DISPC_REG(plane, name, i) name(plane, i)
3275 #define DUMPREG(plane, name, i) \
3276         seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
3277         (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \
3278         dispc_read_reg(DISPC_REG(plane, name, i)))
3279
3280         /* Video pipeline coefficient registers */
3281
3282         /* start from OMAP_DSS_VIDEO1 */
3283         for (i = 1; i < dss_feat_get_num_ovls(); i++) {
3284                 for (j = 0; j < 8; j++)
3285                         DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
3286
3287                 for (j = 0; j < 8; j++)
3288                         DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
3289
3290                 for (j = 0; j < 5; j++)
3291                         DUMPREG(i, DISPC_OVL_CONV_COEF, j);
3292
3293                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
3294                         for (j = 0; j < 8; j++)
3295                                 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
3296                 }
3297
3298                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3299                         for (j = 0; j < 8; j++)
3300                                 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
3301
3302                         for (j = 0; j < 8; j++)
3303                                 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
3304
3305                         for (j = 0; j < 8; j++)
3306                                 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
3307                 }
3308         }
3309
3310         dispc_runtime_put();
3311
3312 #undef DISPC_REG
3313 #undef DUMPREG
3314 }
3315
3316 /* with fck as input clock rate, find dispc dividers that produce req_pck */
3317 void dispc_find_clk_divs(unsigned long req_pck, unsigned long fck,
3318                 struct dispc_clock_info *cinfo)
3319 {
3320         u16 pcd_min, pcd_max;
3321         unsigned long best_pck;
3322         u16 best_ld, cur_ld;
3323         u16 best_pd, cur_pd;
3324
3325         pcd_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
3326         pcd_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
3327
3328         best_pck = 0;
3329         best_ld = 0;
3330         best_pd = 0;
3331
3332         for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
3333                 unsigned long lck = fck / cur_ld;
3334
3335                 for (cur_pd = pcd_min; cur_pd <= pcd_max; ++cur_pd) {
3336                         unsigned long pck = lck / cur_pd;
3337                         long old_delta = abs(best_pck - req_pck);
3338                         long new_delta = abs(pck - req_pck);
3339
3340                         if (best_pck == 0 || new_delta < old_delta) {
3341                                 best_pck = pck;
3342                                 best_ld = cur_ld;
3343                                 best_pd = cur_pd;
3344
3345                                 if (pck == req_pck)
3346                                         goto found;
3347                         }
3348
3349                         if (pck < req_pck)
3350                                 break;
3351                 }
3352
3353                 if (lck / pcd_min < req_pck)
3354                         break;
3355         }
3356
3357 found:
3358         cinfo->lck_div = best_ld;
3359         cinfo->pck_div = best_pd;
3360         cinfo->lck = fck / cinfo->lck_div;
3361         cinfo->pck = cinfo->lck / cinfo->pck_div;
3362 }
3363
3364 /* calculate clock rates using dividers in cinfo */
3365 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
3366                 struct dispc_clock_info *cinfo)
3367 {
3368         if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3369                 return -EINVAL;
3370         if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
3371                 return -EINVAL;
3372
3373         cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3374         cinfo->pck = cinfo->lck / cinfo->pck_div;
3375
3376         return 0;
3377 }
3378
3379 void dispc_mgr_set_clock_div(enum omap_channel channel,
3380                 const struct dispc_clock_info *cinfo)
3381 {
3382         DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3383         DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3384
3385         dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
3386 }
3387
3388 int dispc_mgr_get_clock_div(enum omap_channel channel,
3389                 struct dispc_clock_info *cinfo)
3390 {
3391         unsigned long fck;
3392
3393         fck = dispc_fclk_rate();
3394
3395         cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3396         cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
3397
3398         cinfo->lck = fck / cinfo->lck_div;
3399         cinfo->pck = cinfo->lck / cinfo->pck_div;
3400
3401         return 0;
3402 }
3403
3404 u32 dispc_read_irqstatus(void)
3405 {
3406         return dispc_read_reg(DISPC_IRQSTATUS);
3407 }
3408 EXPORT_SYMBOL(dispc_read_irqstatus);
3409
3410 void dispc_clear_irqstatus(u32 mask)
3411 {
3412         dispc_write_reg(DISPC_IRQSTATUS, mask);
3413 }
3414 EXPORT_SYMBOL(dispc_clear_irqstatus);
3415
3416 u32 dispc_read_irqenable(void)
3417 {
3418         return dispc_read_reg(DISPC_IRQENABLE);
3419 }
3420 EXPORT_SYMBOL(dispc_read_irqenable);
3421
3422 void dispc_write_irqenable(u32 mask)
3423 {
3424         u32 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3425
3426         /* clear the irqstatus for newly enabled irqs */
3427         dispc_clear_irqstatus((mask ^ old_mask) & mask);
3428
3429         dispc_write_reg(DISPC_IRQENABLE, mask);
3430 }
3431 EXPORT_SYMBOL(dispc_write_irqenable);
3432
3433 void dispc_enable_sidle(void)
3434 {
3435         REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3);  /* SIDLEMODE: smart idle */
3436 }
3437
3438 void dispc_disable_sidle(void)
3439 {
3440         REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3);  /* SIDLEMODE: no idle */
3441 }
3442
3443 static void _omap_dispc_initial_config(void)
3444 {
3445         u32 l;
3446
3447         /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3448         if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3449                 l = dispc_read_reg(DISPC_DIVISOR);
3450                 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3451                 l = FLD_MOD(l, 1, 0, 0);
3452                 l = FLD_MOD(l, 1, 23, 16);
3453                 dispc_write_reg(DISPC_DIVISOR, l);
3454         }
3455
3456         /* FUNCGATED */
3457         if (dss_has_feature(FEAT_FUNCGATED))
3458                 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3459
3460         dispc_setup_color_conv_coef();
3461
3462         dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3463
3464         dispc_init_fifos();
3465
3466         dispc_configure_burst_sizes();
3467
3468         dispc_ovl_enable_zorder_planes();
3469 }
3470
3471 static const struct dispc_features omap24xx_dispc_feats __initconst = {
3472         .sw_start               =       5,
3473         .fp_start               =       15,
3474         .bp_start               =       27,
3475         .sw_max                 =       64,
3476         .vp_max                 =       255,
3477         .hp_max                 =       256,
3478         .mgr_width_start        =       10,
3479         .mgr_height_start       =       26,
3480         .mgr_width_max          =       2048,
3481         .mgr_height_max         =       2048,
3482         .calc_scaling           =       dispc_ovl_calc_scaling_24xx,
3483         .calc_core_clk          =       calc_core_clk_24xx,
3484         .num_fifos              =       3,
3485         .no_framedone_tv        =       true,
3486 };
3487
3488 static const struct dispc_features omap34xx_rev1_0_dispc_feats __initconst = {
3489         .sw_start               =       5,
3490         .fp_start               =       15,
3491         .bp_start               =       27,
3492         .sw_max                 =       64,
3493         .vp_max                 =       255,
3494         .hp_max                 =       256,
3495         .mgr_width_start        =       10,
3496         .mgr_height_start       =       26,
3497         .mgr_width_max          =       2048,
3498         .mgr_height_max         =       2048,
3499         .calc_scaling           =       dispc_ovl_calc_scaling_34xx,
3500         .calc_core_clk          =       calc_core_clk_34xx,
3501         .num_fifos              =       3,
3502         .no_framedone_tv        =       true,
3503 };
3504
3505 static const struct dispc_features omap34xx_rev3_0_dispc_feats __initconst = {
3506         .sw_start               =       7,
3507         .fp_start               =       19,
3508         .bp_start               =       31,
3509         .sw_max                 =       256,
3510         .vp_max                 =       4095,
3511         .hp_max                 =       4096,
3512         .mgr_width_start        =       10,
3513         .mgr_height_start       =       26,
3514         .mgr_width_max          =       2048,
3515         .mgr_height_max         =       2048,
3516         .calc_scaling           =       dispc_ovl_calc_scaling_34xx,
3517         .calc_core_clk          =       calc_core_clk_34xx,
3518         .num_fifos              =       3,
3519         .no_framedone_tv        =       true,
3520 };
3521
3522 static const struct dispc_features omap44xx_dispc_feats __initconst = {
3523         .sw_start               =       7,
3524         .fp_start               =       19,
3525         .bp_start               =       31,
3526         .sw_max                 =       256,
3527         .vp_max                 =       4095,
3528         .hp_max                 =       4096,
3529         .mgr_width_start        =       10,
3530         .mgr_height_start       =       26,
3531         .mgr_width_max          =       2048,
3532         .mgr_height_max         =       2048,
3533         .calc_scaling           =       dispc_ovl_calc_scaling_44xx,
3534         .calc_core_clk          =       calc_core_clk_44xx,
3535         .num_fifos              =       5,
3536         .gfx_fifo_workaround    =       true,
3537 };
3538
3539 static const struct dispc_features omap54xx_dispc_feats __initconst = {
3540         .sw_start               =       7,
3541         .fp_start               =       19,
3542         .bp_start               =       31,
3543         .sw_max                 =       256,
3544         .vp_max                 =       4095,
3545         .hp_max                 =       4096,
3546         .mgr_width_start        =       11,
3547         .mgr_height_start       =       27,
3548         .mgr_width_max          =       4096,
3549         .mgr_height_max         =       4096,
3550         .calc_scaling           =       dispc_ovl_calc_scaling_44xx,
3551         .calc_core_clk          =       calc_core_clk_44xx,
3552         .num_fifos              =       5,
3553         .gfx_fifo_workaround    =       true,
3554 };
3555
3556 static int __init dispc_init_features(struct platform_device *pdev)
3557 {
3558         const struct dispc_features *src;
3559         struct dispc_features *dst;
3560
3561         dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL);
3562         if (!dst) {
3563                 dev_err(&pdev->dev, "Failed to allocate DISPC Features\n");
3564                 return -ENOMEM;
3565         }
3566
3567         switch (omapdss_get_version()) {
3568         case OMAPDSS_VER_OMAP24xx:
3569                 src = &omap24xx_dispc_feats;
3570                 break;
3571
3572         case OMAPDSS_VER_OMAP34xx_ES1:
3573                 src = &omap34xx_rev1_0_dispc_feats;
3574                 break;
3575
3576         case OMAPDSS_VER_OMAP34xx_ES3:
3577         case OMAPDSS_VER_OMAP3630:
3578         case OMAPDSS_VER_AM35xx:
3579                 src = &omap34xx_rev3_0_dispc_feats;
3580                 break;
3581
3582         case OMAPDSS_VER_OMAP4430_ES1:
3583         case OMAPDSS_VER_OMAP4430_ES2:
3584         case OMAPDSS_VER_OMAP4:
3585                 src = &omap44xx_dispc_feats;
3586                 break;
3587
3588         case OMAPDSS_VER_OMAP5:
3589                 src = &omap54xx_dispc_feats;
3590                 break;
3591
3592         default:
3593                 return -ENODEV;
3594         }
3595
3596         memcpy(dst, src, sizeof(*dst));
3597         dispc.feat = dst;
3598
3599         return 0;
3600 }
3601
3602 int dispc_request_irq(irq_handler_t handler, void *dev_id)
3603 {
3604         return devm_request_irq(&dispc.pdev->dev, dispc.irq, handler,
3605                              IRQF_SHARED, "OMAP DISPC", dev_id);
3606 }
3607 EXPORT_SYMBOL(dispc_request_irq);
3608
3609 void dispc_free_irq(void *dev_id)
3610 {
3611         devm_free_irq(&dispc.pdev->dev, dispc.irq, dev_id);
3612 }
3613 EXPORT_SYMBOL(dispc_free_irq);
3614
3615 /* DISPC HW IP initialisation */
3616 static int __init omap_dispchw_probe(struct platform_device *pdev)
3617 {
3618         u32 rev;
3619         int r = 0;
3620         struct resource *dispc_mem;
3621
3622         dispc.pdev = pdev;
3623
3624         r = dispc_init_features(dispc.pdev);
3625         if (r)
3626                 return r;
3627
3628         dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3629         if (!dispc_mem) {
3630                 DSSERR("can't get IORESOURCE_MEM DISPC\n");
3631                 return -EINVAL;
3632         }
3633
3634         dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
3635                                   resource_size(dispc_mem));
3636         if (!dispc.base) {
3637                 DSSERR("can't ioremap DISPC\n");
3638                 return -ENOMEM;
3639         }
3640
3641         dispc.irq = platform_get_irq(dispc.pdev, 0);
3642         if (dispc.irq < 0) {
3643                 DSSERR("platform_get_irq failed\n");
3644                 return -ENODEV;
3645         }
3646
3647         pm_runtime_enable(&pdev->dev);
3648
3649         r = dispc_runtime_get();
3650         if (r)
3651                 goto err_runtime_get;
3652
3653         _omap_dispc_initial_config();
3654
3655         rev = dispc_read_reg(DISPC_REVISION);
3656         dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
3657                FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3658
3659         dispc_runtime_put();
3660
3661         dss_debugfs_create_file("dispc", dispc_dump_regs);
3662
3663         return 0;
3664
3665 err_runtime_get:
3666         pm_runtime_disable(&pdev->dev);
3667         return r;
3668 }
3669
3670 static int __exit omap_dispchw_remove(struct platform_device *pdev)
3671 {
3672         pm_runtime_disable(&pdev->dev);
3673
3674         return 0;
3675 }
3676
3677 static int dispc_runtime_suspend(struct device *dev)
3678 {
3679         dispc_save_context();
3680
3681         return 0;
3682 }
3683
3684 static int dispc_runtime_resume(struct device *dev)
3685 {
3686         dispc_restore_context();
3687
3688         return 0;
3689 }
3690
3691 static const struct dev_pm_ops dispc_pm_ops = {
3692         .runtime_suspend = dispc_runtime_suspend,
3693         .runtime_resume = dispc_runtime_resume,
3694 };
3695
3696 static struct platform_driver omap_dispchw_driver = {
3697         .remove         = __exit_p(omap_dispchw_remove),
3698         .driver         = {
3699                 .name   = "omapdss_dispc",
3700                 .owner  = THIS_MODULE,
3701                 .pm     = &dispc_pm_ops,
3702         },
3703 };
3704
3705 int __init dispc_init_platform_driver(void)
3706 {
3707         return platform_driver_probe(&omap_dispchw_driver, omap_dispchw_probe);
3708 }
3709
3710 void __exit dispc_uninit_platform_driver(void)
3711 {
3712         platform_driver_unregister(&omap_dispchw_driver);
3713 }