drivers/video/omap2/dss/dispc.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dispc.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #define DSS_SUBSYS_NAME "DISPC"
  24
  25 #include <linux/kernel.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/vmalloc.h>
  28 #include <linux/clk.h>
  29 #include <linux/io.h>
  30 #include <linux/jiffies.h>
  31 #include <linux/seq_file.h>
  32 #include <linux/delay.h>
  33 #include <linux/workqueue.h>
  34 #include <linux/hardirq.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/platform_device.h>
  37 #include <linux/pm_runtime.h>
  38
  39 #include <plat/sram.h>
  40 #include <plat/clock.h>
  41
  42 #include <video/omapdss.h>
  43
  44 #include "dss.h"
  45 #include "dss_features.h"
  46 #include "dispc.h"
  47
  48 /* DISPC */
  49 #define DISPC_SZ_REGS                   SZ_4K
  50
  51 #define DISPC_IRQ_MASK_ERROR            (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
  52                                          DISPC_IRQ_OCP_ERR | \
  53                                          DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
  54                                          DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
  55                                          DISPC_IRQ_SYNC_LOST | \
  56                                          DISPC_IRQ_SYNC_LOST_DIGIT)
  57
  58 #define DISPC_MAX_NR_ISRS               8
  59
  60 struct omap_dispc_isr_data {
  61         omap_dispc_isr_t        isr;
  62         void                    *arg;
  63         u32                     mask;
  64 };
  65
  66 struct dispc_h_coef {
  67         s8 hc4;
  68         s8 hc3;
  69         u8 hc2;
  70         s8 hc1;
  71         s8 hc0;
  72 };
  73
  74 struct dispc_v_coef {
  75         s8 vc22;
  76         s8 vc2;
  77         u8 vc1;
  78         s8 vc0;
  79         s8 vc00;
  80 };
  81
  82 enum omap_burst_size {
  83         BURST_SIZE_X2 = 0,
  84         BURST_SIZE_X4 = 1,
  85         BURST_SIZE_X8 = 2,
  86 };
  87
  88 #define REG_GET(idx, start, end) \
  89         FLD_GET(dispc_read_reg(idx), start, end)
  90
  91 #define REG_FLD_MOD(idx, val, start, end)                               \
  92         dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
  93
  94 struct dispc_irq_stats {
  95         unsigned long last_reset;
  96         unsigned irq_count;
  97         unsigned irqs[32];
  98 };
  99
 100 static struct {
 101         struct platform_device *pdev;
 102         void __iomem    *base;
 103
 104         int             ctx_loss_cnt;
 105
 106         int irq;
 107         struct clk *dss_clk;
 108
 109         u32     fifo_size[MAX_DSS_OVERLAYS];
 110
 111         spinlock_t irq_lock;
 112         u32 irq_error_mask;
 113         struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
 114         u32 error_irqs;
 115         struct work_struct error_work;
 116
 117         bool            ctx_valid;
 118         u32             ctx[DISPC_SZ_REGS / sizeof(u32)];
 119
 120 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
 121         spinlock_t irq_stats_lock;
 122         struct dispc_irq_stats irq_stats;
 123 #endif
 124 } dispc;
 125
 126 enum omap_color_component {
 127         /* used for all color formats for OMAP3 and earlier
 128          * and for RGB and Y color component on OMAP4
 129          */
 130         DISPC_COLOR_COMPONENT_RGB_Y             = 1 << 0,
 131         /* used for UV component for
 132          * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
 133          * color formats on OMAP4
 134          */
 135         DISPC_COLOR_COMPONENT_UV                = 1 << 1,
 136 };
 137
 138 static void _omap_dispc_set_irqs(void);
 139
 140 static inline void dispc_write_reg(const u16 idx, u32 val)
 141 {
 142         __raw_writel(val, dispc.base + idx);
 143 }
 144
 145 static inline u32 dispc_read_reg(const u16 idx)
 146 {
 147         return __raw_readl(dispc.base + idx);
 148 }
 149
 150 static int dispc_get_ctx_loss_count(void)
 151 {
 152         struct device *dev = &dispc.pdev->dev;
 153         struct omap_display_platform_data *pdata = dev->platform_data;
 154         struct omap_dss_board_info *board_data = pdata->board_data;
 155         int cnt;
 156
 157         if (!board_data->get_context_loss_count)
 158                 return -ENOENT;
 159
 160         cnt = board_data->get_context_loss_count(dev);
 161
 162         WARN_ONCE(cnt < 0, "get_context_loss_count failed: %d\n", cnt);
 163
 164         return cnt;
 165 }
 166
 167 #define SR(reg) \
 168         dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
 169 #define RR(reg) \
 170         dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
 171
 172 static void dispc_save_context(void)
 173 {
 174         int i, j;
 175
 176         DSSDBG("dispc_save_context\n");
 177
 178         SR(IRQENABLE);
 179         SR(CONTROL);
 180         SR(CONFIG);
 181         SR(LINE_NUMBER);
 182         if (dss_has_feature(FEAT_GLOBAL_ALPHA))
 183                 SR(GLOBAL_ALPHA);
 184         if (dss_has_feature(FEAT_MGR_LCD2)) {
 185                 SR(CONTROL2);
 186                 SR(CONFIG2);
 187         }
 188
 189         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
 190                 SR(DEFAULT_COLOR(i));
 191                 SR(TRANS_COLOR(i));
 192                 SR(SIZE_MGR(i));
 193                 if (i == OMAP_DSS_CHANNEL_DIGIT)
 194                         continue;
 195                 SR(TIMING_H(i));
 196                 SR(TIMING_V(i));
 197                 SR(POL_FREQ(i));
 198                 SR(DIVISORo(i));
 199
 200                 SR(DATA_CYCLE1(i));
 201                 SR(DATA_CYCLE2(i));
 202                 SR(DATA_CYCLE3(i));
 203
 204                 if (dss_has_feature(FEAT_CPR)) {
 205                         SR(CPR_COEF_R(i));
 206                         SR(CPR_COEF_G(i));
 207                         SR(CPR_COEF_B(i));
 208                 }
 209         }
 210
 211         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
 212                 SR(OVL_BA0(i));
 213                 SR(OVL_BA1(i));
 214                 SR(OVL_POSITION(i));
 215                 SR(OVL_SIZE(i));
 216                 SR(OVL_ATTRIBUTES(i));
 217                 SR(OVL_FIFO_THRESHOLD(i));
 218                 SR(OVL_ROW_INC(i));
 219                 SR(OVL_PIXEL_INC(i));
 220                 if (dss_has_feature(FEAT_PRELOAD))
 221                         SR(OVL_PRELOAD(i));
 222                 if (i == OMAP_DSS_GFX) {
 223                         SR(OVL_WINDOW_SKIP(i));
 224                         SR(OVL_TABLE_BA(i));
 225                         continue;
 226                 }
 227                 SR(OVL_FIR(i));
 228                 SR(OVL_PICTURE_SIZE(i));
 229                 SR(OVL_ACCU0(i));
 230                 SR(OVL_ACCU1(i));
 231
 232                 for (j = 0; j < 8; j++)
 233                         SR(OVL_FIR_COEF_H(i, j));
 234
 235                 for (j = 0; j < 8; j++)
 236                         SR(OVL_FIR_COEF_HV(i, j));
 237
 238                 for (j = 0; j < 5; j++)
 239                         SR(OVL_CONV_COEF(i, j));
 240
 241                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
 242                         for (j = 0; j < 8; j++)
 243                                 SR(OVL_FIR_COEF_V(i, j));
 244                 }
 245
 246                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
 247                         SR(OVL_BA0_UV(i));
 248                         SR(OVL_BA1_UV(i));
 249                         SR(OVL_FIR2(i));
 250                         SR(OVL_ACCU2_0(i));
 251                         SR(OVL_ACCU2_1(i));
 252
 253                         for (j = 0; j < 8; j++)
 254                                 SR(OVL_FIR_COEF_H2(i, j));
 255
 256                         for (j = 0; j < 8; j++)
 257                                 SR(OVL_FIR_COEF_HV2(i, j));
 258
 259                         for (j = 0; j < 8; j++)
 260                                 SR(OVL_FIR_COEF_V2(i, j));
 261                 }
 262                 if (dss_has_feature(FEAT_ATTR2))
 263                         SR(OVL_ATTRIBUTES2(i));
 264         }
 265
 266         if (dss_has_feature(FEAT_CORE_CLK_DIV))
 267                 SR(DIVISOR);
 268
 269         dispc.ctx_loss_cnt = dispc_get_ctx_loss_count();
 270         dispc.ctx_valid = true;
 271
 272         DSSDBG("context saved, ctx_loss_count %d\n", dispc.ctx_loss_cnt);
 273 }
 274
 275 static void dispc_restore_context(void)
 276 {
 277         int i, j, ctx;
 278
 279         DSSDBG("dispc_restore_context\n");
 280
 281         if (!dispc.ctx_valid)
 282                 return;
 283
 284         ctx = dispc_get_ctx_loss_count();
 285
 286         if (ctx >= 0 && ctx == dispc.ctx_loss_cnt)
 287                 return;
 288
 289         DSSDBG("ctx_loss_count: saved %d, current %d\n",
 290                         dispc.ctx_loss_cnt, ctx);
 291
 292         /*RR(IRQENABLE);*/
 293         /*RR(CONTROL);*/
 294         RR(CONFIG);
 295         RR(LINE_NUMBER);
 296         if (dss_has_feature(FEAT_GLOBAL_ALPHA))
 297                 RR(GLOBAL_ALPHA);
 298         if (dss_has_feature(FEAT_MGR_LCD2))
 299                 RR(CONFIG2);
 300
 301         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
 302                 RR(DEFAULT_COLOR(i));
 303                 RR(TRANS_COLOR(i));
 304                 RR(SIZE_MGR(i));
 305                 if (i == OMAP_DSS_CHANNEL_DIGIT)
 306                         continue;
 307                 RR(TIMING_H(i));
 308                 RR(TIMING_V(i));
 309                 RR(POL_FREQ(i));
 310                 RR(DIVISORo(i));
 311
 312                 RR(DATA_CYCLE1(i));
 313                 RR(DATA_CYCLE2(i));
 314                 RR(DATA_CYCLE3(i));
 315
 316                 if (dss_has_feature(FEAT_CPR)) {
 317                         RR(CPR_COEF_R(i));
 318                         RR(CPR_COEF_G(i));
 319                         RR(CPR_COEF_B(i));
 320                 }
 321         }
 322
 323         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
 324                 RR(OVL_BA0(i));
 325                 RR(OVL_BA1(i));
 326                 RR(OVL_POSITION(i));
 327                 RR(OVL_SIZE(i));
 328                 RR(OVL_ATTRIBUTES(i));
 329                 RR(OVL_FIFO_THRESHOLD(i));
 330                 RR(OVL_ROW_INC(i));
 331                 RR(OVL_PIXEL_INC(i));
 332                 if (dss_has_feature(FEAT_PRELOAD))
 333                         RR(OVL_PRELOAD(i));
 334                 if (i == OMAP_DSS_GFX) {
 335                         RR(OVL_WINDOW_SKIP(i));
 336                         RR(OVL_TABLE_BA(i));
 337                         continue;
 338                 }
 339                 RR(OVL_FIR(i));
 340                 RR(OVL_PICTURE_SIZE(i));
 341                 RR(OVL_ACCU0(i));
 342                 RR(OVL_ACCU1(i));
 343
 344                 for (j = 0; j < 8; j++)
 345                         RR(OVL_FIR_COEF_H(i, j));
 346
 347                 for (j = 0; j < 8; j++)
 348                         RR(OVL_FIR_COEF_HV(i, j));
 349
 350                 for (j = 0; j < 5; j++)
 351                         RR(OVL_CONV_COEF(i, j));
 352
 353                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
 354                         for (j = 0; j < 8; j++)
 355                                 RR(OVL_FIR_COEF_V(i, j));
 356                 }
 357
 358                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
 359                         RR(OVL_BA0_UV(i));
 360                         RR(OVL_BA1_UV(i));
 361                         RR(OVL_FIR2(i));
 362                         RR(OVL_ACCU2_0(i));
 363                         RR(OVL_ACCU2_1(i));
 364
 365                         for (j = 0; j < 8; j++)
 366                                 RR(OVL_FIR_COEF_H2(i, j));
 367
 368                         for (j = 0; j < 8; j++)
 369                                 RR(OVL_FIR_COEF_HV2(i, j));
 370
 371                         for (j = 0; j < 8; j++)
 372                                 RR(OVL_FIR_COEF_V2(i, j));
 373                 }
 374                 if (dss_has_feature(FEAT_ATTR2))
 375                         RR(OVL_ATTRIBUTES2(i));
 376         }
 377
 378         if (dss_has_feature(FEAT_CORE_CLK_DIV))
 379                 RR(DIVISOR);
 380
 381         /* enable last, because LCD & DIGIT enable are here */
 382         RR(CONTROL);
 383         if (dss_has_feature(FEAT_MGR_LCD2))
 384                 RR(CONTROL2);
 385         /* clear spurious SYNC_LOST_DIGIT interrupts */
 386         dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
 387
 388         /*
 389          * enable last so IRQs won't trigger before
 390          * the context is fully restored
 391          */
 392         RR(IRQENABLE);
 393
 394         DSSDBG("context restored\n");
 395 }
 396
 397 #undef SR
 398 #undef RR
 399
 400 int dispc_runtime_get(void)
 401 {
 402         int r;
 403
 404         DSSDBG("dispc_runtime_get\n");
 405
 406         r = pm_runtime_get_sync(&dispc.pdev->dev);
 407         WARN_ON(r < 0);
 408         return r < 0 ? r : 0;
 409 }
 410
 411 void dispc_runtime_put(void)
 412 {
 413         int r;
 414
 415         DSSDBG("dispc_runtime_put\n");
 416
 417         r = pm_runtime_put(&dispc.pdev->dev);
 418         WARN_ON(r < 0);
 419 }
 420
 421
 422 bool dispc_go_busy(enum omap_channel channel)
 423 {
 424         int bit;
 425
 426         if (channel == OMAP_DSS_CHANNEL_LCD ||
 427                         channel == OMAP_DSS_CHANNEL_LCD2)
 428                 bit = 5; /* GOLCD */
 429         else
 430                 bit = 6; /* GODIGIT */
 431
 432         if (channel == OMAP_DSS_CHANNEL_LCD2)
 433                 return REG_GET(DISPC_CONTROL2, bit, bit) == 1;
 434         else
 435                 return REG_GET(DISPC_CONTROL, bit, bit) == 1;
 436 }
 437
 438 void dispc_go(enum omap_channel channel)
 439 {
 440         int bit;
 441         bool enable_bit, go_bit;
 442
 443         if (channel == OMAP_DSS_CHANNEL_LCD ||
 444                         channel == OMAP_DSS_CHANNEL_LCD2)
 445                 bit = 0; /* LCDENABLE */
 446         else
 447                 bit = 1; /* DIGITALENABLE */
 448
 449         /* if the channel is not enabled, we don't need GO */
 450         if (channel == OMAP_DSS_CHANNEL_LCD2)
 451                 enable_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
 452         else
 453                 enable_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
 454
 455         if (!enable_bit)
 456                 return;
 457
 458         if (channel == OMAP_DSS_CHANNEL_LCD ||
 459                         channel == OMAP_DSS_CHANNEL_LCD2)
 460                 bit = 5; /* GOLCD */
 461         else
 462                 bit = 6; /* GODIGIT */
 463
 464         if (channel == OMAP_DSS_CHANNEL_LCD2)
 465                 go_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
 466         else
 467                 go_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
 468
 469         if (go_bit) {
 470                 DSSERR("GO bit not down for channel %d\n", channel);
 471                 return;
 472         }
 473
 474         DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" :
 475                 (channel == OMAP_DSS_CHANNEL_LCD2 ? "LCD2" : "DIGIT"));
 476
 477         if (channel == OMAP_DSS_CHANNEL_LCD2)
 478                 REG_FLD_MOD(DISPC_CONTROL2, 1, bit, bit);
 479         else
 480                 REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
 481 }
 482
 483 static void _dispc_write_firh_reg(enum omap_plane plane, int reg, u32 value)
 484 {
 485         dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
 486 }
 487
 488 static void _dispc_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
 489 {
 490         dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
 491 }
 492
 493 static void _dispc_write_firv_reg(enum omap_plane plane, int reg, u32 value)
 494 {
 495         dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
 496 }
 497
 498 static void _dispc_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
 499 {
 500         BUG_ON(plane == OMAP_DSS_GFX);
 501
 502         dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
 503 }
 504
 505 static void _dispc_write_firhv2_reg(enum omap_plane plane, int reg, u32 value)
 506 {
 507         BUG_ON(plane == OMAP_DSS_GFX);
 508
 509         dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
 510 }
 511
 512 static void _dispc_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
 513 {
 514         BUG_ON(plane == OMAP_DSS_GFX);
 515
 516         dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
 517 }
 518
 519 static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup,
 520                                   int vscaleup, int five_taps,
 521                                   enum omap_color_component color_comp)
 522 {
 523         /* Coefficients for horizontal up-sampling */
 524         static const struct dispc_h_coef coef_hup[8] = {
 525                 {  0,   0, 128,   0,  0 },
 526                 { -1,  13, 124,  -8,  0 },
 527                 { -2,  30, 112, -11, -1 },
 528                 { -5,  51,  95, -11, -2 },
 529                 {  0,  -9,  73,  73, -9 },
 530                 { -2, -11,  95,  51, -5 },
 531                 { -1, -11, 112,  30, -2 },
 532                 {  0,  -8, 124,  13, -1 },
 533         };
 534
 535         /* Coefficients for vertical up-sampling */
 536         static const struct dispc_v_coef coef_vup_3tap[8] = {
 537                 { 0,  0, 128,  0, 0 },
 538                 { 0,  3, 123,  2, 0 },
 539                 { 0, 12, 111,  5, 0 },
 540                 { 0, 32,  89,  7, 0 },
 541                 { 0,  0,  64, 64, 0 },
 542                 { 0,  7,  89, 32, 0 },
 543                 { 0,  5, 111, 12, 0 },
 544                 { 0,  2, 123,  3, 0 },
 545         };
 546
 547         static const struct dispc_v_coef coef_vup_5tap[8] = {
 548                 {  0,   0, 128,   0,  0 },
 549                 { -1,  13, 124,  -8,  0 },
 550                 { -2,  30, 112, -11, -1 },
 551                 { -5,  51,  95, -11, -2 },
 552                 {  0,  -9,  73,  73, -9 },
 553                 { -2, -11,  95,  51, -5 },
 554                 { -1, -11, 112,  30, -2 },
 555                 {  0,  -8, 124,  13, -1 },
 556         };
 557
 558         /* Coefficients for horizontal down-sampling */
 559         static const struct dispc_h_coef coef_hdown[8] = {
 560                 {   0, 36, 56, 36,  0 },
 561                 {   4, 40, 55, 31, -2 },
 562                 {   8, 44, 54, 27, -5 },
 563                 {  12, 48, 53, 22, -7 },
 564                 {  -9, 17, 52, 51, 17 },
 565                 {  -7, 22, 53, 48, 12 },
 566                 {  -5, 27, 54, 44,  8 },
 567                 {  -2, 31, 55, 40,  4 },
 568         };
 569
 570         /* Coefficients for vertical down-sampling */
 571         static const struct dispc_v_coef coef_vdown_3tap[8] = {
 572                 { 0, 36, 56, 36, 0 },
 573                 { 0, 40, 57, 31, 0 },
 574                 { 0, 45, 56, 27, 0 },
 575                 { 0, 50, 55, 23, 0 },
 576                 { 0, 18, 55, 55, 0 },
 577                 { 0, 23, 55, 50, 0 },
 578                 { 0, 27, 56, 45, 0 },
 579                 { 0, 31, 57, 40, 0 },
 580         };
 581
 582         static const struct dispc_v_coef coef_vdown_5tap[8] = {
 583                 {   0, 36, 56, 36,  0 },
 584                 {   4, 40, 55, 31, -2 },
 585                 {   8, 44, 54, 27, -5 },
 586                 {  12, 48, 53, 22, -7 },
 587                 {  -9, 17, 52, 51, 17 },
 588                 {  -7, 22, 53, 48, 12 },
 589                 {  -5, 27, 54, 44,  8 },
 590                 {  -2, 31, 55, 40,  4 },
 591         };
 592
 593         const struct dispc_h_coef *h_coef;
 594         const struct dispc_v_coef *v_coef;
 595         int i;
 596
 597         if (hscaleup)
 598                 h_coef = coef_hup;
 599         else
 600                 h_coef = coef_hdown;
 601
 602         if (vscaleup)
 603                 v_coef = five_taps ? coef_vup_5tap : coef_vup_3tap;
 604         else
 605                 v_coef = five_taps ? coef_vdown_5tap : coef_vdown_3tap;
 606
 607         for (i = 0; i < 8; i++) {
 608                 u32 h, hv;
 609
 610                 h = FLD_VAL(h_coef[i].hc0, 7, 0)
 611                         | FLD_VAL(h_coef[i].hc1, 15, 8)
 612                         | FLD_VAL(h_coef[i].hc2, 23, 16)
 613                         | FLD_VAL(h_coef[i].hc3, 31, 24);
 614                 hv = FLD_VAL(h_coef[i].hc4, 7, 0)
 615                         | FLD_VAL(v_coef[i].vc0, 15, 8)
 616                         | FLD_VAL(v_coef[i].vc1, 23, 16)
 617                         | FLD_VAL(v_coef[i].vc2, 31, 24);
 618
 619                 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
 620                         _dispc_write_firh_reg(plane, i, h);
 621                         _dispc_write_firhv_reg(plane, i, hv);
 622                 } else {
 623                         _dispc_write_firh2_reg(plane, i, h);
 624                         _dispc_write_firhv2_reg(plane, i, hv);
 625                 }
 626
 627         }
 628
 629         if (five_taps) {
 630                 for (i = 0; i < 8; i++) {
 631                         u32 v;
 632                         v = FLD_VAL(v_coef[i].vc00, 7, 0)
 633                                 | FLD_VAL(v_coef[i].vc22, 15, 8);
 634                         if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
 635                                 _dispc_write_firv_reg(plane, i, v);
 636                         else
 637                                 _dispc_write_firv2_reg(plane, i, v);
 638                 }
 639         }
 640 }
 641
 642 static void _dispc_setup_color_conv_coef(void)
 643 {
 644         int i;
 645         const struct color_conv_coef {
 646                 int  ry,  rcr,  rcb,   gy,  gcr,  gcb,   by,  bcr,  bcb;
 647                 int  full_range;
 648         }  ctbl_bt601_5 = {
 649                 298,  409,    0,  298, -208, -100,  298,    0,  517, 0,
 650         };
 651
 652         const struct color_conv_coef *ct;
 653
 654 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
 655
 656         ct = &ctbl_bt601_5;
 657
 658         for (i = 1; i < dss_feat_get_num_ovls(); i++) {
 659                 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 0),
 660                         CVAL(ct->rcr, ct->ry));
 661                 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 1),
 662                         CVAL(ct->gy,  ct->rcb));
 663                 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 2),
 664                         CVAL(ct->gcb, ct->gcr));
 665                 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 3),
 666                         CVAL(ct->bcr, ct->by));
 667                 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 4),
 668                         CVAL(0, ct->bcb));
 669
 670                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), ct->full_range,
 671                         11, 11);
 672         }
 673
 674 #undef CVAL
 675 }
 676
 677
 678 static void _dispc_set_plane_ba0(enum omap_plane plane, u32 paddr)
 679 {
 680         dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
 681 }
 682
 683 static void _dispc_set_plane_ba1(enum omap_plane plane, u32 paddr)
 684 {
 685         dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
 686 }
 687
 688 static void _dispc_set_plane_ba0_uv(enum omap_plane plane, u32 paddr)
 689 {
 690         dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
 691 }
 692
 693 static void _dispc_set_plane_ba1_uv(enum omap_plane plane, u32 paddr)
 694 {
 695         dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
 696 }
 697
 698 static void _dispc_set_plane_pos(enum omap_plane plane, int x, int y)
 699 {
 700         u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
 701
 702         dispc_write_reg(DISPC_OVL_POSITION(plane), val);
 703 }
 704
 705 static void _dispc_set_pic_size(enum omap_plane plane, int width, int height)
 706 {
 707         u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 708
 709         if (plane == OMAP_DSS_GFX)
 710                 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
 711         else
 712                 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
 713 }
 714
 715 static void _dispc_set_vid_size(enum omap_plane plane, int width, int height)
 716 {
 717         u32 val;
 718
 719         BUG_ON(plane == OMAP_DSS_GFX);
 720
 721         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 722
 723         dispc_write_reg(DISPC_OVL_SIZE(plane), val);
 724 }
 725
 726 static void _dispc_set_pre_mult_alpha(enum omap_plane plane, bool enable)
 727 {
 728         struct omap_overlay *ovl = omap_dss_get_overlay(plane);
 729
 730         if ((ovl->caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
 731                 return;
 732
 733         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
 734 }
 735
 736 static void _dispc_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
 737 {
 738         static const unsigned shifts[] = { 0, 8, 16, };
 739         int shift;
 740         struct omap_overlay *ovl = omap_dss_get_overlay(plane);
 741
 742         if ((ovl->caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
 743                 return;
 744
 745         shift = shifts[plane];
 746         REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
 747 }
 748
 749 static void _dispc_set_pix_inc(enum omap_plane plane, s32 inc)
 750 {
 751         dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
 752 }
 753
 754 static void _dispc_set_row_inc(enum omap_plane plane, s32 inc)
 755 {
 756         dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
 757 }
 758
 759 static void _dispc_set_color_mode(enum omap_plane plane,
 760                 enum omap_color_mode color_mode)
 761 {
 762         u32 m = 0;
 763         if (plane != OMAP_DSS_GFX) {
 764                 switch (color_mode) {
 765                 case OMAP_DSS_COLOR_NV12:
 766                         m = 0x0; break;
 767                 case OMAP_DSS_COLOR_RGB12U:
 768                         m = 0x1; break;
 769                 case OMAP_DSS_COLOR_RGBA16:
 770                         m = 0x2; break;
 771                 case OMAP_DSS_COLOR_RGBX16:
 772                         m = 0x4; break;
 773                 case OMAP_DSS_COLOR_ARGB16:
 774                         m = 0x5; break;
 775                 case OMAP_DSS_COLOR_RGB16:
 776                         m = 0x6; break;
 777                 case OMAP_DSS_COLOR_ARGB16_1555:
 778                         m = 0x7; break;
 779                 case OMAP_DSS_COLOR_RGB24U:
 780                         m = 0x8; break;
 781                 case OMAP_DSS_COLOR_RGB24P:
 782                         m = 0x9; break;
 783                 case OMAP_DSS_COLOR_YUV2:
 784                         m = 0xa; break;
 785                 case OMAP_DSS_COLOR_UYVY:
 786                         m = 0xb; break;
 787                 case OMAP_DSS_COLOR_ARGB32:
 788                         m = 0xc; break;
 789                 case OMAP_DSS_COLOR_RGBA32:
 790                         m = 0xd; break;
 791                 case OMAP_DSS_COLOR_RGBX32:
 792                         m = 0xe; break;
 793                 case OMAP_DSS_COLOR_XRGB16_1555:
 794                         m = 0xf; break;
 795                 default:
 796                         BUG(); break;
 797                 }
 798         } else {
 799                 switch (color_mode) {
 800                 case OMAP_DSS_COLOR_CLUT1:
 801                         m = 0x0; break;
 802                 case OMAP_DSS_COLOR_CLUT2:
 803                         m = 0x1; break;
 804                 case OMAP_DSS_COLOR_CLUT4:
 805                         m = 0x2; break;
 806                 case OMAP_DSS_COLOR_CLUT8:
 807                         m = 0x3; break;
 808                 case OMAP_DSS_COLOR_RGB12U:
 809                         m = 0x4; break;
 810                 case OMAP_DSS_COLOR_ARGB16:
 811                         m = 0x5; break;
 812                 case OMAP_DSS_COLOR_RGB16:
 813                         m = 0x6; break;
 814                 case OMAP_DSS_COLOR_ARGB16_1555:
 815                         m = 0x7; break;
 816                 case OMAP_DSS_COLOR_RGB24U:
 817                         m = 0x8; break;
 818                 case OMAP_DSS_COLOR_RGB24P:
 819                         m = 0x9; break;
 820                 case OMAP_DSS_COLOR_YUV2:
 821                         m = 0xa; break;
 822                 case OMAP_DSS_COLOR_UYVY:
 823                         m = 0xb; break;
 824                 case OMAP_DSS_COLOR_ARGB32:
 825                         m = 0xc; break;
 826                 case OMAP_DSS_COLOR_RGBA32:
 827                         m = 0xd; break;
 828                 case OMAP_DSS_COLOR_RGBX32:
 829                         m = 0xe; break;
 830                 case OMAP_DSS_COLOR_XRGB16_1555:
 831                         m = 0xf; break;
 832                 default:
 833                         BUG(); break;
 834                 }
 835         }
 836
 837         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
 838 }
 839
 840 static void dispc_set_channel_out(enum omap_plane plane,
 841                 enum omap_channel channel)
 842 {
 843         int shift;
 844         u32 val;
 845         int chan = 0, chan2 = 0;
 846
 847         switch (plane) {
 848         case OMAP_DSS_GFX:
 849                 shift = 8;
 850                 break;
 851         case OMAP_DSS_VIDEO1:
 852         case OMAP_DSS_VIDEO2:
 853                 shift = 16;
 854                 break;
 855         default:
 856                 BUG();
 857                 return;
 858         }
 859
 860         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
 861         if (dss_has_feature(FEAT_MGR_LCD2)) {
 862                 switch (channel) {
 863                 case OMAP_DSS_CHANNEL_LCD:
 864                         chan = 0;
 865                         chan2 = 0;
 866                         break;
 867                 case OMAP_DSS_CHANNEL_DIGIT:
 868                         chan = 1;
 869                         chan2 = 0;
 870                         break;
 871                 case OMAP_DSS_CHANNEL_LCD2:
 872                         chan = 0;
 873                         chan2 = 1;
 874                         break;
 875                 default:
 876                         BUG();
 877                 }
 878
 879                 val = FLD_MOD(val, chan, shift, shift);
 880                 val = FLD_MOD(val, chan2, 31, 30);
 881         } else {
 882                 val = FLD_MOD(val, channel, shift, shift);
 883         }
 884         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
 885 }
 886
 887 static void dispc_set_burst_size(enum omap_plane plane,
 888                 enum omap_burst_size burst_size)
 889 {
 890         static const unsigned shifts[] = { 6, 14, 14, };
 891         int shift;
 892
 893         shift = shifts[plane];
 894         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
 895 }
 896
 897 static void dispc_configure_burst_sizes(void)
 898 {
 899         int i;
 900         const int burst_size = BURST_SIZE_X8;
 901
 902         /* Configure burst size always to maximum size */
 903         for (i = 0; i < omap_dss_get_num_overlays(); ++i)
 904                 dispc_set_burst_size(i, burst_size);
 905 }
 906
 907 u32 dispc_get_burst_size(enum omap_plane plane)
 908 {
 909         unsigned unit = dss_feat_get_burst_size_unit();
 910         /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
 911         return unit * 8;
 912 }
 913
 914 void dispc_enable_gamma_table(bool enable)
 915 {
 916         /*
 917          * This is partially implemented to support only disabling of
 918          * the gamma table.
 919          */
 920         if (enable) {
 921                 DSSWARN("Gamma table enabling for TV not yet supported");
 922                 return;
 923         }
 924
 925         REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
 926 }
 927
 928 void dispc_enable_cpr(enum omap_channel channel, bool enable)
 929 {
 930         u16 reg;
 931
 932         if (channel == OMAP_DSS_CHANNEL_LCD)
 933                 reg = DISPC_CONFIG;
 934         else if (channel == OMAP_DSS_CHANNEL_LCD2)
 935                 reg = DISPC_CONFIG2;
 936         else
 937                 return;
 938
 939         REG_FLD_MOD(reg, enable, 15, 15);
 940 }
 941
 942 void dispc_set_cpr_coef(enum omap_channel channel,
 943                 struct omap_dss_cpr_coefs *coefs)
 944 {
 945         u32 coef_r, coef_g, coef_b;
 946
 947         if (channel != OMAP_DSS_CHANNEL_LCD && channel != OMAP_DSS_CHANNEL_LCD2)
 948                 return;
 949
 950         coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
 951                 FLD_VAL(coefs->rb, 9, 0);
 952         coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
 953                 FLD_VAL(coefs->gb, 9, 0);
 954         coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
 955                 FLD_VAL(coefs->bb, 9, 0);
 956
 957         dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
 958         dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
 959         dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
 960 }
 961
 962 static void _dispc_set_vid_color_conv(enum omap_plane plane, bool enable)
 963 {
 964         u32 val;
 965
 966         BUG_ON(plane == OMAP_DSS_GFX);
 967
 968         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
 969         val = FLD_MOD(val, enable, 9, 9);
 970         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
 971 }
 972
 973 void dispc_enable_replication(enum omap_plane plane, bool enable)
 974 {
 975         static const unsigned shifts[] = { 5, 10, 10 };
 976         int shift;
 977
 978         shift = shifts[plane];
 979         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
 980 }
 981
 982 void dispc_set_lcd_size(enum omap_channel channel, u16 width, u16 height)
 983 {
 984         u32 val;
 985         BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
 986         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 987         dispc_write_reg(DISPC_SIZE_MGR(channel), val);
 988 }
 989
 990 void dispc_set_digit_size(u16 width, u16 height)
 991 {
 992         u32 val;
 993         BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
 994         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 995         dispc_write_reg(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT), val);
 996 }
 997
 998 static void dispc_read_plane_fifo_sizes(void)
 999 {
1000         u32 size;
1001         int plane;
1002         u8 start, end;
1003         u32 unit;
1004
1005         unit = dss_feat_get_buffer_size_unit();
1006
1007         dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
1008
1009         for (plane = 0; plane < dss_feat_get_num_ovls(); ++plane) {
1010                 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(plane), start, end);
1011                 size *= unit;
1012                 dispc.fifo_size[plane] = size;
1013         }
1014 }
1015
1016 u32 dispc_get_plane_fifo_size(enum omap_plane plane)
1017 {
1018         return dispc.fifo_size[plane];
1019 }
1020
1021 void dispc_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
1022 {
1023         u8 hi_start, hi_end, lo_start, lo_end;
1024         u32 unit;
1025
1026         unit = dss_feat_get_buffer_size_unit();
1027
1028         WARN_ON(low % unit != 0);
1029         WARN_ON(high % unit != 0);
1030
1031         low /= unit;
1032         high /= unit;
1033
1034         dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1035         dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1036
1037         DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n",
1038                         plane,
1039                         REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1040                                 lo_start, lo_end),
1041                         REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1042                                 hi_start, hi_end),
1043                         low, high);
1044
1045         dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
1046                         FLD_VAL(high, hi_start, hi_end) |
1047                         FLD_VAL(low, lo_start, lo_end));
1048 }
1049
1050 void dispc_enable_fifomerge(bool enable)
1051 {
1052         DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1053         REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1054 }
1055
1056 static void _dispc_set_fir(enum omap_plane plane,
1057                                 int hinc, int vinc,
1058                                 enum omap_color_component color_comp)
1059 {
1060         u32 val;
1061
1062         if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1063                 u8 hinc_start, hinc_end, vinc_start, vinc_end;
1064
1065                 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1066                                         &hinc_start, &hinc_end);
1067                 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1068                                         &vinc_start, &vinc_end);
1069                 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1070                                 FLD_VAL(hinc, hinc_start, hinc_end);
1071
1072                 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1073         } else {
1074                 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1075                 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1076         }
1077 }
1078
1079 static void _dispc_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1080 {
1081         u32 val;
1082         u8 hor_start, hor_end, vert_start, vert_end;
1083
1084         dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1085         dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1086
1087         val = FLD_VAL(vaccu, vert_start, vert_end) |
1088                         FLD_VAL(haccu, hor_start, hor_end);
1089
1090         dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
1091 }
1092
1093 static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1094 {
1095         u32 val;
1096         u8 hor_start, hor_end, vert_start, vert_end;
1097
1098         dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1099         dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1100
1101         val = FLD_VAL(vaccu, vert_start, vert_end) |
1102                         FLD_VAL(haccu, hor_start, hor_end);
1103
1104         dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
1105 }
1106
1107 static void _dispc_set_vid_accu2_0(enum omap_plane plane, int haccu, int vaccu)
1108 {
1109         u32 val;
1110
1111         val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1112         dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1113 }
1114
1115 static void _dispc_set_vid_accu2_1(enum omap_plane plane, int haccu, int vaccu)
1116 {
1117         u32 val;
1118
1119         val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1120         dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1121 }
1122
1123 static void _dispc_set_scale_param(enum omap_plane plane,
1124                 u16 orig_width, u16 orig_height,
1125                 u16 out_width, u16 out_height,
1126                 bool five_taps, u8 rotation,
1127                 enum omap_color_component color_comp)
1128 {
1129         int fir_hinc, fir_vinc;
1130         int hscaleup, vscaleup;
1131
1132         hscaleup = orig_width <= out_width;
1133         vscaleup = orig_height <= out_height;
1134
1135         _dispc_set_scale_coef(plane, hscaleup, vscaleup, five_taps, color_comp);
1136
1137         fir_hinc = 1024 * orig_width / out_width;
1138         fir_vinc = 1024 * orig_height / out_height;
1139
1140         _dispc_set_fir(plane, fir_hinc, fir_vinc, color_comp);
1141 }
1142
1143 static void _dispc_set_scaling_common(enum omap_plane plane,
1144                 u16 orig_width, u16 orig_height,
1145                 u16 out_width, u16 out_height,
1146                 bool ilace, bool five_taps,
1147                 bool fieldmode, enum omap_color_mode color_mode,
1148                 u8 rotation)
1149 {
1150         int accu0 = 0;
1151         int accu1 = 0;
1152         u32 l;
1153
1154         _dispc_set_scale_param(plane, orig_width, orig_height,
1155                                 out_width, out_height, five_taps,
1156                                 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
1157         l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1158
1159         /* RESIZEENABLE and VERTICALTAPS */
1160         l &= ~((0x3 << 5) | (0x1 << 21));
1161         l |= (orig_width != out_width) ? (1 << 5) : 0;
1162         l |= (orig_height != out_height) ? (1 << 6) : 0;
1163         l |= five_taps ? (1 << 21) : 0;
1164
1165         /* VRESIZECONF and HRESIZECONF */
1166         if (dss_has_feature(FEAT_RESIZECONF)) {
1167                 l &= ~(0x3 << 7);
1168                 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1169                 l |= (orig_height <= out_height) ? 0 : (1 << 8);
1170         }
1171
1172         /* LINEBUFFERSPLIT */
1173         if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1174                 l &= ~(0x1 << 22);
1175                 l |= five_taps ? (1 << 22) : 0;
1176         }
1177
1178         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
1179
1180         /*
1181          * field 0 = even field = bottom field
1182          * field 1 = odd field = top field
1183          */
1184         if (ilace && !fieldmode) {
1185                 accu1 = 0;
1186                 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
1187                 if (accu0 >= 1024/2) {
1188                         accu1 = 1024/2;
1189                         accu0 -= accu1;
1190                 }
1191         }
1192
1193         _dispc_set_vid_accu0(plane, 0, accu0);
1194         _dispc_set_vid_accu1(plane, 0, accu1);
1195 }
1196
1197 static void _dispc_set_scaling_uv(enum omap_plane plane,
1198                 u16 orig_width, u16 orig_height,
1199                 u16 out_width, u16 out_height,
1200                 bool ilace, bool five_taps,
1201                 bool fieldmode, enum omap_color_mode color_mode,
1202                 u8 rotation)
1203 {
1204         int scale_x = out_width != orig_width;
1205         int scale_y = out_height != orig_height;
1206
1207         if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1208                 return;
1209         if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1210                         color_mode != OMAP_DSS_COLOR_UYVY &&
1211                         color_mode != OMAP_DSS_COLOR_NV12)) {
1212                 /* reset chroma resampling for RGB formats  */
1213                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1214                 return;
1215         }
1216         switch (color_mode) {
1217         case OMAP_DSS_COLOR_NV12:
1218                 /* UV is subsampled by 2 vertically*/
1219                 orig_height >>= 1;
1220                 /* UV is subsampled by 2 horz.*/
1221                 orig_width >>= 1;
1222                 break;
1223         case OMAP_DSS_COLOR_YUV2:
1224         case OMAP_DSS_COLOR_UYVY:
1225                 /*For YUV422 with 90/270 rotation,
1226                  *we don't upsample chroma
1227                  */
1228                 if (rotation == OMAP_DSS_ROT_0 ||
1229                         rotation == OMAP_DSS_ROT_180)
1230                         /* UV is subsampled by 2 hrz*/
1231                         orig_width >>= 1;
1232                 /* must use FIR for YUV422 if rotated */
1233                 if (rotation != OMAP_DSS_ROT_0)
1234                         scale_x = scale_y = true;
1235                 break;
1236         default:
1237                 BUG();
1238         }
1239
1240         if (out_width != orig_width)
1241                 scale_x = true;
1242         if (out_height != orig_height)
1243                 scale_y = true;
1244
1245         _dispc_set_scale_param(plane, orig_width, orig_height,
1246                         out_width, out_height, five_taps,
1247                                 rotation, DISPC_COLOR_COMPONENT_UV);
1248
1249         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1250                 (scale_x || scale_y) ? 1 : 0, 8, 8);
1251         /* set H scaling */
1252         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1253         /* set V scaling */
1254         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1255
1256         _dispc_set_vid_accu2_0(plane, 0x80, 0);
1257         _dispc_set_vid_accu2_1(plane, 0x80, 0);
1258 }
1259
1260 static void _dispc_set_scaling(enum omap_plane plane,
1261                 u16 orig_width, u16 orig_height,
1262                 u16 out_width, u16 out_height,
1263                 bool ilace, bool five_taps,
1264                 bool fieldmode, enum omap_color_mode color_mode,
1265                 u8 rotation)
1266 {
1267         BUG_ON(plane == OMAP_DSS_GFX);
1268
1269         _dispc_set_scaling_common(plane,
1270                         orig_width, orig_height,
1271                         out_width, out_height,
1272                         ilace, five_taps,
1273                         fieldmode, color_mode,
1274                         rotation);
1275
1276         _dispc_set_scaling_uv(plane,
1277                 orig_width, orig_height,
1278                 out_width, out_height,
1279                 ilace, five_taps,
1280                 fieldmode, color_mode,
1281                 rotation);
1282 }
1283
1284 static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1285                 bool mirroring, enum omap_color_mode color_mode)
1286 {
1287         bool row_repeat = false;
1288         int vidrot = 0;
1289
1290         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1291                         color_mode == OMAP_DSS_COLOR_UYVY) {
1292
1293                 if (mirroring) {
1294                         switch (rotation) {
1295                         case OMAP_DSS_ROT_0:
1296                                 vidrot = 2;
1297                                 break;
1298                         case OMAP_DSS_ROT_90:
1299                                 vidrot = 1;
1300                                 break;
1301                         case OMAP_DSS_ROT_180:
1302                                 vidrot = 0;
1303                                 break;
1304                         case OMAP_DSS_ROT_270:
1305                                 vidrot = 3;
1306                                 break;
1307                         }
1308                 } else {
1309                         switch (rotation) {
1310                         case OMAP_DSS_ROT_0:
1311                                 vidrot = 0;
1312                                 break;
1313                         case OMAP_DSS_ROT_90:
1314                                 vidrot = 1;
1315                                 break;
1316                         case OMAP_DSS_ROT_180:
1317                                 vidrot = 2;
1318                                 break;
1319                         case OMAP_DSS_ROT_270:
1320                                 vidrot = 3;
1321                                 break;
1322                         }
1323                 }
1324
1325                 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1326                         row_repeat = true;
1327                 else
1328                         row_repeat = false;
1329         }
1330
1331         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
1332         if (dss_has_feature(FEAT_ROWREPEATENABLE))
1333                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1334                         row_repeat ? 1 : 0, 18, 18);
1335 }
1336
1337 static int color_mode_to_bpp(enum omap_color_mode color_mode)
1338 {
1339         switch (color_mode) {
1340         case OMAP_DSS_COLOR_CLUT1:
1341                 return 1;
1342         case OMAP_DSS_COLOR_CLUT2:
1343                 return 2;
1344         case OMAP_DSS_COLOR_CLUT4:
1345                 return 4;
1346         case OMAP_DSS_COLOR_CLUT8:
1347         case OMAP_DSS_COLOR_NV12:
1348                 return 8;
1349         case OMAP_DSS_COLOR_RGB12U:
1350         case OMAP_DSS_COLOR_RGB16:
1351         case OMAP_DSS_COLOR_ARGB16:
1352         case OMAP_DSS_COLOR_YUV2:
1353         case OMAP_DSS_COLOR_UYVY:
1354         case OMAP_DSS_COLOR_RGBA16:
1355         case OMAP_DSS_COLOR_RGBX16:
1356         case OMAP_DSS_COLOR_ARGB16_1555:
1357         case OMAP_DSS_COLOR_XRGB16_1555:
1358                 return 16;
1359         case OMAP_DSS_COLOR_RGB24P:
1360                 return 24;
1361         case OMAP_DSS_COLOR_RGB24U:
1362         case OMAP_DSS_COLOR_ARGB32:
1363         case OMAP_DSS_COLOR_RGBA32:
1364         case OMAP_DSS_COLOR_RGBX32:
1365                 return 32;
1366         default:
1367                 BUG();
1368         }
1369 }
1370
1371 static s32 pixinc(int pixels, u8 ps)
1372 {
1373         if (pixels == 1)
1374                 return 1;
1375         else if (pixels > 1)
1376                 return 1 + (pixels - 1) * ps;
1377         else if (pixels < 0)
1378                 return 1 - (-pixels + 1) * ps;
1379         else
1380                 BUG();
1381 }
1382
1383 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1384                 u16 screen_width,
1385                 u16 width, u16 height,
1386                 enum omap_color_mode color_mode, bool fieldmode,
1387                 unsigned int field_offset,
1388                 unsigned *offset0, unsigned *offset1,
1389                 s32 *row_inc, s32 *pix_inc)
1390 {
1391         u8 ps;
1392
1393         /* FIXME CLUT formats */
1394         switch (color_mode) {
1395         case OMAP_DSS_COLOR_CLUT1:
1396         case OMAP_DSS_COLOR_CLUT2:
1397         case OMAP_DSS_COLOR_CLUT4:
1398         case OMAP_DSS_COLOR_CLUT8:
1399                 BUG();
1400                 return;
1401         case OMAP_DSS_COLOR_YUV2:
1402         case OMAP_DSS_COLOR_UYVY:
1403                 ps = 4;
1404                 break;
1405         default:
1406                 ps = color_mode_to_bpp(color_mode) / 8;
1407                 break;
1408         }
1409
1410         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1411                         width, height);
1412
1413         /*
1414          * field 0 = even field = bottom field
1415          * field 1 = odd field = top field
1416          */
1417         switch (rotation + mirror * 4) {
1418         case OMAP_DSS_ROT_0:
1419         case OMAP_DSS_ROT_180:
1420                 /*
1421                  * If the pixel format is YUV or UYVY divide the width
1422                  * of the image by 2 for 0 and 180 degree rotation.
1423                  */
1424                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1425                         color_mode == OMAP_DSS_COLOR_UYVY)
1426                         width = width >> 1;
1427         case OMAP_DSS_ROT_90:
1428         case OMAP_DSS_ROT_270:
1429                 *offset1 = 0;
1430                 if (field_offset)
1431                         *offset0 = field_offset * screen_width * ps;
1432                 else
1433                         *offset0 = 0;
1434
1435                 *row_inc = pixinc(1 + (screen_width - width) +
1436                                 (fieldmode ? screen_width : 0),
1437                                 ps);
1438                 *pix_inc = pixinc(1, ps);
1439                 break;
1440
1441         case OMAP_DSS_ROT_0 + 4:
1442         case OMAP_DSS_ROT_180 + 4:
1443                 /* If the pixel format is YUV or UYVY divide the width
1444                  * of the image by 2  for 0 degree and 180 degree
1445                  */
1446                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1447                         color_mode == OMAP_DSS_COLOR_UYVY)
1448                         width = width >> 1;
1449         case OMAP_DSS_ROT_90 + 4:
1450         case OMAP_DSS_ROT_270 + 4:
1451                 *offset1 = 0;
1452                 if (field_offset)
1453                         *offset0 = field_offset * screen_width * ps;
1454                 else
1455                         *offset0 = 0;
1456                 *row_inc = pixinc(1 - (screen_width + width) -
1457                                 (fieldmode ? screen_width : 0),
1458                                 ps);
1459                 *pix_inc = pixinc(1, ps);
1460                 break;
1461
1462         default:
1463                 BUG();
1464         }
1465 }
1466
1467 static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1468                 u16 screen_width,
1469                 u16 width, u16 height,
1470                 enum omap_color_mode color_mode, bool fieldmode,
1471                 unsigned int field_offset,
1472                 unsigned *offset0, unsigned *offset1,
1473                 s32 *row_inc, s32 *pix_inc)
1474 {
1475         u8 ps;
1476         u16 fbw, fbh;
1477
1478         /* FIXME CLUT formats */
1479         switch (color_mode) {
1480         case OMAP_DSS_COLOR_CLUT1:
1481         case OMAP_DSS_COLOR_CLUT2:
1482         case OMAP_DSS_COLOR_CLUT4:
1483         case OMAP_DSS_COLOR_CLUT8:
1484                 BUG();
1485                 return;
1486         default:
1487                 ps = color_mode_to_bpp(color_mode) / 8;
1488                 break;
1489         }
1490
1491         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1492                         width, height);
1493
1494         /* width & height are overlay sizes, convert to fb sizes */
1495
1496         if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1497                 fbw = width;
1498                 fbh = height;
1499         } else {
1500                 fbw = height;
1501                 fbh = width;
1502         }
1503
1504         /*
1505          * field 0 = even field = bottom field
1506          * field 1 = odd field = top field
1507          */
1508         switch (rotation + mirror * 4) {
1509         case OMAP_DSS_ROT_0:
1510                 *offset1 = 0;
1511                 if (field_offset)
1512                         *offset0 = *offset1 + field_offset * screen_width * ps;
1513                 else
1514                         *offset0 = *offset1;
1515                 *row_inc = pixinc(1 + (screen_width - fbw) +
1516                                 (fieldmode ? screen_width : 0),
1517                                 ps);
1518                 *pix_inc = pixinc(1, ps);
1519                 break;
1520         case OMAP_DSS_ROT_90:
1521                 *offset1 = screen_width * (fbh - 1) * ps;
1522                 if (field_offset)
1523                         *offset0 = *offset1 + field_offset * ps;
1524                 else
1525                         *offset0 = *offset1;
1526                 *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
1527                                 (fieldmode ? 1 : 0), ps);
1528                 *pix_inc = pixinc(-screen_width, ps);
1529                 break;
1530         case OMAP_DSS_ROT_180:
1531                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1532                 if (field_offset)
1533                         *offset0 = *offset1 - field_offset * screen_width * ps;
1534                 else
1535                         *offset0 = *offset1;
1536                 *row_inc = pixinc(-1 -
1537                                 (screen_width - fbw) -
1538                                 (fieldmode ? screen_width : 0),
1539                                 ps);
1540                 *pix_inc = pixinc(-1, ps);
1541                 break;
1542         case OMAP_DSS_ROT_270:
1543                 *offset1 = (fbw - 1) * ps;
1544                 if (field_offset)
1545                         *offset0 = *offset1 - field_offset * ps;
1546                 else
1547                         *offset0 = *offset1;
1548                 *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
1549                                 (fieldmode ? 1 : 0), ps);
1550                 *pix_inc = pixinc(screen_width, ps);
1551                 break;
1552
1553         /* mirroring */
1554         case OMAP_DSS_ROT_0 + 4:
1555                 *offset1 = (fbw - 1) * ps;
1556                 if (field_offset)
1557                         *offset0 = *offset1 + field_offset * screen_width * ps;
1558                 else
1559                         *offset0 = *offset1;
1560                 *row_inc = pixinc(screen_width * 2 - 1 +
1561                                 (fieldmode ? screen_width : 0),
1562                                 ps);
1563                 *pix_inc = pixinc(-1, ps);
1564                 break;
1565
1566         case OMAP_DSS_ROT_90 + 4:
1567                 *offset1 = 0;
1568                 if (field_offset)
1569                         *offset0 = *offset1 + field_offset * ps;
1570                 else
1571                         *offset0 = *offset1;
1572                 *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
1573                                 (fieldmode ? 1 : 0),
1574                                 ps);
1575                 *pix_inc = pixinc(screen_width, ps);
1576                 break;
1577
1578         case OMAP_DSS_ROT_180 + 4:
1579                 *offset1 = screen_width * (fbh - 1) * ps;
1580                 if (field_offset)
1581                         *offset0 = *offset1 - field_offset * screen_width * ps;
1582                 else
1583                         *offset0 = *offset1;
1584                 *row_inc = pixinc(1 - screen_width * 2 -
1585                                 (fieldmode ? screen_width : 0),
1586                                 ps);
1587                 *pix_inc = pixinc(1, ps);
1588                 break;
1589
1590         case OMAP_DSS_ROT_270 + 4:
1591                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1592                 if (field_offset)
1593                         *offset0 = *offset1 - field_offset * ps;
1594                 else
1595                         *offset0 = *offset1;
1596                 *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
1597                                 (fieldmode ? 1 : 0),
1598                                 ps);
1599                 *pix_inc = pixinc(-screen_width, ps);
1600                 break;
1601
1602         default:
1603                 BUG();
1604         }
1605 }
1606
1607 static unsigned long calc_fclk_five_taps(enum omap_channel channel, u16 width,
1608                 u16 height, u16 out_width, u16 out_height,
1609                 enum omap_color_mode color_mode)
1610 {
1611         u32 fclk = 0;
1612         /* FIXME venc pclk? */
1613         u64 tmp, pclk = dispc_pclk_rate(channel);
1614
1615         if (height > out_height) {
1616                 /* FIXME get real display PPL */
1617                 unsigned int ppl = 800;
1618
1619                 tmp = pclk * height * out_width;
1620                 do_div(tmp, 2 * out_height * ppl);
1621                 fclk = tmp;
1622
1623                 if (height > 2 * out_height) {
1624                         if (ppl == out_width)
1625                                 return 0;
1626
1627                         tmp = pclk * (height - 2 * out_height) * out_width;
1628                         do_div(tmp, 2 * out_height * (ppl - out_width));
1629                         fclk = max(fclk, (u32) tmp);
1630                 }
1631         }
1632
1633         if (width > out_width) {
1634                 tmp = pclk * width;
1635                 do_div(tmp, out_width);
1636                 fclk = max(fclk, (u32) tmp);
1637
1638                 if (color_mode == OMAP_DSS_COLOR_RGB24U)
1639                         fclk <<= 1;
1640         }
1641
1642         return fclk;
1643 }
1644
1645 static unsigned long calc_fclk(enum omap_channel channel, u16 width,
1646                 u16 height, u16 out_width, u16 out_height)
1647 {
1648         unsigned int hf, vf;
1649
1650         /*
1651          * FIXME how to determine the 'A' factor
1652          * for the no downscaling case ?
1653          */
1654
1655         if (width > 3 * out_width)
1656                 hf = 4;
1657         else if (width > 2 * out_width)
1658                 hf = 3;
1659         else if (width > out_width)
1660                 hf = 2;
1661         else
1662                 hf = 1;
1663
1664         if (height > out_height)
1665                 vf = 2;
1666         else
1667                 vf = 1;
1668
1669         /* FIXME venc pclk? */
1670         return dispc_pclk_rate(channel) * vf * hf;
1671 }
1672
1673 int dispc_setup_plane(enum omap_plane plane,
1674                 u32 paddr, u16 screen_width,
1675                 u16 pos_x, u16 pos_y,
1676                 u16 width, u16 height,
1677                 u16 out_width, u16 out_height,
1678                 enum omap_color_mode color_mode,
1679                 bool ilace,
1680                 enum omap_dss_rotation_type rotation_type,
1681                 u8 rotation, bool mirror,
1682                 u8 global_alpha, u8 pre_mult_alpha,
1683                 enum omap_channel channel, u32 puv_addr)
1684 {
1685         const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
1686         bool five_taps = 0;
1687         bool fieldmode = 0;
1688         int cconv = 0;
1689         unsigned offset0, offset1;
1690         s32 row_inc;
1691         s32 pix_inc;
1692         u16 frame_height = height;
1693         unsigned int field_offset = 0;
1694
1695         DSSDBG("dispc_setup_plane %d, pa %x, sw %d, %d,%d, %dx%d -> "
1696                "%dx%d, ilace %d, cmode %x, rot %d, mir %d chan %d\n",
1697                plane, paddr, screen_width, pos_x, pos_y,
1698                width, height,
1699                out_width, out_height,
1700                ilace, color_mode,
1701                rotation, mirror, channel);
1702
1703         if (paddr == 0)
1704                 return -EINVAL;
1705
1706         if (ilace && height == out_height)
1707                 fieldmode = 1;
1708
1709         if (ilace) {
1710                 if (fieldmode)
1711                         height /= 2;
1712                 pos_y /= 2;
1713                 out_height /= 2;
1714
1715                 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
1716                                 "out_height %d\n",
1717                                 height, pos_y, out_height);
1718         }
1719
1720         if (!dss_feat_color_mode_supported(plane, color_mode))
1721                 return -EINVAL;
1722
1723         if (plane == OMAP_DSS_GFX) {
1724                 if (width != out_width || height != out_height)
1725                         return -EINVAL;
1726         } else {
1727                 /* video plane */
1728
1729                 unsigned long fclk = 0;
1730
1731                 if (out_width < width / maxdownscale ||
1732                    out_width > width * 8)
1733                         return -EINVAL;
1734
1735                 if (out_height < height / maxdownscale ||
1736                    out_height > height * 8)
1737                         return -EINVAL;
1738
1739                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1740                         color_mode == OMAP_DSS_COLOR_UYVY ||
1741                         color_mode == OMAP_DSS_COLOR_NV12)
1742                         cconv = 1;
1743
1744                 /* Must use 5-tap filter? */
1745                 five_taps = height > out_height * 2;
1746
1747                 if (!five_taps) {
1748                         fclk = calc_fclk(channel, width, height, out_width,
1749                                         out_height);
1750
1751                         /* Try 5-tap filter if 3-tap fclk is too high */
1752                         if (cpu_is_omap34xx() && height > out_height &&
1753                                         fclk > dispc_fclk_rate())
1754                                 five_taps = true;
1755                 }
1756
1757                 if (width > (2048 >> five_taps)) {
1758                         DSSERR("failed to set up scaling, fclk too low\n");
1759                         return -EINVAL;
1760                 }
1761
1762                 if (five_taps)
1763                         fclk = calc_fclk_five_taps(channel, width, height,
1764                                         out_width, out_height, color_mode);
1765
1766                 DSSDBG("required fclk rate = %lu Hz\n", fclk);
1767                 DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
1768
1769                 if (!fclk || fclk > dispc_fclk_rate()) {
1770                         DSSERR("failed to set up scaling, "
1771                                         "required fclk rate = %lu Hz, "
1772                                         "current fclk rate = %lu Hz\n",
1773                                         fclk, dispc_fclk_rate());
1774                         return -EINVAL;
1775                 }
1776         }
1777
1778         if (ilace && !fieldmode) {
1779                 /*
1780                  * when downscaling the bottom field may have to start several
1781                  * source lines below the top field. Unfortunately ACCUI
1782                  * registers will only hold the fractional part of the offset
1783                  * so the integer part must be added to the base address of the
1784                  * bottom field.
1785                  */
1786                 if (!height || height == out_height)
1787                         field_offset = 0;
1788                 else
1789                         field_offset = height / out_height / 2;
1790         }
1791
1792         /* Fields are independent but interleaved in memory. */
1793         if (fieldmode)
1794                 field_offset = 1;
1795
1796         if (rotation_type == OMAP_DSS_ROT_DMA)
1797                 calc_dma_rotation_offset(rotation, mirror,
1798                                 screen_width, width, frame_height, color_mode,
1799                                 fieldmode, field_offset,
1800                                 &offset0, &offset1, &row_inc, &pix_inc);
1801         else
1802                 calc_vrfb_rotation_offset(rotation, mirror,
1803                                 screen_width, width, frame_height, color_mode,
1804                                 fieldmode, field_offset,
1805                                 &offset0, &offset1, &row_inc, &pix_inc);
1806
1807         DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
1808                         offset0, offset1, row_inc, pix_inc);
1809
1810         _dispc_set_color_mode(plane, color_mode);
1811
1812         _dispc_set_plane_ba0(plane, paddr + offset0);
1813         _dispc_set_plane_ba1(plane, paddr + offset1);
1814
1815         if (OMAP_DSS_COLOR_NV12 == color_mode) {
1816                 _dispc_set_plane_ba0_uv(plane, puv_addr + offset0);
1817                 _dispc_set_plane_ba1_uv(plane, puv_addr + offset1);
1818         }
1819
1820
1821         _dispc_set_row_inc(plane, row_inc);
1822         _dispc_set_pix_inc(plane, pix_inc);
1823
1824         DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, width, height,
1825                         out_width, out_height);
1826
1827         _dispc_set_plane_pos(plane, pos_x, pos_y);
1828
1829         _dispc_set_pic_size(plane, width, height);
1830
1831         if (plane != OMAP_DSS_GFX) {
1832                 _dispc_set_scaling(plane, width, height,
1833                                    out_width, out_height,
1834                                    ilace, five_taps, fieldmode,
1835                                    color_mode, rotation);
1836                 _dispc_set_vid_size(plane, out_width, out_height);
1837                 _dispc_set_vid_color_conv(plane, cconv);
1838         }
1839
1840         _dispc_set_rotation_attrs(plane, rotation, mirror, color_mode);
1841
1842         _dispc_set_pre_mult_alpha(plane, pre_mult_alpha);
1843         _dispc_setup_global_alpha(plane, global_alpha);
1844
1845         dispc_set_channel_out(plane, channel);
1846
1847         return 0;
1848 }
1849
1850 int dispc_enable_plane(enum omap_plane plane, bool enable)
1851 {
1852         DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
1853
1854         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
1855
1856         return 0;
1857 }
1858
1859 static void dispc_disable_isr(void *data, u32 mask)
1860 {
1861         struct completion *compl = data;
1862         complete(compl);
1863 }
1864
1865 static void _enable_lcd_out(enum omap_channel channel, bool enable)
1866 {
1867         if (channel == OMAP_DSS_CHANNEL_LCD2)
1868                 REG_FLD_MOD(DISPC_CONTROL2, enable ? 1 : 0, 0, 0);
1869         else
1870                 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
1871 }
1872
1873 static void dispc_enable_lcd_out(enum omap_channel channel, bool enable)
1874 {
1875         struct completion frame_done_completion;
1876         bool is_on;
1877         int r;
1878         u32 irq;
1879
1880         /* When we disable LCD output, we need to wait until frame is done.
1881          * Otherwise the DSS is still working, and turning off the clocks
1882          * prevents DSS from going to OFF mode */
1883         is_on = channel == OMAP_DSS_CHANNEL_LCD2 ?
1884                         REG_GET(DISPC_CONTROL2, 0, 0) :
1885                         REG_GET(DISPC_CONTROL, 0, 0);
1886
1887         irq = channel == OMAP_DSS_CHANNEL_LCD2 ? DISPC_IRQ_FRAMEDONE2 :
1888                         DISPC_IRQ_FRAMEDONE;
1889
1890         if (!enable && is_on) {
1891                 init_completion(&frame_done_completion);
1892
1893                 r = omap_dispc_register_isr(dispc_disable_isr,
1894                                 &frame_done_completion, irq);
1895
1896                 if (r)
1897                         DSSERR("failed to register FRAMEDONE isr\n");
1898         }
1899
1900         _enable_lcd_out(channel, enable);
1901
1902         if (!enable && is_on) {
1903                 if (!wait_for_completion_timeout(&frame_done_completion,
1904                                         msecs_to_jiffies(100)))
1905                         DSSERR("timeout waiting for FRAME DONE\n");
1906
1907                 r = omap_dispc_unregister_isr(dispc_disable_isr,
1908                                 &frame_done_completion, irq);
1909
1910                 if (r)
1911                         DSSERR("failed to unregister FRAMEDONE isr\n");
1912         }
1913 }
1914
1915 static void _enable_digit_out(bool enable)
1916 {
1917         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
1918 }
1919
1920 static void dispc_enable_digit_out(bool enable)
1921 {
1922         struct completion frame_done_completion;
1923         int r;
1924
1925         if (REG_GET(DISPC_CONTROL, 1, 1) == enable)
1926                 return;
1927
1928         if (enable) {
1929                 unsigned long flags;
1930                 /* When we enable digit output, we'll get an extra digit
1931                  * sync lost interrupt, that we need to ignore */
1932                 spin_lock_irqsave(&dispc.irq_lock, flags);
1933                 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
1934                 _omap_dispc_set_irqs();
1935                 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1936         }
1937
1938         /* When we disable digit output, we need to wait until fields are done.
1939          * Otherwise the DSS is still working, and turning off the clocks
1940          * prevents DSS from going to OFF mode. And when enabling, we need to
1941          * wait for the extra sync losts */
1942         init_completion(&frame_done_completion);
1943
1944         r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
1945                         DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1946         if (r)
1947                 DSSERR("failed to register EVSYNC isr\n");
1948
1949         _enable_digit_out(enable);
1950
1951         /* XXX I understand from TRM that we should only wait for the
1952          * current field to complete. But it seems we have to wait
1953          * for both fields */
1954         if (!wait_for_completion_timeout(&frame_done_completion,
1955                                 msecs_to_jiffies(100)))
1956                 DSSERR("timeout waiting for EVSYNC\n");
1957
1958         if (!wait_for_completion_timeout(&frame_done_completion,
1959                                 msecs_to_jiffies(100)))
1960                 DSSERR("timeout waiting for EVSYNC\n");
1961
1962         r = omap_dispc_unregister_isr(dispc_disable_isr,
1963                         &frame_done_completion,
1964                         DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1965         if (r)
1966                 DSSERR("failed to unregister EVSYNC isr\n");
1967
1968         if (enable) {
1969                 unsigned long flags;
1970                 spin_lock_irqsave(&dispc.irq_lock, flags);
1971                 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
1972                 if (dss_has_feature(FEAT_MGR_LCD2))
1973                         dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
1974                 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
1975                 _omap_dispc_set_irqs();
1976                 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1977         }
1978 }
1979
1980 bool dispc_is_channel_enabled(enum omap_channel channel)
1981 {
1982         if (channel == OMAP_DSS_CHANNEL_LCD)
1983                 return !!REG_GET(DISPC_CONTROL, 0, 0);
1984         else if (channel == OMAP_DSS_CHANNEL_DIGIT)
1985                 return !!REG_GET(DISPC_CONTROL, 1, 1);
1986         else if (channel == OMAP_DSS_CHANNEL_LCD2)
1987                 return !!REG_GET(DISPC_CONTROL2, 0, 0);
1988         else
1989                 BUG();
1990 }
1991
1992 void dispc_enable_channel(enum omap_channel channel, bool enable)
1993 {
1994         if (channel == OMAP_DSS_CHANNEL_LCD ||
1995                         channel == OMAP_DSS_CHANNEL_LCD2)
1996                 dispc_enable_lcd_out(channel, enable);
1997         else if (channel == OMAP_DSS_CHANNEL_DIGIT)
1998                 dispc_enable_digit_out(enable);
1999         else
2000                 BUG();
2001 }
2002
2003 void dispc_lcd_enable_signal_polarity(bool act_high)
2004 {
2005         if (!dss_has_feature(FEAT_LCDENABLEPOL))
2006                 return;
2007
2008         REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
2009 }
2010
2011 void dispc_lcd_enable_signal(bool enable)
2012 {
2013         if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2014                 return;
2015
2016         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
2017 }
2018
2019 void dispc_pck_free_enable(bool enable)
2020 {
2021         if (!dss_has_feature(FEAT_PCKFREEENABLE))
2022                 return;
2023
2024         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
2025 }
2026
2027 void dispc_enable_fifohandcheck(enum omap_channel channel, bool enable)
2028 {
2029         if (channel == OMAP_DSS_CHANNEL_LCD2)
2030                 REG_FLD_MOD(DISPC_CONFIG2, enable ? 1 : 0, 16, 16);
2031         else
2032                 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
2033 }
2034
2035
2036 void dispc_set_lcd_display_type(enum omap_channel channel,
2037                 enum omap_lcd_display_type type)
2038 {
2039         int mode;
2040
2041         switch (type) {
2042         case OMAP_DSS_LCD_DISPLAY_STN:
2043                 mode = 0;
2044                 break;
2045
2046         case OMAP_DSS_LCD_DISPLAY_TFT:
2047                 mode = 1;
2048                 break;
2049
2050         default:
2051                 BUG();
2052                 return;
2053         }
2054
2055         if (channel == OMAP_DSS_CHANNEL_LCD2)
2056                 REG_FLD_MOD(DISPC_CONTROL2, mode, 3, 3);
2057         else
2058                 REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
2059 }
2060
2061 void dispc_set_loadmode(enum omap_dss_load_mode mode)
2062 {
2063         REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
2064 }
2065
2066
2067 void dispc_set_default_color(enum omap_channel channel, u32 color)
2068 {
2069         dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
2070 }
2071
2072 u32 dispc_get_default_color(enum omap_channel channel)
2073 {
2074         u32 l;
2075
2076         BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
2077                 channel != OMAP_DSS_CHANNEL_LCD &&
2078                 channel != OMAP_DSS_CHANNEL_LCD2);
2079
2080         l = dispc_read_reg(DISPC_DEFAULT_COLOR(channel));
2081
2082         return l;
2083 }
2084
2085 void dispc_set_trans_key(enum omap_channel ch,
2086                 enum omap_dss_trans_key_type type,
2087                 u32 trans_key)
2088 {
2089         if (ch == OMAP_DSS_CHANNEL_LCD)
2090                 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
2091         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2092                 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
2093         else /* OMAP_DSS_CHANNEL_LCD2 */
2094                 REG_FLD_MOD(DISPC_CONFIG2, type, 11, 11);
2095
2096         dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
2097 }
2098
2099 void dispc_get_trans_key(enum omap_channel ch,
2100                 enum omap_dss_trans_key_type *type,
2101                 u32 *trans_key)
2102 {
2103         if (type) {
2104                 if (ch == OMAP_DSS_CHANNEL_LCD)
2105                         *type = REG_GET(DISPC_CONFIG, 11, 11);
2106                 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2107                         *type = REG_GET(DISPC_CONFIG, 13, 13);
2108                 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2109                         *type = REG_GET(DISPC_CONFIG2, 11, 11);
2110                 else
2111                         BUG();
2112         }
2113
2114         if (trans_key)
2115                 *trans_key = dispc_read_reg(DISPC_TRANS_COLOR(ch));
2116 }
2117
2118 void dispc_enable_trans_key(enum omap_channel ch, bool enable)
2119 {
2120         if (ch == OMAP_DSS_CHANNEL_LCD)
2121                 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
2122         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2123                 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
2124         else /* OMAP_DSS_CHANNEL_LCD2 */
2125                 REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10);
2126 }
2127 void dispc_enable_alpha_blending(enum omap_channel ch, bool enable)
2128 {
2129         if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
2130                 return;
2131
2132         if (ch == OMAP_DSS_CHANNEL_LCD)
2133                 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2134         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2135                 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2136         else /* OMAP_DSS_CHANNEL_LCD2 */
2137                 REG_FLD_MOD(DISPC_CONFIG2, enable, 18, 18);
2138 }
2139 bool dispc_alpha_blending_enabled(enum omap_channel ch)
2140 {
2141         bool enabled;
2142
2143         if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
2144                 return false;
2145
2146         if (ch == OMAP_DSS_CHANNEL_LCD)
2147                 enabled = REG_GET(DISPC_CONFIG, 18, 18);
2148         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2149                 enabled = REG_GET(DISPC_CONFIG, 19, 19);
2150         else if (ch == OMAP_DSS_CHANNEL_LCD2)
2151                 enabled = REG_GET(DISPC_CONFIG2, 18, 18);
2152         else
2153                 BUG();
2154
2155         return enabled;
2156 }
2157
2158
2159 bool dispc_trans_key_enabled(enum omap_channel ch)
2160 {
2161         bool enabled;
2162
2163         if (ch == OMAP_DSS_CHANNEL_LCD)
2164                 enabled = REG_GET(DISPC_CONFIG, 10, 10);
2165         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2166                 enabled = REG_GET(DISPC_CONFIG, 12, 12);
2167         else if (ch == OMAP_DSS_CHANNEL_LCD2)
2168                 enabled = REG_GET(DISPC_CONFIG2, 10, 10);
2169         else
2170                 BUG();
2171
2172         return enabled;
2173 }
2174
2175
2176 void dispc_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
2177 {
2178         int code;
2179
2180         switch (data_lines) {
2181         case 12:
2182                 code = 0;
2183                 break;
2184         case 16:
2185                 code = 1;
2186                 break;
2187         case 18:
2188                 code = 2;
2189                 break;
2190         case 24:
2191                 code = 3;
2192                 break;
2193         default:
2194                 BUG();
2195                 return;
2196         }
2197
2198         if (channel == OMAP_DSS_CHANNEL_LCD2)
2199                 REG_FLD_MOD(DISPC_CONTROL2, code, 9, 8);
2200         else
2201                 REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
2202 }
2203
2204 void dispc_set_parallel_interface_mode(enum omap_channel channel,
2205                 enum omap_parallel_interface_mode mode)
2206 {
2207         u32 l;
2208         int stallmode;
2209         int gpout0 = 1;
2210         int gpout1;
2211
2212         switch (mode) {
2213         case OMAP_DSS_PARALLELMODE_BYPASS:
2214                 stallmode = 0;
2215                 gpout1 = 1;
2216                 break;
2217
2218         case OMAP_DSS_PARALLELMODE_RFBI:
2219                 stallmode = 1;
2220                 gpout1 = 0;
2221                 break;
2222
2223         case OMAP_DSS_PARALLELMODE_DSI:
2224                 stallmode = 1;
2225                 gpout1 = 1;
2226                 break;
2227
2228         default:
2229                 BUG();
2230                 return;
2231         }
2232
2233         if (channel == OMAP_DSS_CHANNEL_LCD2) {
2234                 l = dispc_read_reg(DISPC_CONTROL2);
2235                 l = FLD_MOD(l, stallmode, 11, 11);
2236                 dispc_write_reg(DISPC_CONTROL2, l);
2237         } else {
2238                 l = dispc_read_reg(DISPC_CONTROL);
2239                 l = FLD_MOD(l, stallmode, 11, 11);
2240                 l = FLD_MOD(l, gpout0, 15, 15);
2241                 l = FLD_MOD(l, gpout1, 16, 16);
2242                 dispc_write_reg(DISPC_CONTROL, l);
2243         }
2244 }
2245
2246 static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2247                 int vsw, int vfp, int vbp)
2248 {
2249         if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2250                 if (hsw < 1 || hsw > 64 ||
2251                                 hfp < 1 || hfp > 256 ||
2252                                 hbp < 1 || hbp > 256 ||
2253                                 vsw < 1 || vsw > 64 ||
2254                                 vfp < 0 || vfp > 255 ||
2255                                 vbp < 0 || vbp > 255)
2256                         return false;
2257         } else {
2258                 if (hsw < 1 || hsw > 256 ||
2259                                 hfp < 1 || hfp > 4096 ||
2260                                 hbp < 1 || hbp > 4096 ||
2261                                 vsw < 1 || vsw > 256 ||
2262                                 vfp < 0 || vfp > 4095 ||
2263                                 vbp < 0 || vbp > 4095)
2264                         return false;
2265         }
2266
2267         return true;
2268 }
2269
2270 bool dispc_lcd_timings_ok(struct omap_video_timings *timings)
2271 {
2272         return _dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2273                         timings->hbp, timings->vsw,
2274                         timings->vfp, timings->vbp);
2275 }
2276
2277 static void _dispc_set_lcd_timings(enum omap_channel channel, int hsw,
2278                 int hfp, int hbp, int vsw, int vfp, int vbp)
2279 {
2280         u32 timing_h, timing_v;
2281
2282         if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2283                 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
2284                         FLD_VAL(hbp-1, 27, 20);
2285
2286                 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
2287                         FLD_VAL(vbp, 27, 20);
2288         } else {
2289                 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
2290                         FLD_VAL(hbp-1, 31, 20);
2291
2292                 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
2293                         FLD_VAL(vbp, 31, 20);
2294         }
2295
2296         dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2297         dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
2298 }
2299
2300 /* change name to mode? */
2301 void dispc_set_lcd_timings(enum omap_channel channel,
2302                 struct omap_video_timings *timings)
2303 {
2304         unsigned xtot, ytot;
2305         unsigned long ht, vt;
2306
2307         if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2308                                 timings->hbp, timings->vsw,
2309                                 timings->vfp, timings->vbp))
2310                 BUG();
2311
2312         _dispc_set_lcd_timings(channel, timings->hsw, timings->hfp,
2313                         timings->hbp, timings->vsw, timings->vfp,
2314                         timings->vbp);
2315
2316         dispc_set_lcd_size(channel, timings->x_res, timings->y_res);
2317
2318         xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
2319         ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
2320
2321         ht = (timings->pixel_clock * 1000) / xtot;
2322         vt = (timings->pixel_clock * 1000) / xtot / ytot;
2323
2324         DSSDBG("channel %d xres %u yres %u\n", channel, timings->x_res,
2325                         timings->y_res);
2326         DSSDBG("pck %u\n", timings->pixel_clock);
2327         DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2328                         timings->hsw, timings->hfp, timings->hbp,
2329                         timings->vsw, timings->vfp, timings->vbp);
2330
2331         DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2332 }
2333
2334 static void dispc_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
2335                 u16 pck_div)
2336 {
2337         BUG_ON(lck_div < 1);
2338         BUG_ON(pck_div < 2);
2339
2340         dispc_write_reg(DISPC_DIVISORo(channel),
2341                         FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
2342 }
2343
2344 static void dispc_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2345                 int *pck_div)
2346 {
2347         u32 l;
2348         l = dispc_read_reg(DISPC_DIVISORo(channel));
2349         *lck_div = FLD_GET(l, 23, 16);
2350         *pck_div = FLD_GET(l, 7, 0);
2351 }
2352
2353 unsigned long dispc_fclk_rate(void)
2354 {
2355         struct platform_device *dsidev;
2356         unsigned long r = 0;
2357
2358         switch (dss_get_dispc_clk_source()) {
2359         case OMAP_DSS_CLK_SRC_FCK:
2360                 r = clk_get_rate(dispc.dss_clk);
2361                 break;
2362         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
2363                 dsidev = dsi_get_dsidev_from_id(0);
2364                 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2365                 break;
2366         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2367                 dsidev = dsi_get_dsidev_from_id(1);
2368                 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2369                 break;
2370         default:
2371                 BUG();
2372         }
2373
2374         return r;
2375 }
2376
2377 unsigned long dispc_lclk_rate(enum omap_channel channel)
2378 {
2379         struct platform_device *dsidev;
2380         int lcd;
2381         unsigned long r;
2382         u32 l;
2383
2384         l = dispc_read_reg(DISPC_DIVISORo(channel));
2385
2386         lcd = FLD_GET(l, 23, 16);
2387
2388         switch (dss_get_lcd_clk_source(channel)) {
2389         case OMAP_DSS_CLK_SRC_FCK:
2390                 r = clk_get_rate(dispc.dss_clk);
2391                 break;
2392         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
2393                 dsidev = dsi_get_dsidev_from_id(0);
2394                 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2395                 break;
2396         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2397                 dsidev = dsi_get_dsidev_from_id(1);
2398                 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2399                 break;
2400         default:
2401                 BUG();
2402         }
2403
2404         return r / lcd;
2405 }
2406
2407 unsigned long dispc_pclk_rate(enum omap_channel channel)
2408 {
2409         int pcd;
2410         unsigned long r;
2411         u32 l;
2412
2413         l = dispc_read_reg(DISPC_DIVISORo(channel));
2414
2415         pcd = FLD_GET(l, 7, 0);
2416
2417         r = dispc_lclk_rate(channel);
2418
2419         return r / pcd;
2420 }
2421
2422 void dispc_dump_clocks(struct seq_file *s)
2423 {
2424         int lcd, pcd;
2425         u32 l;
2426         enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
2427         enum omap_dss_clk_source lcd_clk_src;
2428
2429         if (dispc_runtime_get())
2430                 return;
2431
2432         seq_printf(s, "- DISPC -\n");
2433
2434         seq_printf(s, "dispc fclk source = %s (%s)\n",
2435                         dss_get_generic_clk_source_name(dispc_clk_src),
2436                         dss_feat_get_clk_source_name(dispc_clk_src));
2437
2438         seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2439
2440         if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
2441                 seq_printf(s, "- DISPC-CORE-CLK -\n");
2442                 l = dispc_read_reg(DISPC_DIVISOR);
2443                 lcd = FLD_GET(l, 23, 16);
2444
2445                 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2446                                 (dispc_fclk_rate()/lcd), lcd);
2447         }
2448         seq_printf(s, "- LCD1 -\n");
2449
2450         lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD);
2451
2452         seq_printf(s, "lcd1_clk source = %s (%s)\n",
2453                 dss_get_generic_clk_source_name(lcd_clk_src),
2454                 dss_feat_get_clk_source_name(lcd_clk_src));
2455
2456         dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd);
2457
2458         seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2459                         dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD), lcd);
2460         seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2461                         dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD), pcd);
2462         if (dss_has_feature(FEAT_MGR_LCD2)) {
2463                 seq_printf(s, "- LCD2 -\n");
2464
2465                 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD2);
2466
2467                 seq_printf(s, "lcd2_clk source = %s (%s)\n",
2468                         dss_get_generic_clk_source_name(lcd_clk_src),
2469                         dss_feat_get_clk_source_name(lcd_clk_src));
2470
2471                 dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd);
2472
2473                 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2474                                 dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD2), lcd);
2475                 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2476                                 dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD2), pcd);
2477         }
2478
2479         dispc_runtime_put();
2480 }
2481
2482 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2483 void dispc_dump_irqs(struct seq_file *s)
2484 {
2485         unsigned long flags;
2486         struct dispc_irq_stats stats;
2487
2488         spin_lock_irqsave(&dispc.irq_stats_lock, flags);
2489
2490         stats = dispc.irq_stats;
2491         memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
2492         dispc.irq_stats.last_reset = jiffies;
2493
2494         spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
2495
2496         seq_printf(s, "period %u ms\n",
2497                         jiffies_to_msecs(jiffies - stats.last_reset));
2498
2499         seq_printf(s, "irqs %d\n", stats.irq_count);
2500 #define PIS(x) \
2501         seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
2502
2503         PIS(FRAMEDONE);
2504         PIS(VSYNC);
2505         PIS(EVSYNC_EVEN);
2506         PIS(EVSYNC_ODD);
2507         PIS(ACBIAS_COUNT_STAT);
2508         PIS(PROG_LINE_NUM);
2509         PIS(GFX_FIFO_UNDERFLOW);
2510         PIS(GFX_END_WIN);
2511         PIS(PAL_GAMMA_MASK);
2512         PIS(OCP_ERR);
2513         PIS(VID1_FIFO_UNDERFLOW);
2514         PIS(VID1_END_WIN);
2515         PIS(VID2_FIFO_UNDERFLOW);
2516         PIS(VID2_END_WIN);
2517         PIS(SYNC_LOST);
2518         PIS(SYNC_LOST_DIGIT);
2519         PIS(WAKEUP);
2520         if (dss_has_feature(FEAT_MGR_LCD2)) {
2521                 PIS(FRAMEDONE2);
2522                 PIS(VSYNC2);
2523                 PIS(ACBIAS_COUNT_STAT2);
2524                 PIS(SYNC_LOST2);
2525         }
2526 #undef PIS
2527 }
2528 #endif
2529
2530 void dispc_dump_regs(struct seq_file *s)
2531 {
2532         int i, j;
2533         const char *mgr_names[] = {
2534                 [OMAP_DSS_CHANNEL_LCD]          = "LCD",
2535                 [OMAP_DSS_CHANNEL_DIGIT]        = "TV",
2536                 [OMAP_DSS_CHANNEL_LCD2]         = "LCD2",
2537         };
2538         const char *ovl_names[] = {
2539                 [OMAP_DSS_GFX]          = "GFX",
2540                 [OMAP_DSS_VIDEO1]       = "VID1",
2541                 [OMAP_DSS_VIDEO2]       = "VID2",
2542         };
2543         const char **p_names;
2544
2545 #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
2546
2547         if (dispc_runtime_get())
2548                 return;
2549
2550         /* DISPC common registers */
2551         DUMPREG(DISPC_REVISION);
2552         DUMPREG(DISPC_SYSCONFIG);
2553         DUMPREG(DISPC_SYSSTATUS);
2554         DUMPREG(DISPC_IRQSTATUS);
2555         DUMPREG(DISPC_IRQENABLE);
2556         DUMPREG(DISPC_CONTROL);
2557         DUMPREG(DISPC_CONFIG);
2558         DUMPREG(DISPC_CAPABLE);
2559         DUMPREG(DISPC_LINE_STATUS);
2560         DUMPREG(DISPC_LINE_NUMBER);
2561         if (dss_has_feature(FEAT_GLOBAL_ALPHA))
2562                 DUMPREG(DISPC_GLOBAL_ALPHA);
2563         if (dss_has_feature(FEAT_MGR_LCD2)) {
2564                 DUMPREG(DISPC_CONTROL2);
2565                 DUMPREG(DISPC_CONFIG2);
2566         }
2567
2568 #undef DUMPREG
2569
2570 #define DISPC_REG(i, name) name(i)
2571 #define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
2572         48 - strlen(#r) - strlen(p_names[i]), " ", \
2573         dispc_read_reg(DISPC_REG(i, r)))
2574
2575         p_names = mgr_names;
2576
2577         /* DISPC channel specific registers */
2578         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
2579                 DUMPREG(i, DISPC_DEFAULT_COLOR);
2580                 DUMPREG(i, DISPC_TRANS_COLOR);
2581                 DUMPREG(i, DISPC_SIZE_MGR);
2582
2583                 if (i == OMAP_DSS_CHANNEL_DIGIT)
2584                         continue;
2585
2586                 DUMPREG(i, DISPC_DEFAULT_COLOR);
2587                 DUMPREG(i, DISPC_TRANS_COLOR);
2588                 DUMPREG(i, DISPC_TIMING_H);
2589                 DUMPREG(i, DISPC_TIMING_V);
2590                 DUMPREG(i, DISPC_POL_FREQ);
2591                 DUMPREG(i, DISPC_DIVISORo);
2592                 DUMPREG(i, DISPC_SIZE_MGR);
2593
2594                 DUMPREG(i, DISPC_DATA_CYCLE1);
2595                 DUMPREG(i, DISPC_DATA_CYCLE2);
2596                 DUMPREG(i, DISPC_DATA_CYCLE3);
2597
2598                 if (dss_has_feature(FEAT_CPR)) {
2599                         DUMPREG(i, DISPC_CPR_COEF_R);
2600                         DUMPREG(i, DISPC_CPR_COEF_G);
2601                         DUMPREG(i, DISPC_CPR_COEF_B);
2602                 }
2603         }
2604
2605         p_names = ovl_names;
2606
2607         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
2608                 DUMPREG(i, DISPC_OVL_BA0);
2609                 DUMPREG(i, DISPC_OVL_BA1);
2610                 DUMPREG(i, DISPC_OVL_POSITION);
2611                 DUMPREG(i, DISPC_OVL_SIZE);
2612                 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
2613                 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
2614                 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
2615                 DUMPREG(i, DISPC_OVL_ROW_INC);
2616                 DUMPREG(i, DISPC_OVL_PIXEL_INC);
2617                 if (dss_has_feature(FEAT_PRELOAD))
2618                         DUMPREG(i, DISPC_OVL_PRELOAD);
2619
2620                 if (i == OMAP_DSS_GFX) {
2621                         DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
2622                         DUMPREG(i, DISPC_OVL_TABLE_BA);
2623                         continue;
2624                 }
2625
2626                 DUMPREG(i, DISPC_OVL_FIR);
2627                 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
2628                 DUMPREG(i, DISPC_OVL_ACCU0);
2629                 DUMPREG(i, DISPC_OVL_ACCU1);
2630                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2631                         DUMPREG(i, DISPC_OVL_BA0_UV);
2632                         DUMPREG(i, DISPC_OVL_BA1_UV);
2633                         DUMPREG(i, DISPC_OVL_FIR2);
2634                         DUMPREG(i, DISPC_OVL_ACCU2_0);
2635                         DUMPREG(i, DISPC_OVL_ACCU2_1);
2636                 }
2637                 if (dss_has_feature(FEAT_ATTR2))
2638                         DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
2639                 if (dss_has_feature(FEAT_PRELOAD))
2640                         DUMPREG(i, DISPC_OVL_PRELOAD);
2641         }
2642
2643 #undef DISPC_REG
2644 #undef DUMPREG
2645
2646 #define DISPC_REG(plane, name, i) name(plane, i)
2647 #define DUMPREG(plane, name, i) \
2648         seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
2649         46 - strlen(#name) - strlen(p_names[plane]), " ", \
2650         dispc_read_reg(DISPC_REG(plane, name, i)))
2651
2652         /* Video pipeline coefficient registers */
2653
2654         /* start from OMAP_DSS_VIDEO1 */
2655         for (i = 1; i < dss_feat_get_num_ovls(); i++) {
2656                 for (j = 0; j < 8; j++)
2657                         DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
2658
2659                 for (j = 0; j < 8; j++)
2660                         DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
2661
2662                 for (j = 0; j < 5; j++)
2663                         DUMPREG(i, DISPC_OVL_CONV_COEF, j);
2664
2665                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
2666                         for (j = 0; j < 8; j++)
2667                                 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
2668                 }
2669
2670                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2671                         for (j = 0; j < 8; j++)
2672                                 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
2673
2674                         for (j = 0; j < 8; j++)
2675                                 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
2676
2677                         for (j = 0; j < 8; j++)
2678                                 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
2679                 }
2680         }
2681
2682         dispc_runtime_put();
2683
2684 #undef DISPC_REG
2685 #undef DUMPREG
2686 }
2687
2688 static void _dispc_set_pol_freq(enum omap_channel channel, bool onoff, bool rf,
2689                 bool ieo, bool ipc, bool ihs, bool ivs, u8 acbi, u8 acb)
2690 {
2691         u32 l = 0;
2692
2693         DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
2694                         onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
2695
2696         l |= FLD_VAL(onoff, 17, 17);
2697         l |= FLD_VAL(rf, 16, 16);
2698         l |= FLD_VAL(ieo, 15, 15);
2699         l |= FLD_VAL(ipc, 14, 14);
2700         l |= FLD_VAL(ihs, 13, 13);
2701         l |= FLD_VAL(ivs, 12, 12);
2702         l |= FLD_VAL(acbi, 11, 8);
2703         l |= FLD_VAL(acb, 7, 0);
2704
2705         dispc_write_reg(DISPC_POL_FREQ(channel), l);
2706 }
2707
2708 void dispc_set_pol_freq(enum omap_channel channel,
2709                 enum omap_panel_config config, u8 acbi, u8 acb)
2710 {
2711         _dispc_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0,
2712                         (config & OMAP_DSS_LCD_RF) != 0,
2713                         (config & OMAP_DSS_LCD_IEO) != 0,
2714                         (config & OMAP_DSS_LCD_IPC) != 0,
2715                         (config & OMAP_DSS_LCD_IHS) != 0,
2716                         (config & OMAP_DSS_LCD_IVS) != 0,
2717                         acbi, acb);
2718 }
2719
2720 /* with fck as input clock rate, find dispc dividers that produce req_pck */
2721 void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
2722                 struct dispc_clock_info *cinfo)
2723 {
2724         u16 pcd_min = is_tft ? 2 : 3;
2725         unsigned long best_pck;
2726         u16 best_ld, cur_ld;
2727         u16 best_pd, cur_pd;
2728
2729         best_pck = 0;
2730         best_ld = 0;
2731         best_pd = 0;
2732
2733         for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
2734                 unsigned long lck = fck / cur_ld;
2735
2736                 for (cur_pd = pcd_min; cur_pd <= 255; ++cur_pd) {
2737                         unsigned long pck = lck / cur_pd;
2738                         long old_delta = abs(best_pck - req_pck);
2739                         long new_delta = abs(pck - req_pck);
2740
2741                         if (best_pck == 0 || new_delta < old_delta) {
2742                                 best_pck = pck;
2743                                 best_ld = cur_ld;
2744                                 best_pd = cur_pd;
2745
2746                                 if (pck == req_pck)
2747                                         goto found;
2748                         }
2749
2750                         if (pck < req_pck)
2751                                 break;
2752                 }
2753
2754                 if (lck / pcd_min < req_pck)
2755                         break;
2756         }
2757
2758 found:
2759         cinfo->lck_div = best_ld;
2760         cinfo->pck_div = best_pd;
2761         cinfo->lck = fck / cinfo->lck_div;
2762         cinfo->pck = cinfo->lck / cinfo->pck_div;
2763 }
2764
2765 /* calculate clock rates using dividers in cinfo */
2766 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
2767                 struct dispc_clock_info *cinfo)
2768 {
2769         if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
2770                 return -EINVAL;
2771         if (cinfo->pck_div < 2 || cinfo->pck_div > 255)
2772                 return -EINVAL;
2773
2774         cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
2775         cinfo->pck = cinfo->lck / cinfo->pck_div;
2776
2777         return 0;
2778 }
2779
2780 int dispc_set_clock_div(enum omap_channel channel,
2781                 struct dispc_clock_info *cinfo)
2782 {
2783         DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
2784         DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
2785
2786         dispc_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
2787
2788         return 0;
2789 }
2790
2791 int dispc_get_clock_div(enum omap_channel channel,
2792                 struct dispc_clock_info *cinfo)
2793 {
2794         unsigned long fck;
2795
2796         fck = dispc_fclk_rate();
2797
2798         cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
2799         cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
2800
2801         cinfo->lck = fck / cinfo->lck_div;
2802         cinfo->pck = cinfo->lck / cinfo->pck_div;
2803
2804         return 0;
2805 }
2806
2807 /* dispc.irq_lock has to be locked by the caller */
2808 static void _omap_dispc_set_irqs(void)
2809 {
2810         u32 mask;
2811         u32 old_mask;
2812         int i;
2813         struct omap_dispc_isr_data *isr_data;
2814
2815         mask = dispc.irq_error_mask;
2816
2817         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2818                 isr_data = &dispc.registered_isr[i];
2819
2820                 if (isr_data->isr == NULL)
2821                         continue;
2822
2823                 mask |= isr_data->mask;
2824         }
2825
2826         old_mask = dispc_read_reg(DISPC_IRQENABLE);
2827         /* clear the irqstatus for newly enabled irqs */
2828         dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
2829
2830         dispc_write_reg(DISPC_IRQENABLE, mask);
2831 }
2832
2833 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2834 {
2835         int i;
2836         int ret;
2837         unsigned long flags;
2838         struct omap_dispc_isr_data *isr_data;
2839
2840         if (isr == NULL)
2841                 return -EINVAL;
2842
2843         spin_lock_irqsave(&dispc.irq_lock, flags);
2844
2845         /* check for duplicate entry */
2846         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2847                 isr_data = &dispc.registered_isr[i];
2848                 if (isr_data->isr == isr && isr_data->arg == arg &&
2849                                 isr_data->mask == mask) {
2850                         ret = -EINVAL;
2851                         goto err;
2852                 }
2853         }
2854
2855         isr_data = NULL;
2856         ret = -EBUSY;
2857
2858         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2859                 isr_data = &dispc.registered_isr[i];
2860
2861                 if (isr_data->isr != NULL)
2862                         continue;
2863
2864                 isr_data->isr = isr;
2865                 isr_data->arg = arg;
2866                 isr_data->mask = mask;
2867                 ret = 0;
2868
2869                 break;
2870         }
2871
2872         if (ret)
2873                 goto err;
2874
2875         _omap_dispc_set_irqs();
2876
2877         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2878
2879         return 0;
2880 err:
2881         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2882
2883         return ret;
2884 }
2885 EXPORT_SYMBOL(omap_dispc_register_isr);
2886
2887 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2888 {
2889         int i;
2890         unsigned long flags;
2891         int ret = -EINVAL;
2892         struct omap_dispc_isr_data *isr_data;
2893
2894         spin_lock_irqsave(&dispc.irq_lock, flags);
2895
2896         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2897                 isr_data = &dispc.registered_isr[i];
2898                 if (isr_data->isr != isr || isr_data->arg != arg ||
2899                                 isr_data->mask != mask)
2900                         continue;
2901
2902                 /* found the correct isr */
2903
2904                 isr_data->isr = NULL;
2905                 isr_data->arg = NULL;
2906                 isr_data->mask = 0;
2907
2908                 ret = 0;
2909                 break;
2910         }
2911
2912         if (ret == 0)
2913                 _omap_dispc_set_irqs();
2914
2915         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2916
2917         return ret;
2918 }
2919 EXPORT_SYMBOL(omap_dispc_unregister_isr);
2920
2921 #ifdef DEBUG
2922 static void print_irq_status(u32 status)
2923 {
2924         if ((status & dispc.irq_error_mask) == 0)
2925                 return;
2926
2927         printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
2928
2929 #define PIS(x) \
2930         if (status & DISPC_IRQ_##x) \
2931                 printk(#x " ");
2932         PIS(GFX_FIFO_UNDERFLOW);
2933         PIS(OCP_ERR);
2934         PIS(VID1_FIFO_UNDERFLOW);
2935         PIS(VID2_FIFO_UNDERFLOW);
2936         PIS(SYNC_LOST);
2937         PIS(SYNC_LOST_DIGIT);
2938         if (dss_has_feature(FEAT_MGR_LCD2))
2939                 PIS(SYNC_LOST2);
2940 #undef PIS
2941
2942         printk("\n");
2943 }
2944 #endif
2945
2946 /* Called from dss.c. Note that we don't touch clocks here,
2947  * but we presume they are on because we got an IRQ. However,
2948  * an irq handler may turn the clocks off, so we may not have
2949  * clock later in the function. */
2950 static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
2951 {
2952         int i;
2953         u32 irqstatus, irqenable;
2954         u32 handledirqs = 0;
2955         u32 unhandled_errors;
2956         struct omap_dispc_isr_data *isr_data;
2957         struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
2958
2959         spin_lock(&dispc.irq_lock);
2960
2961         irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
2962         irqenable = dispc_read_reg(DISPC_IRQENABLE);
2963
2964         /* IRQ is not for us */
2965         if (!(irqstatus & irqenable)) {
2966                 spin_unlock(&dispc.irq_lock);
2967                 return IRQ_NONE;
2968         }
2969
2970 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2971         spin_lock(&dispc.irq_stats_lock);
2972         dispc.irq_stats.irq_count++;
2973         dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
2974         spin_unlock(&dispc.irq_stats_lock);
2975 #endif
2976
2977 #ifdef DEBUG
2978         if (dss_debug)
2979                 print_irq_status(irqstatus);
2980 #endif
2981         /* Ack the interrupt. Do it here before clocks are possibly turned
2982          * off */
2983         dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
2984         /* flush posted write */
2985         dispc_read_reg(DISPC_IRQSTATUS);
2986
2987         /* make a copy and unlock, so that isrs can unregister
2988          * themselves */
2989         memcpy(registered_isr, dispc.registered_isr,
2990                         sizeof(registered_isr));
2991
2992         spin_unlock(&dispc.irq_lock);
2993
2994         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2995                 isr_data = &registered_isr[i];
2996
2997                 if (!isr_data->isr)
2998                         continue;
2999
3000                 if (isr_data->mask & irqstatus) {
3001                         isr_data->isr(isr_data->arg, irqstatus);
3002                         handledirqs |= isr_data->mask;
3003                 }
3004         }
3005
3006         spin_lock(&dispc.irq_lock);
3007
3008         unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
3009
3010         if (unhandled_errors) {
3011                 dispc.error_irqs |= unhandled_errors;
3012
3013                 dispc.irq_error_mask &= ~unhandled_errors;
3014                 _omap_dispc_set_irqs();
3015
3016                 schedule_work(&dispc.error_work);
3017         }
3018
3019         spin_unlock(&dispc.irq_lock);
3020
3021         return IRQ_HANDLED;
3022 }
3023
3024 static void dispc_error_worker(struct work_struct *work)
3025 {
3026         int i;
3027         u32 errors;
3028         unsigned long flags;
3029         static const unsigned fifo_underflow_bits[] = {
3030                 DISPC_IRQ_GFX_FIFO_UNDERFLOW,
3031                 DISPC_IRQ_VID1_FIFO_UNDERFLOW,
3032                 DISPC_IRQ_VID2_FIFO_UNDERFLOW,
3033         };
3034
3035         static const unsigned sync_lost_bits[] = {
3036                 DISPC_IRQ_SYNC_LOST,
3037                 DISPC_IRQ_SYNC_LOST_DIGIT,
3038                 DISPC_IRQ_SYNC_LOST2,
3039         };
3040
3041         spin_lock_irqsave(&dispc.irq_lock, flags);
3042         errors = dispc.error_irqs;
3043         dispc.error_irqs = 0;
3044         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3045
3046         dispc_runtime_get();
3047
3048         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3049                 struct omap_overlay *ovl;
3050                 unsigned bit;
3051
3052                 ovl = omap_dss_get_overlay(i);
3053                 bit = fifo_underflow_bits[i];
3054
3055                 if (bit & errors) {
3056                         DSSERR("FIFO UNDERFLOW on %s, disabling the overlay\n",
3057                                         ovl->name);
3058                         dispc_enable_plane(ovl->id, false);
3059                         dispc_go(ovl->manager->id);
3060                         mdelay(50);
3061                 }
3062         }
3063
3064         for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3065                 struct omap_overlay_manager *mgr;
3066                 unsigned bit;
3067
3068                 mgr = omap_dss_get_overlay_manager(i);
3069                 bit = sync_lost_bits[i];
3070
3071                 if (bit & errors) {
3072                         struct omap_dss_device *dssdev = mgr->device;
3073                         bool enable;
3074
3075                         DSSERR("SYNC_LOST on channel %s, restarting the output "
3076                                         "with video overlays disabled\n",
3077                                         mgr->name);
3078
3079                         enable = dssdev->state == OMAP_DSS_DISPLAY_ACTIVE;
3080                         dssdev->driver->disable(dssdev);
3081
3082                         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3083                                 struct omap_overlay *ovl;
3084                                 ovl = omap_dss_get_overlay(i);
3085
3086                                 if (ovl->id != OMAP_DSS_GFX &&
3087                                                 ovl->manager == mgr)
3088                                         dispc_enable_plane(ovl->id, false);
3089                         }
3090
3091                         dispc_go(mgr->id);
3092                         mdelay(50);
3093
3094                         if (enable)
3095                                 dssdev->driver->enable(dssdev);
3096                 }
3097         }
3098
3099         if (errors & DISPC_IRQ_OCP_ERR) {
3100                 DSSERR("OCP_ERR\n");
3101                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3102                         struct omap_overlay_manager *mgr;
3103                         mgr = omap_dss_get_overlay_manager(i);
3104                         mgr->device->driver->disable(mgr->device);
3105                 }
3106         }
3107
3108         spin_lock_irqsave(&dispc.irq_lock, flags);
3109         dispc.irq_error_mask |= errors;
3110         _omap_dispc_set_irqs();
3111         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3112
3113         dispc_runtime_put();
3114 }
3115
3116 int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3117 {
3118         void dispc_irq_wait_handler(void *data, u32 mask)
3119         {
3120                 complete((struct completion *)data);
3121         }
3122
3123         int r;
3124         DECLARE_COMPLETION_ONSTACK(completion);
3125
3126         r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3127                         irqmask);
3128
3129         if (r)
3130                 return r;
3131
3132         timeout = wait_for_completion_timeout(&completion, timeout);
3133
3134         omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3135
3136         if (timeout == 0)
3137                 return -ETIMEDOUT;
3138
3139         if (timeout == -ERESTARTSYS)
3140                 return -ERESTARTSYS;
3141
3142         return 0;
3143 }
3144
3145 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3146                 unsigned long timeout)
3147 {
3148         void dispc_irq_wait_handler(void *data, u32 mask)
3149         {
3150                 complete((struct completion *)data);
3151         }
3152
3153         int r;
3154         DECLARE_COMPLETION_ONSTACK(completion);
3155
3156         r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3157                         irqmask);
3158
3159         if (r)
3160                 return r;
3161
3162         timeout = wait_for_completion_interruptible_timeout(&completion,
3163                         timeout);
3164
3165         omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3166
3167         if (timeout == 0)
3168                 return -ETIMEDOUT;
3169
3170         if (timeout == -ERESTARTSYS)
3171                 return -ERESTARTSYS;
3172
3173         return 0;
3174 }
3175
3176 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
3177 void dispc_fake_vsync_irq(void)
3178 {
3179         u32 irqstatus = DISPC_IRQ_VSYNC;
3180         int i;
3181
3182         WARN_ON(!in_interrupt());
3183
3184         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3185                 struct omap_dispc_isr_data *isr_data;
3186                 isr_data = &dispc.registered_isr[i];
3187
3188                 if (!isr_data->isr)
3189                         continue;
3190
3191                 if (isr_data->mask & irqstatus)
3192                         isr_data->isr(isr_data->arg, irqstatus);
3193         }
3194 }
3195 #endif
3196
3197 static void _omap_dispc_initialize_irq(void)
3198 {
3199         unsigned long flags;
3200
3201         spin_lock_irqsave(&dispc.irq_lock, flags);
3202
3203         memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3204
3205         dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
3206         if (dss_has_feature(FEAT_MGR_LCD2))
3207                 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
3208
3209         /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3210          * so clear it */
3211         dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3212
3213         _omap_dispc_set_irqs();
3214
3215         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3216 }
3217
3218 void dispc_enable_sidle(void)
3219 {
3220         REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3);  /* SIDLEMODE: smart idle */
3221 }
3222
3223 void dispc_disable_sidle(void)
3224 {
3225         REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3);  /* SIDLEMODE: no idle */
3226 }
3227
3228 static void _omap_dispc_initial_config(void)
3229 {
3230         u32 l;
3231
3232         /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3233         if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3234                 l = dispc_read_reg(DISPC_DIVISOR);
3235                 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3236                 l = FLD_MOD(l, 1, 0, 0);
3237                 l = FLD_MOD(l, 1, 23, 16);
3238                 dispc_write_reg(DISPC_DIVISOR, l);
3239         }
3240
3241         /* FUNCGATED */
3242         if (dss_has_feature(FEAT_FUNCGATED))
3243                 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3244
3245         /* L3 firewall setting: enable access to OCM RAM */
3246         /* XXX this should be somewhere in plat-omap */
3247         if (cpu_is_omap24xx())
3248                 __raw_writel(0x402000b0, OMAP2_L3_IO_ADDRESS(0x680050a0));
3249
3250         _dispc_setup_color_conv_coef();
3251
3252         dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3253
3254         dispc_read_plane_fifo_sizes();
3255
3256         dispc_configure_burst_sizes();
3257 }
3258
3259 /* DISPC HW IP initialisation */
3260 static int omap_dispchw_probe(struct platform_device *pdev)
3261 {
3262         u32 rev;
3263         int r = 0;
3264         struct resource *dispc_mem;
3265         struct clk *clk;
3266
3267         dispc.pdev = pdev;
3268
3269         clk = clk_get(&pdev->dev, "fck");
3270         if (IS_ERR(clk)) {
3271                 DSSERR("can't get fck\n");
3272                 r = PTR_ERR(clk);
3273                 goto err_get_clk;
3274         }
3275
3276         dispc.dss_clk = clk;
3277
3278         spin_lock_init(&dispc.irq_lock);
3279
3280 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3281         spin_lock_init(&dispc.irq_stats_lock);
3282         dispc.irq_stats.last_reset = jiffies;
3283 #endif
3284
3285         INIT_WORK(&dispc.error_work, dispc_error_worker);
3286
3287         dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3288         if (!dispc_mem) {
3289                 DSSERR("can't get IORESOURCE_MEM DISPC\n");
3290                 r = -EINVAL;
3291                 goto err_ioremap;
3292         }
3293         dispc.base = ioremap(dispc_mem->start, resource_size(dispc_mem));
3294         if (!dispc.base) {
3295                 DSSERR("can't ioremap DISPC\n");
3296                 r = -ENOMEM;
3297                 goto err_ioremap;
3298         }
3299         dispc.irq = platform_get_irq(dispc.pdev, 0);
3300         if (dispc.irq < 0) {
3301                 DSSERR("platform_get_irq failed\n");
3302                 r = -ENODEV;
3303                 goto err_irq;
3304         }
3305
3306         r = request_irq(dispc.irq, omap_dispc_irq_handler, IRQF_SHARED,
3307                 "OMAP DISPC", dispc.pdev);
3308         if (r < 0) {
3309                 DSSERR("request_irq failed\n");
3310                 goto err_irq;
3311         }
3312
3313         pm_runtime_enable(&pdev->dev);
3314
3315         r = dispc_runtime_get();
3316         if (r)
3317                 goto err_runtime_get;
3318
3319         _omap_dispc_initial_config();
3320
3321         _omap_dispc_initialize_irq();
3322
3323         rev = dispc_read_reg(DISPC_REVISION);
3324         dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
3325                FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3326
3327         dispc_runtime_put();
3328
3329         return 0;
3330
3331 err_runtime_get:
3332         pm_runtime_disable(&pdev->dev);
3333         free_irq(dispc.irq, dispc.pdev);
3334 err_irq:
3335         iounmap(dispc.base);
3336 err_ioremap:
3337         clk_put(dispc.dss_clk);
3338 err_get_clk:
3339         return r;
3340 }
3341
3342 static int omap_dispchw_remove(struct platform_device *pdev)
3343 {
3344         pm_runtime_disable(&pdev->dev);
3345
3346         clk_put(dispc.dss_clk);
3347
3348         free_irq(dispc.irq, dispc.pdev);
3349         iounmap(dispc.base);
3350         return 0;
3351 }
3352
3353 static int dispc_runtime_suspend(struct device *dev)
3354 {
3355         dispc_save_context();
3356         dss_runtime_put();
3357
3358         return 0;
3359 }
3360
3361 static int dispc_runtime_resume(struct device *dev)
3362 {
3363         int r;
3364
3365         r = dss_runtime_get();
3366         if (r < 0)
3367                 return r;
3368
3369         dispc_restore_context();
3370
3371         return 0;
3372 }
3373
3374 static const struct dev_pm_ops dispc_pm_ops = {
3375         .runtime_suspend = dispc_runtime_suspend,
3376         .runtime_resume = dispc_runtime_resume,
3377 };
3378
3379 static struct platform_driver omap_dispchw_driver = {
3380         .probe          = omap_dispchw_probe,
3381         .remove         = omap_dispchw_remove,
3382         .driver         = {
3383                 .name   = "omapdss_dispc",
3384                 .owner  = THIS_MODULE,
3385                 .pm     = &dispc_pm_ops,
3386         },
3387 };
3388
3389 int dispc_init_platform_driver(void)
3390 {
3391         return platform_driver_register(&omap_dispchw_driver);
3392 }
3393
3394 void dispc_uninit_platform_driver(void)
3395 {
3396         return platform_driver_unregister(&omap_dispchw_driver);
3397 }