drivers/video/omap2/dss/dispc.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dispc.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #define DSS_SUBSYS_NAME "DISPC"
  24
  25 #include <linux/kernel.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/vmalloc.h>
  28 #include <linux/clk.h>
  29 #include <linux/io.h>
  30 #include <linux/jiffies.h>
  31 #include <linux/seq_file.h>
  32 #include <linux/delay.h>
  33 #include <linux/workqueue.h>
  34 #include <linux/hardirq.h>
  35 #include <linux/interrupt.h>
  36
  37 #include <plat/sram.h>
  38 #include <plat/clock.h>
  39
  40 #include <plat/display.h>
  41
  42 #include "dss.h"
  43 #include "dss_features.h"
  44
  45 /* DISPC */
  46 #define DISPC_SZ_REGS                   SZ_4K
  47
  48 struct dispc_reg { u16 idx; };
  49
  50 #define DISPC_REG(idx)                  ((const struct dispc_reg) { idx })
  51
  52 /*
  53  * DISPC common registers and
  54  * DISPC channel registers , ch = 0 for LCD, ch = 1 for
  55  * DIGIT, and ch = 2 for LCD2
  56  */
  57 #define DISPC_REVISION                  DISPC_REG(0x0000)
  58 #define DISPC_SYSCONFIG                 DISPC_REG(0x0010)
  59 #define DISPC_SYSSTATUS                 DISPC_REG(0x0014)
  60 #define DISPC_IRQSTATUS                 DISPC_REG(0x0018)
  61 #define DISPC_IRQENABLE                 DISPC_REG(0x001C)
  62 #define DISPC_CONTROL                   DISPC_REG(0x0040)
  63 #define DISPC_CONTROL2                  DISPC_REG(0x0238)
  64 #define DISPC_CONFIG                    DISPC_REG(0x0044)
  65 #define DISPC_CONFIG2                   DISPC_REG(0x0620)
  66 #define DISPC_CAPABLE                   DISPC_REG(0x0048)
  67 #define DISPC_DEFAULT_COLOR(ch)         DISPC_REG(ch == 0 ? 0x004C : \
  68                                         (ch == 1 ? 0x0050 : 0x03AC))
  69 #define DISPC_TRANS_COLOR(ch)           DISPC_REG(ch == 0 ? 0x0054 : \
  70                                         (ch == 1 ? 0x0058 : 0x03B0))
  71 #define DISPC_LINE_STATUS               DISPC_REG(0x005C)
  72 #define DISPC_LINE_NUMBER               DISPC_REG(0x0060)
  73 #define DISPC_TIMING_H(ch)              DISPC_REG(ch != 2 ? 0x0064 : 0x0400)
  74 #define DISPC_TIMING_V(ch)              DISPC_REG(ch != 2 ? 0x0068 : 0x0404)
  75 #define DISPC_POL_FREQ(ch)              DISPC_REG(ch != 2 ? 0x006C : 0x0408)
  76 #define DISPC_DIVISORo(ch)              DISPC_REG(ch != 2 ? 0x0070 : 0x040C)
  77 #define DISPC_GLOBAL_ALPHA              DISPC_REG(0x0074)
  78 #define DISPC_SIZE_DIG                  DISPC_REG(0x0078)
  79 #define DISPC_SIZE_LCD(ch)              DISPC_REG(ch != 2 ? 0x007C : 0x03CC)
  80
  81 /* DISPC GFX plane */
  82 #define DISPC_GFX_BA0                   DISPC_REG(0x0080)
  83 #define DISPC_GFX_BA1                   DISPC_REG(0x0084)
  84 #define DISPC_GFX_POSITION              DISPC_REG(0x0088)
  85 #define DISPC_GFX_SIZE                  DISPC_REG(0x008C)
  86 #define DISPC_GFX_ATTRIBUTES            DISPC_REG(0x00A0)
  87 #define DISPC_GFX_FIFO_THRESHOLD        DISPC_REG(0x00A4)
  88 #define DISPC_GFX_FIFO_SIZE_STATUS      DISPC_REG(0x00A8)
  89 #define DISPC_GFX_ROW_INC               DISPC_REG(0x00AC)
  90 #define DISPC_GFX_PIXEL_INC             DISPC_REG(0x00B0)
  91 #define DISPC_GFX_WINDOW_SKIP           DISPC_REG(0x00B4)
  92 #define DISPC_GFX_TABLE_BA              DISPC_REG(0x00B8)
  93
  94 #define DISPC_DATA_CYCLE1(ch)           DISPC_REG(ch != 2 ? 0x01D4 : 0x03C0)
  95 #define DISPC_DATA_CYCLE2(ch)           DISPC_REG(ch != 2 ? 0x01D8 : 0x03C4)
  96 #define DISPC_DATA_CYCLE3(ch)           DISPC_REG(ch != 2 ? 0x01DC : 0x03C8)
  97 #define DISPC_CPR_COEF_R(ch)            DISPC_REG(ch != 2 ? 0x0220 : 0x03BC)
  98 #define DISPC_CPR_COEF_G(ch)            DISPC_REG(ch != 2 ? 0x0224 : 0x03B8)
  99 #define DISPC_CPR_COEF_B(ch)            DISPC_REG(ch != 2 ? 0x0228 : 0x03B4)
 100
 101 #define DISPC_GFX_PRELOAD               DISPC_REG(0x022C)
 102
 103 /* DISPC Video plane, n = 0 for VID1 and n = 1 for VID2 */
 104 #define DISPC_VID_REG(n, idx)           DISPC_REG(0x00BC + (n)*0x90 + idx)
 105
 106 #define DISPC_VID_BA0(n)                DISPC_VID_REG(n, 0x0000)
 107 #define DISPC_VID_BA1(n)                DISPC_VID_REG(n, 0x0004)
 108 #define DISPC_VID_POSITION(n)           DISPC_VID_REG(n, 0x0008)
 109 #define DISPC_VID_SIZE(n)               DISPC_VID_REG(n, 0x000C)
 110 #define DISPC_VID_ATTRIBUTES(n)         DISPC_VID_REG(n, 0x0010)
 111 #define DISPC_VID_FIFO_THRESHOLD(n)     DISPC_VID_REG(n, 0x0014)
 112 #define DISPC_VID_FIFO_SIZE_STATUS(n)   DISPC_VID_REG(n, 0x0018)
 113 #define DISPC_VID_ROW_INC(n)            DISPC_VID_REG(n, 0x001C)
 114 #define DISPC_VID_PIXEL_INC(n)          DISPC_VID_REG(n, 0x0020)
 115 #define DISPC_VID_FIR(n)                DISPC_VID_REG(n, 0x0024)
 116 #define DISPC_VID_PICTURE_SIZE(n)       DISPC_VID_REG(n, 0x0028)
 117 #define DISPC_VID_ACCU0(n)              DISPC_VID_REG(n, 0x002C)
 118 #define DISPC_VID_ACCU1(n)              DISPC_VID_REG(n, 0x0030)
 119
 120 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 121 #define DISPC_VID_FIR_COEF_H(n, i)      DISPC_REG(0x00F0 + (n)*0x90 + (i)*0x8)
 122 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 123 #define DISPC_VID_FIR_COEF_HV(n, i)     DISPC_REG(0x00F4 + (n)*0x90 + (i)*0x8)
 124 /* coef index i = {0, 1, 2, 3, 4} */
 125 #define DISPC_VID_CONV_COEF(n, i)       DISPC_REG(0x0130 + (n)*0x90 + (i)*0x4)
 126 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 127 #define DISPC_VID_FIR_COEF_V(n, i)      DISPC_REG(0x01E0 + (n)*0x20 + (i)*0x4)
 128
 129 #define DISPC_VID_PRELOAD(n)            DISPC_REG(0x230 + (n)*0x04)
 130
 131 #define DISPC_DIVISOR                   DISPC_REG(0x0804)
 132
 133 #define DISPC_IRQ_MASK_ERROR            (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
 134                                          DISPC_IRQ_OCP_ERR | \
 135                                          DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
 136                                          DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
 137                                          DISPC_IRQ_SYNC_LOST | \
 138                                          DISPC_IRQ_SYNC_LOST_DIGIT)
 139
 140 #define DISPC_MAX_NR_ISRS               8
 141
 142 struct omap_dispc_isr_data {
 143         omap_dispc_isr_t        isr;
 144         void                    *arg;
 145         u32                     mask;
 146 };
 147
 148 struct dispc_h_coef {
 149         s8 hc4;
 150         s8 hc3;
 151         u8 hc2;
 152         s8 hc1;
 153         s8 hc0;
 154 };
 155
 156 struct dispc_v_coef {
 157         s8 vc22;
 158         s8 vc2;
 159         u8 vc1;
 160         s8 vc0;
 161         s8 vc00;
 162 };
 163
 164 #define REG_GET(idx, start, end) \
 165         FLD_GET(dispc_read_reg(idx), start, end)
 166
 167 #define REG_FLD_MOD(idx, val, start, end)                               \
 168         dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
 169
 170 static const struct dispc_reg dispc_reg_att[] = { DISPC_GFX_ATTRIBUTES,
 171         DISPC_VID_ATTRIBUTES(0),
 172         DISPC_VID_ATTRIBUTES(1) };
 173
 174 struct dispc_irq_stats {
 175         unsigned long last_reset;
 176         unsigned irq_count;
 177         unsigned irqs[32];
 178 };
 179
 180 static struct {
 181         struct platform_device *pdev;
 182         void __iomem    *base;
 183         int irq;
 184
 185         u32     fifo_size[3];
 186
 187         spinlock_t irq_lock;
 188         u32 irq_error_mask;
 189         struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
 190         u32 error_irqs;
 191         struct work_struct error_work;
 192
 193         u32             ctx[DISPC_SZ_REGS / sizeof(u32)];
 194
 195 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
 196         spinlock_t irq_stats_lock;
 197         struct dispc_irq_stats irq_stats;
 198 #endif
 199 } dispc;
 200
 201 static void _omap_dispc_set_irqs(void);
 202
 203 static inline void dispc_write_reg(const struct dispc_reg idx, u32 val)
 204 {
 205         __raw_writel(val, dispc.base + idx.idx);
 206 }
 207
 208 static inline u32 dispc_read_reg(const struct dispc_reg idx)
 209 {
 210         return __raw_readl(dispc.base + idx.idx);
 211 }
 212
 213 #define SR(reg) \
 214         dispc.ctx[(DISPC_##reg).idx / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
 215 #define RR(reg) \
 216         dispc_write_reg(DISPC_##reg, dispc.ctx[(DISPC_##reg).idx / sizeof(u32)])
 217
 218 void dispc_save_context(void)
 219 {
 220         if (cpu_is_omap24xx())
 221                 return;
 222
 223         SR(SYSCONFIG);
 224         SR(IRQENABLE);
 225         SR(CONTROL);
 226         SR(CONFIG);
 227         SR(DEFAULT_COLOR(0));
 228         SR(DEFAULT_COLOR(1));
 229         SR(TRANS_COLOR(0));
 230         SR(TRANS_COLOR(1));
 231         SR(LINE_NUMBER);
 232         SR(TIMING_H(0));
 233         SR(TIMING_V(0));
 234         SR(POL_FREQ(0));
 235         SR(DIVISORo(0));
 236         SR(GLOBAL_ALPHA);
 237         SR(SIZE_DIG);
 238         SR(SIZE_LCD(0));
 239         if (dss_has_feature(FEAT_MGR_LCD2)) {
 240                 SR(CONTROL2);
 241                 SR(DEFAULT_COLOR(2));
 242                 SR(TRANS_COLOR(2));
 243                 SR(SIZE_LCD(2));
 244                 SR(TIMING_H(2));
 245                 SR(TIMING_V(2));
 246                 SR(POL_FREQ(2));
 247                 SR(DIVISORo(2));
 248                 SR(CONFIG2);
 249         }
 250
 251         SR(GFX_BA0);
 252         SR(GFX_BA1);
 253         SR(GFX_POSITION);
 254         SR(GFX_SIZE);
 255         SR(GFX_ATTRIBUTES);
 256         SR(GFX_FIFO_THRESHOLD);
 257         SR(GFX_ROW_INC);
 258         SR(GFX_PIXEL_INC);
 259         SR(GFX_WINDOW_SKIP);
 260         SR(GFX_TABLE_BA);
 261
 262         SR(DATA_CYCLE1(0));
 263         SR(DATA_CYCLE2(0));
 264         SR(DATA_CYCLE3(0));
 265
 266         SR(CPR_COEF_R(0));
 267         SR(CPR_COEF_G(0));
 268         SR(CPR_COEF_B(0));
 269         if (dss_has_feature(FEAT_MGR_LCD2)) {
 270                 SR(CPR_COEF_B(2));
 271                 SR(CPR_COEF_G(2));
 272                 SR(CPR_COEF_R(2));
 273
 274                 SR(DATA_CYCLE1(2));
 275                 SR(DATA_CYCLE2(2));
 276                 SR(DATA_CYCLE3(2));
 277         }
 278
 279         SR(GFX_PRELOAD);
 280
 281         /* VID1 */
 282         SR(VID_BA0(0));
 283         SR(VID_BA1(0));
 284         SR(VID_POSITION(0));
 285         SR(VID_SIZE(0));
 286         SR(VID_ATTRIBUTES(0));
 287         SR(VID_FIFO_THRESHOLD(0));
 288         SR(VID_ROW_INC(0));
 289         SR(VID_PIXEL_INC(0));
 290         SR(VID_FIR(0));
 291         SR(VID_PICTURE_SIZE(0));
 292         SR(VID_ACCU0(0));
 293         SR(VID_ACCU1(0));
 294
 295         SR(VID_FIR_COEF_H(0, 0));
 296         SR(VID_FIR_COEF_H(0, 1));
 297         SR(VID_FIR_COEF_H(0, 2));
 298         SR(VID_FIR_COEF_H(0, 3));
 299         SR(VID_FIR_COEF_H(0, 4));
 300         SR(VID_FIR_COEF_H(0, 5));
 301         SR(VID_FIR_COEF_H(0, 6));
 302         SR(VID_FIR_COEF_H(0, 7));
 303
 304         SR(VID_FIR_COEF_HV(0, 0));
 305         SR(VID_FIR_COEF_HV(0, 1));
 306         SR(VID_FIR_COEF_HV(0, 2));
 307         SR(VID_FIR_COEF_HV(0, 3));
 308         SR(VID_FIR_COEF_HV(0, 4));
 309         SR(VID_FIR_COEF_HV(0, 5));
 310         SR(VID_FIR_COEF_HV(0, 6));
 311         SR(VID_FIR_COEF_HV(0, 7));
 312
 313         SR(VID_CONV_COEF(0, 0));
 314         SR(VID_CONV_COEF(0, 1));
 315         SR(VID_CONV_COEF(0, 2));
 316         SR(VID_CONV_COEF(0, 3));
 317         SR(VID_CONV_COEF(0, 4));
 318
 319         SR(VID_FIR_COEF_V(0, 0));
 320         SR(VID_FIR_COEF_V(0, 1));
 321         SR(VID_FIR_COEF_V(0, 2));
 322         SR(VID_FIR_COEF_V(0, 3));
 323         SR(VID_FIR_COEF_V(0, 4));
 324         SR(VID_FIR_COEF_V(0, 5));
 325         SR(VID_FIR_COEF_V(0, 6));
 326         SR(VID_FIR_COEF_V(0, 7));
 327
 328         SR(VID_PRELOAD(0));
 329
 330         /* VID2 */
 331         SR(VID_BA0(1));
 332         SR(VID_BA1(1));
 333         SR(VID_POSITION(1));
 334         SR(VID_SIZE(1));
 335         SR(VID_ATTRIBUTES(1));
 336         SR(VID_FIFO_THRESHOLD(1));
 337         SR(VID_ROW_INC(1));
 338         SR(VID_PIXEL_INC(1));
 339         SR(VID_FIR(1));
 340         SR(VID_PICTURE_SIZE(1));
 341         SR(VID_ACCU0(1));
 342         SR(VID_ACCU1(1));
 343
 344         SR(VID_FIR_COEF_H(1, 0));
 345         SR(VID_FIR_COEF_H(1, 1));
 346         SR(VID_FIR_COEF_H(1, 2));
 347         SR(VID_FIR_COEF_H(1, 3));
 348         SR(VID_FIR_COEF_H(1, 4));
 349         SR(VID_FIR_COEF_H(1, 5));
 350         SR(VID_FIR_COEF_H(1, 6));
 351         SR(VID_FIR_COEF_H(1, 7));
 352
 353         SR(VID_FIR_COEF_HV(1, 0));
 354         SR(VID_FIR_COEF_HV(1, 1));
 355         SR(VID_FIR_COEF_HV(1, 2));
 356         SR(VID_FIR_COEF_HV(1, 3));
 357         SR(VID_FIR_COEF_HV(1, 4));
 358         SR(VID_FIR_COEF_HV(1, 5));
 359         SR(VID_FIR_COEF_HV(1, 6));
 360         SR(VID_FIR_COEF_HV(1, 7));
 361
 362         SR(VID_CONV_COEF(1, 0));
 363         SR(VID_CONV_COEF(1, 1));
 364         SR(VID_CONV_COEF(1, 2));
 365         SR(VID_CONV_COEF(1, 3));
 366         SR(VID_CONV_COEF(1, 4));
 367
 368         SR(VID_FIR_COEF_V(1, 0));
 369         SR(VID_FIR_COEF_V(1, 1));
 370         SR(VID_FIR_COEF_V(1, 2));
 371         SR(VID_FIR_COEF_V(1, 3));
 372         SR(VID_FIR_COEF_V(1, 4));
 373         SR(VID_FIR_COEF_V(1, 5));
 374         SR(VID_FIR_COEF_V(1, 6));
 375         SR(VID_FIR_COEF_V(1, 7));
 376
 377         SR(VID_PRELOAD(1));
 378
 379         if (dss_has_feature(FEAT_CORE_CLK_DIV))
 380                 SR(DIVISOR);
 381 }
 382
 383 void dispc_restore_context(void)
 384 {
 385         RR(SYSCONFIG);
 386         /*RR(IRQENABLE);*/
 387         /*RR(CONTROL);*/
 388         RR(CONFIG);
 389         RR(DEFAULT_COLOR(0));
 390         RR(DEFAULT_COLOR(1));
 391         RR(TRANS_COLOR(0));
 392         RR(TRANS_COLOR(1));
 393         RR(LINE_NUMBER);
 394         RR(TIMING_H(0));
 395         RR(TIMING_V(0));
 396         RR(POL_FREQ(0));
 397         RR(DIVISORo(0));
 398         RR(GLOBAL_ALPHA);
 399         RR(SIZE_DIG);
 400         RR(SIZE_LCD(0));
 401         if (dss_has_feature(FEAT_MGR_LCD2)) {
 402                 RR(DEFAULT_COLOR(2));
 403                 RR(TRANS_COLOR(2));
 404                 RR(SIZE_LCD(2));
 405                 RR(TIMING_H(2));
 406                 RR(TIMING_V(2));
 407                 RR(POL_FREQ(2));
 408                 RR(DIVISORo(2));
 409                 RR(CONFIG2);
 410         }
 411
 412         RR(GFX_BA0);
 413         RR(GFX_BA1);
 414         RR(GFX_POSITION);
 415         RR(GFX_SIZE);
 416         RR(GFX_ATTRIBUTES);
 417         RR(GFX_FIFO_THRESHOLD);
 418         RR(GFX_ROW_INC);
 419         RR(GFX_PIXEL_INC);
 420         RR(GFX_WINDOW_SKIP);
 421         RR(GFX_TABLE_BA);
 422
 423         RR(DATA_CYCLE1(0));
 424         RR(DATA_CYCLE2(0));
 425         RR(DATA_CYCLE3(0));
 426
 427         RR(CPR_COEF_R(0));
 428         RR(CPR_COEF_G(0));
 429         RR(CPR_COEF_B(0));
 430         if (dss_has_feature(FEAT_MGR_LCD2)) {
 431                 RR(DATA_CYCLE1(2));
 432                 RR(DATA_CYCLE2(2));
 433                 RR(DATA_CYCLE3(2));
 434
 435                 RR(CPR_COEF_B(2));
 436                 RR(CPR_COEF_G(2));
 437                 RR(CPR_COEF_R(2));
 438         }
 439
 440         RR(GFX_PRELOAD);
 441
 442         /* VID1 */
 443         RR(VID_BA0(0));
 444         RR(VID_BA1(0));
 445         RR(VID_POSITION(0));
 446         RR(VID_SIZE(0));
 447         RR(VID_ATTRIBUTES(0));
 448         RR(VID_FIFO_THRESHOLD(0));
 449         RR(VID_ROW_INC(0));
 450         RR(VID_PIXEL_INC(0));
 451         RR(VID_FIR(0));
 452         RR(VID_PICTURE_SIZE(0));
 453         RR(VID_ACCU0(0));
 454         RR(VID_ACCU1(0));
 455
 456         RR(VID_FIR_COEF_H(0, 0));
 457         RR(VID_FIR_COEF_H(0, 1));
 458         RR(VID_FIR_COEF_H(0, 2));
 459         RR(VID_FIR_COEF_H(0, 3));
 460         RR(VID_FIR_COEF_H(0, 4));
 461         RR(VID_FIR_COEF_H(0, 5));
 462         RR(VID_FIR_COEF_H(0, 6));
 463         RR(VID_FIR_COEF_H(0, 7));
 464
 465         RR(VID_FIR_COEF_HV(0, 0));
 466         RR(VID_FIR_COEF_HV(0, 1));
 467         RR(VID_FIR_COEF_HV(0, 2));
 468         RR(VID_FIR_COEF_HV(0, 3));
 469         RR(VID_FIR_COEF_HV(0, 4));
 470         RR(VID_FIR_COEF_HV(0, 5));
 471         RR(VID_FIR_COEF_HV(0, 6));
 472         RR(VID_FIR_COEF_HV(0, 7));
 473
 474         RR(VID_CONV_COEF(0, 0));
 475         RR(VID_CONV_COEF(0, 1));
 476         RR(VID_CONV_COEF(0, 2));
 477         RR(VID_CONV_COEF(0, 3));
 478         RR(VID_CONV_COEF(0, 4));
 479
 480         RR(VID_FIR_COEF_V(0, 0));
 481         RR(VID_FIR_COEF_V(0, 1));
 482         RR(VID_FIR_COEF_V(0, 2));
 483         RR(VID_FIR_COEF_V(0, 3));
 484         RR(VID_FIR_COEF_V(0, 4));
 485         RR(VID_FIR_COEF_V(0, 5));
 486         RR(VID_FIR_COEF_V(0, 6));
 487         RR(VID_FIR_COEF_V(0, 7));
 488
 489         RR(VID_PRELOAD(0));
 490
 491         /* VID2 */
 492         RR(VID_BA0(1));
 493         RR(VID_BA1(1));
 494         RR(VID_POSITION(1));
 495         RR(VID_SIZE(1));
 496         RR(VID_ATTRIBUTES(1));
 497         RR(VID_FIFO_THRESHOLD(1));
 498         RR(VID_ROW_INC(1));
 499         RR(VID_PIXEL_INC(1));
 500         RR(VID_FIR(1));
 501         RR(VID_PICTURE_SIZE(1));
 502         RR(VID_ACCU0(1));
 503         RR(VID_ACCU1(1));
 504
 505         RR(VID_FIR_COEF_H(1, 0));
 506         RR(VID_FIR_COEF_H(1, 1));
 507         RR(VID_FIR_COEF_H(1, 2));
 508         RR(VID_FIR_COEF_H(1, 3));
 509         RR(VID_FIR_COEF_H(1, 4));
 510         RR(VID_FIR_COEF_H(1, 5));
 511         RR(VID_FIR_COEF_H(1, 6));
 512         RR(VID_FIR_COEF_H(1, 7));
 513
 514         RR(VID_FIR_COEF_HV(1, 0));
 515         RR(VID_FIR_COEF_HV(1, 1));
 516         RR(VID_FIR_COEF_HV(1, 2));
 517         RR(VID_FIR_COEF_HV(1, 3));
 518         RR(VID_FIR_COEF_HV(1, 4));
 519         RR(VID_FIR_COEF_HV(1, 5));
 520         RR(VID_FIR_COEF_HV(1, 6));
 521         RR(VID_FIR_COEF_HV(1, 7));
 522
 523         RR(VID_CONV_COEF(1, 0));
 524         RR(VID_CONV_COEF(1, 1));
 525         RR(VID_CONV_COEF(1, 2));
 526         RR(VID_CONV_COEF(1, 3));
 527         RR(VID_CONV_COEF(1, 4));
 528
 529         RR(VID_FIR_COEF_V(1, 0));
 530         RR(VID_FIR_COEF_V(1, 1));
 531         RR(VID_FIR_COEF_V(1, 2));
 532         RR(VID_FIR_COEF_V(1, 3));
 533         RR(VID_FIR_COEF_V(1, 4));
 534         RR(VID_FIR_COEF_V(1, 5));
 535         RR(VID_FIR_COEF_V(1, 6));
 536         RR(VID_FIR_COEF_V(1, 7));
 537
 538         RR(VID_PRELOAD(1));
 539
 540         if (dss_has_feature(FEAT_CORE_CLK_DIV))
 541                 RR(DIVISOR);
 542
 543         /* enable last, because LCD & DIGIT enable are here */
 544         RR(CONTROL);
 545         if (dss_has_feature(FEAT_MGR_LCD2))
 546                 RR(CONTROL2);
 547         /* clear spurious SYNC_LOST_DIGIT interrupts */
 548         dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
 549
 550         /*
 551          * enable last so IRQs won't trigger before
 552          * the context is fully restored
 553          */
 554         RR(IRQENABLE);
 555 }
 556
 557 #undef SR
 558 #undef RR
 559
 560 static inline void enable_clocks(bool enable)
 561 {
 562         if (enable)
 563                 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
 564         else
 565                 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
 566 }
 567
 568 bool dispc_go_busy(enum omap_channel channel)
 569 {
 570         int bit;
 571
 572         if (channel == OMAP_DSS_CHANNEL_LCD ||
 573                         channel == OMAP_DSS_CHANNEL_LCD2)
 574                 bit = 5; /* GOLCD */
 575         else
 576                 bit = 6; /* GODIGIT */
 577
 578         if (channel == OMAP_DSS_CHANNEL_LCD2)
 579                 return REG_GET(DISPC_CONTROL2, bit, bit) == 1;
 580         else
 581                 return REG_GET(DISPC_CONTROL, bit, bit) == 1;
 582 }
 583
 584 void dispc_go(enum omap_channel channel)
 585 {
 586         int bit;
 587         bool enable_bit, go_bit;
 588
 589         enable_clocks(1);
 590
 591         if (channel == OMAP_DSS_CHANNEL_LCD ||
 592                         channel == OMAP_DSS_CHANNEL_LCD2)
 593                 bit = 0; /* LCDENABLE */
 594         else
 595                 bit = 1; /* DIGITALENABLE */
 596
 597         /* if the channel is not enabled, we don't need GO */
 598         if (channel == OMAP_DSS_CHANNEL_LCD2)
 599                 enable_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
 600         else
 601                 enable_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
 602
 603         if (!enable_bit)
 604                 goto end;
 605
 606         if (channel == OMAP_DSS_CHANNEL_LCD ||
 607                         channel == OMAP_DSS_CHANNEL_LCD2)
 608                 bit = 5; /* GOLCD */
 609         else
 610                 bit = 6; /* GODIGIT */
 611
 612         if (channel == OMAP_DSS_CHANNEL_LCD2)
 613                 go_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
 614         else
 615                 go_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
 616
 617         if (go_bit) {
 618                 DSSERR("GO bit not down for channel %d\n", channel);
 619                 goto end;
 620         }
 621
 622         DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" :
 623                 (channel == OMAP_DSS_CHANNEL_LCD2 ? "LCD2" : "DIGIT"));
 624
 625         if (channel == OMAP_DSS_CHANNEL_LCD2)
 626                 REG_FLD_MOD(DISPC_CONTROL2, 1, bit, bit);
 627         else
 628                 REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
 629 end:
 630         enable_clocks(0);
 631 }
 632
 633 static void _dispc_write_firh_reg(enum omap_plane plane, int reg, u32 value)
 634 {
 635         BUG_ON(plane == OMAP_DSS_GFX);
 636
 637         dispc_write_reg(DISPC_VID_FIR_COEF_H(plane-1, reg), value);
 638 }
 639
 640 static void _dispc_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
 641 {
 642         BUG_ON(plane == OMAP_DSS_GFX);
 643
 644         dispc_write_reg(DISPC_VID_FIR_COEF_HV(plane-1, reg), value);
 645 }
 646
 647 static void _dispc_write_firv_reg(enum omap_plane plane, int reg, u32 value)
 648 {
 649         BUG_ON(plane == OMAP_DSS_GFX);
 650
 651         dispc_write_reg(DISPC_VID_FIR_COEF_V(plane-1, reg), value);
 652 }
 653
 654 static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup,
 655                 int vscaleup, int five_taps)
 656 {
 657         /* Coefficients for horizontal up-sampling */
 658         static const struct dispc_h_coef coef_hup[8] = {
 659                 {  0,   0, 128,   0,  0 },
 660                 { -1,  13, 124,  -8,  0 },
 661                 { -2,  30, 112, -11, -1 },
 662                 { -5,  51,  95, -11, -2 },
 663                 {  0,  -9,  73,  73, -9 },
 664                 { -2, -11,  95,  51, -5 },
 665                 { -1, -11, 112,  30, -2 },
 666                 {  0,  -8, 124,  13, -1 },
 667         };
 668
 669         /* Coefficients for vertical up-sampling */
 670         static const struct dispc_v_coef coef_vup_3tap[8] = {
 671                 { 0,  0, 128,  0, 0 },
 672                 { 0,  3, 123,  2, 0 },
 673                 { 0, 12, 111,  5, 0 },
 674                 { 0, 32,  89,  7, 0 },
 675                 { 0,  0,  64, 64, 0 },
 676                 { 0,  7,  89, 32, 0 },
 677                 { 0,  5, 111, 12, 0 },
 678                 { 0,  2, 123,  3, 0 },
 679         };
 680
 681         static const struct dispc_v_coef coef_vup_5tap[8] = {
 682                 {  0,   0, 128,   0,  0 },
 683                 { -1,  13, 124,  -8,  0 },
 684                 { -2,  30, 112, -11, -1 },
 685                 { -5,  51,  95, -11, -2 },
 686                 {  0,  -9,  73,  73, -9 },
 687                 { -2, -11,  95,  51, -5 },
 688                 { -1, -11, 112,  30, -2 },
 689                 {  0,  -8, 124,  13, -1 },
 690         };
 691
 692         /* Coefficients for horizontal down-sampling */
 693         static const struct dispc_h_coef coef_hdown[8] = {
 694                 {   0, 36, 56, 36,  0 },
 695                 {   4, 40, 55, 31, -2 },
 696                 {   8, 44, 54, 27, -5 },
 697                 {  12, 48, 53, 22, -7 },
 698                 {  -9, 17, 52, 51, 17 },
 699                 {  -7, 22, 53, 48, 12 },
 700                 {  -5, 27, 54, 44,  8 },
 701                 {  -2, 31, 55, 40,  4 },
 702         };
 703
 704         /* Coefficients for vertical down-sampling */
 705         static const struct dispc_v_coef coef_vdown_3tap[8] = {
 706                 { 0, 36, 56, 36, 0 },
 707                 { 0, 40, 57, 31, 0 },
 708                 { 0, 45, 56, 27, 0 },
 709                 { 0, 50, 55, 23, 0 },
 710                 { 0, 18, 55, 55, 0 },
 711                 { 0, 23, 55, 50, 0 },
 712                 { 0, 27, 56, 45, 0 },
 713                 { 0, 31, 57, 40, 0 },
 714         };
 715
 716         static const struct dispc_v_coef coef_vdown_5tap[8] = {
 717                 {   0, 36, 56, 36,  0 },
 718                 {   4, 40, 55, 31, -2 },
 719                 {   8, 44, 54, 27, -5 },
 720                 {  12, 48, 53, 22, -7 },
 721                 {  -9, 17, 52, 51, 17 },
 722                 {  -7, 22, 53, 48, 12 },
 723                 {  -5, 27, 54, 44,  8 },
 724                 {  -2, 31, 55, 40,  4 },
 725         };
 726
 727         const struct dispc_h_coef *h_coef;
 728         const struct dispc_v_coef *v_coef;
 729         int i;
 730
 731         if (hscaleup)
 732                 h_coef = coef_hup;
 733         else
 734                 h_coef = coef_hdown;
 735
 736         if (vscaleup)
 737                 v_coef = five_taps ? coef_vup_5tap : coef_vup_3tap;
 738         else
 739                 v_coef = five_taps ? coef_vdown_5tap : coef_vdown_3tap;
 740
 741         for (i = 0; i < 8; i++) {
 742                 u32 h, hv;
 743
 744                 h = FLD_VAL(h_coef[i].hc0, 7, 0)
 745                         | FLD_VAL(h_coef[i].hc1, 15, 8)
 746                         | FLD_VAL(h_coef[i].hc2, 23, 16)
 747                         | FLD_VAL(h_coef[i].hc3, 31, 24);
 748                 hv = FLD_VAL(h_coef[i].hc4, 7, 0)
 749                         | FLD_VAL(v_coef[i].vc0, 15, 8)
 750                         | FLD_VAL(v_coef[i].vc1, 23, 16)
 751                         | FLD_VAL(v_coef[i].vc2, 31, 24);
 752
 753                 _dispc_write_firh_reg(plane, i, h);
 754                 _dispc_write_firhv_reg(plane, i, hv);
 755         }
 756
 757         if (five_taps) {
 758                 for (i = 0; i < 8; i++) {
 759                         u32 v;
 760                         v = FLD_VAL(v_coef[i].vc00, 7, 0)
 761                                 | FLD_VAL(v_coef[i].vc22, 15, 8);
 762                         _dispc_write_firv_reg(plane, i, v);
 763                 }
 764         }
 765 }
 766
 767 static void _dispc_setup_color_conv_coef(void)
 768 {
 769         const struct color_conv_coef {
 770                 int  ry,  rcr,  rcb,   gy,  gcr,  gcb,   by,  bcr,  bcb;
 771                 int  full_range;
 772         }  ctbl_bt601_5 = {
 773                 298,  409,    0,  298, -208, -100,  298,    0,  517, 0,
 774         };
 775
 776         const struct color_conv_coef *ct;
 777
 778 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
 779
 780         ct = &ctbl_bt601_5;
 781
 782         dispc_write_reg(DISPC_VID_CONV_COEF(0, 0), CVAL(ct->rcr, ct->ry));
 783         dispc_write_reg(DISPC_VID_CONV_COEF(0, 1), CVAL(ct->gy,  ct->rcb));
 784         dispc_write_reg(DISPC_VID_CONV_COEF(0, 2), CVAL(ct->gcb, ct->gcr));
 785         dispc_write_reg(DISPC_VID_CONV_COEF(0, 3), CVAL(ct->bcr, ct->by));
 786         dispc_write_reg(DISPC_VID_CONV_COEF(0, 4), CVAL(0,       ct->bcb));
 787
 788         dispc_write_reg(DISPC_VID_CONV_COEF(1, 0), CVAL(ct->rcr, ct->ry));
 789         dispc_write_reg(DISPC_VID_CONV_COEF(1, 1), CVAL(ct->gy,  ct->rcb));
 790         dispc_write_reg(DISPC_VID_CONV_COEF(1, 2), CVAL(ct->gcb, ct->gcr));
 791         dispc_write_reg(DISPC_VID_CONV_COEF(1, 3), CVAL(ct->bcr, ct->by));
 792         dispc_write_reg(DISPC_VID_CONV_COEF(1, 4), CVAL(0,       ct->bcb));
 793
 794 #undef CVAL
 795
 796         REG_FLD_MOD(DISPC_VID_ATTRIBUTES(0), ct->full_range, 11, 11);
 797         REG_FLD_MOD(DISPC_VID_ATTRIBUTES(1), ct->full_range, 11, 11);
 798 }
 799
 800
 801 static void _dispc_set_plane_ba0(enum omap_plane plane, u32 paddr)
 802 {
 803         const struct dispc_reg ba0_reg[] = { DISPC_GFX_BA0,
 804                 DISPC_VID_BA0(0),
 805                 DISPC_VID_BA0(1) };
 806
 807         dispc_write_reg(ba0_reg[plane], paddr);
 808 }
 809
 810 static void _dispc_set_plane_ba1(enum omap_plane plane, u32 paddr)
 811 {
 812         const struct dispc_reg ba1_reg[] = { DISPC_GFX_BA1,
 813                                       DISPC_VID_BA1(0),
 814                                       DISPC_VID_BA1(1) };
 815
 816         dispc_write_reg(ba1_reg[plane], paddr);
 817 }
 818
 819 static void _dispc_set_plane_pos(enum omap_plane plane, int x, int y)
 820 {
 821         const struct dispc_reg pos_reg[] = { DISPC_GFX_POSITION,
 822                                       DISPC_VID_POSITION(0),
 823                                       DISPC_VID_POSITION(1) };
 824
 825         u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
 826         dispc_write_reg(pos_reg[plane], val);
 827 }
 828
 829 static void _dispc_set_pic_size(enum omap_plane plane, int width, int height)
 830 {
 831         const struct dispc_reg siz_reg[] = { DISPC_GFX_SIZE,
 832                                       DISPC_VID_PICTURE_SIZE(0),
 833                                       DISPC_VID_PICTURE_SIZE(1) };
 834         u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 835         dispc_write_reg(siz_reg[plane], val);
 836 }
 837
 838 static void _dispc_set_vid_size(enum omap_plane plane, int width, int height)
 839 {
 840         u32 val;
 841         const struct dispc_reg vsi_reg[] = { DISPC_VID_SIZE(0),
 842                                       DISPC_VID_SIZE(1) };
 843
 844         BUG_ON(plane == OMAP_DSS_GFX);
 845
 846         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 847         dispc_write_reg(vsi_reg[plane-1], val);
 848 }
 849
 850 static void _dispc_set_pre_mult_alpha(enum omap_plane plane, bool enable)
 851 {
 852         if (!dss_has_feature(FEAT_PRE_MULT_ALPHA))
 853                 return;
 854
 855         if (!dss_has_feature(FEAT_GLOBAL_ALPHA_VID1) &&
 856                 plane == OMAP_DSS_VIDEO1)
 857                 return;
 858
 859         REG_FLD_MOD(dispc_reg_att[plane], enable ? 1 : 0, 28, 28);
 860 }
 861
 862 static void _dispc_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
 863 {
 864         if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
 865                 return;
 866
 867         if (!dss_has_feature(FEAT_GLOBAL_ALPHA_VID1) &&
 868                 plane == OMAP_DSS_VIDEO1)
 869                 return;
 870
 871         if (plane == OMAP_DSS_GFX)
 872                 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 7, 0);
 873         else if (plane == OMAP_DSS_VIDEO2)
 874                 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 23, 16);
 875 }
 876
 877 static void _dispc_set_pix_inc(enum omap_plane plane, s32 inc)
 878 {
 879         const struct dispc_reg ri_reg[] = { DISPC_GFX_PIXEL_INC,
 880                                      DISPC_VID_PIXEL_INC(0),
 881                                      DISPC_VID_PIXEL_INC(1) };
 882
 883         dispc_write_reg(ri_reg[plane], inc);
 884 }
 885
 886 static void _dispc_set_row_inc(enum omap_plane plane, s32 inc)
 887 {
 888         const struct dispc_reg ri_reg[] = { DISPC_GFX_ROW_INC,
 889                                      DISPC_VID_ROW_INC(0),
 890                                      DISPC_VID_ROW_INC(1) };
 891
 892         dispc_write_reg(ri_reg[plane], inc);
 893 }
 894
 895 static void _dispc_set_color_mode(enum omap_plane plane,
 896                 enum omap_color_mode color_mode)
 897 {
 898         u32 m = 0;
 899
 900         switch (color_mode) {
 901         case OMAP_DSS_COLOR_CLUT1:
 902                 m = 0x0; break;
 903         case OMAP_DSS_COLOR_CLUT2:
 904                 m = 0x1; break;
 905         case OMAP_DSS_COLOR_CLUT4:
 906                 m = 0x2; break;
 907         case OMAP_DSS_COLOR_CLUT8:
 908                 m = 0x3; break;
 909         case OMAP_DSS_COLOR_RGB12U:
 910                 m = 0x4; break;
 911         case OMAP_DSS_COLOR_ARGB16:
 912                 m = 0x5; break;
 913         case OMAP_DSS_COLOR_RGB16:
 914                 m = 0x6; break;
 915         case OMAP_DSS_COLOR_RGB24U:
 916                 m = 0x8; break;
 917         case OMAP_DSS_COLOR_RGB24P:
 918                 m = 0x9; break;
 919         case OMAP_DSS_COLOR_YUV2:
 920                 m = 0xa; break;
 921         case OMAP_DSS_COLOR_UYVY:
 922                 m = 0xb; break;
 923         case OMAP_DSS_COLOR_ARGB32:
 924                 m = 0xc; break;
 925         case OMAP_DSS_COLOR_RGBA32:
 926                 m = 0xd; break;
 927         case OMAP_DSS_COLOR_RGBX32:
 928                 m = 0xe; break;
 929         default:
 930                 BUG(); break;
 931         }
 932
 933         REG_FLD_MOD(dispc_reg_att[plane], m, 4, 1);
 934 }
 935
 936 static void _dispc_set_channel_out(enum omap_plane plane,
 937                 enum omap_channel channel)
 938 {
 939         int shift;
 940         u32 val;
 941         int chan = 0, chan2 = 0;
 942
 943         switch (plane) {
 944         case OMAP_DSS_GFX:
 945                 shift = 8;
 946                 break;
 947         case OMAP_DSS_VIDEO1:
 948         case OMAP_DSS_VIDEO2:
 949                 shift = 16;
 950                 break;
 951         default:
 952                 BUG();
 953                 return;
 954         }
 955
 956         val = dispc_read_reg(dispc_reg_att[plane]);
 957         if (dss_has_feature(FEAT_MGR_LCD2)) {
 958                 switch (channel) {
 959                 case OMAP_DSS_CHANNEL_LCD:
 960                         chan = 0;
 961                         chan2 = 0;
 962                         break;
 963                 case OMAP_DSS_CHANNEL_DIGIT:
 964                         chan = 1;
 965                         chan2 = 0;
 966                         break;
 967                 case OMAP_DSS_CHANNEL_LCD2:
 968                         chan = 0;
 969                         chan2 = 1;
 970                         break;
 971                 default:
 972                         BUG();
 973                 }
 974
 975                 val = FLD_MOD(val, chan, shift, shift);
 976                 val = FLD_MOD(val, chan2, 31, 30);
 977         } else {
 978                 val = FLD_MOD(val, channel, shift, shift);
 979         }
 980         dispc_write_reg(dispc_reg_att[plane], val);
 981 }
 982
 983 void dispc_set_burst_size(enum omap_plane plane,
 984                 enum omap_burst_size burst_size)
 985 {
 986         int shift;
 987         u32 val;
 988
 989         enable_clocks(1);
 990
 991         switch (plane) {
 992         case OMAP_DSS_GFX:
 993                 shift = 6;
 994                 break;
 995         case OMAP_DSS_VIDEO1:
 996         case OMAP_DSS_VIDEO2:
 997                 shift = 14;
 998                 break;
 999         default:
1000                 BUG();
1001                 return;
1002         }
1003
1004         val = dispc_read_reg(dispc_reg_att[plane]);
1005         val = FLD_MOD(val, burst_size, shift+1, shift);
1006         dispc_write_reg(dispc_reg_att[plane], val);
1007
1008         enable_clocks(0);
1009 }
1010
1011 static void _dispc_set_vid_color_conv(enum omap_plane plane, bool enable)
1012 {
1013         u32 val;
1014
1015         BUG_ON(plane == OMAP_DSS_GFX);
1016
1017         val = dispc_read_reg(dispc_reg_att[plane]);
1018         val = FLD_MOD(val, enable, 9, 9);
1019         dispc_write_reg(dispc_reg_att[plane], val);
1020 }
1021
1022 void dispc_enable_replication(enum omap_plane plane, bool enable)
1023 {
1024         int bit;
1025
1026         if (plane == OMAP_DSS_GFX)
1027                 bit = 5;
1028         else
1029                 bit = 10;
1030
1031         enable_clocks(1);
1032         REG_FLD_MOD(dispc_reg_att[plane], enable, bit, bit);
1033         enable_clocks(0);
1034 }
1035
1036 void dispc_set_lcd_size(enum omap_channel channel, u16 width, u16 height)
1037 {
1038         u32 val;
1039         BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1040         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
1041         enable_clocks(1);
1042         dispc_write_reg(DISPC_SIZE_LCD(channel), val);
1043         enable_clocks(0);
1044 }
1045
1046 void dispc_set_digit_size(u16 width, u16 height)
1047 {
1048         u32 val;
1049         BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1050         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
1051         enable_clocks(1);
1052         dispc_write_reg(DISPC_SIZE_DIG, val);
1053         enable_clocks(0);
1054 }
1055
1056 static void dispc_read_plane_fifo_sizes(void)
1057 {
1058         const struct dispc_reg fsz_reg[] = { DISPC_GFX_FIFO_SIZE_STATUS,
1059                                       DISPC_VID_FIFO_SIZE_STATUS(0),
1060                                       DISPC_VID_FIFO_SIZE_STATUS(1) };
1061         u32 size;
1062         int plane;
1063         u8 start, end;
1064
1065         enable_clocks(1);
1066
1067         dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
1068
1069         for (plane = 0; plane < ARRAY_SIZE(dispc.fifo_size); ++plane) {
1070                 size = FLD_GET(dispc_read_reg(fsz_reg[plane]), start, end);
1071                 dispc.fifo_size[plane] = size;
1072         }
1073
1074         enable_clocks(0);
1075 }
1076
1077 u32 dispc_get_plane_fifo_size(enum omap_plane plane)
1078 {
1079         return dispc.fifo_size[plane];
1080 }
1081
1082 void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high)
1083 {
1084         const struct dispc_reg ftrs_reg[] = { DISPC_GFX_FIFO_THRESHOLD,
1085                                        DISPC_VID_FIFO_THRESHOLD(0),
1086                                        DISPC_VID_FIFO_THRESHOLD(1) };
1087         u8 hi_start, hi_end, lo_start, lo_end;
1088
1089         enable_clocks(1);
1090
1091         DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n",
1092                         plane,
1093                         REG_GET(ftrs_reg[plane], 11, 0),
1094                         REG_GET(ftrs_reg[plane], 27, 16),
1095                         low, high);
1096
1097         dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1098         dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1099
1100         dispc_write_reg(ftrs_reg[plane],
1101                         FLD_VAL(high, hi_start, hi_end) |
1102                         FLD_VAL(low, lo_start, lo_end));
1103
1104         enable_clocks(0);
1105 }
1106
1107 void dispc_enable_fifomerge(bool enable)
1108 {
1109         enable_clocks(1);
1110
1111         DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1112         REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1113
1114         enable_clocks(0);
1115 }
1116
1117 static void _dispc_set_fir(enum omap_plane plane, int hinc, int vinc)
1118 {
1119         u32 val;
1120         const struct dispc_reg fir_reg[] = { DISPC_VID_FIR(0),
1121                                       DISPC_VID_FIR(1) };
1122         u8 hinc_start, hinc_end, vinc_start, vinc_end;
1123
1124         BUG_ON(plane == OMAP_DSS_GFX);
1125
1126         dss_feat_get_reg_field(FEAT_REG_FIRHINC, &hinc_start, &hinc_end);
1127         dss_feat_get_reg_field(FEAT_REG_FIRVINC, &vinc_start, &vinc_end);
1128
1129         val = FLD_VAL(vinc, vinc_start, vinc_end) |
1130                         FLD_VAL(hinc, hinc_start, hinc_end);
1131
1132         dispc_write_reg(fir_reg[plane-1], val);
1133 }
1134
1135 static void _dispc_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1136 {
1137         u32 val;
1138         const struct dispc_reg ac0_reg[] = { DISPC_VID_ACCU0(0),
1139                                       DISPC_VID_ACCU0(1) };
1140         u8 hor_start, hor_end, vert_start, vert_end;
1141
1142         BUG_ON(plane == OMAP_DSS_GFX);
1143
1144         dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1145         dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1146
1147         val = FLD_VAL(vaccu, vert_start, vert_end) |
1148                         FLD_VAL(haccu, hor_start, hor_end);
1149
1150         dispc_write_reg(ac0_reg[plane-1], val);
1151 }
1152
1153 static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1154 {
1155         u32 val;
1156         const struct dispc_reg ac1_reg[] = { DISPC_VID_ACCU1(0),
1157                                       DISPC_VID_ACCU1(1) };
1158         u8 hor_start, hor_end, vert_start, vert_end;
1159
1160         BUG_ON(plane == OMAP_DSS_GFX);
1161
1162         dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1163         dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1164
1165         val = FLD_VAL(vaccu, vert_start, vert_end) |
1166                         FLD_VAL(haccu, hor_start, hor_end);
1167
1168         dispc_write_reg(ac1_reg[plane-1], val);
1169 }
1170
1171
1172 static void _dispc_set_scaling(enum omap_plane plane,
1173                 u16 orig_width, u16 orig_height,
1174                 u16 out_width, u16 out_height,
1175                 bool ilace, bool five_taps,
1176                 bool fieldmode)
1177 {
1178         int fir_hinc;
1179         int fir_vinc;
1180         int hscaleup, vscaleup;
1181         int accu0 = 0;
1182         int accu1 = 0;
1183         u32 l;
1184
1185         BUG_ON(plane == OMAP_DSS_GFX);
1186
1187         hscaleup = orig_width <= out_width;
1188         vscaleup = orig_height <= out_height;
1189
1190         _dispc_set_scale_coef(plane, hscaleup, vscaleup, five_taps);
1191
1192         if (!orig_width || orig_width == out_width)
1193                 fir_hinc = 0;
1194         else
1195                 fir_hinc = 1024 * orig_width / out_width;
1196
1197         if (!orig_height || orig_height == out_height)
1198                 fir_vinc = 0;
1199         else
1200                 fir_vinc = 1024 * orig_height / out_height;
1201
1202         _dispc_set_fir(plane, fir_hinc, fir_vinc);
1203
1204         l = dispc_read_reg(dispc_reg_att[plane]);
1205
1206         /* RESIZEENABLE and VERTICALTAPS */
1207         l &= ~((0x3 << 5) | (0x1 << 21));
1208         l |= fir_hinc ? (1 << 5) : 0;
1209         l |= fir_vinc ? (1 << 6) : 0;
1210         l |= five_taps ? (1 << 21) : 0;
1211
1212         /* VRESIZECONF and HRESIZECONF */
1213         if (dss_has_feature(FEAT_RESIZECONF)) {
1214                 l &= ~(0x3 << 7);
1215                 l |= hscaleup ? 0 : (1 << 7);
1216                 l |= vscaleup ? 0 : (1 << 8);
1217         }
1218
1219         /* LINEBUFFERSPLIT */
1220         if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1221                 l &= ~(0x1 << 22);
1222                 l |= five_taps ? (1 << 22) : 0;
1223         }
1224
1225         dispc_write_reg(dispc_reg_att[plane], l);
1226
1227         /*
1228          * field 0 = even field = bottom field
1229          * field 1 = odd field = top field
1230          */
1231         if (ilace && !fieldmode) {
1232                 accu1 = 0;
1233                 accu0 = (fir_vinc / 2) & 0x3ff;
1234                 if (accu0 >= 1024/2) {
1235                         accu1 = 1024/2;
1236                         accu0 -= accu1;
1237                 }
1238         }
1239
1240         _dispc_set_vid_accu0(plane, 0, accu0);
1241         _dispc_set_vid_accu1(plane, 0, accu1);
1242 }
1243
1244 static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1245                 bool mirroring, enum omap_color_mode color_mode)
1246 {
1247         bool row_repeat = false;
1248         int vidrot = 0;
1249
1250         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1251                         color_mode == OMAP_DSS_COLOR_UYVY) {
1252
1253                 if (mirroring) {
1254                         switch (rotation) {
1255                         case OMAP_DSS_ROT_0:
1256                                 vidrot = 2;
1257                                 break;
1258                         case OMAP_DSS_ROT_90:
1259                                 vidrot = 1;
1260                                 break;
1261                         case OMAP_DSS_ROT_180:
1262                                 vidrot = 0;
1263                                 break;
1264                         case OMAP_DSS_ROT_270:
1265                                 vidrot = 3;
1266                                 break;
1267                         }
1268                 } else {
1269                         switch (rotation) {
1270                         case OMAP_DSS_ROT_0:
1271                                 vidrot = 0;
1272                                 break;
1273                         case OMAP_DSS_ROT_90:
1274                                 vidrot = 1;
1275                                 break;
1276                         case OMAP_DSS_ROT_180:
1277                                 vidrot = 2;
1278                                 break;
1279                         case OMAP_DSS_ROT_270:
1280                                 vidrot = 3;
1281                                 break;
1282                         }
1283                 }
1284
1285                 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1286                         row_repeat = true;
1287                 else
1288                         row_repeat = false;
1289         }
1290
1291         REG_FLD_MOD(dispc_reg_att[plane], vidrot, 13, 12);
1292         if (dss_has_feature(FEAT_ROWREPEATENABLE))
1293                 REG_FLD_MOD(dispc_reg_att[plane], row_repeat ? 1 : 0, 18, 18);
1294 }
1295
1296 static int color_mode_to_bpp(enum omap_color_mode color_mode)
1297 {
1298         switch (color_mode) {
1299         case OMAP_DSS_COLOR_CLUT1:
1300                 return 1;
1301         case OMAP_DSS_COLOR_CLUT2:
1302                 return 2;
1303         case OMAP_DSS_COLOR_CLUT4:
1304                 return 4;
1305         case OMAP_DSS_COLOR_CLUT8:
1306                 return 8;
1307         case OMAP_DSS_COLOR_RGB12U:
1308         case OMAP_DSS_COLOR_RGB16:
1309         case OMAP_DSS_COLOR_ARGB16:
1310         case OMAP_DSS_COLOR_YUV2:
1311         case OMAP_DSS_COLOR_UYVY:
1312                 return 16;
1313         case OMAP_DSS_COLOR_RGB24P:
1314                 return 24;
1315         case OMAP_DSS_COLOR_RGB24U:
1316         case OMAP_DSS_COLOR_ARGB32:
1317         case OMAP_DSS_COLOR_RGBA32:
1318         case OMAP_DSS_COLOR_RGBX32:
1319                 return 32;
1320         default:
1321                 BUG();
1322         }
1323 }
1324
1325 static s32 pixinc(int pixels, u8 ps)
1326 {
1327         if (pixels == 1)
1328                 return 1;
1329         else if (pixels > 1)
1330                 return 1 + (pixels - 1) * ps;
1331         else if (pixels < 0)
1332                 return 1 - (-pixels + 1) * ps;
1333         else
1334                 BUG();
1335 }
1336
1337 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1338                 u16 screen_width,
1339                 u16 width, u16 height,
1340                 enum omap_color_mode color_mode, bool fieldmode,
1341                 unsigned int field_offset,
1342                 unsigned *offset0, unsigned *offset1,
1343                 s32 *row_inc, s32 *pix_inc)
1344 {
1345         u8 ps;
1346
1347         /* FIXME CLUT formats */
1348         switch (color_mode) {
1349         case OMAP_DSS_COLOR_CLUT1:
1350         case OMAP_DSS_COLOR_CLUT2:
1351         case OMAP_DSS_COLOR_CLUT4:
1352         case OMAP_DSS_COLOR_CLUT8:
1353                 BUG();
1354                 return;
1355         case OMAP_DSS_COLOR_YUV2:
1356         case OMAP_DSS_COLOR_UYVY:
1357                 ps = 4;
1358                 break;
1359         default:
1360                 ps = color_mode_to_bpp(color_mode) / 8;
1361                 break;
1362         }
1363
1364         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1365                         width, height);
1366
1367         /*
1368          * field 0 = even field = bottom field
1369          * field 1 = odd field = top field
1370          */
1371         switch (rotation + mirror * 4) {
1372         case OMAP_DSS_ROT_0:
1373         case OMAP_DSS_ROT_180:
1374                 /*
1375                  * If the pixel format is YUV or UYVY divide the width
1376                  * of the image by 2 for 0 and 180 degree rotation.
1377                  */
1378                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1379                         color_mode == OMAP_DSS_COLOR_UYVY)
1380                         width = width >> 1;
1381         case OMAP_DSS_ROT_90:
1382         case OMAP_DSS_ROT_270:
1383                 *offset1 = 0;
1384                 if (field_offset)
1385                         *offset0 = field_offset * screen_width * ps;
1386                 else
1387                         *offset0 = 0;
1388
1389                 *row_inc = pixinc(1 + (screen_width - width) +
1390                                 (fieldmode ? screen_width : 0),
1391                                 ps);
1392                 *pix_inc = pixinc(1, ps);
1393                 break;
1394
1395         case OMAP_DSS_ROT_0 + 4:
1396         case OMAP_DSS_ROT_180 + 4:
1397                 /* If the pixel format is YUV or UYVY divide the width
1398                  * of the image by 2  for 0 degree and 180 degree
1399                  */
1400                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1401                         color_mode == OMAP_DSS_COLOR_UYVY)
1402                         width = width >> 1;
1403         case OMAP_DSS_ROT_90 + 4:
1404         case OMAP_DSS_ROT_270 + 4:
1405                 *offset1 = 0;
1406                 if (field_offset)
1407                         *offset0 = field_offset * screen_width * ps;
1408                 else
1409                         *offset0 = 0;
1410                 *row_inc = pixinc(1 - (screen_width + width) -
1411                                 (fieldmode ? screen_width : 0),
1412                                 ps);
1413                 *pix_inc = pixinc(1, ps);
1414                 break;
1415
1416         default:
1417                 BUG();
1418         }
1419 }
1420
1421 static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1422                 u16 screen_width,
1423                 u16 width, u16 height,
1424                 enum omap_color_mode color_mode, bool fieldmode,
1425                 unsigned int field_offset,
1426                 unsigned *offset0, unsigned *offset1,
1427                 s32 *row_inc, s32 *pix_inc)
1428 {
1429         u8 ps;
1430         u16 fbw, fbh;
1431
1432         /* FIXME CLUT formats */
1433         switch (color_mode) {
1434         case OMAP_DSS_COLOR_CLUT1:
1435         case OMAP_DSS_COLOR_CLUT2:
1436         case OMAP_DSS_COLOR_CLUT4:
1437         case OMAP_DSS_COLOR_CLUT8:
1438                 BUG();
1439                 return;
1440         default:
1441                 ps = color_mode_to_bpp(color_mode) / 8;
1442                 break;
1443         }
1444
1445         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1446                         width, height);
1447
1448         /* width & height are overlay sizes, convert to fb sizes */
1449
1450         if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1451                 fbw = width;
1452                 fbh = height;
1453         } else {
1454                 fbw = height;
1455                 fbh = width;
1456         }
1457
1458         /*
1459          * field 0 = even field = bottom field
1460          * field 1 = odd field = top field
1461          */
1462         switch (rotation + mirror * 4) {
1463         case OMAP_DSS_ROT_0:
1464                 *offset1 = 0;
1465                 if (field_offset)
1466                         *offset0 = *offset1 + field_offset * screen_width * ps;
1467                 else
1468                         *offset0 = *offset1;
1469                 *row_inc = pixinc(1 + (screen_width - fbw) +
1470                                 (fieldmode ? screen_width : 0),
1471                                 ps);
1472                 *pix_inc = pixinc(1, ps);
1473                 break;
1474         case OMAP_DSS_ROT_90:
1475                 *offset1 = screen_width * (fbh - 1) * ps;
1476                 if (field_offset)
1477                         *offset0 = *offset1 + field_offset * ps;
1478                 else
1479                         *offset0 = *offset1;
1480                 *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
1481                                 (fieldmode ? 1 : 0), ps);
1482                 *pix_inc = pixinc(-screen_width, ps);
1483                 break;
1484         case OMAP_DSS_ROT_180:
1485                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1486                 if (field_offset)
1487                         *offset0 = *offset1 - field_offset * screen_width * ps;
1488                 else
1489                         *offset0 = *offset1;
1490                 *row_inc = pixinc(-1 -
1491                                 (screen_width - fbw) -
1492                                 (fieldmode ? screen_width : 0),
1493                                 ps);
1494                 *pix_inc = pixinc(-1, ps);
1495                 break;
1496         case OMAP_DSS_ROT_270:
1497                 *offset1 = (fbw - 1) * ps;
1498                 if (field_offset)
1499                         *offset0 = *offset1 - field_offset * ps;
1500                 else
1501                         *offset0 = *offset1;
1502                 *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
1503                                 (fieldmode ? 1 : 0), ps);
1504                 *pix_inc = pixinc(screen_width, ps);
1505                 break;
1506
1507         /* mirroring */
1508         case OMAP_DSS_ROT_0 + 4:
1509                 *offset1 = (fbw - 1) * ps;
1510                 if (field_offset)
1511                         *offset0 = *offset1 + field_offset * screen_width * ps;
1512                 else
1513                         *offset0 = *offset1;
1514                 *row_inc = pixinc(screen_width * 2 - 1 +
1515                                 (fieldmode ? screen_width : 0),
1516                                 ps);
1517                 *pix_inc = pixinc(-1, ps);
1518                 break;
1519
1520         case OMAP_DSS_ROT_90 + 4:
1521                 *offset1 = 0;
1522                 if (field_offset)
1523                         *offset0 = *offset1 + field_offset * ps;
1524                 else
1525                         *offset0 = *offset1;
1526                 *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
1527                                 (fieldmode ? 1 : 0),
1528                                 ps);
1529                 *pix_inc = pixinc(screen_width, ps);
1530                 break;
1531
1532         case OMAP_DSS_ROT_180 + 4:
1533                 *offset1 = screen_width * (fbh - 1) * ps;
1534                 if (field_offset)
1535                         *offset0 = *offset1 - field_offset * screen_width * ps;
1536                 else
1537                         *offset0 = *offset1;
1538                 *row_inc = pixinc(1 - screen_width * 2 -
1539                                 (fieldmode ? screen_width : 0),
1540                                 ps);
1541                 *pix_inc = pixinc(1, ps);
1542                 break;
1543
1544         case OMAP_DSS_ROT_270 + 4:
1545                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1546                 if (field_offset)
1547                         *offset0 = *offset1 - field_offset * ps;
1548                 else
1549                         *offset0 = *offset1;
1550                 *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
1551                                 (fieldmode ? 1 : 0),
1552                                 ps);
1553                 *pix_inc = pixinc(-screen_width, ps);
1554                 break;
1555
1556         default:
1557                 BUG();
1558         }
1559 }
1560
1561 static unsigned long calc_fclk_five_taps(enum omap_channel channel, u16 width,
1562                 u16 height, u16 out_width, u16 out_height,
1563                 enum omap_color_mode color_mode)
1564 {
1565         u32 fclk = 0;
1566         /* FIXME venc pclk? */
1567         u64 tmp, pclk = dispc_pclk_rate(channel);
1568
1569         if (height > out_height) {
1570                 /* FIXME get real display PPL */
1571                 unsigned int ppl = 800;
1572
1573                 tmp = pclk * height * out_width;
1574                 do_div(tmp, 2 * out_height * ppl);
1575                 fclk = tmp;
1576
1577                 if (height > 2 * out_height) {
1578                         if (ppl == out_width)
1579                                 return 0;
1580
1581                         tmp = pclk * (height - 2 * out_height) * out_width;
1582                         do_div(tmp, 2 * out_height * (ppl - out_width));
1583                         fclk = max(fclk, (u32) tmp);
1584                 }
1585         }
1586
1587         if (width > out_width) {
1588                 tmp = pclk * width;
1589                 do_div(tmp, out_width);
1590                 fclk = max(fclk, (u32) tmp);
1591
1592                 if (color_mode == OMAP_DSS_COLOR_RGB24U)
1593                         fclk <<= 1;
1594         }
1595
1596         return fclk;
1597 }
1598
1599 static unsigned long calc_fclk(enum omap_channel channel, u16 width,
1600                 u16 height, u16 out_width, u16 out_height)
1601 {
1602         unsigned int hf, vf;
1603
1604         /*
1605          * FIXME how to determine the 'A' factor
1606          * for the no downscaling case ?
1607          */
1608
1609         if (width > 3 * out_width)
1610                 hf = 4;
1611         else if (width > 2 * out_width)
1612                 hf = 3;
1613         else if (width > out_width)
1614                 hf = 2;
1615         else
1616                 hf = 1;
1617
1618         if (height > out_height)
1619                 vf = 2;
1620         else
1621                 vf = 1;
1622
1623         /* FIXME venc pclk? */
1624         return dispc_pclk_rate(channel) * vf * hf;
1625 }
1626
1627 void dispc_set_channel_out(enum omap_plane plane, enum omap_channel channel_out)
1628 {
1629         enable_clocks(1);
1630         _dispc_set_channel_out(plane, channel_out);
1631         enable_clocks(0);
1632 }
1633
1634 static int _dispc_setup_plane(enum omap_plane plane,
1635                 u32 paddr, u16 screen_width,
1636                 u16 pos_x, u16 pos_y,
1637                 u16 width, u16 height,
1638                 u16 out_width, u16 out_height,
1639                 enum omap_color_mode color_mode,
1640                 bool ilace,
1641                 enum omap_dss_rotation_type rotation_type,
1642                 u8 rotation, int mirror,
1643                 u8 global_alpha, u8 pre_mult_alpha,
1644                 enum omap_channel channel)
1645 {
1646         const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
1647         bool five_taps = 0;
1648         bool fieldmode = 0;
1649         int cconv = 0;
1650         unsigned offset0, offset1;
1651         s32 row_inc;
1652         s32 pix_inc;
1653         u16 frame_height = height;
1654         unsigned int field_offset = 0;
1655
1656         if (paddr == 0)
1657                 return -EINVAL;
1658
1659         if (ilace && height == out_height)
1660                 fieldmode = 1;
1661
1662         if (ilace) {
1663                 if (fieldmode)
1664                         height /= 2;
1665                 pos_y /= 2;
1666                 out_height /= 2;
1667
1668                 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
1669                                 "out_height %d\n",
1670                                 height, pos_y, out_height);
1671         }
1672
1673         if (!dss_feat_color_mode_supported(plane, color_mode))
1674                 return -EINVAL;
1675
1676         if (plane == OMAP_DSS_GFX) {
1677                 if (width != out_width || height != out_height)
1678                         return -EINVAL;
1679         } else {
1680                 /* video plane */
1681
1682                 unsigned long fclk = 0;
1683
1684                 if (out_width < width / maxdownscale ||
1685                    out_width > width * 8)
1686                         return -EINVAL;
1687
1688                 if (out_height < height / maxdownscale ||
1689                    out_height > height * 8)
1690                         return -EINVAL;
1691
1692                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1693                         color_mode == OMAP_DSS_COLOR_UYVY)
1694                         cconv = 1;
1695
1696                 /* Must use 5-tap filter? */
1697                 five_taps = height > out_height * 2;
1698
1699                 if (!five_taps) {
1700                         fclk = calc_fclk(channel, width, height, out_width,
1701                                         out_height);
1702
1703                         /* Try 5-tap filter if 3-tap fclk is too high */
1704                         if (cpu_is_omap34xx() && height > out_height &&
1705                                         fclk > dispc_fclk_rate())
1706                                 five_taps = true;
1707                 }
1708
1709                 if (width > (2048 >> five_taps)) {
1710                         DSSERR("failed to set up scaling, fclk too low\n");
1711                         return -EINVAL;
1712                 }
1713
1714                 if (five_taps)
1715                         fclk = calc_fclk_five_taps(channel, width, height,
1716                                         out_width, out_height, color_mode);
1717
1718                 DSSDBG("required fclk rate = %lu Hz\n", fclk);
1719                 DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
1720
1721                 if (!fclk || fclk > dispc_fclk_rate()) {
1722                         DSSERR("failed to set up scaling, "
1723                                         "required fclk rate = %lu Hz, "
1724                                         "current fclk rate = %lu Hz\n",
1725                                         fclk, dispc_fclk_rate());
1726                         return -EINVAL;
1727                 }
1728         }
1729
1730         if (ilace && !fieldmode) {
1731                 /*
1732                  * when downscaling the bottom field may have to start several
1733                  * source lines below the top field. Unfortunately ACCUI
1734                  * registers will only hold the fractional part of the offset
1735                  * so the integer part must be added to the base address of the
1736                  * bottom field.
1737                  */
1738                 if (!height || height == out_height)
1739                         field_offset = 0;
1740                 else
1741                         field_offset = height / out_height / 2;
1742         }
1743
1744         /* Fields are independent but interleaved in memory. */
1745         if (fieldmode)
1746                 field_offset = 1;
1747
1748         if (rotation_type == OMAP_DSS_ROT_DMA)
1749                 calc_dma_rotation_offset(rotation, mirror,
1750                                 screen_width, width, frame_height, color_mode,
1751                                 fieldmode, field_offset,
1752                                 &offset0, &offset1, &row_inc, &pix_inc);
1753         else
1754                 calc_vrfb_rotation_offset(rotation, mirror,
1755                                 screen_width, width, frame_height, color_mode,
1756                                 fieldmode, field_offset,
1757                                 &offset0, &offset1, &row_inc, &pix_inc);
1758
1759         DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
1760                         offset0, offset1, row_inc, pix_inc);
1761
1762         _dispc_set_color_mode(plane, color_mode);
1763
1764         _dispc_set_plane_ba0(plane, paddr + offset0);
1765         _dispc_set_plane_ba1(plane, paddr + offset1);
1766
1767         _dispc_set_row_inc(plane, row_inc);
1768         _dispc_set_pix_inc(plane, pix_inc);
1769
1770         DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, width, height,
1771                         out_width, out_height);
1772
1773         _dispc_set_plane_pos(plane, pos_x, pos_y);
1774
1775         _dispc_set_pic_size(plane, width, height);
1776
1777         if (plane != OMAP_DSS_GFX) {
1778                 _dispc_set_scaling(plane, width, height,
1779                                    out_width, out_height,
1780                                    ilace, five_taps, fieldmode);
1781                 _dispc_set_vid_size(plane, out_width, out_height);
1782                 _dispc_set_vid_color_conv(plane, cconv);
1783         }
1784
1785         _dispc_set_rotation_attrs(plane, rotation, mirror, color_mode);
1786
1787         _dispc_set_pre_mult_alpha(plane, pre_mult_alpha);
1788         _dispc_setup_global_alpha(plane, global_alpha);
1789
1790         return 0;
1791 }
1792
1793 static void _dispc_enable_plane(enum omap_plane plane, bool enable)
1794 {
1795         REG_FLD_MOD(dispc_reg_att[plane], enable ? 1 : 0, 0, 0);
1796 }
1797
1798 static void dispc_disable_isr(void *data, u32 mask)
1799 {
1800         struct completion *compl = data;
1801         complete(compl);
1802 }
1803
1804 static void _enable_lcd_out(enum omap_channel channel, bool enable)
1805 {
1806         if (channel == OMAP_DSS_CHANNEL_LCD2)
1807                 REG_FLD_MOD(DISPC_CONTROL2, enable ? 1 : 0, 0, 0);
1808         else
1809                 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
1810 }
1811
1812 static void dispc_enable_lcd_out(enum omap_channel channel, bool enable)
1813 {
1814         struct completion frame_done_completion;
1815         bool is_on;
1816         int r;
1817         u32 irq;
1818
1819         enable_clocks(1);
1820
1821         /* When we disable LCD output, we need to wait until frame is done.
1822          * Otherwise the DSS is still working, and turning off the clocks
1823          * prevents DSS from going to OFF mode */
1824         is_on = channel == OMAP_DSS_CHANNEL_LCD2 ?
1825                         REG_GET(DISPC_CONTROL2, 0, 0) :
1826                         REG_GET(DISPC_CONTROL, 0, 0);
1827
1828         irq = channel == OMAP_DSS_CHANNEL_LCD2 ? DISPC_IRQ_FRAMEDONE2 :
1829                         DISPC_IRQ_FRAMEDONE;
1830
1831         if (!enable && is_on) {
1832                 init_completion(&frame_done_completion);
1833
1834                 r = omap_dispc_register_isr(dispc_disable_isr,
1835                                 &frame_done_completion, irq);
1836
1837                 if (r)
1838                         DSSERR("failed to register FRAMEDONE isr\n");
1839         }
1840
1841         _enable_lcd_out(channel, enable);
1842
1843         if (!enable && is_on) {
1844                 if (!wait_for_completion_timeout(&frame_done_completion,
1845                                         msecs_to_jiffies(100)))
1846                         DSSERR("timeout waiting for FRAME DONE\n");
1847
1848                 r = omap_dispc_unregister_isr(dispc_disable_isr,
1849                                 &frame_done_completion, irq);
1850
1851                 if (r)
1852                         DSSERR("failed to unregister FRAMEDONE isr\n");
1853         }
1854
1855         enable_clocks(0);
1856 }
1857
1858 static void _enable_digit_out(bool enable)
1859 {
1860         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
1861 }
1862
1863 static void dispc_enable_digit_out(bool enable)
1864 {
1865         struct completion frame_done_completion;
1866         int r;
1867
1868         enable_clocks(1);
1869
1870         if (REG_GET(DISPC_CONTROL, 1, 1) == enable) {
1871                 enable_clocks(0);
1872                 return;
1873         }
1874
1875         if (enable) {
1876                 unsigned long flags;
1877                 /* When we enable digit output, we'll get an extra digit
1878                  * sync lost interrupt, that we need to ignore */
1879                 spin_lock_irqsave(&dispc.irq_lock, flags);
1880                 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
1881                 _omap_dispc_set_irqs();
1882                 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1883         }
1884
1885         /* When we disable digit output, we need to wait until fields are done.
1886          * Otherwise the DSS is still working, and turning off the clocks
1887          * prevents DSS from going to OFF mode. And when enabling, we need to
1888          * wait for the extra sync losts */
1889         init_completion(&frame_done_completion);
1890
1891         r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
1892                         DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1893         if (r)
1894                 DSSERR("failed to register EVSYNC isr\n");
1895
1896         _enable_digit_out(enable);
1897
1898         /* XXX I understand from TRM that we should only wait for the
1899          * current field to complete. But it seems we have to wait
1900          * for both fields */
1901         if (!wait_for_completion_timeout(&frame_done_completion,
1902                                 msecs_to_jiffies(100)))
1903                 DSSERR("timeout waiting for EVSYNC\n");
1904
1905         if (!wait_for_completion_timeout(&frame_done_completion,
1906                                 msecs_to_jiffies(100)))
1907                 DSSERR("timeout waiting for EVSYNC\n");
1908
1909         r = omap_dispc_unregister_isr(dispc_disable_isr,
1910                         &frame_done_completion,
1911                         DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1912         if (r)
1913                 DSSERR("failed to unregister EVSYNC isr\n");
1914
1915         if (enable) {
1916                 unsigned long flags;
1917                 spin_lock_irqsave(&dispc.irq_lock, flags);
1918                 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
1919                 if (dss_has_feature(FEAT_MGR_LCD2))
1920                         dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
1921                 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
1922                 _omap_dispc_set_irqs();
1923                 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1924         }
1925
1926         enable_clocks(0);
1927 }
1928
1929 bool dispc_is_channel_enabled(enum omap_channel channel)
1930 {
1931         if (channel == OMAP_DSS_CHANNEL_LCD)
1932                 return !!REG_GET(DISPC_CONTROL, 0, 0);
1933         else if (channel == OMAP_DSS_CHANNEL_DIGIT)
1934                 return !!REG_GET(DISPC_CONTROL, 1, 1);
1935         else if (channel == OMAP_DSS_CHANNEL_LCD2)
1936                 return !!REG_GET(DISPC_CONTROL2, 0, 0);
1937         else
1938                 BUG();
1939 }
1940
1941 void dispc_enable_channel(enum omap_channel channel, bool enable)
1942 {
1943         if (channel == OMAP_DSS_CHANNEL_LCD ||
1944                         channel == OMAP_DSS_CHANNEL_LCD2)
1945                 dispc_enable_lcd_out(channel, enable);
1946         else if (channel == OMAP_DSS_CHANNEL_DIGIT)
1947                 dispc_enable_digit_out(enable);
1948         else
1949                 BUG();
1950 }
1951
1952 void dispc_lcd_enable_signal_polarity(bool act_high)
1953 {
1954         if (!dss_has_feature(FEAT_LCDENABLEPOL))
1955                 return;
1956
1957         enable_clocks(1);
1958         REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
1959         enable_clocks(0);
1960 }
1961
1962 void dispc_lcd_enable_signal(bool enable)
1963 {
1964         if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
1965                 return;
1966
1967         enable_clocks(1);
1968         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
1969         enable_clocks(0);
1970 }
1971
1972 void dispc_pck_free_enable(bool enable)
1973 {
1974         if (!dss_has_feature(FEAT_PCKFREEENABLE))
1975                 return;
1976
1977         enable_clocks(1);
1978         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
1979         enable_clocks(0);
1980 }
1981
1982 void dispc_enable_fifohandcheck(enum omap_channel channel, bool enable)
1983 {
1984         enable_clocks(1);
1985         if (channel == OMAP_DSS_CHANNEL_LCD2)
1986                 REG_FLD_MOD(DISPC_CONFIG2, enable ? 1 : 0, 16, 16);
1987         else
1988                 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
1989         enable_clocks(0);
1990 }
1991
1992
1993 void dispc_set_lcd_display_type(enum omap_channel channel,
1994                 enum omap_lcd_display_type type)
1995 {
1996         int mode;
1997
1998         switch (type) {
1999         case OMAP_DSS_LCD_DISPLAY_STN:
2000                 mode = 0;
2001                 break;
2002
2003         case OMAP_DSS_LCD_DISPLAY_TFT:
2004                 mode = 1;
2005                 break;
2006
2007         default:
2008                 BUG();
2009                 return;
2010         }
2011
2012         enable_clocks(1);
2013         if (channel == OMAP_DSS_CHANNEL_LCD2)
2014                 REG_FLD_MOD(DISPC_CONTROL2, mode, 3, 3);
2015         else
2016                 REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
2017         enable_clocks(0);
2018 }
2019
2020 void dispc_set_loadmode(enum omap_dss_load_mode mode)
2021 {
2022         enable_clocks(1);
2023         REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
2024         enable_clocks(0);
2025 }
2026
2027
2028 void dispc_set_default_color(enum omap_channel channel, u32 color)
2029 {
2030         enable_clocks(1);
2031         dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
2032         enable_clocks(0);
2033 }
2034
2035 u32 dispc_get_default_color(enum omap_channel channel)
2036 {
2037         u32 l;
2038
2039         BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
2040                 channel != OMAP_DSS_CHANNEL_LCD &&
2041                 channel != OMAP_DSS_CHANNEL_LCD2);
2042
2043         enable_clocks(1);
2044         l = dispc_read_reg(DISPC_DEFAULT_COLOR(channel));
2045         enable_clocks(0);
2046
2047         return l;
2048 }
2049
2050 void dispc_set_trans_key(enum omap_channel ch,
2051                 enum omap_dss_trans_key_type type,
2052                 u32 trans_key)
2053 {
2054         enable_clocks(1);
2055         if (ch == OMAP_DSS_CHANNEL_LCD)
2056                 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
2057         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2058                 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
2059         else /* OMAP_DSS_CHANNEL_LCD2 */
2060                 REG_FLD_MOD(DISPC_CONFIG2, type, 11, 11);
2061
2062         dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
2063         enable_clocks(0);
2064 }
2065
2066 void dispc_get_trans_key(enum omap_channel ch,
2067                 enum omap_dss_trans_key_type *type,
2068                 u32 *trans_key)
2069 {
2070         enable_clocks(1);
2071         if (type) {
2072                 if (ch == OMAP_DSS_CHANNEL_LCD)
2073                         *type = REG_GET(DISPC_CONFIG, 11, 11);
2074                 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2075                         *type = REG_GET(DISPC_CONFIG, 13, 13);
2076                 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2077                         *type = REG_GET(DISPC_CONFIG2, 11, 11);
2078                 else
2079                         BUG();
2080         }
2081
2082         if (trans_key)
2083                 *trans_key = dispc_read_reg(DISPC_TRANS_COLOR(ch));
2084         enable_clocks(0);
2085 }
2086
2087 void dispc_enable_trans_key(enum omap_channel ch, bool enable)
2088 {
2089         enable_clocks(1);
2090         if (ch == OMAP_DSS_CHANNEL_LCD)
2091                 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
2092         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2093                 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
2094         else /* OMAP_DSS_CHANNEL_LCD2 */
2095                 REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10);
2096         enable_clocks(0);
2097 }
2098 void dispc_enable_alpha_blending(enum omap_channel ch, bool enable)
2099 {
2100         if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
2101                 return;
2102
2103         enable_clocks(1);
2104         if (ch == OMAP_DSS_CHANNEL_LCD)
2105                 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2106         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2107                 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2108         else /* OMAP_DSS_CHANNEL_LCD2 */
2109                 REG_FLD_MOD(DISPC_CONFIG2, enable, 18, 18);
2110         enable_clocks(0);
2111 }
2112 bool dispc_alpha_blending_enabled(enum omap_channel ch)
2113 {
2114         bool enabled;
2115
2116         if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
2117                 return false;
2118
2119         enable_clocks(1);
2120         if (ch == OMAP_DSS_CHANNEL_LCD)
2121                 enabled = REG_GET(DISPC_CONFIG, 18, 18);
2122         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2123                 enabled = REG_GET(DISPC_CONFIG, 19, 19);
2124         else if (ch == OMAP_DSS_CHANNEL_LCD2)
2125                 enabled = REG_GET(DISPC_CONFIG2, 18, 18);
2126         else
2127                 BUG();
2128         enable_clocks(0);
2129
2130         return enabled;
2131 }
2132
2133
2134 bool dispc_trans_key_enabled(enum omap_channel ch)
2135 {
2136         bool enabled;
2137
2138         enable_clocks(1);
2139         if (ch == OMAP_DSS_CHANNEL_LCD)
2140                 enabled = REG_GET(DISPC_CONFIG, 10, 10);
2141         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2142                 enabled = REG_GET(DISPC_CONFIG, 12, 12);
2143         else if (ch == OMAP_DSS_CHANNEL_LCD2)
2144                 enabled = REG_GET(DISPC_CONFIG2, 10, 10);
2145         else
2146                 BUG();
2147         enable_clocks(0);
2148
2149         return enabled;
2150 }
2151
2152
2153 void dispc_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
2154 {
2155         int code;
2156
2157         switch (data_lines) {
2158         case 12:
2159                 code = 0;
2160                 break;
2161         case 16:
2162                 code = 1;
2163                 break;
2164         case 18:
2165                 code = 2;
2166                 break;
2167         case 24:
2168                 code = 3;
2169                 break;
2170         default:
2171                 BUG();
2172                 return;
2173         }
2174
2175         enable_clocks(1);
2176         if (channel == OMAP_DSS_CHANNEL_LCD2)
2177                 REG_FLD_MOD(DISPC_CONTROL2, code, 9, 8);
2178         else
2179                 REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
2180         enable_clocks(0);
2181 }
2182
2183 void dispc_set_parallel_interface_mode(enum omap_channel channel,
2184                 enum omap_parallel_interface_mode mode)
2185 {
2186         u32 l;
2187         int stallmode;
2188         int gpout0 = 1;
2189         int gpout1;
2190
2191         switch (mode) {
2192         case OMAP_DSS_PARALLELMODE_BYPASS:
2193                 stallmode = 0;
2194                 gpout1 = 1;
2195                 break;
2196
2197         case OMAP_DSS_PARALLELMODE_RFBI:
2198                 stallmode = 1;
2199                 gpout1 = 0;
2200                 break;
2201
2202         case OMAP_DSS_PARALLELMODE_DSI:
2203                 stallmode = 1;
2204                 gpout1 = 1;
2205                 break;
2206
2207         default:
2208                 BUG();
2209                 return;
2210         }
2211
2212         enable_clocks(1);
2213
2214         if (channel == OMAP_DSS_CHANNEL_LCD2) {
2215                 l = dispc_read_reg(DISPC_CONTROL2);
2216                 l = FLD_MOD(l, stallmode, 11, 11);
2217                 dispc_write_reg(DISPC_CONTROL2, l);
2218         } else {
2219                 l = dispc_read_reg(DISPC_CONTROL);
2220                 l = FLD_MOD(l, stallmode, 11, 11);
2221                 l = FLD_MOD(l, gpout0, 15, 15);
2222                 l = FLD_MOD(l, gpout1, 16, 16);
2223                 dispc_write_reg(DISPC_CONTROL, l);
2224         }
2225
2226         enable_clocks(0);
2227 }
2228
2229 static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2230                 int vsw, int vfp, int vbp)
2231 {
2232         if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2233                 if (hsw < 1 || hsw > 64 ||
2234                                 hfp < 1 || hfp > 256 ||
2235                                 hbp < 1 || hbp > 256 ||
2236                                 vsw < 1 || vsw > 64 ||
2237                                 vfp < 0 || vfp > 255 ||
2238                                 vbp < 0 || vbp > 255)
2239                         return false;
2240         } else {
2241                 if (hsw < 1 || hsw > 256 ||
2242                                 hfp < 1 || hfp > 4096 ||
2243                                 hbp < 1 || hbp > 4096 ||
2244                                 vsw < 1 || vsw > 256 ||
2245                                 vfp < 0 || vfp > 4095 ||
2246                                 vbp < 0 || vbp > 4095)
2247                         return false;
2248         }
2249
2250         return true;
2251 }
2252
2253 bool dispc_lcd_timings_ok(struct omap_video_timings *timings)
2254 {
2255         return _dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2256                         timings->hbp, timings->vsw,
2257                         timings->vfp, timings->vbp);
2258 }
2259
2260 static void _dispc_set_lcd_timings(enum omap_channel channel, int hsw,
2261                 int hfp, int hbp, int vsw, int vfp, int vbp)
2262 {
2263         u32 timing_h, timing_v;
2264
2265         if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2266                 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
2267                         FLD_VAL(hbp-1, 27, 20);
2268
2269                 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
2270                         FLD_VAL(vbp, 27, 20);
2271         } else {
2272                 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
2273                         FLD_VAL(hbp-1, 31, 20);
2274
2275                 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
2276                         FLD_VAL(vbp, 31, 20);
2277         }
2278
2279         enable_clocks(1);
2280         dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2281         dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
2282         enable_clocks(0);
2283 }
2284
2285 /* change name to mode? */
2286 void dispc_set_lcd_timings(enum omap_channel channel,
2287                 struct omap_video_timings *timings)
2288 {
2289         unsigned xtot, ytot;
2290         unsigned long ht, vt;
2291
2292         if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2293                                 timings->hbp, timings->vsw,
2294                                 timings->vfp, timings->vbp))
2295                 BUG();
2296
2297         _dispc_set_lcd_timings(channel, timings->hsw, timings->hfp,
2298                         timings->hbp, timings->vsw, timings->vfp,
2299                         timings->vbp);
2300
2301         dispc_set_lcd_size(channel, timings->x_res, timings->y_res);
2302
2303         xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
2304         ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
2305
2306         ht = (timings->pixel_clock * 1000) / xtot;
2307         vt = (timings->pixel_clock * 1000) / xtot / ytot;
2308
2309         DSSDBG("channel %d xres %u yres %u\n", channel, timings->x_res,
2310                         timings->y_res);
2311         DSSDBG("pck %u\n", timings->pixel_clock);
2312         DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2313                         timings->hsw, timings->hfp, timings->hbp,
2314                         timings->vsw, timings->vfp, timings->vbp);
2315
2316         DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2317 }
2318
2319 static void dispc_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
2320                 u16 pck_div)
2321 {
2322         BUG_ON(lck_div < 1);
2323         BUG_ON(pck_div < 2);
2324
2325         enable_clocks(1);
2326         dispc_write_reg(DISPC_DIVISORo(channel),
2327                         FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
2328         enable_clocks(0);
2329 }
2330
2331 static void dispc_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2332                 int *pck_div)
2333 {
2334         u32 l;
2335         l = dispc_read_reg(DISPC_DIVISORo(channel));
2336         *lck_div = FLD_GET(l, 23, 16);
2337         *pck_div = FLD_GET(l, 7, 0);
2338 }
2339
2340 unsigned long dispc_fclk_rate(void)
2341 {
2342         unsigned long r = 0;
2343
2344         if (dss_get_dispc_clk_source() == DSS_CLK_SRC_FCK)
2345                 r = dss_clk_get_rate(DSS_CLK_FCK);
2346         else
2347 #ifdef CONFIG_OMAP2_DSS_DSI
2348                 r = dsi_get_pll_hsdiv_dispc_rate();
2349 #else
2350         BUG();
2351 #endif
2352         return r;
2353 }
2354
2355 unsigned long dispc_lclk_rate(enum omap_channel channel)
2356 {
2357         int lcd;
2358         unsigned long r;
2359         u32 l;
2360
2361         l = dispc_read_reg(DISPC_DIVISORo(channel));
2362
2363         lcd = FLD_GET(l, 23, 16);
2364
2365         r = dispc_fclk_rate();
2366
2367         return r / lcd;
2368 }
2369
2370 unsigned long dispc_pclk_rate(enum omap_channel channel)
2371 {
2372         int lcd, pcd;
2373         unsigned long r;
2374         u32 l;
2375
2376         l = dispc_read_reg(DISPC_DIVISORo(channel));
2377
2378         lcd = FLD_GET(l, 23, 16);
2379         pcd = FLD_GET(l, 7, 0);
2380
2381         r = dispc_fclk_rate();
2382
2383         return r / lcd / pcd;
2384 }
2385
2386 void dispc_dump_clocks(struct seq_file *s)
2387 {
2388         int lcd, pcd;
2389         u32 l;
2390         enum dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
2391
2392         enable_clocks(1);
2393
2394         seq_printf(s, "- DISPC -\n");
2395
2396         seq_printf(s, "dispc fclk source = %s (%s)\n",
2397                         dss_get_generic_clk_source_name(dispc_clk_src),
2398                         dss_feat_get_clk_source_name(dispc_clk_src));
2399
2400         seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2401
2402         if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
2403                 seq_printf(s, "- DISPC-CORE-CLK -\n");
2404                 l = dispc_read_reg(DISPC_DIVISOR);
2405                 lcd = FLD_GET(l, 23, 16);
2406
2407                 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2408                                 (dispc_fclk_rate()/lcd), lcd);
2409         }
2410         seq_printf(s, "- LCD1 -\n");
2411
2412         dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd);
2413
2414         seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2415                         dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD), lcd);
2416         seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2417                         dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD), pcd);
2418         if (dss_has_feature(FEAT_MGR_LCD2)) {
2419                 seq_printf(s, "- LCD2 -\n");
2420
2421                 dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd);
2422
2423                 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2424                                 dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD2), lcd);
2425                 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2426                                 dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD2), pcd);
2427         }
2428         enable_clocks(0);
2429 }
2430
2431 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2432 void dispc_dump_irqs(struct seq_file *s)
2433 {
2434         unsigned long flags;
2435         struct dispc_irq_stats stats;
2436
2437         spin_lock_irqsave(&dispc.irq_stats_lock, flags);
2438
2439         stats = dispc.irq_stats;
2440         memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
2441         dispc.irq_stats.last_reset = jiffies;
2442
2443         spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
2444
2445         seq_printf(s, "period %u ms\n",
2446                         jiffies_to_msecs(jiffies - stats.last_reset));
2447
2448         seq_printf(s, "irqs %d\n", stats.irq_count);
2449 #define PIS(x) \
2450         seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
2451
2452         PIS(FRAMEDONE);
2453         PIS(VSYNC);
2454         PIS(EVSYNC_EVEN);
2455         PIS(EVSYNC_ODD);
2456         PIS(ACBIAS_COUNT_STAT);
2457         PIS(PROG_LINE_NUM);
2458         PIS(GFX_FIFO_UNDERFLOW);
2459         PIS(GFX_END_WIN);
2460         PIS(PAL_GAMMA_MASK);
2461         PIS(OCP_ERR);
2462         PIS(VID1_FIFO_UNDERFLOW);
2463         PIS(VID1_END_WIN);
2464         PIS(VID2_FIFO_UNDERFLOW);
2465         PIS(VID2_END_WIN);
2466         PIS(SYNC_LOST);
2467         PIS(SYNC_LOST_DIGIT);
2468         PIS(WAKEUP);
2469         if (dss_has_feature(FEAT_MGR_LCD2)) {
2470                 PIS(FRAMEDONE2);
2471                 PIS(VSYNC2);
2472                 PIS(ACBIAS_COUNT_STAT2);
2473                 PIS(SYNC_LOST2);
2474         }
2475 #undef PIS
2476 }
2477 #endif
2478
2479 void dispc_dump_regs(struct seq_file *s)
2480 {
2481 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dispc_read_reg(r))
2482
2483         dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
2484
2485         DUMPREG(DISPC_REVISION);
2486         DUMPREG(DISPC_SYSCONFIG);
2487         DUMPREG(DISPC_SYSSTATUS);
2488         DUMPREG(DISPC_IRQSTATUS);
2489         DUMPREG(DISPC_IRQENABLE);
2490         DUMPREG(DISPC_CONTROL);
2491         DUMPREG(DISPC_CONFIG);
2492         DUMPREG(DISPC_CAPABLE);
2493         DUMPREG(DISPC_DEFAULT_COLOR(0));
2494         DUMPREG(DISPC_DEFAULT_COLOR(1));
2495         DUMPREG(DISPC_TRANS_COLOR(0));
2496         DUMPREG(DISPC_TRANS_COLOR(1));
2497         DUMPREG(DISPC_LINE_STATUS);
2498         DUMPREG(DISPC_LINE_NUMBER);
2499         DUMPREG(DISPC_TIMING_H(0));
2500         DUMPREG(DISPC_TIMING_V(0));
2501         DUMPREG(DISPC_POL_FREQ(0));
2502         DUMPREG(DISPC_DIVISORo(0));
2503         DUMPREG(DISPC_GLOBAL_ALPHA);
2504         DUMPREG(DISPC_SIZE_DIG);
2505         DUMPREG(DISPC_SIZE_LCD(0));
2506         if (dss_has_feature(FEAT_MGR_LCD2)) {
2507                 DUMPREG(DISPC_CONTROL2);
2508                 DUMPREG(DISPC_CONFIG2);
2509                 DUMPREG(DISPC_DEFAULT_COLOR(2));
2510                 DUMPREG(DISPC_TRANS_COLOR(2));
2511                 DUMPREG(DISPC_TIMING_H(2));
2512                 DUMPREG(DISPC_TIMING_V(2));
2513                 DUMPREG(DISPC_POL_FREQ(2));
2514                 DUMPREG(DISPC_DIVISORo(2));
2515                 DUMPREG(DISPC_SIZE_LCD(2));
2516         }
2517
2518         DUMPREG(DISPC_GFX_BA0);
2519         DUMPREG(DISPC_GFX_BA1);
2520         DUMPREG(DISPC_GFX_POSITION);
2521         DUMPREG(DISPC_GFX_SIZE);
2522         DUMPREG(DISPC_GFX_ATTRIBUTES);
2523         DUMPREG(DISPC_GFX_FIFO_THRESHOLD);
2524         DUMPREG(DISPC_GFX_FIFO_SIZE_STATUS);
2525         DUMPREG(DISPC_GFX_ROW_INC);
2526         DUMPREG(DISPC_GFX_PIXEL_INC);
2527         DUMPREG(DISPC_GFX_WINDOW_SKIP);
2528         DUMPREG(DISPC_GFX_TABLE_BA);
2529
2530         DUMPREG(DISPC_DATA_CYCLE1(0));
2531         DUMPREG(DISPC_DATA_CYCLE2(0));
2532         DUMPREG(DISPC_DATA_CYCLE3(0));
2533
2534         DUMPREG(DISPC_CPR_COEF_R(0));
2535         DUMPREG(DISPC_CPR_COEF_G(0));
2536         DUMPREG(DISPC_CPR_COEF_B(0));
2537         if (dss_has_feature(FEAT_MGR_LCD2)) {
2538                 DUMPREG(DISPC_DATA_CYCLE1(2));
2539                 DUMPREG(DISPC_DATA_CYCLE2(2));
2540                 DUMPREG(DISPC_DATA_CYCLE3(2));
2541
2542                 DUMPREG(DISPC_CPR_COEF_R(2));
2543                 DUMPREG(DISPC_CPR_COEF_G(2));
2544                 DUMPREG(DISPC_CPR_COEF_B(2));
2545         }
2546
2547         DUMPREG(DISPC_GFX_PRELOAD);
2548
2549         DUMPREG(DISPC_VID_BA0(0));
2550         DUMPREG(DISPC_VID_BA1(0));
2551         DUMPREG(DISPC_VID_POSITION(0));
2552         DUMPREG(DISPC_VID_SIZE(0));
2553         DUMPREG(DISPC_VID_ATTRIBUTES(0));
2554         DUMPREG(DISPC_VID_FIFO_THRESHOLD(0));
2555         DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(0));
2556         DUMPREG(DISPC_VID_ROW_INC(0));
2557         DUMPREG(DISPC_VID_PIXEL_INC(0));
2558         DUMPREG(DISPC_VID_FIR(0));
2559         DUMPREG(DISPC_VID_PICTURE_SIZE(0));
2560         DUMPREG(DISPC_VID_ACCU0(0));
2561         DUMPREG(DISPC_VID_ACCU1(0));
2562
2563         DUMPREG(DISPC_VID_BA0(1));
2564         DUMPREG(DISPC_VID_BA1(1));
2565         DUMPREG(DISPC_VID_POSITION(1));
2566         DUMPREG(DISPC_VID_SIZE(1));
2567         DUMPREG(DISPC_VID_ATTRIBUTES(1));
2568         DUMPREG(DISPC_VID_FIFO_THRESHOLD(1));
2569         DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(1));
2570         DUMPREG(DISPC_VID_ROW_INC(1));
2571         DUMPREG(DISPC_VID_PIXEL_INC(1));
2572         DUMPREG(DISPC_VID_FIR(1));
2573         DUMPREG(DISPC_VID_PICTURE_SIZE(1));
2574         DUMPREG(DISPC_VID_ACCU0(1));
2575         DUMPREG(DISPC_VID_ACCU1(1));
2576
2577         DUMPREG(DISPC_VID_FIR_COEF_H(0, 0));
2578         DUMPREG(DISPC_VID_FIR_COEF_H(0, 1));
2579         DUMPREG(DISPC_VID_FIR_COEF_H(0, 2));
2580         DUMPREG(DISPC_VID_FIR_COEF_H(0, 3));
2581         DUMPREG(DISPC_VID_FIR_COEF_H(0, 4));
2582         DUMPREG(DISPC_VID_FIR_COEF_H(0, 5));
2583         DUMPREG(DISPC_VID_FIR_COEF_H(0, 6));
2584         DUMPREG(DISPC_VID_FIR_COEF_H(0, 7));
2585         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 0));
2586         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 1));
2587         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 2));
2588         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 3));
2589         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 4));
2590         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 5));
2591         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 6));
2592         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 7));
2593         DUMPREG(DISPC_VID_CONV_COEF(0, 0));
2594         DUMPREG(DISPC_VID_CONV_COEF(0, 1));
2595         DUMPREG(DISPC_VID_CONV_COEF(0, 2));
2596         DUMPREG(DISPC_VID_CONV_COEF(0, 3));
2597         DUMPREG(DISPC_VID_CONV_COEF(0, 4));
2598         DUMPREG(DISPC_VID_FIR_COEF_V(0, 0));
2599         DUMPREG(DISPC_VID_FIR_COEF_V(0, 1));
2600         DUMPREG(DISPC_VID_FIR_COEF_V(0, 2));
2601         DUMPREG(DISPC_VID_FIR_COEF_V(0, 3));
2602         DUMPREG(DISPC_VID_FIR_COEF_V(0, 4));
2603         DUMPREG(DISPC_VID_FIR_COEF_V(0, 5));
2604         DUMPREG(DISPC_VID_FIR_COEF_V(0, 6));
2605         DUMPREG(DISPC_VID_FIR_COEF_V(0, 7));
2606
2607         DUMPREG(DISPC_VID_FIR_COEF_H(1, 0));
2608         DUMPREG(DISPC_VID_FIR_COEF_H(1, 1));
2609         DUMPREG(DISPC_VID_FIR_COEF_H(1, 2));
2610         DUMPREG(DISPC_VID_FIR_COEF_H(1, 3));
2611         DUMPREG(DISPC_VID_FIR_COEF_H(1, 4));
2612         DUMPREG(DISPC_VID_FIR_COEF_H(1, 5));
2613         DUMPREG(DISPC_VID_FIR_COEF_H(1, 6));
2614         DUMPREG(DISPC_VID_FIR_COEF_H(1, 7));
2615         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 0));
2616         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 1));
2617         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 2));
2618         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 3));
2619         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 4));
2620         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 5));
2621         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 6));
2622         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 7));
2623         DUMPREG(DISPC_VID_CONV_COEF(1, 0));
2624         DUMPREG(DISPC_VID_CONV_COEF(1, 1));
2625         DUMPREG(DISPC_VID_CONV_COEF(1, 2));
2626         DUMPREG(DISPC_VID_CONV_COEF(1, 3));
2627         DUMPREG(DISPC_VID_CONV_COEF(1, 4));
2628         DUMPREG(DISPC_VID_FIR_COEF_V(1, 0));
2629         DUMPREG(DISPC_VID_FIR_COEF_V(1, 1));
2630         DUMPREG(DISPC_VID_FIR_COEF_V(1, 2));
2631         DUMPREG(DISPC_VID_FIR_COEF_V(1, 3));
2632         DUMPREG(DISPC_VID_FIR_COEF_V(1, 4));
2633         DUMPREG(DISPC_VID_FIR_COEF_V(1, 5));
2634         DUMPREG(DISPC_VID_FIR_COEF_V(1, 6));
2635         DUMPREG(DISPC_VID_FIR_COEF_V(1, 7));
2636
2637         DUMPREG(DISPC_VID_PRELOAD(0));
2638         DUMPREG(DISPC_VID_PRELOAD(1));
2639
2640         dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
2641 #undef DUMPREG
2642 }
2643
2644 static void _dispc_set_pol_freq(enum omap_channel channel, bool onoff, bool rf,
2645                 bool ieo, bool ipc, bool ihs, bool ivs, u8 acbi, u8 acb)
2646 {
2647         u32 l = 0;
2648
2649         DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
2650                         onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
2651
2652         l |= FLD_VAL(onoff, 17, 17);
2653         l |= FLD_VAL(rf, 16, 16);
2654         l |= FLD_VAL(ieo, 15, 15);
2655         l |= FLD_VAL(ipc, 14, 14);
2656         l |= FLD_VAL(ihs, 13, 13);
2657         l |= FLD_VAL(ivs, 12, 12);
2658         l |= FLD_VAL(acbi, 11, 8);
2659         l |= FLD_VAL(acb, 7, 0);
2660
2661         enable_clocks(1);
2662         dispc_write_reg(DISPC_POL_FREQ(channel), l);
2663         enable_clocks(0);
2664 }
2665
2666 void dispc_set_pol_freq(enum omap_channel channel,
2667                 enum omap_panel_config config, u8 acbi, u8 acb)
2668 {
2669         _dispc_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0,
2670                         (config & OMAP_DSS_LCD_RF) != 0,
2671                         (config & OMAP_DSS_LCD_IEO) != 0,
2672                         (config & OMAP_DSS_LCD_IPC) != 0,
2673                         (config & OMAP_DSS_LCD_IHS) != 0,
2674                         (config & OMAP_DSS_LCD_IVS) != 0,
2675                         acbi, acb);
2676 }
2677
2678 /* with fck as input clock rate, find dispc dividers that produce req_pck */
2679 void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
2680                 struct dispc_clock_info *cinfo)
2681 {
2682         u16 pcd_min = is_tft ? 2 : 3;
2683         unsigned long best_pck;
2684         u16 best_ld, cur_ld;
2685         u16 best_pd, cur_pd;
2686
2687         best_pck = 0;
2688         best_ld = 0;
2689         best_pd = 0;
2690
2691         for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
2692                 unsigned long lck = fck / cur_ld;
2693
2694                 for (cur_pd = pcd_min; cur_pd <= 255; ++cur_pd) {
2695                         unsigned long pck = lck / cur_pd;
2696                         long old_delta = abs(best_pck - req_pck);
2697                         long new_delta = abs(pck - req_pck);
2698
2699                         if (best_pck == 0 || new_delta < old_delta) {
2700                                 best_pck = pck;
2701                                 best_ld = cur_ld;
2702                                 best_pd = cur_pd;
2703
2704                                 if (pck == req_pck)
2705                                         goto found;
2706                         }
2707
2708                         if (pck < req_pck)
2709                                 break;
2710                 }
2711
2712                 if (lck / pcd_min < req_pck)
2713                         break;
2714         }
2715
2716 found:
2717         cinfo->lck_div = best_ld;
2718         cinfo->pck_div = best_pd;
2719         cinfo->lck = fck / cinfo->lck_div;
2720         cinfo->pck = cinfo->lck / cinfo->pck_div;
2721 }
2722
2723 /* calculate clock rates using dividers in cinfo */
2724 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
2725                 struct dispc_clock_info *cinfo)
2726 {
2727         if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
2728                 return -EINVAL;
2729         if (cinfo->pck_div < 2 || cinfo->pck_div > 255)
2730                 return -EINVAL;
2731
2732         cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
2733         cinfo->pck = cinfo->lck / cinfo->pck_div;
2734
2735         return 0;
2736 }
2737
2738 int dispc_set_clock_div(enum omap_channel channel,
2739                 struct dispc_clock_info *cinfo)
2740 {
2741         DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
2742         DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
2743
2744         dispc_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
2745
2746         return 0;
2747 }
2748
2749 int dispc_get_clock_div(enum omap_channel channel,
2750                 struct dispc_clock_info *cinfo)
2751 {
2752         unsigned long fck;
2753
2754         fck = dispc_fclk_rate();
2755
2756         cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
2757         cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
2758
2759         cinfo->lck = fck / cinfo->lck_div;
2760         cinfo->pck = cinfo->lck / cinfo->pck_div;
2761
2762         return 0;
2763 }
2764
2765 /* dispc.irq_lock has to be locked by the caller */
2766 static void _omap_dispc_set_irqs(void)
2767 {
2768         u32 mask;
2769         u32 old_mask;
2770         int i;
2771         struct omap_dispc_isr_data *isr_data;
2772
2773         mask = dispc.irq_error_mask;
2774
2775         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2776                 isr_data = &dispc.registered_isr[i];
2777
2778                 if (isr_data->isr == NULL)
2779                         continue;
2780
2781                 mask |= isr_data->mask;
2782         }
2783
2784         enable_clocks(1);
2785
2786         old_mask = dispc_read_reg(DISPC_IRQENABLE);
2787         /* clear the irqstatus for newly enabled irqs */
2788         dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
2789
2790         dispc_write_reg(DISPC_IRQENABLE, mask);
2791
2792         enable_clocks(0);
2793 }
2794
2795 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2796 {
2797         int i;
2798         int ret;
2799         unsigned long flags;
2800         struct omap_dispc_isr_data *isr_data;
2801
2802         if (isr == NULL)
2803                 return -EINVAL;
2804
2805         spin_lock_irqsave(&dispc.irq_lock, flags);
2806
2807         /* check for duplicate entry */
2808         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2809                 isr_data = &dispc.registered_isr[i];
2810                 if (isr_data->isr == isr && isr_data->arg == arg &&
2811                                 isr_data->mask == mask) {
2812                         ret = -EINVAL;
2813                         goto err;
2814                 }
2815         }
2816
2817         isr_data = NULL;
2818         ret = -EBUSY;
2819
2820         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2821                 isr_data = &dispc.registered_isr[i];
2822
2823                 if (isr_data->isr != NULL)
2824                         continue;
2825
2826                 isr_data->isr = isr;
2827                 isr_data->arg = arg;
2828                 isr_data->mask = mask;
2829                 ret = 0;
2830
2831                 break;
2832         }
2833
2834         if (ret)
2835                 goto err;
2836
2837         _omap_dispc_set_irqs();
2838
2839         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2840
2841         return 0;
2842 err:
2843         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2844
2845         return ret;
2846 }
2847 EXPORT_SYMBOL(omap_dispc_register_isr);
2848
2849 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2850 {
2851         int i;
2852         unsigned long flags;
2853         int ret = -EINVAL;
2854         struct omap_dispc_isr_data *isr_data;
2855
2856         spin_lock_irqsave(&dispc.irq_lock, flags);
2857
2858         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2859                 isr_data = &dispc.registered_isr[i];
2860                 if (isr_data->isr != isr || isr_data->arg != arg ||
2861                                 isr_data->mask != mask)
2862                         continue;
2863
2864                 /* found the correct isr */
2865
2866                 isr_data->isr = NULL;
2867                 isr_data->arg = NULL;
2868                 isr_data->mask = 0;
2869
2870                 ret = 0;
2871                 break;
2872         }
2873
2874         if (ret == 0)
2875                 _omap_dispc_set_irqs();
2876
2877         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2878
2879         return ret;
2880 }
2881 EXPORT_SYMBOL(omap_dispc_unregister_isr);
2882
2883 #ifdef DEBUG
2884 static void print_irq_status(u32 status)
2885 {
2886         if ((status & dispc.irq_error_mask) == 0)
2887                 return;
2888
2889         printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
2890
2891 #define PIS(x) \
2892         if (status & DISPC_IRQ_##x) \
2893                 printk(#x " ");
2894         PIS(GFX_FIFO_UNDERFLOW);
2895         PIS(OCP_ERR);
2896         PIS(VID1_FIFO_UNDERFLOW);
2897         PIS(VID2_FIFO_UNDERFLOW);
2898         PIS(SYNC_LOST);
2899         PIS(SYNC_LOST_DIGIT);
2900         if (dss_has_feature(FEAT_MGR_LCD2))
2901                 PIS(SYNC_LOST2);
2902 #undef PIS
2903
2904         printk("\n");
2905 }
2906 #endif
2907
2908 /* Called from dss.c. Note that we don't touch clocks here,
2909  * but we presume they are on because we got an IRQ. However,
2910  * an irq handler may turn the clocks off, so we may not have
2911  * clock later in the function. */
2912 static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
2913 {
2914         int i;
2915         u32 irqstatus, irqenable;
2916         u32 handledirqs = 0;
2917         u32 unhandled_errors;
2918         struct omap_dispc_isr_data *isr_data;
2919         struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
2920
2921         spin_lock(&dispc.irq_lock);
2922
2923         irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
2924         irqenable = dispc_read_reg(DISPC_IRQENABLE);
2925
2926         /* IRQ is not for us */
2927         if (!(irqstatus & irqenable)) {
2928                 spin_unlock(&dispc.irq_lock);
2929                 return IRQ_NONE;
2930         }
2931
2932 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2933         spin_lock(&dispc.irq_stats_lock);
2934         dispc.irq_stats.irq_count++;
2935         dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
2936         spin_unlock(&dispc.irq_stats_lock);
2937 #endif
2938
2939 #ifdef DEBUG
2940         if (dss_debug)
2941                 print_irq_status(irqstatus);
2942 #endif
2943         /* Ack the interrupt. Do it here before clocks are possibly turned
2944          * off */
2945         dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
2946         /* flush posted write */
2947         dispc_read_reg(DISPC_IRQSTATUS);
2948
2949         /* make a copy and unlock, so that isrs can unregister
2950          * themselves */
2951         memcpy(registered_isr, dispc.registered_isr,
2952                         sizeof(registered_isr));
2953
2954         spin_unlock(&dispc.irq_lock);
2955
2956         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2957                 isr_data = &registered_isr[i];
2958
2959                 if (!isr_data->isr)
2960                         continue;
2961
2962                 if (isr_data->mask & irqstatus) {
2963                         isr_data->isr(isr_data->arg, irqstatus);
2964                         handledirqs |= isr_data->mask;
2965                 }
2966         }
2967
2968         spin_lock(&dispc.irq_lock);
2969
2970         unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
2971
2972         if (unhandled_errors) {
2973                 dispc.error_irqs |= unhandled_errors;
2974
2975                 dispc.irq_error_mask &= ~unhandled_errors;
2976                 _omap_dispc_set_irqs();
2977
2978                 schedule_work(&dispc.error_work);
2979         }
2980
2981         spin_unlock(&dispc.irq_lock);
2982
2983         return IRQ_HANDLED;
2984 }
2985
2986 static void dispc_error_worker(struct work_struct *work)
2987 {
2988         int i;
2989         u32 errors;
2990         unsigned long flags;
2991
2992         spin_lock_irqsave(&dispc.irq_lock, flags);
2993         errors = dispc.error_irqs;
2994         dispc.error_irqs = 0;
2995         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2996
2997         if (errors & DISPC_IRQ_GFX_FIFO_UNDERFLOW) {
2998                 DSSERR("GFX_FIFO_UNDERFLOW, disabling GFX\n");
2999                 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3000                         struct omap_overlay *ovl;
3001                         ovl = omap_dss_get_overlay(i);
3002
3003                         if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3004                                 continue;
3005
3006                         if (ovl->id == 0) {
3007                                 dispc_enable_plane(ovl->id, 0);
3008                                 dispc_go(ovl->manager->id);
3009                                 mdelay(50);
3010                                 break;
3011                         }
3012                 }
3013         }
3014
3015         if (errors & DISPC_IRQ_VID1_FIFO_UNDERFLOW) {
3016                 DSSERR("VID1_FIFO_UNDERFLOW, disabling VID1\n");
3017                 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3018                         struct omap_overlay *ovl;
3019                         ovl = omap_dss_get_overlay(i);
3020
3021                         if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3022                                 continue;
3023
3024                         if (ovl->id == 1) {
3025                                 dispc_enable_plane(ovl->id, 0);
3026                                 dispc_go(ovl->manager->id);
3027                                 mdelay(50);
3028                                 break;
3029                         }
3030                 }
3031         }
3032
3033         if (errors & DISPC_IRQ_VID2_FIFO_UNDERFLOW) {
3034                 DSSERR("VID2_FIFO_UNDERFLOW, disabling VID2\n");
3035                 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3036                         struct omap_overlay *ovl;
3037                         ovl = omap_dss_get_overlay(i);
3038
3039                         if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3040                                 continue;
3041
3042                         if (ovl->id == 2) {
3043                                 dispc_enable_plane(ovl->id, 0);
3044                                 dispc_go(ovl->manager->id);
3045                                 mdelay(50);
3046                                 break;
3047                         }
3048                 }
3049         }
3050
3051         if (errors & DISPC_IRQ_SYNC_LOST) {
3052                 struct omap_overlay_manager *manager = NULL;
3053                 bool enable = false;
3054
3055                 DSSERR("SYNC_LOST, disabling LCD\n");
3056
3057                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3058                         struct omap_overlay_manager *mgr;
3059                         mgr = omap_dss_get_overlay_manager(i);
3060
3061                         if (mgr->id == OMAP_DSS_CHANNEL_LCD) {
3062                                 manager = mgr;
3063                                 enable = mgr->device->state ==
3064                                                 OMAP_DSS_DISPLAY_ACTIVE;
3065                                 mgr->device->driver->disable(mgr->device);
3066                                 break;
3067                         }
3068                 }
3069
3070                 if (manager) {
3071                         struct omap_dss_device *dssdev = manager->device;
3072                         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3073                                 struct omap_overlay *ovl;
3074                                 ovl = omap_dss_get_overlay(i);
3075
3076                                 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3077                                         continue;
3078
3079                                 if (ovl->id != 0 && ovl->manager == manager)
3080                                         dispc_enable_plane(ovl->id, 0);
3081                         }
3082
3083                         dispc_go(manager->id);
3084                         mdelay(50);
3085                         if (enable)
3086                                 dssdev->driver->enable(dssdev);
3087                 }
3088         }
3089
3090         if (errors & DISPC_IRQ_SYNC_LOST_DIGIT) {
3091                 struct omap_overlay_manager *manager = NULL;
3092                 bool enable = false;
3093
3094                 DSSERR("SYNC_LOST_DIGIT, disabling TV\n");
3095
3096                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3097                         struct omap_overlay_manager *mgr;
3098                         mgr = omap_dss_get_overlay_manager(i);
3099
3100                         if (mgr->id == OMAP_DSS_CHANNEL_DIGIT) {
3101                                 manager = mgr;
3102                                 enable = mgr->device->state ==
3103                                                 OMAP_DSS_DISPLAY_ACTIVE;
3104                                 mgr->device->driver->disable(mgr->device);
3105                                 break;
3106                         }
3107                 }
3108
3109                 if (manager) {
3110                         struct omap_dss_device *dssdev = manager->device;
3111                         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3112                                 struct omap_overlay *ovl;
3113                                 ovl = omap_dss_get_overlay(i);
3114
3115                                 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3116                                         continue;
3117
3118                                 if (ovl->id != 0 && ovl->manager == manager)
3119                                         dispc_enable_plane(ovl->id, 0);
3120                         }
3121
3122                         dispc_go(manager->id);
3123                         mdelay(50);
3124                         if (enable)
3125                                 dssdev->driver->enable(dssdev);
3126                 }
3127         }
3128
3129         if (errors & DISPC_IRQ_SYNC_LOST2) {
3130                 struct omap_overlay_manager *manager = NULL;
3131                 bool enable = false;
3132
3133                 DSSERR("SYNC_LOST for LCD2, disabling LCD2\n");
3134
3135                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3136                         struct omap_overlay_manager *mgr;
3137                         mgr = omap_dss_get_overlay_manager(i);
3138
3139                         if (mgr->id == OMAP_DSS_CHANNEL_LCD2) {
3140                                 manager = mgr;
3141                                 enable = mgr->device->state ==
3142                                                 OMAP_DSS_DISPLAY_ACTIVE;
3143                                 mgr->device->driver->disable(mgr->device);
3144                                 break;
3145                         }
3146                 }
3147
3148                 if (manager) {
3149                         struct omap_dss_device *dssdev = manager->device;
3150                         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3151                                 struct omap_overlay *ovl;
3152                                 ovl = omap_dss_get_overlay(i);
3153
3154                                 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3155                                         continue;
3156
3157                                 if (ovl->id != 0 && ovl->manager == manager)
3158                                         dispc_enable_plane(ovl->id, 0);
3159                         }
3160
3161                         dispc_go(manager->id);
3162                         mdelay(50);
3163                         if (enable)
3164                                 dssdev->driver->enable(dssdev);
3165                 }
3166         }
3167
3168         if (errors & DISPC_IRQ_OCP_ERR) {
3169                 DSSERR("OCP_ERR\n");
3170                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3171                         struct omap_overlay_manager *mgr;
3172                         mgr = omap_dss_get_overlay_manager(i);
3173
3174                         if (mgr->caps & OMAP_DSS_OVL_CAP_DISPC)
3175                                 mgr->device->driver->disable(mgr->device);
3176                 }
3177         }
3178
3179         spin_lock_irqsave(&dispc.irq_lock, flags);
3180         dispc.irq_error_mask |= errors;
3181         _omap_dispc_set_irqs();
3182         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3183 }
3184
3185 int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3186 {
3187         void dispc_irq_wait_handler(void *data, u32 mask)
3188         {
3189                 complete((struct completion *)data);
3190         }
3191
3192         int r;
3193         DECLARE_COMPLETION_ONSTACK(completion);
3194
3195         r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3196                         irqmask);
3197
3198         if (r)
3199                 return r;
3200
3201         timeout = wait_for_completion_timeout(&completion, timeout);
3202
3203         omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3204
3205         if (timeout == 0)
3206                 return -ETIMEDOUT;
3207
3208         if (timeout == -ERESTARTSYS)
3209                 return -ERESTARTSYS;
3210
3211         return 0;
3212 }
3213
3214 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3215                 unsigned long timeout)
3216 {
3217         void dispc_irq_wait_handler(void *data, u32 mask)
3218         {
3219                 complete((struct completion *)data);
3220         }
3221
3222         int r;
3223         DECLARE_COMPLETION_ONSTACK(completion);
3224
3225         r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3226                         irqmask);
3227
3228         if (r)
3229                 return r;
3230
3231         timeout = wait_for_completion_interruptible_timeout(&completion,
3232                         timeout);
3233
3234         omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3235
3236         if (timeout == 0)
3237                 return -ETIMEDOUT;
3238
3239         if (timeout == -ERESTARTSYS)
3240                 return -ERESTARTSYS;
3241
3242         return 0;
3243 }
3244
3245 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
3246 void dispc_fake_vsync_irq(void)
3247 {
3248         u32 irqstatus = DISPC_IRQ_VSYNC;
3249         int i;
3250
3251         WARN_ON(!in_interrupt());
3252
3253         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3254                 struct omap_dispc_isr_data *isr_data;
3255                 isr_data = &dispc.registered_isr[i];
3256
3257                 if (!isr_data->isr)
3258                         continue;
3259
3260                 if (isr_data->mask & irqstatus)
3261                         isr_data->isr(isr_data->arg, irqstatus);
3262         }
3263 }
3264 #endif
3265
3266 static void _omap_dispc_initialize_irq(void)
3267 {
3268         unsigned long flags;
3269
3270         spin_lock_irqsave(&dispc.irq_lock, flags);
3271
3272         memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3273
3274         dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
3275         if (dss_has_feature(FEAT_MGR_LCD2))
3276                 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
3277
3278         /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3279          * so clear it */
3280         dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3281
3282         _omap_dispc_set_irqs();
3283
3284         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3285 }
3286
3287 void dispc_enable_sidle(void)
3288 {
3289         REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3);  /* SIDLEMODE: smart idle */
3290 }
3291
3292 void dispc_disable_sidle(void)
3293 {
3294         REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3);  /* SIDLEMODE: no idle */
3295 }
3296
3297 static void _omap_dispc_initial_config(void)
3298 {
3299         u32 l;
3300
3301         l = dispc_read_reg(DISPC_SYSCONFIG);
3302         l = FLD_MOD(l, 2, 13, 12);      /* MIDLEMODE: smart standby */
3303         l = FLD_MOD(l, 2, 4, 3);        /* SIDLEMODE: smart idle */
3304         l = FLD_MOD(l, 1, 2, 2);        /* ENWAKEUP */
3305         l = FLD_MOD(l, 1, 0, 0);        /* AUTOIDLE */
3306         dispc_write_reg(DISPC_SYSCONFIG, l);
3307
3308         /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3309         if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3310                 l = dispc_read_reg(DISPC_DIVISOR);
3311                 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3312                 l = FLD_MOD(l, 1, 0, 0);
3313                 l = FLD_MOD(l, 1, 23, 16);
3314                 dispc_write_reg(DISPC_DIVISOR, l);
3315         }
3316
3317         /* FUNCGATED */
3318         if (dss_has_feature(FEAT_FUNCGATED))
3319                 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3320
3321         /* L3 firewall setting: enable access to OCM RAM */
3322         /* XXX this should be somewhere in plat-omap */
3323         if (cpu_is_omap24xx())
3324                 __raw_writel(0x402000b0, OMAP2_L3_IO_ADDRESS(0x680050a0));
3325
3326         _dispc_setup_color_conv_coef();
3327
3328         dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3329
3330         dispc_read_plane_fifo_sizes();
3331 }
3332
3333 int dispc_enable_plane(enum omap_plane plane, bool enable)
3334 {
3335         DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
3336
3337         enable_clocks(1);
3338         _dispc_enable_plane(plane, enable);
3339         enable_clocks(0);
3340
3341         return 0;
3342 }
3343
3344 int dispc_setup_plane(enum omap_plane plane,
3345                        u32 paddr, u16 screen_width,
3346                        u16 pos_x, u16 pos_y,
3347                        u16 width, u16 height,
3348                        u16 out_width, u16 out_height,
3349                        enum omap_color_mode color_mode,
3350                        bool ilace,
3351                        enum omap_dss_rotation_type rotation_type,
3352                        u8 rotation, bool mirror, u8 global_alpha,
3353                        u8 pre_mult_alpha, enum omap_channel channel)
3354 {
3355         int r = 0;
3356
3357         DSSDBG("dispc_setup_plane %d, pa %x, sw %d, %d,%d, %dx%d -> "
3358                "%dx%d, ilace %d, cmode %x, rot %d, mir %d chan %d\n",
3359                plane, paddr, screen_width, pos_x, pos_y,
3360                width, height,
3361                out_width, out_height,
3362                ilace, color_mode,
3363                rotation, mirror, channel);
3364
3365         enable_clocks(1);
3366
3367         r = _dispc_setup_plane(plane,
3368                            paddr, screen_width,
3369                            pos_x, pos_y,
3370                            width, height,
3371                            out_width, out_height,
3372                            color_mode, ilace,
3373                            rotation_type,
3374                            rotation, mirror,
3375                            global_alpha,
3376                            pre_mult_alpha, channel);
3377
3378         enable_clocks(0);
3379
3380         return r;
3381 }
3382
3383 /* DISPC HW IP initialisation */
3384 static int omap_dispchw_probe(struct platform_device *pdev)
3385 {
3386         u32 rev;
3387         int r = 0;
3388         struct resource *dispc_mem;
3389
3390         dispc.pdev = pdev;
3391
3392         spin_lock_init(&dispc.irq_lock);
3393
3394 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3395         spin_lock_init(&dispc.irq_stats_lock);
3396         dispc.irq_stats.last_reset = jiffies;
3397 #endif
3398
3399         INIT_WORK(&dispc.error_work, dispc_error_worker);
3400
3401         dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3402         if (!dispc_mem) {
3403                 DSSERR("can't get IORESOURCE_MEM DISPC\n");
3404                 r = -EINVAL;
3405                 goto fail0;
3406         }
3407         dispc.base = ioremap(dispc_mem->start, resource_size(dispc_mem));
3408         if (!dispc.base) {
3409                 DSSERR("can't ioremap DISPC\n");
3410                 r = -ENOMEM;
3411                 goto fail0;
3412         }
3413         dispc.irq = platform_get_irq(dispc.pdev, 0);
3414         if (dispc.irq < 0) {
3415                 DSSERR("platform_get_irq failed\n");
3416                 r = -ENODEV;
3417                 goto fail1;
3418         }
3419
3420         r = request_irq(dispc.irq, omap_dispc_irq_handler, IRQF_SHARED,
3421                 "OMAP DISPC", dispc.pdev);
3422         if (r < 0) {
3423                 DSSERR("request_irq failed\n");
3424                 goto fail1;
3425         }
3426
3427         enable_clocks(1);
3428
3429         _omap_dispc_initial_config();
3430
3431         _omap_dispc_initialize_irq();
3432
3433         dispc_save_context();
3434
3435         rev = dispc_read_reg(DISPC_REVISION);
3436         dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
3437                FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3438
3439         enable_clocks(0);
3440
3441         return 0;
3442 fail1:
3443         iounmap(dispc.base);
3444 fail0:
3445         return r;
3446 }
3447
3448 static int omap_dispchw_remove(struct platform_device *pdev)
3449 {
3450         free_irq(dispc.irq, dispc.pdev);
3451         iounmap(dispc.base);
3452         return 0;
3453 }
3454
3455 static struct platform_driver omap_dispchw_driver = {
3456         .probe          = omap_dispchw_probe,
3457         .remove         = omap_dispchw_remove,
3458         .driver         = {
3459                 .name   = "omapdss_dispc",
3460                 .owner  = THIS_MODULE,
3461         },
3462 };
3463
3464 int dispc_init_platform_driver(void)
3465 {
3466         return platform_driver_register(&omap_dispchw_driver);
3467 }
3468
3469 void dispc_uninit_platform_driver(void)
3470 {
3471         return platform_driver_unregister(&omap_dispchw_driver);
3472 }