drivers/video/omap2/dss/dispc.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dispc.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #define DSS_SUBSYS_NAME "DISPC"
  24
  25 #include <linux/kernel.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/vmalloc.h>
  28 #include <linux/clk.h>
  29 #include <linux/io.h>
  30 #include <linux/jiffies.h>
  31 #include <linux/seq_file.h>
  32 #include <linux/delay.h>
  33 #include <linux/workqueue.h>
  34 #include <linux/hardirq.h>
  35
  36 #include <plat/sram.h>
  37 #include <plat/clock.h>
  38
  39 #include <plat/display.h>
  40
  41 #include "dss.h"
  42 #include "dss_features.h"
  43
  44 /* DISPC */
  45 #define DISPC_BASE                      0x48050400
  46
  47 #define DISPC_SZ_REGS                   SZ_1K
  48
  49 struct dispc_reg { u16 idx; };
  50
  51 #define DISPC_REG(idx)                  ((const struct dispc_reg) { idx })
  52
  53 /* DISPC common */
  54 #define DISPC_REVISION                  DISPC_REG(0x0000)
  55 #define DISPC_SYSCONFIG                 DISPC_REG(0x0010)
  56 #define DISPC_SYSSTATUS                 DISPC_REG(0x0014)
  57 #define DISPC_IRQSTATUS                 DISPC_REG(0x0018)
  58 #define DISPC_IRQENABLE                 DISPC_REG(0x001C)
  59 #define DISPC_CONTROL                   DISPC_REG(0x0040)
  60 #define DISPC_CONFIG                    DISPC_REG(0x0044)
  61 #define DISPC_CAPABLE                   DISPC_REG(0x0048)
  62 #define DISPC_DEFAULT_COLOR0            DISPC_REG(0x004C)
  63 #define DISPC_DEFAULT_COLOR1            DISPC_REG(0x0050)
  64 #define DISPC_TRANS_COLOR0              DISPC_REG(0x0054)
  65 #define DISPC_TRANS_COLOR1              DISPC_REG(0x0058)
  66 #define DISPC_LINE_STATUS               DISPC_REG(0x005C)
  67 #define DISPC_LINE_NUMBER               DISPC_REG(0x0060)
  68 #define DISPC_TIMING_H                  DISPC_REG(0x0064)
  69 #define DISPC_TIMING_V                  DISPC_REG(0x0068)
  70 #define DISPC_POL_FREQ                  DISPC_REG(0x006C)
  71 #define DISPC_DIVISOR                   DISPC_REG(0x0070)
  72 #define DISPC_GLOBAL_ALPHA              DISPC_REG(0x0074)
  73 #define DISPC_SIZE_DIG                  DISPC_REG(0x0078)
  74 #define DISPC_SIZE_LCD                  DISPC_REG(0x007C)
  75
  76 /* DISPC GFX plane */
  77 #define DISPC_GFX_BA0                   DISPC_REG(0x0080)
  78 #define DISPC_GFX_BA1                   DISPC_REG(0x0084)
  79 #define DISPC_GFX_POSITION              DISPC_REG(0x0088)
  80 #define DISPC_GFX_SIZE                  DISPC_REG(0x008C)
  81 #define DISPC_GFX_ATTRIBUTES            DISPC_REG(0x00A0)
  82 #define DISPC_GFX_FIFO_THRESHOLD        DISPC_REG(0x00A4)
  83 #define DISPC_GFX_FIFO_SIZE_STATUS      DISPC_REG(0x00A8)
  84 #define DISPC_GFX_ROW_INC               DISPC_REG(0x00AC)
  85 #define DISPC_GFX_PIXEL_INC             DISPC_REG(0x00B0)
  86 #define DISPC_GFX_WINDOW_SKIP           DISPC_REG(0x00B4)
  87 #define DISPC_GFX_TABLE_BA              DISPC_REG(0x00B8)
  88
  89 #define DISPC_DATA_CYCLE1               DISPC_REG(0x01D4)
  90 #define DISPC_DATA_CYCLE2               DISPC_REG(0x01D8)
  91 #define DISPC_DATA_CYCLE3               DISPC_REG(0x01DC)
  92
  93 #define DISPC_CPR_COEF_R                DISPC_REG(0x0220)
  94 #define DISPC_CPR_COEF_G                DISPC_REG(0x0224)
  95 #define DISPC_CPR_COEF_B                DISPC_REG(0x0228)
  96
  97 #define DISPC_GFX_PRELOAD               DISPC_REG(0x022C)
  98
  99 /* DISPC Video plane, n = 0 for VID1 and n = 1 for VID2 */
 100 #define DISPC_VID_REG(n, idx)           DISPC_REG(0x00BC + (n)*0x90 + idx)
 101
 102 #define DISPC_VID_BA0(n)                DISPC_VID_REG(n, 0x0000)
 103 #define DISPC_VID_BA1(n)                DISPC_VID_REG(n, 0x0004)
 104 #define DISPC_VID_POSITION(n)           DISPC_VID_REG(n, 0x0008)
 105 #define DISPC_VID_SIZE(n)               DISPC_VID_REG(n, 0x000C)
 106 #define DISPC_VID_ATTRIBUTES(n)         DISPC_VID_REG(n, 0x0010)
 107 #define DISPC_VID_FIFO_THRESHOLD(n)     DISPC_VID_REG(n, 0x0014)
 108 #define DISPC_VID_FIFO_SIZE_STATUS(n)   DISPC_VID_REG(n, 0x0018)
 109 #define DISPC_VID_ROW_INC(n)            DISPC_VID_REG(n, 0x001C)
 110 #define DISPC_VID_PIXEL_INC(n)          DISPC_VID_REG(n, 0x0020)
 111 #define DISPC_VID_FIR(n)                DISPC_VID_REG(n, 0x0024)
 112 #define DISPC_VID_PICTURE_SIZE(n)       DISPC_VID_REG(n, 0x0028)
 113 #define DISPC_VID_ACCU0(n)              DISPC_VID_REG(n, 0x002C)
 114 #define DISPC_VID_ACCU1(n)              DISPC_VID_REG(n, 0x0030)
 115
 116 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 117 #define DISPC_VID_FIR_COEF_H(n, i)      DISPC_REG(0x00F0 + (n)*0x90 + (i)*0x8)
 118 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 119 #define DISPC_VID_FIR_COEF_HV(n, i)     DISPC_REG(0x00F4 + (n)*0x90 + (i)*0x8)
 120 /* coef index i = {0, 1, 2, 3, 4} */
 121 #define DISPC_VID_CONV_COEF(n, i)       DISPC_REG(0x0130 + (n)*0x90 + (i)*0x4)
 122 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 123 #define DISPC_VID_FIR_COEF_V(n, i)      DISPC_REG(0x01E0 + (n)*0x20 + (i)*0x4)
 124
 125 #define DISPC_VID_PRELOAD(n)            DISPC_REG(0x230 + (n)*0x04)
 126
 127
 128 #define DISPC_IRQ_MASK_ERROR            (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
 129                                          DISPC_IRQ_OCP_ERR | \
 130                                          DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
 131                                          DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
 132                                          DISPC_IRQ_SYNC_LOST | \
 133                                          DISPC_IRQ_SYNC_LOST_DIGIT)
 134
 135 #define DISPC_MAX_NR_ISRS               8
 136
 137 struct omap_dispc_isr_data {
 138         omap_dispc_isr_t        isr;
 139         void                    *arg;
 140         u32                     mask;
 141 };
 142
 143 struct dispc_h_coef {
 144         s8 hc4;
 145         s8 hc3;
 146         u8 hc2;
 147         s8 hc1;
 148         s8 hc0;
 149 };
 150
 151 struct dispc_v_coef {
 152         s8 vc22;
 153         s8 vc2;
 154         u8 vc1;
 155         s8 vc0;
 156         s8 vc00;
 157 };
 158
 159 #define REG_GET(idx, start, end) \
 160         FLD_GET(dispc_read_reg(idx), start, end)
 161
 162 #define REG_FLD_MOD(idx, val, start, end)                               \
 163         dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
 164
 165 static const struct dispc_reg dispc_reg_att[] = { DISPC_GFX_ATTRIBUTES,
 166         DISPC_VID_ATTRIBUTES(0),
 167         DISPC_VID_ATTRIBUTES(1) };
 168
 169 struct dispc_irq_stats {
 170         unsigned long last_reset;
 171         unsigned irq_count;
 172         unsigned irqs[32];
 173 };
 174
 175 static struct {
 176         void __iomem    *base;
 177
 178         u32     fifo_size[3];
 179
 180         spinlock_t irq_lock;
 181         u32 irq_error_mask;
 182         struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
 183         u32 error_irqs;
 184         struct work_struct error_work;
 185
 186         u32             ctx[DISPC_SZ_REGS / sizeof(u32)];
 187
 188 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
 189         spinlock_t irq_stats_lock;
 190         struct dispc_irq_stats irq_stats;
 191 #endif
 192 } dispc;
 193
 194 static void _omap_dispc_set_irqs(void);
 195
 196 static inline void dispc_write_reg(const struct dispc_reg idx, u32 val)
 197 {
 198         __raw_writel(val, dispc.base + idx.idx);
 199 }
 200
 201 static inline u32 dispc_read_reg(const struct dispc_reg idx)
 202 {
 203         return __raw_readl(dispc.base + idx.idx);
 204 }
 205
 206 #define SR(reg) \
 207         dispc.ctx[(DISPC_##reg).idx / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
 208 #define RR(reg) \
 209         dispc_write_reg(DISPC_##reg, dispc.ctx[(DISPC_##reg).idx / sizeof(u32)])
 210
 211 void dispc_save_context(void)
 212 {
 213         if (cpu_is_omap24xx())
 214                 return;
 215
 216         SR(SYSCONFIG);
 217         SR(IRQENABLE);
 218         SR(CONTROL);
 219         SR(CONFIG);
 220         SR(DEFAULT_COLOR0);
 221         SR(DEFAULT_COLOR1);
 222         SR(TRANS_COLOR0);
 223         SR(TRANS_COLOR1);
 224         SR(LINE_NUMBER);
 225         SR(TIMING_H);
 226         SR(TIMING_V);
 227         SR(POL_FREQ);
 228         SR(DIVISOR);
 229         SR(GLOBAL_ALPHA);
 230         SR(SIZE_DIG);
 231         SR(SIZE_LCD);
 232
 233         SR(GFX_BA0);
 234         SR(GFX_BA1);
 235         SR(GFX_POSITION);
 236         SR(GFX_SIZE);
 237         SR(GFX_ATTRIBUTES);
 238         SR(GFX_FIFO_THRESHOLD);
 239         SR(GFX_ROW_INC);
 240         SR(GFX_PIXEL_INC);
 241         SR(GFX_WINDOW_SKIP);
 242         SR(GFX_TABLE_BA);
 243
 244         SR(DATA_CYCLE1);
 245         SR(DATA_CYCLE2);
 246         SR(DATA_CYCLE3);
 247
 248         SR(CPR_COEF_R);
 249         SR(CPR_COEF_G);
 250         SR(CPR_COEF_B);
 251
 252         SR(GFX_PRELOAD);
 253
 254         /* VID1 */
 255         SR(VID_BA0(0));
 256         SR(VID_BA1(0));
 257         SR(VID_POSITION(0));
 258         SR(VID_SIZE(0));
 259         SR(VID_ATTRIBUTES(0));
 260         SR(VID_FIFO_THRESHOLD(0));
 261         SR(VID_ROW_INC(0));
 262         SR(VID_PIXEL_INC(0));
 263         SR(VID_FIR(0));
 264         SR(VID_PICTURE_SIZE(0));
 265         SR(VID_ACCU0(0));
 266         SR(VID_ACCU1(0));
 267
 268         SR(VID_FIR_COEF_H(0, 0));
 269         SR(VID_FIR_COEF_H(0, 1));
 270         SR(VID_FIR_COEF_H(0, 2));
 271         SR(VID_FIR_COEF_H(0, 3));
 272         SR(VID_FIR_COEF_H(0, 4));
 273         SR(VID_FIR_COEF_H(0, 5));
 274         SR(VID_FIR_COEF_H(0, 6));
 275         SR(VID_FIR_COEF_H(0, 7));
 276
 277         SR(VID_FIR_COEF_HV(0, 0));
 278         SR(VID_FIR_COEF_HV(0, 1));
 279         SR(VID_FIR_COEF_HV(0, 2));
 280         SR(VID_FIR_COEF_HV(0, 3));
 281         SR(VID_FIR_COEF_HV(0, 4));
 282         SR(VID_FIR_COEF_HV(0, 5));
 283         SR(VID_FIR_COEF_HV(0, 6));
 284         SR(VID_FIR_COEF_HV(0, 7));
 285
 286         SR(VID_CONV_COEF(0, 0));
 287         SR(VID_CONV_COEF(0, 1));
 288         SR(VID_CONV_COEF(0, 2));
 289         SR(VID_CONV_COEF(0, 3));
 290         SR(VID_CONV_COEF(0, 4));
 291
 292         SR(VID_FIR_COEF_V(0, 0));
 293         SR(VID_FIR_COEF_V(0, 1));
 294         SR(VID_FIR_COEF_V(0, 2));
 295         SR(VID_FIR_COEF_V(0, 3));
 296         SR(VID_FIR_COEF_V(0, 4));
 297         SR(VID_FIR_COEF_V(0, 5));
 298         SR(VID_FIR_COEF_V(0, 6));
 299         SR(VID_FIR_COEF_V(0, 7));
 300
 301         SR(VID_PRELOAD(0));
 302
 303         /* VID2 */
 304         SR(VID_BA0(1));
 305         SR(VID_BA1(1));
 306         SR(VID_POSITION(1));
 307         SR(VID_SIZE(1));
 308         SR(VID_ATTRIBUTES(1));
 309         SR(VID_FIFO_THRESHOLD(1));
 310         SR(VID_ROW_INC(1));
 311         SR(VID_PIXEL_INC(1));
 312         SR(VID_FIR(1));
 313         SR(VID_PICTURE_SIZE(1));
 314         SR(VID_ACCU0(1));
 315         SR(VID_ACCU1(1));
 316
 317         SR(VID_FIR_COEF_H(1, 0));
 318         SR(VID_FIR_COEF_H(1, 1));
 319         SR(VID_FIR_COEF_H(1, 2));
 320         SR(VID_FIR_COEF_H(1, 3));
 321         SR(VID_FIR_COEF_H(1, 4));
 322         SR(VID_FIR_COEF_H(1, 5));
 323         SR(VID_FIR_COEF_H(1, 6));
 324         SR(VID_FIR_COEF_H(1, 7));
 325
 326         SR(VID_FIR_COEF_HV(1, 0));
 327         SR(VID_FIR_COEF_HV(1, 1));
 328         SR(VID_FIR_COEF_HV(1, 2));
 329         SR(VID_FIR_COEF_HV(1, 3));
 330         SR(VID_FIR_COEF_HV(1, 4));
 331         SR(VID_FIR_COEF_HV(1, 5));
 332         SR(VID_FIR_COEF_HV(1, 6));
 333         SR(VID_FIR_COEF_HV(1, 7));
 334
 335         SR(VID_CONV_COEF(1, 0));
 336         SR(VID_CONV_COEF(1, 1));
 337         SR(VID_CONV_COEF(1, 2));
 338         SR(VID_CONV_COEF(1, 3));
 339         SR(VID_CONV_COEF(1, 4));
 340
 341         SR(VID_FIR_COEF_V(1, 0));
 342         SR(VID_FIR_COEF_V(1, 1));
 343         SR(VID_FIR_COEF_V(1, 2));
 344         SR(VID_FIR_COEF_V(1, 3));
 345         SR(VID_FIR_COEF_V(1, 4));
 346         SR(VID_FIR_COEF_V(1, 5));
 347         SR(VID_FIR_COEF_V(1, 6));
 348         SR(VID_FIR_COEF_V(1, 7));
 349
 350         SR(VID_PRELOAD(1));
 351 }
 352
 353 void dispc_restore_context(void)
 354 {
 355         RR(SYSCONFIG);
 356         /*RR(IRQENABLE);*/
 357         /*RR(CONTROL);*/
 358         RR(CONFIG);
 359         RR(DEFAULT_COLOR0);
 360         RR(DEFAULT_COLOR1);
 361         RR(TRANS_COLOR0);
 362         RR(TRANS_COLOR1);
 363         RR(LINE_NUMBER);
 364         RR(TIMING_H);
 365         RR(TIMING_V);
 366         RR(POL_FREQ);
 367         RR(DIVISOR);
 368         RR(GLOBAL_ALPHA);
 369         RR(SIZE_DIG);
 370         RR(SIZE_LCD);
 371
 372         RR(GFX_BA0);
 373         RR(GFX_BA1);
 374         RR(GFX_POSITION);
 375         RR(GFX_SIZE);
 376         RR(GFX_ATTRIBUTES);
 377         RR(GFX_FIFO_THRESHOLD);
 378         RR(GFX_ROW_INC);
 379         RR(GFX_PIXEL_INC);
 380         RR(GFX_WINDOW_SKIP);
 381         RR(GFX_TABLE_BA);
 382
 383         RR(DATA_CYCLE1);
 384         RR(DATA_CYCLE2);
 385         RR(DATA_CYCLE3);
 386
 387         RR(CPR_COEF_R);
 388         RR(CPR_COEF_G);
 389         RR(CPR_COEF_B);
 390
 391         RR(GFX_PRELOAD);
 392
 393         /* VID1 */
 394         RR(VID_BA0(0));
 395         RR(VID_BA1(0));
 396         RR(VID_POSITION(0));
 397         RR(VID_SIZE(0));
 398         RR(VID_ATTRIBUTES(0));
 399         RR(VID_FIFO_THRESHOLD(0));
 400         RR(VID_ROW_INC(0));
 401         RR(VID_PIXEL_INC(0));
 402         RR(VID_FIR(0));
 403         RR(VID_PICTURE_SIZE(0));
 404         RR(VID_ACCU0(0));
 405         RR(VID_ACCU1(0));
 406
 407         RR(VID_FIR_COEF_H(0, 0));
 408         RR(VID_FIR_COEF_H(0, 1));
 409         RR(VID_FIR_COEF_H(0, 2));
 410         RR(VID_FIR_COEF_H(0, 3));
 411         RR(VID_FIR_COEF_H(0, 4));
 412         RR(VID_FIR_COEF_H(0, 5));
 413         RR(VID_FIR_COEF_H(0, 6));
 414         RR(VID_FIR_COEF_H(0, 7));
 415
 416         RR(VID_FIR_COEF_HV(0, 0));
 417         RR(VID_FIR_COEF_HV(0, 1));
 418         RR(VID_FIR_COEF_HV(0, 2));
 419         RR(VID_FIR_COEF_HV(0, 3));
 420         RR(VID_FIR_COEF_HV(0, 4));
 421         RR(VID_FIR_COEF_HV(0, 5));
 422         RR(VID_FIR_COEF_HV(0, 6));
 423         RR(VID_FIR_COEF_HV(0, 7));
 424
 425         RR(VID_CONV_COEF(0, 0));
 426         RR(VID_CONV_COEF(0, 1));
 427         RR(VID_CONV_COEF(0, 2));
 428         RR(VID_CONV_COEF(0, 3));
 429         RR(VID_CONV_COEF(0, 4));
 430
 431         RR(VID_FIR_COEF_V(0, 0));
 432         RR(VID_FIR_COEF_V(0, 1));
 433         RR(VID_FIR_COEF_V(0, 2));
 434         RR(VID_FIR_COEF_V(0, 3));
 435         RR(VID_FIR_COEF_V(0, 4));
 436         RR(VID_FIR_COEF_V(0, 5));
 437         RR(VID_FIR_COEF_V(0, 6));
 438         RR(VID_FIR_COEF_V(0, 7));
 439
 440         RR(VID_PRELOAD(0));
 441
 442         /* VID2 */
 443         RR(VID_BA0(1));
 444         RR(VID_BA1(1));
 445         RR(VID_POSITION(1));
 446         RR(VID_SIZE(1));
 447         RR(VID_ATTRIBUTES(1));
 448         RR(VID_FIFO_THRESHOLD(1));
 449         RR(VID_ROW_INC(1));
 450         RR(VID_PIXEL_INC(1));
 451         RR(VID_FIR(1));
 452         RR(VID_PICTURE_SIZE(1));
 453         RR(VID_ACCU0(1));
 454         RR(VID_ACCU1(1));
 455
 456         RR(VID_FIR_COEF_H(1, 0));
 457         RR(VID_FIR_COEF_H(1, 1));
 458         RR(VID_FIR_COEF_H(1, 2));
 459         RR(VID_FIR_COEF_H(1, 3));
 460         RR(VID_FIR_COEF_H(1, 4));
 461         RR(VID_FIR_COEF_H(1, 5));
 462         RR(VID_FIR_COEF_H(1, 6));
 463         RR(VID_FIR_COEF_H(1, 7));
 464
 465         RR(VID_FIR_COEF_HV(1, 0));
 466         RR(VID_FIR_COEF_HV(1, 1));
 467         RR(VID_FIR_COEF_HV(1, 2));
 468         RR(VID_FIR_COEF_HV(1, 3));
 469         RR(VID_FIR_COEF_HV(1, 4));
 470         RR(VID_FIR_COEF_HV(1, 5));
 471         RR(VID_FIR_COEF_HV(1, 6));
 472         RR(VID_FIR_COEF_HV(1, 7));
 473
 474         RR(VID_CONV_COEF(1, 0));
 475         RR(VID_CONV_COEF(1, 1));
 476         RR(VID_CONV_COEF(1, 2));
 477         RR(VID_CONV_COEF(1, 3));
 478         RR(VID_CONV_COEF(1, 4));
 479
 480         RR(VID_FIR_COEF_V(1, 0));
 481         RR(VID_FIR_COEF_V(1, 1));
 482         RR(VID_FIR_COEF_V(1, 2));
 483         RR(VID_FIR_COEF_V(1, 3));
 484         RR(VID_FIR_COEF_V(1, 4));
 485         RR(VID_FIR_COEF_V(1, 5));
 486         RR(VID_FIR_COEF_V(1, 6));
 487         RR(VID_FIR_COEF_V(1, 7));
 488
 489         RR(VID_PRELOAD(1));
 490
 491         /* enable last, because LCD & DIGIT enable are here */
 492         RR(CONTROL);
 493
 494         /* clear spurious SYNC_LOST_DIGIT interrupts */
 495         dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
 496
 497         /*
 498          * enable last so IRQs won't trigger before
 499          * the context is fully restored
 500          */
 501         RR(IRQENABLE);
 502 }
 503
 504 #undef SR
 505 #undef RR
 506
 507 static inline void enable_clocks(bool enable)
 508 {
 509         if (enable)
 510                 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
 511         else
 512                 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
 513 }
 514
 515 bool dispc_go_busy(enum omap_channel channel)
 516 {
 517         int bit;
 518
 519         if (channel == OMAP_DSS_CHANNEL_LCD)
 520                 bit = 5; /* GOLCD */
 521         else
 522                 bit = 6; /* GODIGIT */
 523
 524         return REG_GET(DISPC_CONTROL, bit, bit) == 1;
 525 }
 526
 527 void dispc_go(enum omap_channel channel)
 528 {
 529         int bit;
 530
 531         enable_clocks(1);
 532
 533         if (channel == OMAP_DSS_CHANNEL_LCD)
 534                 bit = 0; /* LCDENABLE */
 535         else
 536                 bit = 1; /* DIGITALENABLE */
 537
 538         /* if the channel is not enabled, we don't need GO */
 539         if (REG_GET(DISPC_CONTROL, bit, bit) == 0)
 540                 goto end;
 541
 542         if (channel == OMAP_DSS_CHANNEL_LCD)
 543                 bit = 5; /* GOLCD */
 544         else
 545                 bit = 6; /* GODIGIT */
 546
 547         if (REG_GET(DISPC_CONTROL, bit, bit) == 1) {
 548                 DSSERR("GO bit not down for channel %d\n", channel);
 549                 goto end;
 550         }
 551
 552         DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" : "DIGIT");
 553
 554         REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
 555 end:
 556         enable_clocks(0);
 557 }
 558
 559 static void _dispc_write_firh_reg(enum omap_plane plane, int reg, u32 value)
 560 {
 561         BUG_ON(plane == OMAP_DSS_GFX);
 562
 563         dispc_write_reg(DISPC_VID_FIR_COEF_H(plane-1, reg), value);
 564 }
 565
 566 static void _dispc_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
 567 {
 568         BUG_ON(plane == OMAP_DSS_GFX);
 569
 570         dispc_write_reg(DISPC_VID_FIR_COEF_HV(plane-1, reg), value);
 571 }
 572
 573 static void _dispc_write_firv_reg(enum omap_plane plane, int reg, u32 value)
 574 {
 575         BUG_ON(plane == OMAP_DSS_GFX);
 576
 577         dispc_write_reg(DISPC_VID_FIR_COEF_V(plane-1, reg), value);
 578 }
 579
 580 static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup,
 581                 int vscaleup, int five_taps)
 582 {
 583         /* Coefficients for horizontal up-sampling */
 584         static const struct dispc_h_coef coef_hup[8] = {
 585                 {  0,   0, 128,   0,  0 },
 586                 { -1,  13, 124,  -8,  0 },
 587                 { -2,  30, 112, -11, -1 },
 588                 { -5,  51,  95, -11, -2 },
 589                 {  0,  -9,  73,  73, -9 },
 590                 { -2, -11,  95,  51, -5 },
 591                 { -1, -11, 112,  30, -2 },
 592                 {  0,  -8, 124,  13, -1 },
 593         };
 594
 595         /* Coefficients for vertical up-sampling */
 596         static const struct dispc_v_coef coef_vup_3tap[8] = {
 597                 { 0,  0, 128,  0, 0 },
 598                 { 0,  3, 123,  2, 0 },
 599                 { 0, 12, 111,  5, 0 },
 600                 { 0, 32,  89,  7, 0 },
 601                 { 0,  0,  64, 64, 0 },
 602                 { 0,  7,  89, 32, 0 },
 603                 { 0,  5, 111, 12, 0 },
 604                 { 0,  2, 123,  3, 0 },
 605         };
 606
 607         static const struct dispc_v_coef coef_vup_5tap[8] = {
 608                 {  0,   0, 128,   0,  0 },
 609                 { -1,  13, 124,  -8,  0 },
 610                 { -2,  30, 112, -11, -1 },
 611                 { -5,  51,  95, -11, -2 },
 612                 {  0,  -9,  73,  73, -9 },
 613                 { -2, -11,  95,  51, -5 },
 614                 { -1, -11, 112,  30, -2 },
 615                 {  0,  -8, 124,  13, -1 },
 616         };
 617
 618         /* Coefficients for horizontal down-sampling */
 619         static const struct dispc_h_coef coef_hdown[8] = {
 620                 {   0, 36, 56, 36,  0 },
 621                 {   4, 40, 55, 31, -2 },
 622                 {   8, 44, 54, 27, -5 },
 623                 {  12, 48, 53, 22, -7 },
 624                 {  -9, 17, 52, 51, 17 },
 625                 {  -7, 22, 53, 48, 12 },
 626                 {  -5, 27, 54, 44,  8 },
 627                 {  -2, 31, 55, 40,  4 },
 628         };
 629
 630         /* Coefficients for vertical down-sampling */
 631         static const struct dispc_v_coef coef_vdown_3tap[8] = {
 632                 { 0, 36, 56, 36, 0 },
 633                 { 0, 40, 57, 31, 0 },
 634                 { 0, 45, 56, 27, 0 },
 635                 { 0, 50, 55, 23, 0 },
 636                 { 0, 18, 55, 55, 0 },
 637                 { 0, 23, 55, 50, 0 },
 638                 { 0, 27, 56, 45, 0 },
 639                 { 0, 31, 57, 40, 0 },
 640         };
 641
 642         static const struct dispc_v_coef coef_vdown_5tap[8] = {
 643                 {   0, 36, 56, 36,  0 },
 644                 {   4, 40, 55, 31, -2 },
 645                 {   8, 44, 54, 27, -5 },
 646                 {  12, 48, 53, 22, -7 },
 647                 {  -9, 17, 52, 51, 17 },
 648                 {  -7, 22, 53, 48, 12 },
 649                 {  -5, 27, 54, 44,  8 },
 650                 {  -2, 31, 55, 40,  4 },
 651         };
 652
 653         const struct dispc_h_coef *h_coef;
 654         const struct dispc_v_coef *v_coef;
 655         int i;
 656
 657         if (hscaleup)
 658                 h_coef = coef_hup;
 659         else
 660                 h_coef = coef_hdown;
 661
 662         if (vscaleup)
 663                 v_coef = five_taps ? coef_vup_5tap : coef_vup_3tap;
 664         else
 665                 v_coef = five_taps ? coef_vdown_5tap : coef_vdown_3tap;
 666
 667         for (i = 0; i < 8; i++) {
 668                 u32 h, hv;
 669
 670                 h = FLD_VAL(h_coef[i].hc0, 7, 0)
 671                         | FLD_VAL(h_coef[i].hc1, 15, 8)
 672                         | FLD_VAL(h_coef[i].hc2, 23, 16)
 673                         | FLD_VAL(h_coef[i].hc3, 31, 24);
 674                 hv = FLD_VAL(h_coef[i].hc4, 7, 0)
 675                         | FLD_VAL(v_coef[i].vc0, 15, 8)
 676                         | FLD_VAL(v_coef[i].vc1, 23, 16)
 677                         | FLD_VAL(v_coef[i].vc2, 31, 24);
 678
 679                 _dispc_write_firh_reg(plane, i, h);
 680                 _dispc_write_firhv_reg(plane, i, hv);
 681         }
 682
 683         if (five_taps) {
 684                 for (i = 0; i < 8; i++) {
 685                         u32 v;
 686                         v = FLD_VAL(v_coef[i].vc00, 7, 0)
 687                                 | FLD_VAL(v_coef[i].vc22, 15, 8);
 688                         _dispc_write_firv_reg(plane, i, v);
 689                 }
 690         }
 691 }
 692
 693 static void _dispc_setup_color_conv_coef(void)
 694 {
 695         const struct color_conv_coef {
 696                 int  ry,  rcr,  rcb,   gy,  gcr,  gcb,   by,  bcr,  bcb;
 697                 int  full_range;
 698         }  ctbl_bt601_5 = {
 699                 298,  409,    0,  298, -208, -100,  298,    0,  517, 0,
 700         };
 701
 702         const struct color_conv_coef *ct;
 703
 704 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
 705
 706         ct = &ctbl_bt601_5;
 707
 708         dispc_write_reg(DISPC_VID_CONV_COEF(0, 0), CVAL(ct->rcr, ct->ry));
 709         dispc_write_reg(DISPC_VID_CONV_COEF(0, 1), CVAL(ct->gy,  ct->rcb));
 710         dispc_write_reg(DISPC_VID_CONV_COEF(0, 2), CVAL(ct->gcb, ct->gcr));
 711         dispc_write_reg(DISPC_VID_CONV_COEF(0, 3), CVAL(ct->bcr, ct->by));
 712         dispc_write_reg(DISPC_VID_CONV_COEF(0, 4), CVAL(0,       ct->bcb));
 713
 714         dispc_write_reg(DISPC_VID_CONV_COEF(1, 0), CVAL(ct->rcr, ct->ry));
 715         dispc_write_reg(DISPC_VID_CONV_COEF(1, 1), CVAL(ct->gy,  ct->rcb));
 716         dispc_write_reg(DISPC_VID_CONV_COEF(1, 2), CVAL(ct->gcb, ct->gcr));
 717         dispc_write_reg(DISPC_VID_CONV_COEF(1, 3), CVAL(ct->bcr, ct->by));
 718         dispc_write_reg(DISPC_VID_CONV_COEF(1, 4), CVAL(0,       ct->bcb));
 719
 720 #undef CVAL
 721
 722         REG_FLD_MOD(DISPC_VID_ATTRIBUTES(0), ct->full_range, 11, 11);
 723         REG_FLD_MOD(DISPC_VID_ATTRIBUTES(1), ct->full_range, 11, 11);
 724 }
 725
 726
 727 static void _dispc_set_plane_ba0(enum omap_plane plane, u32 paddr)
 728 {
 729         const struct dispc_reg ba0_reg[] = { DISPC_GFX_BA0,
 730                 DISPC_VID_BA0(0),
 731                 DISPC_VID_BA0(1) };
 732
 733         dispc_write_reg(ba0_reg[plane], paddr);
 734 }
 735
 736 static void _dispc_set_plane_ba1(enum omap_plane plane, u32 paddr)
 737 {
 738         const struct dispc_reg ba1_reg[] = { DISPC_GFX_BA1,
 739                                       DISPC_VID_BA1(0),
 740                                       DISPC_VID_BA1(1) };
 741
 742         dispc_write_reg(ba1_reg[plane], paddr);
 743 }
 744
 745 static void _dispc_set_plane_pos(enum omap_plane plane, int x, int y)
 746 {
 747         const struct dispc_reg pos_reg[] = { DISPC_GFX_POSITION,
 748                                       DISPC_VID_POSITION(0),
 749                                       DISPC_VID_POSITION(1) };
 750
 751         u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
 752         dispc_write_reg(pos_reg[plane], val);
 753 }
 754
 755 static void _dispc_set_pic_size(enum omap_plane plane, int width, int height)
 756 {
 757         const struct dispc_reg siz_reg[] = { DISPC_GFX_SIZE,
 758                                       DISPC_VID_PICTURE_SIZE(0),
 759                                       DISPC_VID_PICTURE_SIZE(1) };
 760         u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 761         dispc_write_reg(siz_reg[plane], val);
 762 }
 763
 764 static void _dispc_set_vid_size(enum omap_plane plane, int width, int height)
 765 {
 766         u32 val;
 767         const struct dispc_reg vsi_reg[] = { DISPC_VID_SIZE(0),
 768                                       DISPC_VID_SIZE(1) };
 769
 770         BUG_ON(plane == OMAP_DSS_GFX);
 771
 772         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 773         dispc_write_reg(vsi_reg[plane-1], val);
 774 }
 775
 776 static void _dispc_set_pre_mult_alpha(enum omap_plane plane, bool enable)
 777 {
 778         if (!dss_has_feature(FEAT_PRE_MULT_ALPHA))
 779                 return;
 780
 781         if (!dss_has_feature(FEAT_GLOBAL_ALPHA_VID1) &&
 782                 plane == OMAP_DSS_VIDEO1)
 783                 return;
 784
 785         REG_FLD_MOD(dispc_reg_att[plane], enable ? 1 : 0, 28, 28);
 786 }
 787
 788 static void _dispc_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
 789 {
 790         if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
 791                 return;
 792
 793         if (!dss_has_feature(FEAT_GLOBAL_ALPHA_VID1) &&
 794                 plane == OMAP_DSS_VIDEO1)
 795                 return;
 796
 797         if (plane == OMAP_DSS_GFX)
 798                 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 7, 0);
 799         else if (plane == OMAP_DSS_VIDEO2)
 800                 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 23, 16);
 801 }
 802
 803 static void _dispc_set_pix_inc(enum omap_plane plane, s32 inc)
 804 {
 805         const struct dispc_reg ri_reg[] = { DISPC_GFX_PIXEL_INC,
 806                                      DISPC_VID_PIXEL_INC(0),
 807                                      DISPC_VID_PIXEL_INC(1) };
 808
 809         dispc_write_reg(ri_reg[plane], inc);
 810 }
 811
 812 static void _dispc_set_row_inc(enum omap_plane plane, s32 inc)
 813 {
 814         const struct dispc_reg ri_reg[] = { DISPC_GFX_ROW_INC,
 815                                      DISPC_VID_ROW_INC(0),
 816                                      DISPC_VID_ROW_INC(1) };
 817
 818         dispc_write_reg(ri_reg[plane], inc);
 819 }
 820
 821 static void _dispc_set_color_mode(enum omap_plane plane,
 822                 enum omap_color_mode color_mode)
 823 {
 824         u32 m = 0;
 825
 826         switch (color_mode) {
 827         case OMAP_DSS_COLOR_CLUT1:
 828                 m = 0x0; break;
 829         case OMAP_DSS_COLOR_CLUT2:
 830                 m = 0x1; break;
 831         case OMAP_DSS_COLOR_CLUT4:
 832                 m = 0x2; break;
 833         case OMAP_DSS_COLOR_CLUT8:
 834                 m = 0x3; break;
 835         case OMAP_DSS_COLOR_RGB12U:
 836                 m = 0x4; break;
 837         case OMAP_DSS_COLOR_ARGB16:
 838                 m = 0x5; break;
 839         case OMAP_DSS_COLOR_RGB16:
 840                 m = 0x6; break;
 841         case OMAP_DSS_COLOR_RGB24U:
 842                 m = 0x8; break;
 843         case OMAP_DSS_COLOR_RGB24P:
 844                 m = 0x9; break;
 845         case OMAP_DSS_COLOR_YUV2:
 846                 m = 0xa; break;
 847         case OMAP_DSS_COLOR_UYVY:
 848                 m = 0xb; break;
 849         case OMAP_DSS_COLOR_ARGB32:
 850                 m = 0xc; break;
 851         case OMAP_DSS_COLOR_RGBA32:
 852                 m = 0xd; break;
 853         case OMAP_DSS_COLOR_RGBX32:
 854                 m = 0xe; break;
 855         default:
 856                 BUG(); break;
 857         }
 858
 859         REG_FLD_MOD(dispc_reg_att[plane], m, 4, 1);
 860 }
 861
 862 static void _dispc_set_channel_out(enum omap_plane plane,
 863                 enum omap_channel channel)
 864 {
 865         int shift;
 866         u32 val;
 867
 868         switch (plane) {
 869         case OMAP_DSS_GFX:
 870                 shift = 8;
 871                 break;
 872         case OMAP_DSS_VIDEO1:
 873         case OMAP_DSS_VIDEO2:
 874                 shift = 16;
 875                 break;
 876         default:
 877                 BUG();
 878                 return;
 879         }
 880
 881         val = dispc_read_reg(dispc_reg_att[plane]);
 882         val = FLD_MOD(val, channel, shift, shift);
 883         dispc_write_reg(dispc_reg_att[plane], val);
 884 }
 885
 886 void dispc_set_burst_size(enum omap_plane plane,
 887                 enum omap_burst_size burst_size)
 888 {
 889         int shift;
 890         u32 val;
 891
 892         enable_clocks(1);
 893
 894         switch (plane) {
 895         case OMAP_DSS_GFX:
 896                 shift = 6;
 897                 break;
 898         case OMAP_DSS_VIDEO1:
 899         case OMAP_DSS_VIDEO2:
 900                 shift = 14;
 901                 break;
 902         default:
 903                 BUG();
 904                 return;
 905         }
 906
 907         val = dispc_read_reg(dispc_reg_att[plane]);
 908         val = FLD_MOD(val, burst_size, shift+1, shift);
 909         dispc_write_reg(dispc_reg_att[plane], val);
 910
 911         enable_clocks(0);
 912 }
 913
 914 static void _dispc_set_vid_color_conv(enum omap_plane plane, bool enable)
 915 {
 916         u32 val;
 917
 918         BUG_ON(plane == OMAP_DSS_GFX);
 919
 920         val = dispc_read_reg(dispc_reg_att[plane]);
 921         val = FLD_MOD(val, enable, 9, 9);
 922         dispc_write_reg(dispc_reg_att[plane], val);
 923 }
 924
 925 void dispc_enable_replication(enum omap_plane plane, bool enable)
 926 {
 927         int bit;
 928
 929         if (plane == OMAP_DSS_GFX)
 930                 bit = 5;
 931         else
 932                 bit = 10;
 933
 934         enable_clocks(1);
 935         REG_FLD_MOD(dispc_reg_att[plane], enable, bit, bit);
 936         enable_clocks(0);
 937 }
 938
 939 void dispc_set_lcd_size(u16 width, u16 height)
 940 {
 941         u32 val;
 942         BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
 943         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 944         enable_clocks(1);
 945         dispc_write_reg(DISPC_SIZE_LCD, val);
 946         enable_clocks(0);
 947 }
 948
 949 void dispc_set_digit_size(u16 width, u16 height)
 950 {
 951         u32 val;
 952         BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
 953         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 954         enable_clocks(1);
 955         dispc_write_reg(DISPC_SIZE_DIG, val);
 956         enable_clocks(0);
 957 }
 958
 959 static void dispc_read_plane_fifo_sizes(void)
 960 {
 961         const struct dispc_reg fsz_reg[] = { DISPC_GFX_FIFO_SIZE_STATUS,
 962                                       DISPC_VID_FIFO_SIZE_STATUS(0),
 963                                       DISPC_VID_FIFO_SIZE_STATUS(1) };
 964         u32 size;
 965         int plane;
 966         u8 start, end;
 967
 968         enable_clocks(1);
 969
 970         dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
 971
 972         for (plane = 0; plane < ARRAY_SIZE(dispc.fifo_size); ++plane) {
 973                 size = FLD_GET(dispc_read_reg(fsz_reg[plane]), start, end);
 974                 dispc.fifo_size[plane] = size;
 975         }
 976
 977         enable_clocks(0);
 978 }
 979
 980 u32 dispc_get_plane_fifo_size(enum omap_plane plane)
 981 {
 982         return dispc.fifo_size[plane];
 983 }
 984
 985 void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high)
 986 {
 987         const struct dispc_reg ftrs_reg[] = { DISPC_GFX_FIFO_THRESHOLD,
 988                                        DISPC_VID_FIFO_THRESHOLD(0),
 989                                        DISPC_VID_FIFO_THRESHOLD(1) };
 990         u8 hi_start, hi_end, lo_start, lo_end;
 991
 992         enable_clocks(1);
 993
 994         DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n",
 995                         plane,
 996                         REG_GET(ftrs_reg[plane], 11, 0),
 997                         REG_GET(ftrs_reg[plane], 27, 16),
 998                         low, high);
 999
1000         dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1001         dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1002
1003         dispc_write_reg(ftrs_reg[plane],
1004                         FLD_VAL(high, hi_start, hi_end) |
1005                         FLD_VAL(low, lo_start, lo_end));
1006
1007         enable_clocks(0);
1008 }
1009
1010 void dispc_enable_fifomerge(bool enable)
1011 {
1012         enable_clocks(1);
1013
1014         DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1015         REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1016
1017         enable_clocks(0);
1018 }
1019
1020 static void _dispc_set_fir(enum omap_plane plane, int hinc, int vinc)
1021 {
1022         u32 val;
1023         const struct dispc_reg fir_reg[] = { DISPC_VID_FIR(0),
1024                                       DISPC_VID_FIR(1) };
1025         u8 hinc_start, hinc_end, vinc_start, vinc_end;
1026
1027         BUG_ON(plane == OMAP_DSS_GFX);
1028
1029         dss_feat_get_reg_field(FEAT_REG_FIRHINC, &hinc_start, &hinc_end);
1030         dss_feat_get_reg_field(FEAT_REG_FIRVINC, &vinc_start, &vinc_end);
1031
1032         val = FLD_VAL(vinc, vinc_start, vinc_end) |
1033                         FLD_VAL(hinc, hinc_start, hinc_end);
1034
1035         dispc_write_reg(fir_reg[plane-1], val);
1036 }
1037
1038 static void _dispc_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1039 {
1040         u32 val;
1041         const struct dispc_reg ac0_reg[] = { DISPC_VID_ACCU0(0),
1042                                       DISPC_VID_ACCU0(1) };
1043
1044         BUG_ON(plane == OMAP_DSS_GFX);
1045
1046         val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
1047         dispc_write_reg(ac0_reg[plane-1], val);
1048 }
1049
1050 static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1051 {
1052         u32 val;
1053         const struct dispc_reg ac1_reg[] = { DISPC_VID_ACCU1(0),
1054                                       DISPC_VID_ACCU1(1) };
1055
1056         BUG_ON(plane == OMAP_DSS_GFX);
1057
1058         val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
1059         dispc_write_reg(ac1_reg[plane-1], val);
1060 }
1061
1062
1063 static void _dispc_set_scaling(enum omap_plane plane,
1064                 u16 orig_width, u16 orig_height,
1065                 u16 out_width, u16 out_height,
1066                 bool ilace, bool five_taps,
1067                 bool fieldmode)
1068 {
1069         int fir_hinc;
1070         int fir_vinc;
1071         int hscaleup, vscaleup;
1072         int accu0 = 0;
1073         int accu1 = 0;
1074         u32 l;
1075
1076         BUG_ON(plane == OMAP_DSS_GFX);
1077
1078         hscaleup = orig_width <= out_width;
1079         vscaleup = orig_height <= out_height;
1080
1081         _dispc_set_scale_coef(plane, hscaleup, vscaleup, five_taps);
1082
1083         if (!orig_width || orig_width == out_width)
1084                 fir_hinc = 0;
1085         else
1086                 fir_hinc = 1024 * orig_width / out_width;
1087
1088         if (!orig_height || orig_height == out_height)
1089                 fir_vinc = 0;
1090         else
1091                 fir_vinc = 1024 * orig_height / out_height;
1092
1093         _dispc_set_fir(plane, fir_hinc, fir_vinc);
1094
1095         l = dispc_read_reg(dispc_reg_att[plane]);
1096         l &= ~((0x0f << 5) | (0x3 << 21));
1097
1098         l |= fir_hinc ? (1 << 5) : 0;
1099         l |= fir_vinc ? (1 << 6) : 0;
1100
1101         l |= hscaleup ? 0 : (1 << 7);
1102         l |= vscaleup ? 0 : (1 << 8);
1103
1104         l |= five_taps ? (1 << 21) : 0;
1105         l |= five_taps ? (1 << 22) : 0;
1106
1107         dispc_write_reg(dispc_reg_att[plane], l);
1108
1109         /*
1110          * field 0 = even field = bottom field
1111          * field 1 = odd field = top field
1112          */
1113         if (ilace && !fieldmode) {
1114                 accu1 = 0;
1115                 accu0 = (fir_vinc / 2) & 0x3ff;
1116                 if (accu0 >= 1024/2) {
1117                         accu1 = 1024/2;
1118                         accu0 -= accu1;
1119                 }
1120         }
1121
1122         _dispc_set_vid_accu0(plane, 0, accu0);
1123         _dispc_set_vid_accu1(plane, 0, accu1);
1124 }
1125
1126 static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1127                 bool mirroring, enum omap_color_mode color_mode)
1128 {
1129         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1130                         color_mode == OMAP_DSS_COLOR_UYVY) {
1131                 int vidrot = 0;
1132
1133                 if (mirroring) {
1134                         switch (rotation) {
1135                         case OMAP_DSS_ROT_0:
1136                                 vidrot = 2;
1137                                 break;
1138                         case OMAP_DSS_ROT_90:
1139                                 vidrot = 1;
1140                                 break;
1141                         case OMAP_DSS_ROT_180:
1142                                 vidrot = 0;
1143                                 break;
1144                         case OMAP_DSS_ROT_270:
1145                                 vidrot = 3;
1146                                 break;
1147                         }
1148                 } else {
1149                         switch (rotation) {
1150                         case OMAP_DSS_ROT_0:
1151                                 vidrot = 0;
1152                                 break;
1153                         case OMAP_DSS_ROT_90:
1154                                 vidrot = 1;
1155                                 break;
1156                         case OMAP_DSS_ROT_180:
1157                                 vidrot = 2;
1158                                 break;
1159                         case OMAP_DSS_ROT_270:
1160                                 vidrot = 3;
1161                                 break;
1162                         }
1163                 }
1164
1165                 REG_FLD_MOD(dispc_reg_att[plane], vidrot, 13, 12);
1166
1167                 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1168                         REG_FLD_MOD(dispc_reg_att[plane], 0x1, 18, 18);
1169                 else
1170                         REG_FLD_MOD(dispc_reg_att[plane], 0x0, 18, 18);
1171         } else {
1172                 REG_FLD_MOD(dispc_reg_att[plane], 0, 13, 12);
1173                 REG_FLD_MOD(dispc_reg_att[plane], 0, 18, 18);
1174         }
1175 }
1176
1177 static int color_mode_to_bpp(enum omap_color_mode color_mode)
1178 {
1179         switch (color_mode) {
1180         case OMAP_DSS_COLOR_CLUT1:
1181                 return 1;
1182         case OMAP_DSS_COLOR_CLUT2:
1183                 return 2;
1184         case OMAP_DSS_COLOR_CLUT4:
1185                 return 4;
1186         case OMAP_DSS_COLOR_CLUT8:
1187                 return 8;
1188         case OMAP_DSS_COLOR_RGB12U:
1189         case OMAP_DSS_COLOR_RGB16:
1190         case OMAP_DSS_COLOR_ARGB16:
1191         case OMAP_DSS_COLOR_YUV2:
1192         case OMAP_DSS_COLOR_UYVY:
1193                 return 16;
1194         case OMAP_DSS_COLOR_RGB24P:
1195                 return 24;
1196         case OMAP_DSS_COLOR_RGB24U:
1197         case OMAP_DSS_COLOR_ARGB32:
1198         case OMAP_DSS_COLOR_RGBA32:
1199         case OMAP_DSS_COLOR_RGBX32:
1200                 return 32;
1201         default:
1202                 BUG();
1203         }
1204 }
1205
1206 static s32 pixinc(int pixels, u8 ps)
1207 {
1208         if (pixels == 1)
1209                 return 1;
1210         else if (pixels > 1)
1211                 return 1 + (pixels - 1) * ps;
1212         else if (pixels < 0)
1213                 return 1 - (-pixels + 1) * ps;
1214         else
1215                 BUG();
1216 }
1217
1218 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1219                 u16 screen_width,
1220                 u16 width, u16 height,
1221                 enum omap_color_mode color_mode, bool fieldmode,
1222                 unsigned int field_offset,
1223                 unsigned *offset0, unsigned *offset1,
1224                 s32 *row_inc, s32 *pix_inc)
1225 {
1226         u8 ps;
1227
1228         /* FIXME CLUT formats */
1229         switch (color_mode) {
1230         case OMAP_DSS_COLOR_CLUT1:
1231         case OMAP_DSS_COLOR_CLUT2:
1232         case OMAP_DSS_COLOR_CLUT4:
1233         case OMAP_DSS_COLOR_CLUT8:
1234                 BUG();
1235                 return;
1236         case OMAP_DSS_COLOR_YUV2:
1237         case OMAP_DSS_COLOR_UYVY:
1238                 ps = 4;
1239                 break;
1240         default:
1241                 ps = color_mode_to_bpp(color_mode) / 8;
1242                 break;
1243         }
1244
1245         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1246                         width, height);
1247
1248         /*
1249          * field 0 = even field = bottom field
1250          * field 1 = odd field = top field
1251          */
1252         switch (rotation + mirror * 4) {
1253         case OMAP_DSS_ROT_0:
1254         case OMAP_DSS_ROT_180:
1255                 /*
1256                  * If the pixel format is YUV or UYVY divide the width
1257                  * of the image by 2 for 0 and 180 degree rotation.
1258                  */
1259                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1260                         color_mode == OMAP_DSS_COLOR_UYVY)
1261                         width = width >> 1;
1262         case OMAP_DSS_ROT_90:
1263         case OMAP_DSS_ROT_270:
1264                 *offset1 = 0;
1265                 if (field_offset)
1266                         *offset0 = field_offset * screen_width * ps;
1267                 else
1268                         *offset0 = 0;
1269
1270                 *row_inc = pixinc(1 + (screen_width - width) +
1271                                 (fieldmode ? screen_width : 0),
1272                                 ps);
1273                 *pix_inc = pixinc(1, ps);
1274                 break;
1275
1276         case OMAP_DSS_ROT_0 + 4:
1277         case OMAP_DSS_ROT_180 + 4:
1278                 /* If the pixel format is YUV or UYVY divide the width
1279                  * of the image by 2  for 0 degree and 180 degree
1280                  */
1281                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1282                         color_mode == OMAP_DSS_COLOR_UYVY)
1283                         width = width >> 1;
1284         case OMAP_DSS_ROT_90 + 4:
1285         case OMAP_DSS_ROT_270 + 4:
1286                 *offset1 = 0;
1287                 if (field_offset)
1288                         *offset0 = field_offset * screen_width * ps;
1289                 else
1290                         *offset0 = 0;
1291                 *row_inc = pixinc(1 - (screen_width + width) -
1292                                 (fieldmode ? screen_width : 0),
1293                                 ps);
1294                 *pix_inc = pixinc(1, ps);
1295                 break;
1296
1297         default:
1298                 BUG();
1299         }
1300 }
1301
1302 static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1303                 u16 screen_width,
1304                 u16 width, u16 height,
1305                 enum omap_color_mode color_mode, bool fieldmode,
1306                 unsigned int field_offset,
1307                 unsigned *offset0, unsigned *offset1,
1308                 s32 *row_inc, s32 *pix_inc)
1309 {
1310         u8 ps;
1311         u16 fbw, fbh;
1312
1313         /* FIXME CLUT formats */
1314         switch (color_mode) {
1315         case OMAP_DSS_COLOR_CLUT1:
1316         case OMAP_DSS_COLOR_CLUT2:
1317         case OMAP_DSS_COLOR_CLUT4:
1318         case OMAP_DSS_COLOR_CLUT8:
1319                 BUG();
1320                 return;
1321         default:
1322                 ps = color_mode_to_bpp(color_mode) / 8;
1323                 break;
1324         }
1325
1326         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1327                         width, height);
1328
1329         /* width & height are overlay sizes, convert to fb sizes */
1330
1331         if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1332                 fbw = width;
1333                 fbh = height;
1334         } else {
1335                 fbw = height;
1336                 fbh = width;
1337         }
1338
1339         /*
1340          * field 0 = even field = bottom field
1341          * field 1 = odd field = top field
1342          */
1343         switch (rotation + mirror * 4) {
1344         case OMAP_DSS_ROT_0:
1345                 *offset1 = 0;
1346                 if (field_offset)
1347                         *offset0 = *offset1 + field_offset * screen_width * ps;
1348                 else
1349                         *offset0 = *offset1;
1350                 *row_inc = pixinc(1 + (screen_width - fbw) +
1351                                 (fieldmode ? screen_width : 0),
1352                                 ps);
1353                 *pix_inc = pixinc(1, ps);
1354                 break;
1355         case OMAP_DSS_ROT_90:
1356                 *offset1 = screen_width * (fbh - 1) * ps;
1357                 if (field_offset)
1358                         *offset0 = *offset1 + field_offset * ps;
1359                 else
1360                         *offset0 = *offset1;
1361                 *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
1362                                 (fieldmode ? 1 : 0), ps);
1363                 *pix_inc = pixinc(-screen_width, ps);
1364                 break;
1365         case OMAP_DSS_ROT_180:
1366                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1367                 if (field_offset)
1368                         *offset0 = *offset1 - field_offset * screen_width * ps;
1369                 else
1370                         *offset0 = *offset1;
1371                 *row_inc = pixinc(-1 -
1372                                 (screen_width - fbw) -
1373                                 (fieldmode ? screen_width : 0),
1374                                 ps);
1375                 *pix_inc = pixinc(-1, ps);
1376                 break;
1377         case OMAP_DSS_ROT_270:
1378                 *offset1 = (fbw - 1) * ps;
1379                 if (field_offset)
1380                         *offset0 = *offset1 - field_offset * ps;
1381                 else
1382                         *offset0 = *offset1;
1383                 *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
1384                                 (fieldmode ? 1 : 0), ps);
1385                 *pix_inc = pixinc(screen_width, ps);
1386                 break;
1387
1388         /* mirroring */
1389         case OMAP_DSS_ROT_0 + 4:
1390                 *offset1 = (fbw - 1) * ps;
1391                 if (field_offset)
1392                         *offset0 = *offset1 + field_offset * screen_width * ps;
1393                 else
1394                         *offset0 = *offset1;
1395                 *row_inc = pixinc(screen_width * 2 - 1 +
1396                                 (fieldmode ? screen_width : 0),
1397                                 ps);
1398                 *pix_inc = pixinc(-1, ps);
1399                 break;
1400
1401         case OMAP_DSS_ROT_90 + 4:
1402                 *offset1 = 0;
1403                 if (field_offset)
1404                         *offset0 = *offset1 + field_offset * ps;
1405                 else
1406                         *offset0 = *offset1;
1407                 *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
1408                                 (fieldmode ? 1 : 0),
1409                                 ps);
1410                 *pix_inc = pixinc(screen_width, ps);
1411                 break;
1412
1413         case OMAP_DSS_ROT_180 + 4:
1414                 *offset1 = screen_width * (fbh - 1) * ps;
1415                 if (field_offset)
1416                         *offset0 = *offset1 - field_offset * screen_width * ps;
1417                 else
1418                         *offset0 = *offset1;
1419                 *row_inc = pixinc(1 - screen_width * 2 -
1420                                 (fieldmode ? screen_width : 0),
1421                                 ps);
1422                 *pix_inc = pixinc(1, ps);
1423                 break;
1424
1425         case OMAP_DSS_ROT_270 + 4:
1426                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1427                 if (field_offset)
1428                         *offset0 = *offset1 - field_offset * ps;
1429                 else
1430                         *offset0 = *offset1;
1431                 *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
1432                                 (fieldmode ? 1 : 0),
1433                                 ps);
1434                 *pix_inc = pixinc(-screen_width, ps);
1435                 break;
1436
1437         default:
1438                 BUG();
1439         }
1440 }
1441
1442 static unsigned long calc_fclk_five_taps(u16 width, u16 height,
1443                 u16 out_width, u16 out_height, enum omap_color_mode color_mode)
1444 {
1445         u32 fclk = 0;
1446         /* FIXME venc pclk? */
1447         u64 tmp, pclk = dispc_pclk_rate();
1448
1449         if (height > out_height) {
1450                 /* FIXME get real display PPL */
1451                 unsigned int ppl = 800;
1452
1453                 tmp = pclk * height * out_width;
1454                 do_div(tmp, 2 * out_height * ppl);
1455                 fclk = tmp;
1456
1457                 if (height > 2 * out_height) {
1458                         if (ppl == out_width)
1459                                 return 0;
1460
1461                         tmp = pclk * (height - 2 * out_height) * out_width;
1462                         do_div(tmp, 2 * out_height * (ppl - out_width));
1463                         fclk = max(fclk, (u32) tmp);
1464                 }
1465         }
1466
1467         if (width > out_width) {
1468                 tmp = pclk * width;
1469                 do_div(tmp, out_width);
1470                 fclk = max(fclk, (u32) tmp);
1471
1472                 if (color_mode == OMAP_DSS_COLOR_RGB24U)
1473                         fclk <<= 1;
1474         }
1475
1476         return fclk;
1477 }
1478
1479 static unsigned long calc_fclk(u16 width, u16 height,
1480                 u16 out_width, u16 out_height)
1481 {
1482         unsigned int hf, vf;
1483
1484         /*
1485          * FIXME how to determine the 'A' factor
1486          * for the no downscaling case ?
1487          */
1488
1489         if (width > 3 * out_width)
1490                 hf = 4;
1491         else if (width > 2 * out_width)
1492                 hf = 3;
1493         else if (width > out_width)
1494                 hf = 2;
1495         else
1496                 hf = 1;
1497
1498         if (height > out_height)
1499                 vf = 2;
1500         else
1501                 vf = 1;
1502
1503         /* FIXME venc pclk? */
1504         return dispc_pclk_rate() * vf * hf;
1505 }
1506
1507 void dispc_set_channel_out(enum omap_plane plane, enum omap_channel channel_out)
1508 {
1509         enable_clocks(1);
1510         _dispc_set_channel_out(plane, channel_out);
1511         enable_clocks(0);
1512 }
1513
1514 static int _dispc_setup_plane(enum omap_plane plane,
1515                 u32 paddr, u16 screen_width,
1516                 u16 pos_x, u16 pos_y,
1517                 u16 width, u16 height,
1518                 u16 out_width, u16 out_height,
1519                 enum omap_color_mode color_mode,
1520                 bool ilace,
1521                 enum omap_dss_rotation_type rotation_type,
1522                 u8 rotation, int mirror,
1523                 u8 global_alpha,
1524                 u8 pre_mult_alpha)
1525 {
1526         const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
1527         bool five_taps = 0;
1528         bool fieldmode = 0;
1529         int cconv = 0;
1530         unsigned offset0, offset1;
1531         s32 row_inc;
1532         s32 pix_inc;
1533         u16 frame_height = height;
1534         unsigned int field_offset = 0;
1535
1536         if (paddr == 0)
1537                 return -EINVAL;
1538
1539         if (ilace && height == out_height)
1540                 fieldmode = 1;
1541
1542         if (ilace) {
1543                 if (fieldmode)
1544                         height /= 2;
1545                 pos_y /= 2;
1546                 out_height /= 2;
1547
1548                 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
1549                                 "out_height %d\n",
1550                                 height, pos_y, out_height);
1551         }
1552
1553         if (!dss_feat_color_mode_supported(plane, color_mode))
1554                 return -EINVAL;
1555
1556         if (plane == OMAP_DSS_GFX) {
1557                 if (width != out_width || height != out_height)
1558                         return -EINVAL;
1559         } else {
1560                 /* video plane */
1561
1562                 unsigned long fclk = 0;
1563
1564                 if (out_width < width / maxdownscale ||
1565                    out_width > width * 8)
1566                         return -EINVAL;
1567
1568                 if (out_height < height / maxdownscale ||
1569                    out_height > height * 8)
1570                         return -EINVAL;
1571
1572                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1573                         color_mode == OMAP_DSS_COLOR_UYVY)
1574                         cconv = 1;
1575
1576                 /* Must use 5-tap filter? */
1577                 five_taps = height > out_height * 2;
1578
1579                 if (!five_taps) {
1580                         fclk = calc_fclk(width, height,
1581                                         out_width, out_height);
1582
1583                         /* Try 5-tap filter if 3-tap fclk is too high */
1584                         if (cpu_is_omap34xx() && height > out_height &&
1585                                         fclk > dispc_fclk_rate())
1586                                 five_taps = true;
1587                 }
1588
1589                 if (width > (2048 >> five_taps)) {
1590                         DSSERR("failed to set up scaling, fclk too low\n");
1591                         return -EINVAL;
1592                 }
1593
1594                 if (five_taps)
1595                         fclk = calc_fclk_five_taps(width, height,
1596                                         out_width, out_height, color_mode);
1597
1598                 DSSDBG("required fclk rate = %lu Hz\n", fclk);
1599                 DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
1600
1601                 if (!fclk || fclk > dispc_fclk_rate()) {
1602                         DSSERR("failed to set up scaling, "
1603                                         "required fclk rate = %lu Hz, "
1604                                         "current fclk rate = %lu Hz\n",
1605                                         fclk, dispc_fclk_rate());
1606                         return -EINVAL;
1607                 }
1608         }
1609
1610         if (ilace && !fieldmode) {
1611                 /*
1612                  * when downscaling the bottom field may have to start several
1613                  * source lines below the top field. Unfortunately ACCUI
1614                  * registers will only hold the fractional part of the offset
1615                  * so the integer part must be added to the base address of the
1616                  * bottom field.
1617                  */
1618                 if (!height || height == out_height)
1619                         field_offset = 0;
1620                 else
1621                         field_offset = height / out_height / 2;
1622         }
1623
1624         /* Fields are independent but interleaved in memory. */
1625         if (fieldmode)
1626                 field_offset = 1;
1627
1628         if (rotation_type == OMAP_DSS_ROT_DMA)
1629                 calc_dma_rotation_offset(rotation, mirror,
1630                                 screen_width, width, frame_height, color_mode,
1631                                 fieldmode, field_offset,
1632                                 &offset0, &offset1, &row_inc, &pix_inc);
1633         else
1634                 calc_vrfb_rotation_offset(rotation, mirror,
1635                                 screen_width, width, frame_height, color_mode,
1636                                 fieldmode, field_offset,
1637                                 &offset0, &offset1, &row_inc, &pix_inc);
1638
1639         DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
1640                         offset0, offset1, row_inc, pix_inc);
1641
1642         _dispc_set_color_mode(plane, color_mode);
1643
1644         _dispc_set_plane_ba0(plane, paddr + offset0);
1645         _dispc_set_plane_ba1(plane, paddr + offset1);
1646
1647         _dispc_set_row_inc(plane, row_inc);
1648         _dispc_set_pix_inc(plane, pix_inc);
1649
1650         DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, width, height,
1651                         out_width, out_height);
1652
1653         _dispc_set_plane_pos(plane, pos_x, pos_y);
1654
1655         _dispc_set_pic_size(plane, width, height);
1656
1657         if (plane != OMAP_DSS_GFX) {
1658                 _dispc_set_scaling(plane, width, height,
1659                                    out_width, out_height,
1660                                    ilace, five_taps, fieldmode);
1661                 _dispc_set_vid_size(plane, out_width, out_height);
1662                 _dispc_set_vid_color_conv(plane, cconv);
1663         }
1664
1665         _dispc_set_rotation_attrs(plane, rotation, mirror, color_mode);
1666
1667         _dispc_set_pre_mult_alpha(plane, pre_mult_alpha);
1668         _dispc_setup_global_alpha(plane, global_alpha);
1669
1670         return 0;
1671 }
1672
1673 static void _dispc_enable_plane(enum omap_plane plane, bool enable)
1674 {
1675         REG_FLD_MOD(dispc_reg_att[plane], enable ? 1 : 0, 0, 0);
1676 }
1677
1678 static void dispc_disable_isr(void *data, u32 mask)
1679 {
1680         struct completion *compl = data;
1681         complete(compl);
1682 }
1683
1684 static void _enable_lcd_out(bool enable)
1685 {
1686         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
1687 }
1688
1689 static void dispc_enable_lcd_out(bool enable)
1690 {
1691         struct completion frame_done_completion;
1692         bool is_on;
1693         int r;
1694
1695         enable_clocks(1);
1696
1697         /* When we disable LCD output, we need to wait until frame is done.
1698          * Otherwise the DSS is still working, and turning off the clocks
1699          * prevents DSS from going to OFF mode */
1700         is_on = REG_GET(DISPC_CONTROL, 0, 0);
1701
1702         if (!enable && is_on) {
1703                 init_completion(&frame_done_completion);
1704
1705                 r = omap_dispc_register_isr(dispc_disable_isr,
1706                                 &frame_done_completion,
1707                                 DISPC_IRQ_FRAMEDONE);
1708
1709                 if (r)
1710                         DSSERR("failed to register FRAMEDONE isr\n");
1711         }
1712
1713         _enable_lcd_out(enable);
1714
1715         if (!enable && is_on) {
1716                 if (!wait_for_completion_timeout(&frame_done_completion,
1717                                         msecs_to_jiffies(100)))
1718                         DSSERR("timeout waiting for FRAME DONE\n");
1719
1720                 r = omap_dispc_unregister_isr(dispc_disable_isr,
1721                                 &frame_done_completion,
1722                                 DISPC_IRQ_FRAMEDONE);
1723
1724                 if (r)
1725                         DSSERR("failed to unregister FRAMEDONE isr\n");
1726         }
1727
1728         enable_clocks(0);
1729 }
1730
1731 static void _enable_digit_out(bool enable)
1732 {
1733         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
1734 }
1735
1736 static void dispc_enable_digit_out(bool enable)
1737 {
1738         struct completion frame_done_completion;
1739         int r;
1740
1741         enable_clocks(1);
1742
1743         if (REG_GET(DISPC_CONTROL, 1, 1) == enable) {
1744                 enable_clocks(0);
1745                 return;
1746         }
1747
1748         if (enable) {
1749                 unsigned long flags;
1750                 /* When we enable digit output, we'll get an extra digit
1751                  * sync lost interrupt, that we need to ignore */
1752                 spin_lock_irqsave(&dispc.irq_lock, flags);
1753                 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
1754                 _omap_dispc_set_irqs();
1755                 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1756         }
1757
1758         /* When we disable digit output, we need to wait until fields are done.
1759          * Otherwise the DSS is still working, and turning off the clocks
1760          * prevents DSS from going to OFF mode. And when enabling, we need to
1761          * wait for the extra sync losts */
1762         init_completion(&frame_done_completion);
1763
1764         r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
1765                         DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1766         if (r)
1767                 DSSERR("failed to register EVSYNC isr\n");
1768
1769         _enable_digit_out(enable);
1770
1771         /* XXX I understand from TRM that we should only wait for the
1772          * current field to complete. But it seems we have to wait
1773          * for both fields */
1774         if (!wait_for_completion_timeout(&frame_done_completion,
1775                                 msecs_to_jiffies(100)))
1776                 DSSERR("timeout waiting for EVSYNC\n");
1777
1778         if (!wait_for_completion_timeout(&frame_done_completion,
1779                                 msecs_to_jiffies(100)))
1780                 DSSERR("timeout waiting for EVSYNC\n");
1781
1782         r = omap_dispc_unregister_isr(dispc_disable_isr,
1783                         &frame_done_completion,
1784                         DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1785         if (r)
1786                 DSSERR("failed to unregister EVSYNC isr\n");
1787
1788         if (enable) {
1789                 unsigned long flags;
1790                 spin_lock_irqsave(&dispc.irq_lock, flags);
1791                 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
1792                 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
1793                 _omap_dispc_set_irqs();
1794                 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1795         }
1796
1797         enable_clocks(0);
1798 }
1799
1800 bool dispc_is_channel_enabled(enum omap_channel channel)
1801 {
1802         if (channel == OMAP_DSS_CHANNEL_LCD)
1803                 return !!REG_GET(DISPC_CONTROL, 0, 0);
1804         else if (channel == OMAP_DSS_CHANNEL_DIGIT)
1805                 return !!REG_GET(DISPC_CONTROL, 1, 1);
1806         else
1807                 BUG();
1808 }
1809
1810 void dispc_enable_channel(enum omap_channel channel, bool enable)
1811 {
1812         if (channel == OMAP_DSS_CHANNEL_LCD)
1813                 dispc_enable_lcd_out(enable);
1814         else if (channel == OMAP_DSS_CHANNEL_DIGIT)
1815                 dispc_enable_digit_out(enable);
1816         else
1817                 BUG();
1818 }
1819
1820 void dispc_lcd_enable_signal_polarity(bool act_high)
1821 {
1822         enable_clocks(1);
1823         REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
1824         enable_clocks(0);
1825 }
1826
1827 void dispc_lcd_enable_signal(bool enable)
1828 {
1829         enable_clocks(1);
1830         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
1831         enable_clocks(0);
1832 }
1833
1834 void dispc_pck_free_enable(bool enable)
1835 {
1836         enable_clocks(1);
1837         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
1838         enable_clocks(0);
1839 }
1840
1841 void dispc_enable_fifohandcheck(bool enable)
1842 {
1843         enable_clocks(1);
1844         REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
1845         enable_clocks(0);
1846 }
1847
1848
1849 void dispc_set_lcd_display_type(enum omap_lcd_display_type type)
1850 {
1851         int mode;
1852
1853         switch (type) {
1854         case OMAP_DSS_LCD_DISPLAY_STN:
1855                 mode = 0;
1856                 break;
1857
1858         case OMAP_DSS_LCD_DISPLAY_TFT:
1859                 mode = 1;
1860                 break;
1861
1862         default:
1863                 BUG();
1864                 return;
1865         }
1866
1867         enable_clocks(1);
1868         REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
1869         enable_clocks(0);
1870 }
1871
1872 void dispc_set_loadmode(enum omap_dss_load_mode mode)
1873 {
1874         enable_clocks(1);
1875         REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
1876         enable_clocks(0);
1877 }
1878
1879
1880 void dispc_set_default_color(enum omap_channel channel, u32 color)
1881 {
1882         const struct dispc_reg def_reg[] = { DISPC_DEFAULT_COLOR0,
1883                                 DISPC_DEFAULT_COLOR1 };
1884
1885         enable_clocks(1);
1886         dispc_write_reg(def_reg[channel], color);
1887         enable_clocks(0);
1888 }
1889
1890 u32 dispc_get_default_color(enum omap_channel channel)
1891 {
1892         const struct dispc_reg def_reg[] = { DISPC_DEFAULT_COLOR0,
1893                                 DISPC_DEFAULT_COLOR1 };
1894         u32 l;
1895
1896         BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
1897                channel != OMAP_DSS_CHANNEL_LCD);
1898
1899         enable_clocks(1);
1900         l = dispc_read_reg(def_reg[channel]);
1901         enable_clocks(0);
1902
1903         return l;
1904 }
1905
1906 void dispc_set_trans_key(enum omap_channel ch,
1907                 enum omap_dss_trans_key_type type,
1908                 u32 trans_key)
1909 {
1910         const struct dispc_reg tr_reg[] = {
1911                 DISPC_TRANS_COLOR0, DISPC_TRANS_COLOR1 };
1912
1913         enable_clocks(1);
1914         if (ch == OMAP_DSS_CHANNEL_LCD)
1915                 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
1916         else /* OMAP_DSS_CHANNEL_DIGIT */
1917                 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
1918
1919         dispc_write_reg(tr_reg[ch], trans_key);
1920         enable_clocks(0);
1921 }
1922
1923 void dispc_get_trans_key(enum omap_channel ch,
1924                 enum omap_dss_trans_key_type *type,
1925                 u32 *trans_key)
1926 {
1927         const struct dispc_reg tr_reg[] = {
1928                 DISPC_TRANS_COLOR0, DISPC_TRANS_COLOR1 };
1929
1930         enable_clocks(1);
1931         if (type) {
1932                 if (ch == OMAP_DSS_CHANNEL_LCD)
1933                         *type = REG_GET(DISPC_CONFIG, 11, 11);
1934                 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
1935                         *type = REG_GET(DISPC_CONFIG, 13, 13);
1936                 else
1937                         BUG();
1938         }
1939
1940         if (trans_key)
1941                 *trans_key = dispc_read_reg(tr_reg[ch]);
1942         enable_clocks(0);
1943 }
1944
1945 void dispc_enable_trans_key(enum omap_channel ch, bool enable)
1946 {
1947         enable_clocks(1);
1948         if (ch == OMAP_DSS_CHANNEL_LCD)
1949                 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
1950         else /* OMAP_DSS_CHANNEL_DIGIT */
1951                 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
1952         enable_clocks(0);
1953 }
1954 void dispc_enable_alpha_blending(enum omap_channel ch, bool enable)
1955 {
1956         if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
1957                 return;
1958
1959         enable_clocks(1);
1960         if (ch == OMAP_DSS_CHANNEL_LCD)
1961                 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
1962         else /* OMAP_DSS_CHANNEL_DIGIT */
1963                 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
1964         enable_clocks(0);
1965 }
1966 bool dispc_alpha_blending_enabled(enum omap_channel ch)
1967 {
1968         bool enabled;
1969
1970         if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
1971                 return false;
1972
1973         enable_clocks(1);
1974         if (ch == OMAP_DSS_CHANNEL_LCD)
1975                 enabled = REG_GET(DISPC_CONFIG, 18, 18);
1976         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
1977                 enabled = REG_GET(DISPC_CONFIG, 19, 19);
1978         else
1979                 BUG();
1980         enable_clocks(0);
1981
1982         return enabled;
1983 }
1984
1985
1986 bool dispc_trans_key_enabled(enum omap_channel ch)
1987 {
1988         bool enabled;
1989
1990         enable_clocks(1);
1991         if (ch == OMAP_DSS_CHANNEL_LCD)
1992                 enabled = REG_GET(DISPC_CONFIG, 10, 10);
1993         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
1994                 enabled = REG_GET(DISPC_CONFIG, 12, 12);
1995         else
1996                 BUG();
1997         enable_clocks(0);
1998
1999         return enabled;
2000 }
2001
2002
2003 void dispc_set_tft_data_lines(u8 data_lines)
2004 {
2005         int code;
2006
2007         switch (data_lines) {
2008         case 12:
2009                 code = 0;
2010                 break;
2011         case 16:
2012                 code = 1;
2013                 break;
2014         case 18:
2015                 code = 2;
2016                 break;
2017         case 24:
2018                 code = 3;
2019                 break;
2020         default:
2021                 BUG();
2022                 return;
2023         }
2024
2025         enable_clocks(1);
2026         REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
2027         enable_clocks(0);
2028 }
2029
2030 void dispc_set_parallel_interface_mode(enum omap_parallel_interface_mode mode)
2031 {
2032         u32 l;
2033         int stallmode;
2034         int gpout0 = 1;
2035         int gpout1;
2036
2037         switch (mode) {
2038         case OMAP_DSS_PARALLELMODE_BYPASS:
2039                 stallmode = 0;
2040                 gpout1 = 1;
2041                 break;
2042
2043         case OMAP_DSS_PARALLELMODE_RFBI:
2044                 stallmode = 1;
2045                 gpout1 = 0;
2046                 break;
2047
2048         case OMAP_DSS_PARALLELMODE_DSI:
2049                 stallmode = 1;
2050                 gpout1 = 1;
2051                 break;
2052
2053         default:
2054                 BUG();
2055                 return;
2056         }
2057
2058         enable_clocks(1);
2059
2060         l = dispc_read_reg(DISPC_CONTROL);
2061
2062         l = FLD_MOD(l, stallmode, 11, 11);
2063         l = FLD_MOD(l, gpout0, 15, 15);
2064         l = FLD_MOD(l, gpout1, 16, 16);
2065
2066         dispc_write_reg(DISPC_CONTROL, l);
2067
2068         enable_clocks(0);
2069 }
2070
2071 static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2072                 int vsw, int vfp, int vbp)
2073 {
2074         if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2075                 if (hsw < 1 || hsw > 64 ||
2076                                 hfp < 1 || hfp > 256 ||
2077                                 hbp < 1 || hbp > 256 ||
2078                                 vsw < 1 || vsw > 64 ||
2079                                 vfp < 0 || vfp > 255 ||
2080                                 vbp < 0 || vbp > 255)
2081                         return false;
2082         } else {
2083                 if (hsw < 1 || hsw > 256 ||
2084                                 hfp < 1 || hfp > 4096 ||
2085                                 hbp < 1 || hbp > 4096 ||
2086                                 vsw < 1 || vsw > 256 ||
2087                                 vfp < 0 || vfp > 4095 ||
2088                                 vbp < 0 || vbp > 4095)
2089                         return false;
2090         }
2091
2092         return true;
2093 }
2094
2095 bool dispc_lcd_timings_ok(struct omap_video_timings *timings)
2096 {
2097         return _dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2098                         timings->hbp, timings->vsw,
2099                         timings->vfp, timings->vbp);
2100 }
2101
2102 static void _dispc_set_lcd_timings(int hsw, int hfp, int hbp,
2103                                    int vsw, int vfp, int vbp)
2104 {
2105         u32 timing_h, timing_v;
2106
2107         if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2108                 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
2109                         FLD_VAL(hbp-1, 27, 20);
2110
2111                 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
2112                         FLD_VAL(vbp, 27, 20);
2113         } else {
2114                 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
2115                         FLD_VAL(hbp-1, 31, 20);
2116
2117                 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
2118                         FLD_VAL(vbp, 31, 20);
2119         }
2120
2121         enable_clocks(1);
2122         dispc_write_reg(DISPC_TIMING_H, timing_h);
2123         dispc_write_reg(DISPC_TIMING_V, timing_v);
2124         enable_clocks(0);
2125 }
2126
2127 /* change name to mode? */
2128 void dispc_set_lcd_timings(struct omap_video_timings *timings)
2129 {
2130         unsigned xtot, ytot;
2131         unsigned long ht, vt;
2132
2133         if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2134                                 timings->hbp, timings->vsw,
2135                                 timings->vfp, timings->vbp))
2136                 BUG();
2137
2138         _dispc_set_lcd_timings(timings->hsw, timings->hfp, timings->hbp,
2139                         timings->vsw, timings->vfp, timings->vbp);
2140
2141         dispc_set_lcd_size(timings->x_res, timings->y_res);
2142
2143         xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
2144         ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
2145
2146         ht = (timings->pixel_clock * 1000) / xtot;
2147         vt = (timings->pixel_clock * 1000) / xtot / ytot;
2148
2149         DSSDBG("xres %u yres %u\n", timings->x_res, timings->y_res);
2150         DSSDBG("pck %u\n", timings->pixel_clock);
2151         DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2152                         timings->hsw, timings->hfp, timings->hbp,
2153                         timings->vsw, timings->vfp, timings->vbp);
2154
2155         DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2156 }
2157
2158 static void dispc_set_lcd_divisor(u16 lck_div, u16 pck_div)
2159 {
2160         BUG_ON(lck_div < 1);
2161         BUG_ON(pck_div < 2);
2162
2163         enable_clocks(1);
2164         dispc_write_reg(DISPC_DIVISOR,
2165                         FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
2166         enable_clocks(0);
2167 }
2168
2169 static void dispc_get_lcd_divisor(int *lck_div, int *pck_div)
2170 {
2171         u32 l;
2172         l = dispc_read_reg(DISPC_DIVISOR);
2173         *lck_div = FLD_GET(l, 23, 16);
2174         *pck_div = FLD_GET(l, 7, 0);
2175 }
2176
2177 unsigned long dispc_fclk_rate(void)
2178 {
2179         unsigned long r = 0;
2180
2181         if (dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK)
2182                 r = dss_clk_get_rate(DSS_CLK_FCK1);
2183         else
2184 #ifdef CONFIG_OMAP2_DSS_DSI
2185                 r = dsi_get_dsi1_pll_rate();
2186 #else
2187         BUG();
2188 #endif
2189         return r;
2190 }
2191
2192 unsigned long dispc_lclk_rate(void)
2193 {
2194         int lcd;
2195         unsigned long r;
2196         u32 l;
2197
2198         l = dispc_read_reg(DISPC_DIVISOR);
2199
2200         lcd = FLD_GET(l, 23, 16);
2201
2202         r = dispc_fclk_rate();
2203
2204         return r / lcd;
2205 }
2206
2207 unsigned long dispc_pclk_rate(void)
2208 {
2209         int lcd, pcd;
2210         unsigned long r;
2211         u32 l;
2212
2213         l = dispc_read_reg(DISPC_DIVISOR);
2214
2215         lcd = FLD_GET(l, 23, 16);
2216         pcd = FLD_GET(l, 7, 0);
2217
2218         r = dispc_fclk_rate();
2219
2220         return r / lcd / pcd;
2221 }
2222
2223 void dispc_dump_clocks(struct seq_file *s)
2224 {
2225         int lcd, pcd;
2226
2227         enable_clocks(1);
2228
2229         dispc_get_lcd_divisor(&lcd, &pcd);
2230
2231         seq_printf(s, "- DISPC -\n");
2232
2233         seq_printf(s, "dispc fclk source = %s\n",
2234                         dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ?
2235                         "dss1_alwon_fclk" : "dsi1_pll_fclk");
2236
2237         seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2238         seq_printf(s, "lck\t\t%-16lulck div\t%u\n", dispc_lclk_rate(), lcd);
2239         seq_printf(s, "pck\t\t%-16lupck div\t%u\n", dispc_pclk_rate(), pcd);
2240
2241         enable_clocks(0);
2242 }
2243
2244 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2245 void dispc_dump_irqs(struct seq_file *s)
2246 {
2247         unsigned long flags;
2248         struct dispc_irq_stats stats;
2249
2250         spin_lock_irqsave(&dispc.irq_stats_lock, flags);
2251
2252         stats = dispc.irq_stats;
2253         memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
2254         dispc.irq_stats.last_reset = jiffies;
2255
2256         spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
2257
2258         seq_printf(s, "period %u ms\n",
2259                         jiffies_to_msecs(jiffies - stats.last_reset));
2260
2261         seq_printf(s, "irqs %d\n", stats.irq_count);
2262 #define PIS(x) \
2263         seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
2264
2265         PIS(FRAMEDONE);
2266         PIS(VSYNC);
2267         PIS(EVSYNC_EVEN);
2268         PIS(EVSYNC_ODD);
2269         PIS(ACBIAS_COUNT_STAT);
2270         PIS(PROG_LINE_NUM);
2271         PIS(GFX_FIFO_UNDERFLOW);
2272         PIS(GFX_END_WIN);
2273         PIS(PAL_GAMMA_MASK);
2274         PIS(OCP_ERR);
2275         PIS(VID1_FIFO_UNDERFLOW);
2276         PIS(VID1_END_WIN);
2277         PIS(VID2_FIFO_UNDERFLOW);
2278         PIS(VID2_END_WIN);
2279         PIS(SYNC_LOST);
2280         PIS(SYNC_LOST_DIGIT);
2281         PIS(WAKEUP);
2282 #undef PIS
2283 }
2284 #endif
2285
2286 void dispc_dump_regs(struct seq_file *s)
2287 {
2288 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dispc_read_reg(r))
2289
2290         dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
2291
2292         DUMPREG(DISPC_REVISION);
2293         DUMPREG(DISPC_SYSCONFIG);
2294         DUMPREG(DISPC_SYSSTATUS);
2295         DUMPREG(DISPC_IRQSTATUS);
2296         DUMPREG(DISPC_IRQENABLE);
2297         DUMPREG(DISPC_CONTROL);
2298         DUMPREG(DISPC_CONFIG);
2299         DUMPREG(DISPC_CAPABLE);
2300         DUMPREG(DISPC_DEFAULT_COLOR0);
2301         DUMPREG(DISPC_DEFAULT_COLOR1);
2302         DUMPREG(DISPC_TRANS_COLOR0);
2303         DUMPREG(DISPC_TRANS_COLOR1);
2304         DUMPREG(DISPC_LINE_STATUS);
2305         DUMPREG(DISPC_LINE_NUMBER);
2306         DUMPREG(DISPC_TIMING_H);
2307         DUMPREG(DISPC_TIMING_V);
2308         DUMPREG(DISPC_POL_FREQ);
2309         DUMPREG(DISPC_DIVISOR);
2310         DUMPREG(DISPC_GLOBAL_ALPHA);
2311         DUMPREG(DISPC_SIZE_DIG);
2312         DUMPREG(DISPC_SIZE_LCD);
2313
2314         DUMPREG(DISPC_GFX_BA0);
2315         DUMPREG(DISPC_GFX_BA1);
2316         DUMPREG(DISPC_GFX_POSITION);
2317         DUMPREG(DISPC_GFX_SIZE);
2318         DUMPREG(DISPC_GFX_ATTRIBUTES);
2319         DUMPREG(DISPC_GFX_FIFO_THRESHOLD);
2320         DUMPREG(DISPC_GFX_FIFO_SIZE_STATUS);
2321         DUMPREG(DISPC_GFX_ROW_INC);
2322         DUMPREG(DISPC_GFX_PIXEL_INC);
2323         DUMPREG(DISPC_GFX_WINDOW_SKIP);
2324         DUMPREG(DISPC_GFX_TABLE_BA);
2325
2326         DUMPREG(DISPC_DATA_CYCLE1);
2327         DUMPREG(DISPC_DATA_CYCLE2);
2328         DUMPREG(DISPC_DATA_CYCLE3);
2329
2330         DUMPREG(DISPC_CPR_COEF_R);
2331         DUMPREG(DISPC_CPR_COEF_G);
2332         DUMPREG(DISPC_CPR_COEF_B);
2333
2334         DUMPREG(DISPC_GFX_PRELOAD);
2335
2336         DUMPREG(DISPC_VID_BA0(0));
2337         DUMPREG(DISPC_VID_BA1(0));
2338         DUMPREG(DISPC_VID_POSITION(0));
2339         DUMPREG(DISPC_VID_SIZE(0));
2340         DUMPREG(DISPC_VID_ATTRIBUTES(0));
2341         DUMPREG(DISPC_VID_FIFO_THRESHOLD(0));
2342         DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(0));
2343         DUMPREG(DISPC_VID_ROW_INC(0));
2344         DUMPREG(DISPC_VID_PIXEL_INC(0));
2345         DUMPREG(DISPC_VID_FIR(0));
2346         DUMPREG(DISPC_VID_PICTURE_SIZE(0));
2347         DUMPREG(DISPC_VID_ACCU0(0));
2348         DUMPREG(DISPC_VID_ACCU1(0));
2349
2350         DUMPREG(DISPC_VID_BA0(1));
2351         DUMPREG(DISPC_VID_BA1(1));
2352         DUMPREG(DISPC_VID_POSITION(1));
2353         DUMPREG(DISPC_VID_SIZE(1));
2354         DUMPREG(DISPC_VID_ATTRIBUTES(1));
2355         DUMPREG(DISPC_VID_FIFO_THRESHOLD(1));
2356         DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(1));
2357         DUMPREG(DISPC_VID_ROW_INC(1));
2358         DUMPREG(DISPC_VID_PIXEL_INC(1));
2359         DUMPREG(DISPC_VID_FIR(1));
2360         DUMPREG(DISPC_VID_PICTURE_SIZE(1));
2361         DUMPREG(DISPC_VID_ACCU0(1));
2362         DUMPREG(DISPC_VID_ACCU1(1));
2363
2364         DUMPREG(DISPC_VID_FIR_COEF_H(0, 0));
2365         DUMPREG(DISPC_VID_FIR_COEF_H(0, 1));
2366         DUMPREG(DISPC_VID_FIR_COEF_H(0, 2));
2367         DUMPREG(DISPC_VID_FIR_COEF_H(0, 3));
2368         DUMPREG(DISPC_VID_FIR_COEF_H(0, 4));
2369         DUMPREG(DISPC_VID_FIR_COEF_H(0, 5));
2370         DUMPREG(DISPC_VID_FIR_COEF_H(0, 6));
2371         DUMPREG(DISPC_VID_FIR_COEF_H(0, 7));
2372         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 0));
2373         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 1));
2374         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 2));
2375         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 3));
2376         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 4));
2377         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 5));
2378         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 6));
2379         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 7));
2380         DUMPREG(DISPC_VID_CONV_COEF(0, 0));
2381         DUMPREG(DISPC_VID_CONV_COEF(0, 1));
2382         DUMPREG(DISPC_VID_CONV_COEF(0, 2));
2383         DUMPREG(DISPC_VID_CONV_COEF(0, 3));
2384         DUMPREG(DISPC_VID_CONV_COEF(0, 4));
2385         DUMPREG(DISPC_VID_FIR_COEF_V(0, 0));
2386         DUMPREG(DISPC_VID_FIR_COEF_V(0, 1));
2387         DUMPREG(DISPC_VID_FIR_COEF_V(0, 2));
2388         DUMPREG(DISPC_VID_FIR_COEF_V(0, 3));
2389         DUMPREG(DISPC_VID_FIR_COEF_V(0, 4));
2390         DUMPREG(DISPC_VID_FIR_COEF_V(0, 5));
2391         DUMPREG(DISPC_VID_FIR_COEF_V(0, 6));
2392         DUMPREG(DISPC_VID_FIR_COEF_V(0, 7));
2393
2394         DUMPREG(DISPC_VID_FIR_COEF_H(1, 0));
2395         DUMPREG(DISPC_VID_FIR_COEF_H(1, 1));
2396         DUMPREG(DISPC_VID_FIR_COEF_H(1, 2));
2397         DUMPREG(DISPC_VID_FIR_COEF_H(1, 3));
2398         DUMPREG(DISPC_VID_FIR_COEF_H(1, 4));
2399         DUMPREG(DISPC_VID_FIR_COEF_H(1, 5));
2400         DUMPREG(DISPC_VID_FIR_COEF_H(1, 6));
2401         DUMPREG(DISPC_VID_FIR_COEF_H(1, 7));
2402         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 0));
2403         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 1));
2404         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 2));
2405         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 3));
2406         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 4));
2407         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 5));
2408         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 6));
2409         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 7));
2410         DUMPREG(DISPC_VID_CONV_COEF(1, 0));
2411         DUMPREG(DISPC_VID_CONV_COEF(1, 1));
2412         DUMPREG(DISPC_VID_CONV_COEF(1, 2));
2413         DUMPREG(DISPC_VID_CONV_COEF(1, 3));
2414         DUMPREG(DISPC_VID_CONV_COEF(1, 4));
2415         DUMPREG(DISPC_VID_FIR_COEF_V(1, 0));
2416         DUMPREG(DISPC_VID_FIR_COEF_V(1, 1));
2417         DUMPREG(DISPC_VID_FIR_COEF_V(1, 2));
2418         DUMPREG(DISPC_VID_FIR_COEF_V(1, 3));
2419         DUMPREG(DISPC_VID_FIR_COEF_V(1, 4));
2420         DUMPREG(DISPC_VID_FIR_COEF_V(1, 5));
2421         DUMPREG(DISPC_VID_FIR_COEF_V(1, 6));
2422         DUMPREG(DISPC_VID_FIR_COEF_V(1, 7));
2423
2424         DUMPREG(DISPC_VID_PRELOAD(0));
2425         DUMPREG(DISPC_VID_PRELOAD(1));
2426
2427         dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
2428 #undef DUMPREG
2429 }
2430
2431 static void _dispc_set_pol_freq(bool onoff, bool rf, bool ieo, bool ipc,
2432                                 bool ihs, bool ivs, u8 acbi, u8 acb)
2433 {
2434         u32 l = 0;
2435
2436         DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
2437                         onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
2438
2439         l |= FLD_VAL(onoff, 17, 17);
2440         l |= FLD_VAL(rf, 16, 16);
2441         l |= FLD_VAL(ieo, 15, 15);
2442         l |= FLD_VAL(ipc, 14, 14);
2443         l |= FLD_VAL(ihs, 13, 13);
2444         l |= FLD_VAL(ivs, 12, 12);
2445         l |= FLD_VAL(acbi, 11, 8);
2446         l |= FLD_VAL(acb, 7, 0);
2447
2448         enable_clocks(1);
2449         dispc_write_reg(DISPC_POL_FREQ, l);
2450         enable_clocks(0);
2451 }
2452
2453 void dispc_set_pol_freq(enum omap_panel_config config, u8 acbi, u8 acb)
2454 {
2455         _dispc_set_pol_freq((config & OMAP_DSS_LCD_ONOFF) != 0,
2456                         (config & OMAP_DSS_LCD_RF) != 0,
2457                         (config & OMAP_DSS_LCD_IEO) != 0,
2458                         (config & OMAP_DSS_LCD_IPC) != 0,
2459                         (config & OMAP_DSS_LCD_IHS) != 0,
2460                         (config & OMAP_DSS_LCD_IVS) != 0,
2461                         acbi, acb);
2462 }
2463
2464 /* with fck as input clock rate, find dispc dividers that produce req_pck */
2465 void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
2466                 struct dispc_clock_info *cinfo)
2467 {
2468         u16 pcd_min = is_tft ? 2 : 3;
2469         unsigned long best_pck;
2470         u16 best_ld, cur_ld;
2471         u16 best_pd, cur_pd;
2472
2473         best_pck = 0;
2474         best_ld = 0;
2475         best_pd = 0;
2476
2477         for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
2478                 unsigned long lck = fck / cur_ld;
2479
2480                 for (cur_pd = pcd_min; cur_pd <= 255; ++cur_pd) {
2481                         unsigned long pck = lck / cur_pd;
2482                         long old_delta = abs(best_pck - req_pck);
2483                         long new_delta = abs(pck - req_pck);
2484
2485                         if (best_pck == 0 || new_delta < old_delta) {
2486                                 best_pck = pck;
2487                                 best_ld = cur_ld;
2488                                 best_pd = cur_pd;
2489
2490                                 if (pck == req_pck)
2491                                         goto found;
2492                         }
2493
2494                         if (pck < req_pck)
2495                                 break;
2496                 }
2497
2498                 if (lck / pcd_min < req_pck)
2499                         break;
2500         }
2501
2502 found:
2503         cinfo->lck_div = best_ld;
2504         cinfo->pck_div = best_pd;
2505         cinfo->lck = fck / cinfo->lck_div;
2506         cinfo->pck = cinfo->lck / cinfo->pck_div;
2507 }
2508
2509 /* calculate clock rates using dividers in cinfo */
2510 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
2511                 struct dispc_clock_info *cinfo)
2512 {
2513         if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
2514                 return -EINVAL;
2515         if (cinfo->pck_div < 2 || cinfo->pck_div > 255)
2516                 return -EINVAL;
2517
2518         cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
2519         cinfo->pck = cinfo->lck / cinfo->pck_div;
2520
2521         return 0;
2522 }
2523
2524 int dispc_set_clock_div(struct dispc_clock_info *cinfo)
2525 {
2526         DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
2527         DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
2528
2529         dispc_set_lcd_divisor(cinfo->lck_div, cinfo->pck_div);
2530
2531         return 0;
2532 }
2533
2534 int dispc_get_clock_div(struct dispc_clock_info *cinfo)
2535 {
2536         unsigned long fck;
2537
2538         fck = dispc_fclk_rate();
2539
2540         cinfo->lck_div = REG_GET(DISPC_DIVISOR, 23, 16);
2541         cinfo->pck_div = REG_GET(DISPC_DIVISOR, 7, 0);
2542
2543         cinfo->lck = fck / cinfo->lck_div;
2544         cinfo->pck = cinfo->lck / cinfo->pck_div;
2545
2546         return 0;
2547 }
2548
2549 /* dispc.irq_lock has to be locked by the caller */
2550 static void _omap_dispc_set_irqs(void)
2551 {
2552         u32 mask;
2553         u32 old_mask;
2554         int i;
2555         struct omap_dispc_isr_data *isr_data;
2556
2557         mask = dispc.irq_error_mask;
2558
2559         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2560                 isr_data = &dispc.registered_isr[i];
2561
2562                 if (isr_data->isr == NULL)
2563                         continue;
2564
2565                 mask |= isr_data->mask;
2566         }
2567
2568         enable_clocks(1);
2569
2570         old_mask = dispc_read_reg(DISPC_IRQENABLE);
2571         /* clear the irqstatus for newly enabled irqs */
2572         dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
2573
2574         dispc_write_reg(DISPC_IRQENABLE, mask);
2575
2576         enable_clocks(0);
2577 }
2578
2579 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2580 {
2581         int i;
2582         int ret;
2583         unsigned long flags;
2584         struct omap_dispc_isr_data *isr_data;
2585
2586         if (isr == NULL)
2587                 return -EINVAL;
2588
2589         spin_lock_irqsave(&dispc.irq_lock, flags);
2590
2591         /* check for duplicate entry */
2592         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2593                 isr_data = &dispc.registered_isr[i];
2594                 if (isr_data->isr == isr && isr_data->arg == arg &&
2595                                 isr_data->mask == mask) {
2596                         ret = -EINVAL;
2597                         goto err;
2598                 }
2599         }
2600
2601         isr_data = NULL;
2602         ret = -EBUSY;
2603
2604         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2605                 isr_data = &dispc.registered_isr[i];
2606
2607                 if (isr_data->isr != NULL)
2608                         continue;
2609
2610                 isr_data->isr = isr;
2611                 isr_data->arg = arg;
2612                 isr_data->mask = mask;
2613                 ret = 0;
2614
2615                 break;
2616         }
2617
2618         _omap_dispc_set_irqs();
2619
2620         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2621
2622         return 0;
2623 err:
2624         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2625
2626         return ret;
2627 }
2628 EXPORT_SYMBOL(omap_dispc_register_isr);
2629
2630 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2631 {
2632         int i;
2633         unsigned long flags;
2634         int ret = -EINVAL;
2635         struct omap_dispc_isr_data *isr_data;
2636
2637         spin_lock_irqsave(&dispc.irq_lock, flags);
2638
2639         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2640                 isr_data = &dispc.registered_isr[i];
2641                 if (isr_data->isr != isr || isr_data->arg != arg ||
2642                                 isr_data->mask != mask)
2643                         continue;
2644
2645                 /* found the correct isr */
2646
2647                 isr_data->isr = NULL;
2648                 isr_data->arg = NULL;
2649                 isr_data->mask = 0;
2650
2651                 ret = 0;
2652                 break;
2653         }
2654
2655         if (ret == 0)
2656                 _omap_dispc_set_irqs();
2657
2658         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2659
2660         return ret;
2661 }
2662 EXPORT_SYMBOL(omap_dispc_unregister_isr);
2663
2664 #ifdef DEBUG
2665 static void print_irq_status(u32 status)
2666 {
2667         if ((status & dispc.irq_error_mask) == 0)
2668                 return;
2669
2670         printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
2671
2672 #define PIS(x) \
2673         if (status & DISPC_IRQ_##x) \
2674                 printk(#x " ");
2675         PIS(GFX_FIFO_UNDERFLOW);
2676         PIS(OCP_ERR);
2677         PIS(VID1_FIFO_UNDERFLOW);
2678         PIS(VID2_FIFO_UNDERFLOW);
2679         PIS(SYNC_LOST);
2680         PIS(SYNC_LOST_DIGIT);
2681 #undef PIS
2682
2683         printk("\n");
2684 }
2685 #endif
2686
2687 /* Called from dss.c. Note that we don't touch clocks here,
2688  * but we presume they are on because we got an IRQ. However,
2689  * an irq handler may turn the clocks off, so we may not have
2690  * clock later in the function. */
2691 void dispc_irq_handler(void)
2692 {
2693         int i;
2694         u32 irqstatus;
2695         u32 handledirqs = 0;
2696         u32 unhandled_errors;
2697         struct omap_dispc_isr_data *isr_data;
2698         struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
2699
2700         spin_lock(&dispc.irq_lock);
2701
2702         irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
2703
2704 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2705         spin_lock(&dispc.irq_stats_lock);
2706         dispc.irq_stats.irq_count++;
2707         dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
2708         spin_unlock(&dispc.irq_stats_lock);
2709 #endif
2710
2711 #ifdef DEBUG
2712         if (dss_debug)
2713                 print_irq_status(irqstatus);
2714 #endif
2715         /* Ack the interrupt. Do it here before clocks are possibly turned
2716          * off */
2717         dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
2718         /* flush posted write */
2719         dispc_read_reg(DISPC_IRQSTATUS);
2720
2721         /* make a copy and unlock, so that isrs can unregister
2722          * themselves */
2723         memcpy(registered_isr, dispc.registered_isr,
2724                         sizeof(registered_isr));
2725
2726         spin_unlock(&dispc.irq_lock);
2727
2728         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2729                 isr_data = &registered_isr[i];
2730
2731                 if (!isr_data->isr)
2732                         continue;
2733
2734                 if (isr_data->mask & irqstatus) {
2735                         isr_data->isr(isr_data->arg, irqstatus);
2736                         handledirqs |= isr_data->mask;
2737                 }
2738         }
2739
2740         spin_lock(&dispc.irq_lock);
2741
2742         unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
2743
2744         if (unhandled_errors) {
2745                 dispc.error_irqs |= unhandled_errors;
2746
2747                 dispc.irq_error_mask &= ~unhandled_errors;
2748                 _omap_dispc_set_irqs();
2749
2750                 schedule_work(&dispc.error_work);
2751         }
2752
2753         spin_unlock(&dispc.irq_lock);
2754 }
2755
2756 static void dispc_error_worker(struct work_struct *work)
2757 {
2758         int i;
2759         u32 errors;
2760         unsigned long flags;
2761
2762         spin_lock_irqsave(&dispc.irq_lock, flags);
2763         errors = dispc.error_irqs;
2764         dispc.error_irqs = 0;
2765         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2766
2767         if (errors & DISPC_IRQ_GFX_FIFO_UNDERFLOW) {
2768                 DSSERR("GFX_FIFO_UNDERFLOW, disabling GFX\n");
2769                 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2770                         struct omap_overlay *ovl;
2771                         ovl = omap_dss_get_overlay(i);
2772
2773                         if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2774                                 continue;
2775
2776                         if (ovl->id == 0) {
2777                                 dispc_enable_plane(ovl->id, 0);
2778                                 dispc_go(ovl->manager->id);
2779                                 mdelay(50);
2780                                 break;
2781                         }
2782                 }
2783         }
2784
2785         if (errors & DISPC_IRQ_VID1_FIFO_UNDERFLOW) {
2786                 DSSERR("VID1_FIFO_UNDERFLOW, disabling VID1\n");
2787                 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2788                         struct omap_overlay *ovl;
2789                         ovl = omap_dss_get_overlay(i);
2790
2791                         if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2792                                 continue;
2793
2794                         if (ovl->id == 1) {
2795                                 dispc_enable_plane(ovl->id, 0);
2796                                 dispc_go(ovl->manager->id);
2797                                 mdelay(50);
2798                                 break;
2799                         }
2800                 }
2801         }
2802
2803         if (errors & DISPC_IRQ_VID2_FIFO_UNDERFLOW) {
2804                 DSSERR("VID2_FIFO_UNDERFLOW, disabling VID2\n");
2805                 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2806                         struct omap_overlay *ovl;
2807                         ovl = omap_dss_get_overlay(i);
2808
2809                         if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2810                                 continue;
2811
2812                         if (ovl->id == 2) {
2813                                 dispc_enable_plane(ovl->id, 0);
2814                                 dispc_go(ovl->manager->id);
2815                                 mdelay(50);
2816                                 break;
2817                         }
2818                 }
2819         }
2820
2821         if (errors & DISPC_IRQ_SYNC_LOST) {
2822                 struct omap_overlay_manager *manager = NULL;
2823                 bool enable = false;
2824
2825                 DSSERR("SYNC_LOST, disabling LCD\n");
2826
2827                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
2828                         struct omap_overlay_manager *mgr;
2829                         mgr = omap_dss_get_overlay_manager(i);
2830
2831                         if (mgr->id == OMAP_DSS_CHANNEL_LCD) {
2832                                 manager = mgr;
2833                                 enable = mgr->device->state ==
2834                                                 OMAP_DSS_DISPLAY_ACTIVE;
2835                                 mgr->device->driver->disable(mgr->device);
2836                                 break;
2837                         }
2838                 }
2839
2840                 if (manager) {
2841                         struct omap_dss_device *dssdev = manager->device;
2842                         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2843                                 struct omap_overlay *ovl;
2844                                 ovl = omap_dss_get_overlay(i);
2845
2846                                 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2847                                         continue;
2848
2849                                 if (ovl->id != 0 && ovl->manager == manager)
2850                                         dispc_enable_plane(ovl->id, 0);
2851                         }
2852
2853                         dispc_go(manager->id);
2854                         mdelay(50);
2855                         if (enable)
2856                                 dssdev->driver->enable(dssdev);
2857                 }
2858         }
2859
2860         if (errors & DISPC_IRQ_SYNC_LOST_DIGIT) {
2861                 struct omap_overlay_manager *manager = NULL;
2862                 bool enable = false;
2863
2864                 DSSERR("SYNC_LOST_DIGIT, disabling TV\n");
2865
2866                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
2867                         struct omap_overlay_manager *mgr;
2868                         mgr = omap_dss_get_overlay_manager(i);
2869
2870                         if (mgr->id == OMAP_DSS_CHANNEL_DIGIT) {
2871                                 manager = mgr;
2872                                 enable = mgr->device->state ==
2873                                                 OMAP_DSS_DISPLAY_ACTIVE;
2874                                 mgr->device->driver->disable(mgr->device);
2875                                 break;
2876                         }
2877                 }
2878
2879                 if (manager) {
2880                         struct omap_dss_device *dssdev = manager->device;
2881                         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2882                                 struct omap_overlay *ovl;
2883                                 ovl = omap_dss_get_overlay(i);
2884
2885                                 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2886                                         continue;
2887
2888                                 if (ovl->id != 0 && ovl->manager == manager)
2889                                         dispc_enable_plane(ovl->id, 0);
2890                         }
2891
2892                         dispc_go(manager->id);
2893                         mdelay(50);
2894                         if (enable)
2895                                 dssdev->driver->enable(dssdev);
2896                 }
2897         }
2898
2899         if (errors & DISPC_IRQ_OCP_ERR) {
2900                 DSSERR("OCP_ERR\n");
2901                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
2902                         struct omap_overlay_manager *mgr;
2903                         mgr = omap_dss_get_overlay_manager(i);
2904
2905                         if (mgr->caps & OMAP_DSS_OVL_CAP_DISPC)
2906                                 mgr->device->driver->disable(mgr->device);
2907                 }
2908         }
2909
2910         spin_lock_irqsave(&dispc.irq_lock, flags);
2911         dispc.irq_error_mask |= errors;
2912         _omap_dispc_set_irqs();
2913         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2914 }
2915
2916 int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
2917 {
2918         void dispc_irq_wait_handler(void *data, u32 mask)
2919         {
2920                 complete((struct completion *)data);
2921         }
2922
2923         int r;
2924         DECLARE_COMPLETION_ONSTACK(completion);
2925
2926         r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
2927                         irqmask);
2928
2929         if (r)
2930                 return r;
2931
2932         timeout = wait_for_completion_timeout(&completion, timeout);
2933
2934         omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
2935
2936         if (timeout == 0)
2937                 return -ETIMEDOUT;
2938
2939         if (timeout == -ERESTARTSYS)
2940                 return -ERESTARTSYS;
2941
2942         return 0;
2943 }
2944
2945 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
2946                 unsigned long timeout)
2947 {
2948         void dispc_irq_wait_handler(void *data, u32 mask)
2949         {
2950                 complete((struct completion *)data);
2951         }
2952
2953         int r;
2954         DECLARE_COMPLETION_ONSTACK(completion);
2955
2956         r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
2957                         irqmask);
2958
2959         if (r)
2960                 return r;
2961
2962         timeout = wait_for_completion_interruptible_timeout(&completion,
2963                         timeout);
2964
2965         omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
2966
2967         if (timeout == 0)
2968                 return -ETIMEDOUT;
2969
2970         if (timeout == -ERESTARTSYS)
2971                 return -ERESTARTSYS;
2972
2973         return 0;
2974 }
2975
2976 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
2977 void dispc_fake_vsync_irq(void)
2978 {
2979         u32 irqstatus = DISPC_IRQ_VSYNC;
2980         int i;
2981
2982         WARN_ON(!in_interrupt());
2983
2984         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2985                 struct omap_dispc_isr_data *isr_data;
2986                 isr_data = &dispc.registered_isr[i];
2987
2988                 if (!isr_data->isr)
2989                         continue;
2990
2991                 if (isr_data->mask & irqstatus)
2992                         isr_data->isr(isr_data->arg, irqstatus);
2993         }
2994 }
2995 #endif
2996
2997 static void _omap_dispc_initialize_irq(void)
2998 {
2999         unsigned long flags;
3000
3001         spin_lock_irqsave(&dispc.irq_lock, flags);
3002
3003         memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3004
3005         dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
3006
3007         /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3008          * so clear it */
3009         dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3010
3011         _omap_dispc_set_irqs();
3012
3013         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3014 }
3015
3016 void dispc_enable_sidle(void)
3017 {
3018         REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3);  /* SIDLEMODE: smart idle */
3019 }
3020
3021 void dispc_disable_sidle(void)
3022 {
3023         REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3);  /* SIDLEMODE: no idle */
3024 }
3025
3026 static void _omap_dispc_initial_config(void)
3027 {
3028         u32 l;
3029
3030         l = dispc_read_reg(DISPC_SYSCONFIG);
3031         l = FLD_MOD(l, 2, 13, 12);      /* MIDLEMODE: smart standby */
3032         l = FLD_MOD(l, 2, 4, 3);        /* SIDLEMODE: smart idle */
3033         l = FLD_MOD(l, 1, 2, 2);        /* ENWAKEUP */
3034         l = FLD_MOD(l, 1, 0, 0);        /* AUTOIDLE */
3035         dispc_write_reg(DISPC_SYSCONFIG, l);
3036
3037         /* FUNCGATED */
3038         REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3039
3040         /* L3 firewall setting: enable access to OCM RAM */
3041         /* XXX this should be somewhere in plat-omap */
3042         if (cpu_is_omap24xx())
3043                 __raw_writel(0x402000b0, OMAP2_L3_IO_ADDRESS(0x680050a0));
3044
3045         _dispc_setup_color_conv_coef();
3046
3047         dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3048
3049         dispc_read_plane_fifo_sizes();
3050 }
3051
3052 int dispc_init(void)
3053 {
3054         u32 rev;
3055
3056         spin_lock_init(&dispc.irq_lock);
3057
3058 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3059         spin_lock_init(&dispc.irq_stats_lock);
3060         dispc.irq_stats.last_reset = jiffies;
3061 #endif
3062
3063         INIT_WORK(&dispc.error_work, dispc_error_worker);
3064
3065         dispc.base = ioremap(DISPC_BASE, DISPC_SZ_REGS);
3066         if (!dispc.base) {
3067                 DSSERR("can't ioremap DISPC\n");
3068                 return -ENOMEM;
3069         }
3070
3071         enable_clocks(1);
3072
3073         _omap_dispc_initial_config();
3074
3075         _omap_dispc_initialize_irq();
3076
3077         dispc_save_context();
3078
3079         rev = dispc_read_reg(DISPC_REVISION);
3080         printk(KERN_INFO "OMAP DISPC rev %d.%d\n",
3081                FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3082
3083         enable_clocks(0);
3084
3085         return 0;
3086 }
3087
3088 void dispc_exit(void)
3089 {
3090         iounmap(dispc.base);
3091 }
3092
3093 int dispc_enable_plane(enum omap_plane plane, bool enable)
3094 {
3095         DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
3096
3097         enable_clocks(1);
3098         _dispc_enable_plane(plane, enable);
3099         enable_clocks(0);
3100
3101         return 0;
3102 }
3103
3104 int dispc_setup_plane(enum omap_plane plane,
3105                        u32 paddr, u16 screen_width,
3106                        u16 pos_x, u16 pos_y,
3107                        u16 width, u16 height,
3108                        u16 out_width, u16 out_height,
3109                        enum omap_color_mode color_mode,
3110                        bool ilace,
3111                        enum omap_dss_rotation_type rotation_type,
3112                        u8 rotation, bool mirror, u8 global_alpha,
3113                        u8 pre_mult_alpha)
3114 {
3115         int r = 0;
3116
3117         DSSDBG("dispc_setup_plane %d, pa %x, sw %d, %d,%d, %dx%d -> "
3118                "%dx%d, ilace %d, cmode %x, rot %d, mir %d\n",
3119                plane, paddr, screen_width, pos_x, pos_y,
3120                width, height,
3121                out_width, out_height,
3122                ilace, color_mode,
3123                rotation, mirror);
3124
3125         enable_clocks(1);
3126
3127         r = _dispc_setup_plane(plane,
3128                            paddr, screen_width,
3129                            pos_x, pos_y,
3130                            width, height,
3131                            out_width, out_height,
3132                            color_mode, ilace,
3133                            rotation_type,
3134                            rotation, mirror,
3135                            global_alpha,
3136                            pre_mult_alpha);
3137
3138         enable_clocks(0);
3139
3140         return r;
3141 }