drivers/video/omap2/dss/dispc.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dispc.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #define DSS_SUBSYS_NAME "DISPC"
  24
  25 #include <linux/kernel.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/vmalloc.h>
  28 #include <linux/export.h>
  29 #include <linux/clk.h>
  30 #include <linux/io.h>
  31 #include <linux/jiffies.h>
  32 #include <linux/seq_file.h>
  33 #include <linux/delay.h>
  34 #include <linux/workqueue.h>
  35 #include <linux/hardirq.h>
  36 #include <linux/interrupt.h>
  37 #include <linux/platform_device.h>
  38 #include <linux/pm_runtime.h>
  39
  40 #include <video/omapdss.h>
  41
  42 #include "dss.h"
  43 #include "dss_features.h"
  44 #include "dispc.h"
  45
  46 /* DISPC */
  47 #define DISPC_SZ_REGS                   SZ_4K
  48
  49 #define DISPC_IRQ_MASK_ERROR            (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
  50                                          DISPC_IRQ_OCP_ERR | \
  51                                          DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
  52                                          DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
  53                                          DISPC_IRQ_SYNC_LOST | \
  54                                          DISPC_IRQ_SYNC_LOST_DIGIT)
  55
  56 #define DISPC_MAX_NR_ISRS               8
  57
  58 struct omap_dispc_isr_data {
  59         omap_dispc_isr_t        isr;
  60         void                    *arg;
  61         u32                     mask;
  62 };
  63
  64 enum omap_burst_size {
  65         BURST_SIZE_X2 = 0,
  66         BURST_SIZE_X4 = 1,
  67         BURST_SIZE_X8 = 2,
  68 };
  69
  70 #define REG_GET(idx, start, end) \
  71         FLD_GET(dispc_read_reg(idx), start, end)
  72
  73 #define REG_FLD_MOD(idx, val, start, end)                               \
  74         dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
  75
  76 struct dispc_irq_stats {
  77         unsigned long last_reset;
  78         unsigned irq_count;
  79         unsigned irqs[32];
  80 };
  81
  82 struct dispc_features {
  83         u8 sw_start;
  84         u8 fp_start;
  85         u8 bp_start;
  86         u16 sw_max;
  87         u16 vp_max;
  88         u16 hp_max;
  89         int (*calc_scaling) (enum omap_plane plane,
  90                 const struct omap_video_timings *mgr_timings,
  91                 u16 width, u16 height, u16 out_width, u16 out_height,
  92                 enum omap_color_mode color_mode, bool *five_taps,
  93                 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
  94                 u16 pos_x, unsigned long *core_clk, bool mem_to_mem);
  95         unsigned long (*calc_core_clk) (enum omap_plane plane,
  96                 u16 width, u16 height, u16 out_width, u16 out_height,
  97                 bool mem_to_mem);
  98         u8 num_fifos;
  99
 100         /* swap GFX & WB fifos */
 101         bool gfx_fifo_workaround:1;
 102 };
 103
 104 #define DISPC_MAX_NR_FIFOS 5
 105
 106 static struct {
 107         struct platform_device *pdev;
 108         void __iomem    *base;
 109
 110         int             ctx_loss_cnt;
 111
 112         int irq;
 113         struct clk *dss_clk;
 114
 115         u32 fifo_size[DISPC_MAX_NR_FIFOS];
 116         /* maps which plane is using a fifo. fifo-id -> plane-id */
 117         int fifo_assignment[DISPC_MAX_NR_FIFOS];
 118
 119         spinlock_t irq_lock;
 120         u32 irq_error_mask;
 121         struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
 122         u32 error_irqs;
 123         struct work_struct error_work;
 124
 125         bool            ctx_valid;
 126         u32             ctx[DISPC_SZ_REGS / sizeof(u32)];
 127
 128         const struct dispc_features *feat;
 129
 130 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
 131         spinlock_t irq_stats_lock;
 132         struct dispc_irq_stats irq_stats;
 133 #endif
 134 } dispc;
 135
 136 enum omap_color_component {
 137         /* used for all color formats for OMAP3 and earlier
 138          * and for RGB and Y color component on OMAP4
 139          */
 140         DISPC_COLOR_COMPONENT_RGB_Y             = 1 << 0,
 141         /* used for UV component for
 142          * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
 143          * color formats on OMAP4
 144          */
 145         DISPC_COLOR_COMPONENT_UV                = 1 << 1,
 146 };
 147
 148 enum mgr_reg_fields {
 149         DISPC_MGR_FLD_ENABLE,
 150         DISPC_MGR_FLD_STNTFT,
 151         DISPC_MGR_FLD_GO,
 152         DISPC_MGR_FLD_TFTDATALINES,
 153         DISPC_MGR_FLD_STALLMODE,
 154         DISPC_MGR_FLD_TCKENABLE,
 155         DISPC_MGR_FLD_TCKSELECTION,
 156         DISPC_MGR_FLD_CPR,
 157         DISPC_MGR_FLD_FIFOHANDCHECK,
 158         /* used to maintain a count of the above fields */
 159         DISPC_MGR_FLD_NUM,
 160 };
 161
 162 static const struct {
 163         const char *name;
 164         u32 vsync_irq;
 165         u32 framedone_irq;
 166         u32 sync_lost_irq;
 167         struct reg_field reg_desc[DISPC_MGR_FLD_NUM];
 168 } mgr_desc[] = {
 169         [OMAP_DSS_CHANNEL_LCD] = {
 170                 .name           = "LCD",
 171                 .vsync_irq      = DISPC_IRQ_VSYNC,
 172                 .framedone_irq  = DISPC_IRQ_FRAMEDONE,
 173                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST,
 174                 .reg_desc       = {
 175                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL,  0,  0 },
 176                         [DISPC_MGR_FLD_STNTFT]          = { DISPC_CONTROL,  3,  3 },
 177                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL,  5,  5 },
 178                         [DISPC_MGR_FLD_TFTDATALINES]    = { DISPC_CONTROL,  9,  8 },
 179                         [DISPC_MGR_FLD_STALLMODE]       = { DISPC_CONTROL, 11, 11 },
 180                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG,  10, 10 },
 181                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG,  11, 11 },
 182                         [DISPC_MGR_FLD_CPR]             = { DISPC_CONFIG,  15, 15 },
 183                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG,  16, 16 },
 184                 },
 185         },
 186         [OMAP_DSS_CHANNEL_DIGIT] = {
 187                 .name           = "DIGIT",
 188                 .vsync_irq      = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
 189                 .framedone_irq  = 0,
 190                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST_DIGIT,
 191                 .reg_desc       = {
 192                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL,  1,  1 },
 193                         [DISPC_MGR_FLD_STNTFT]          = { },
 194                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL,  6,  6 },
 195                         [DISPC_MGR_FLD_TFTDATALINES]    = { },
 196                         [DISPC_MGR_FLD_STALLMODE]       = { },
 197                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG,  12, 12 },
 198                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG,  13, 13 },
 199                         [DISPC_MGR_FLD_CPR]             = { },
 200                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG,  16, 16 },
 201                 },
 202         },
 203         [OMAP_DSS_CHANNEL_LCD2] = {
 204                 .name           = "LCD2",
 205                 .vsync_irq      = DISPC_IRQ_VSYNC2,
 206                 .framedone_irq  = DISPC_IRQ_FRAMEDONE2,
 207                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST2,
 208                 .reg_desc       = {
 209                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL2,  0,  0 },
 210                         [DISPC_MGR_FLD_STNTFT]          = { DISPC_CONTROL2,  3,  3 },
 211                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL2,  5,  5 },
 212                         [DISPC_MGR_FLD_TFTDATALINES]    = { DISPC_CONTROL2,  9,  8 },
 213                         [DISPC_MGR_FLD_STALLMODE]       = { DISPC_CONTROL2, 11, 11 },
 214                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG2,  10, 10 },
 215                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG2,  11, 11 },
 216                         [DISPC_MGR_FLD_CPR]             = { DISPC_CONFIG2,  15, 15 },
 217                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG2,  16, 16 },
 218                 },
 219         },
 220         [OMAP_DSS_CHANNEL_LCD3] = {
 221                 .name           = "LCD3",
 222                 .vsync_irq      = DISPC_IRQ_VSYNC3,
 223                 .framedone_irq  = DISPC_IRQ_FRAMEDONE3,
 224                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST3,
 225                 .reg_desc       = {
 226                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL3,  0,  0 },
 227                         [DISPC_MGR_FLD_STNTFT]          = { DISPC_CONTROL3,  3,  3 },
 228                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL3,  5,  5 },
 229                         [DISPC_MGR_FLD_TFTDATALINES]    = { DISPC_CONTROL3,  9,  8 },
 230                         [DISPC_MGR_FLD_STALLMODE]       = { DISPC_CONTROL3, 11, 11 },
 231                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG3,  10, 10 },
 232                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG3,  11, 11 },
 233                         [DISPC_MGR_FLD_CPR]             = { DISPC_CONFIG3,  15, 15 },
 234                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG3,  16, 16 },
 235                 },
 236         },
 237 };
 238
 239 static void _omap_dispc_set_irqs(void);
 240 static unsigned long dispc_plane_pclk_rate(enum omap_plane plane);
 241 static unsigned long dispc_plane_lclk_rate(enum omap_plane plane);
 242
 243 static inline void dispc_write_reg(const u16 idx, u32 val)
 244 {
 245         __raw_writel(val, dispc.base + idx);
 246 }
 247
 248 static inline u32 dispc_read_reg(const u16 idx)
 249 {
 250         return __raw_readl(dispc.base + idx);
 251 }
 252
 253 static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)
 254 {
 255         const struct reg_field rfld = mgr_desc[channel].reg_desc[regfld];
 256         return REG_GET(rfld.reg, rfld.high, rfld.low);
 257 }
 258
 259 static void mgr_fld_write(enum omap_channel channel,
 260                                         enum mgr_reg_fields regfld, int val) {
 261         const struct reg_field rfld = mgr_desc[channel].reg_desc[regfld];
 262         REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
 263 }
 264
 265 #define SR(reg) \
 266         dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
 267 #define RR(reg) \
 268         dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
 269
 270 static void dispc_save_context(void)
 271 {
 272         int i, j;
 273
 274         DSSDBG("dispc_save_context\n");
 275
 276         SR(IRQENABLE);
 277         SR(CONTROL);
 278         SR(CONFIG);
 279         SR(LINE_NUMBER);
 280         if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
 281                         dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
 282                 SR(GLOBAL_ALPHA);
 283         if (dss_has_feature(FEAT_MGR_LCD2)) {
 284                 SR(CONTROL2);
 285                 SR(CONFIG2);
 286         }
 287         if (dss_has_feature(FEAT_MGR_LCD3)) {
 288                 SR(CONTROL3);
 289                 SR(CONFIG3);
 290         }
 291
 292         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
 293                 SR(DEFAULT_COLOR(i));
 294                 SR(TRANS_COLOR(i));
 295                 SR(SIZE_MGR(i));
 296                 if (i == OMAP_DSS_CHANNEL_DIGIT)
 297                         continue;
 298                 SR(TIMING_H(i));
 299                 SR(TIMING_V(i));
 300                 SR(POL_FREQ(i));
 301                 SR(DIVISORo(i));
 302
 303                 SR(DATA_CYCLE1(i));
 304                 SR(DATA_CYCLE2(i));
 305                 SR(DATA_CYCLE3(i));
 306
 307                 if (dss_has_feature(FEAT_CPR)) {
 308                         SR(CPR_COEF_R(i));
 309                         SR(CPR_COEF_G(i));
 310                         SR(CPR_COEF_B(i));
 311                 }
 312         }
 313
 314         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
 315                 SR(OVL_BA0(i));
 316                 SR(OVL_BA1(i));
 317                 SR(OVL_POSITION(i));
 318                 SR(OVL_SIZE(i));
 319                 SR(OVL_ATTRIBUTES(i));
 320                 SR(OVL_FIFO_THRESHOLD(i));
 321                 SR(OVL_ROW_INC(i));
 322                 SR(OVL_PIXEL_INC(i));
 323                 if (dss_has_feature(FEAT_PRELOAD))
 324                         SR(OVL_PRELOAD(i));
 325                 if (i == OMAP_DSS_GFX) {
 326                         SR(OVL_WINDOW_SKIP(i));
 327                         SR(OVL_TABLE_BA(i));
 328                         continue;
 329                 }
 330                 SR(OVL_FIR(i));
 331                 SR(OVL_PICTURE_SIZE(i));
 332                 SR(OVL_ACCU0(i));
 333                 SR(OVL_ACCU1(i));
 334
 335                 for (j = 0; j < 8; j++)
 336                         SR(OVL_FIR_COEF_H(i, j));
 337
 338                 for (j = 0; j < 8; j++)
 339                         SR(OVL_FIR_COEF_HV(i, j));
 340
 341                 for (j = 0; j < 5; j++)
 342                         SR(OVL_CONV_COEF(i, j));
 343
 344                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
 345                         for (j = 0; j < 8; j++)
 346                                 SR(OVL_FIR_COEF_V(i, j));
 347                 }
 348
 349                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
 350                         SR(OVL_BA0_UV(i));
 351                         SR(OVL_BA1_UV(i));
 352                         SR(OVL_FIR2(i));
 353                         SR(OVL_ACCU2_0(i));
 354                         SR(OVL_ACCU2_1(i));
 355
 356                         for (j = 0; j < 8; j++)
 357                                 SR(OVL_FIR_COEF_H2(i, j));
 358
 359                         for (j = 0; j < 8; j++)
 360                                 SR(OVL_FIR_COEF_HV2(i, j));
 361
 362                         for (j = 0; j < 8; j++)
 363                                 SR(OVL_FIR_COEF_V2(i, j));
 364                 }
 365                 if (dss_has_feature(FEAT_ATTR2))
 366                         SR(OVL_ATTRIBUTES2(i));
 367         }
 368
 369         if (dss_has_feature(FEAT_CORE_CLK_DIV))
 370                 SR(DIVISOR);
 371
 372         dispc.ctx_loss_cnt = dss_get_ctx_loss_count(&dispc.pdev->dev);
 373         dispc.ctx_valid = true;
 374
 375         DSSDBG("context saved, ctx_loss_count %d\n", dispc.ctx_loss_cnt);
 376 }
 377
 378 static void dispc_restore_context(void)
 379 {
 380         int i, j, ctx;
 381
 382         DSSDBG("dispc_restore_context\n");
 383
 384         if (!dispc.ctx_valid)
 385                 return;
 386
 387         ctx = dss_get_ctx_loss_count(&dispc.pdev->dev);
 388
 389         if (ctx >= 0 && ctx == dispc.ctx_loss_cnt)
 390                 return;
 391
 392         DSSDBG("ctx_loss_count: saved %d, current %d\n",
 393                         dispc.ctx_loss_cnt, ctx);
 394
 395         /*RR(IRQENABLE);*/
 396         /*RR(CONTROL);*/
 397         RR(CONFIG);
 398         RR(LINE_NUMBER);
 399         if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
 400                         dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
 401                 RR(GLOBAL_ALPHA);
 402         if (dss_has_feature(FEAT_MGR_LCD2))
 403                 RR(CONFIG2);
 404         if (dss_has_feature(FEAT_MGR_LCD3))
 405                 RR(CONFIG3);
 406
 407         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
 408                 RR(DEFAULT_COLOR(i));
 409                 RR(TRANS_COLOR(i));
 410                 RR(SIZE_MGR(i));
 411                 if (i == OMAP_DSS_CHANNEL_DIGIT)
 412                         continue;
 413                 RR(TIMING_H(i));
 414                 RR(TIMING_V(i));
 415                 RR(POL_FREQ(i));
 416                 RR(DIVISORo(i));
 417
 418                 RR(DATA_CYCLE1(i));
 419                 RR(DATA_CYCLE2(i));
 420                 RR(DATA_CYCLE3(i));
 421
 422                 if (dss_has_feature(FEAT_CPR)) {
 423                         RR(CPR_COEF_R(i));
 424                         RR(CPR_COEF_G(i));
 425                         RR(CPR_COEF_B(i));
 426                 }
 427         }
 428
 429         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
 430                 RR(OVL_BA0(i));
 431                 RR(OVL_BA1(i));
 432                 RR(OVL_POSITION(i));
 433                 RR(OVL_SIZE(i));
 434                 RR(OVL_ATTRIBUTES(i));
 435                 RR(OVL_FIFO_THRESHOLD(i));
 436                 RR(OVL_ROW_INC(i));
 437                 RR(OVL_PIXEL_INC(i));
 438                 if (dss_has_feature(FEAT_PRELOAD))
 439                         RR(OVL_PRELOAD(i));
 440                 if (i == OMAP_DSS_GFX) {
 441                         RR(OVL_WINDOW_SKIP(i));
 442                         RR(OVL_TABLE_BA(i));
 443                         continue;
 444                 }
 445                 RR(OVL_FIR(i));
 446                 RR(OVL_PICTURE_SIZE(i));
 447                 RR(OVL_ACCU0(i));
 448                 RR(OVL_ACCU1(i));
 449
 450                 for (j = 0; j < 8; j++)
 451                         RR(OVL_FIR_COEF_H(i, j));
 452
 453                 for (j = 0; j < 8; j++)
 454                         RR(OVL_FIR_COEF_HV(i, j));
 455
 456                 for (j = 0; j < 5; j++)
 457                         RR(OVL_CONV_COEF(i, j));
 458
 459                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
 460                         for (j = 0; j < 8; j++)
 461                                 RR(OVL_FIR_COEF_V(i, j));
 462                 }
 463
 464                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
 465                         RR(OVL_BA0_UV(i));
 466                         RR(OVL_BA1_UV(i));
 467                         RR(OVL_FIR2(i));
 468                         RR(OVL_ACCU2_0(i));
 469                         RR(OVL_ACCU2_1(i));
 470
 471                         for (j = 0; j < 8; j++)
 472                                 RR(OVL_FIR_COEF_H2(i, j));
 473
 474                         for (j = 0; j < 8; j++)
 475                                 RR(OVL_FIR_COEF_HV2(i, j));
 476
 477                         for (j = 0; j < 8; j++)
 478                                 RR(OVL_FIR_COEF_V2(i, j));
 479                 }
 480                 if (dss_has_feature(FEAT_ATTR2))
 481                         RR(OVL_ATTRIBUTES2(i));
 482         }
 483
 484         if (dss_has_feature(FEAT_CORE_CLK_DIV))
 485                 RR(DIVISOR);
 486
 487         /* enable last, because LCD & DIGIT enable are here */
 488         RR(CONTROL);
 489         if (dss_has_feature(FEAT_MGR_LCD2))
 490                 RR(CONTROL2);
 491         if (dss_has_feature(FEAT_MGR_LCD3))
 492                 RR(CONTROL3);
 493         /* clear spurious SYNC_LOST_DIGIT interrupts */
 494         dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
 495
 496         /*
 497          * enable last so IRQs won't trigger before
 498          * the context is fully restored
 499          */
 500         RR(IRQENABLE);
 501
 502         DSSDBG("context restored\n");
 503 }
 504
 505 #undef SR
 506 #undef RR
 507
 508 int dispc_runtime_get(void)
 509 {
 510         int r;
 511
 512         DSSDBG("dispc_runtime_get\n");
 513
 514         r = pm_runtime_get_sync(&dispc.pdev->dev);
 515         WARN_ON(r < 0);
 516         return r < 0 ? r : 0;
 517 }
 518
 519 void dispc_runtime_put(void)
 520 {
 521         int r;
 522
 523         DSSDBG("dispc_runtime_put\n");
 524
 525         r = pm_runtime_put_sync(&dispc.pdev->dev);
 526         WARN_ON(r < 0 && r != -ENOSYS);
 527 }
 528
 529 u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
 530 {
 531         return mgr_desc[channel].vsync_irq;
 532 }
 533
 534 u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
 535 {
 536         return mgr_desc[channel].framedone_irq;
 537 }
 538
 539 bool dispc_mgr_go_busy(enum omap_channel channel)
 540 {
 541         return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
 542 }
 543
 544 void dispc_mgr_go(enum omap_channel channel)
 545 {
 546         bool enable_bit, go_bit;
 547
 548         /* if the channel is not enabled, we don't need GO */
 549         enable_bit = mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE) == 1;
 550
 551         if (!enable_bit)
 552                 return;
 553
 554         go_bit = mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
 555
 556         if (go_bit) {
 557                 DSSERR("GO bit not down for channel %d\n", channel);
 558                 return;
 559         }
 560
 561         DSSDBG("GO %s\n", mgr_desc[channel].name);
 562
 563         mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
 564 }
 565
 566 static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
 567 {
 568         dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
 569 }
 570
 571 static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
 572 {
 573         dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
 574 }
 575
 576 static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
 577 {
 578         dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
 579 }
 580
 581 static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
 582 {
 583         BUG_ON(plane == OMAP_DSS_GFX);
 584
 585         dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
 586 }
 587
 588 static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
 589                 u32 value)
 590 {
 591         BUG_ON(plane == OMAP_DSS_GFX);
 592
 593         dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
 594 }
 595
 596 static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
 597 {
 598         BUG_ON(plane == OMAP_DSS_GFX);
 599
 600         dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
 601 }
 602
 603 static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
 604                                 int fir_vinc, int five_taps,
 605                                 enum omap_color_component color_comp)
 606 {
 607         const struct dispc_coef *h_coef, *v_coef;
 608         int i;
 609
 610         h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
 611         v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
 612
 613         for (i = 0; i < 8; i++) {
 614                 u32 h, hv;
 615
 616                 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
 617                         | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
 618                         | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
 619                         | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
 620                 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
 621                         | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
 622                         | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
 623                         | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
 624
 625                 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
 626                         dispc_ovl_write_firh_reg(plane, i, h);
 627                         dispc_ovl_write_firhv_reg(plane, i, hv);
 628                 } else {
 629                         dispc_ovl_write_firh2_reg(plane, i, h);
 630                         dispc_ovl_write_firhv2_reg(plane, i, hv);
 631                 }
 632
 633         }
 634
 635         if (five_taps) {
 636                 for (i = 0; i < 8; i++) {
 637                         u32 v;
 638                         v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
 639                                 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
 640                         if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
 641                                 dispc_ovl_write_firv_reg(plane, i, v);
 642                         else
 643                                 dispc_ovl_write_firv2_reg(plane, i, v);
 644                 }
 645         }
 646 }
 647
 648 static void _dispc_setup_color_conv_coef(void)
 649 {
 650         int i;
 651         const struct color_conv_coef {
 652                 int  ry,  rcr,  rcb,   gy,  gcr,  gcb,   by,  bcr,  bcb;
 653                 int  full_range;
 654         }  ctbl_bt601_5 = {
 655                 298,  409,    0,  298, -208, -100,  298,    0,  517, 0,
 656         };
 657
 658         const struct color_conv_coef *ct;
 659
 660 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
 661
 662         ct = &ctbl_bt601_5;
 663
 664         for (i = 1; i < dss_feat_get_num_ovls(); i++) {
 665                 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 0),
 666                         CVAL(ct->rcr, ct->ry));
 667                 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 1),
 668                         CVAL(ct->gy,  ct->rcb));
 669                 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 2),
 670                         CVAL(ct->gcb, ct->gcr));
 671                 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 3),
 672                         CVAL(ct->bcr, ct->by));
 673                 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 4),
 674                         CVAL(0, ct->bcb));
 675
 676                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), ct->full_range,
 677                         11, 11);
 678         }
 679
 680 #undef CVAL
 681 }
 682
 683
 684 static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
 685 {
 686         dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
 687 }
 688
 689 static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
 690 {
 691         dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
 692 }
 693
 694 static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
 695 {
 696         dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
 697 }
 698
 699 static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
 700 {
 701         dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
 702 }
 703
 704 static void dispc_ovl_set_pos(enum omap_plane plane,
 705                 enum omap_overlay_caps caps, int x, int y)
 706 {
 707         u32 val;
 708
 709         if ((caps & OMAP_DSS_OVL_CAP_POS) == 0)
 710                 return;
 711
 712         val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
 713
 714         dispc_write_reg(DISPC_OVL_POSITION(plane), val);
 715 }
 716
 717 static void dispc_ovl_set_input_size(enum omap_plane plane, int width,
 718                 int height)
 719 {
 720         u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 721
 722         if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB)
 723                 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
 724         else
 725                 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
 726 }
 727
 728 static void dispc_ovl_set_output_size(enum omap_plane plane, int width,
 729                 int height)
 730 {
 731         u32 val;
 732
 733         BUG_ON(plane == OMAP_DSS_GFX);
 734
 735         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 736
 737         if (plane == OMAP_DSS_WB)
 738                 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
 739         else
 740                 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
 741 }
 742
 743 static void dispc_ovl_set_zorder(enum omap_plane plane,
 744                 enum omap_overlay_caps caps, u8 zorder)
 745 {
 746         if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
 747                 return;
 748
 749         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
 750 }
 751
 752 static void dispc_ovl_enable_zorder_planes(void)
 753 {
 754         int i;
 755
 756         if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
 757                 return;
 758
 759         for (i = 0; i < dss_feat_get_num_ovls(); i++)
 760                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
 761 }
 762
 763 static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane,
 764                 enum omap_overlay_caps caps, bool enable)
 765 {
 766         if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
 767                 return;
 768
 769         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
 770 }
 771
 772 static void dispc_ovl_setup_global_alpha(enum omap_plane plane,
 773                 enum omap_overlay_caps caps, u8 global_alpha)
 774 {
 775         static const unsigned shifts[] = { 0, 8, 16, 24, };
 776         int shift;
 777
 778         if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
 779                 return;
 780
 781         shift = shifts[plane];
 782         REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
 783 }
 784
 785 static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
 786 {
 787         dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
 788 }
 789
 790 static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
 791 {
 792         dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
 793 }
 794
 795 static void dispc_ovl_set_color_mode(enum omap_plane plane,
 796                 enum omap_color_mode color_mode)
 797 {
 798         u32 m = 0;
 799         if (plane != OMAP_DSS_GFX) {
 800                 switch (color_mode) {
 801                 case OMAP_DSS_COLOR_NV12:
 802                         m = 0x0; break;
 803                 case OMAP_DSS_COLOR_RGBX16:
 804                         m = 0x1; break;
 805                 case OMAP_DSS_COLOR_RGBA16:
 806                         m = 0x2; break;
 807                 case OMAP_DSS_COLOR_RGB12U:
 808                         m = 0x4; break;
 809                 case OMAP_DSS_COLOR_ARGB16:
 810                         m = 0x5; break;
 811                 case OMAP_DSS_COLOR_RGB16:
 812                         m = 0x6; break;
 813                 case OMAP_DSS_COLOR_ARGB16_1555:
 814                         m = 0x7; break;
 815                 case OMAP_DSS_COLOR_RGB24U:
 816                         m = 0x8; break;
 817                 case OMAP_DSS_COLOR_RGB24P:
 818                         m = 0x9; break;
 819                 case OMAP_DSS_COLOR_YUV2:
 820                         m = 0xa; break;
 821                 case OMAP_DSS_COLOR_UYVY:
 822                         m = 0xb; break;
 823                 case OMAP_DSS_COLOR_ARGB32:
 824                         m = 0xc; break;
 825                 case OMAP_DSS_COLOR_RGBA32:
 826                         m = 0xd; break;
 827                 case OMAP_DSS_COLOR_RGBX32:
 828                         m = 0xe; break;
 829                 case OMAP_DSS_COLOR_XRGB16_1555:
 830                         m = 0xf; break;
 831                 default:
 832                         BUG(); return;
 833                 }
 834         } else {
 835                 switch (color_mode) {
 836                 case OMAP_DSS_COLOR_CLUT1:
 837                         m = 0x0; break;
 838                 case OMAP_DSS_COLOR_CLUT2:
 839                         m = 0x1; break;
 840                 case OMAP_DSS_COLOR_CLUT4:
 841                         m = 0x2; break;
 842                 case OMAP_DSS_COLOR_CLUT8:
 843                         m = 0x3; break;
 844                 case OMAP_DSS_COLOR_RGB12U:
 845                         m = 0x4; break;
 846                 case OMAP_DSS_COLOR_ARGB16:
 847                         m = 0x5; break;
 848                 case OMAP_DSS_COLOR_RGB16:
 849                         m = 0x6; break;
 850                 case OMAP_DSS_COLOR_ARGB16_1555:
 851                         m = 0x7; break;
 852                 case OMAP_DSS_COLOR_RGB24U:
 853                         m = 0x8; break;
 854                 case OMAP_DSS_COLOR_RGB24P:
 855                         m = 0x9; break;
 856                 case OMAP_DSS_COLOR_RGBX16:
 857                         m = 0xa; break;
 858                 case OMAP_DSS_COLOR_RGBA16:
 859                         m = 0xb; break;
 860                 case OMAP_DSS_COLOR_ARGB32:
 861                         m = 0xc; break;
 862                 case OMAP_DSS_COLOR_RGBA32:
 863                         m = 0xd; break;
 864                 case OMAP_DSS_COLOR_RGBX32:
 865                         m = 0xe; break;
 866                 case OMAP_DSS_COLOR_XRGB16_1555:
 867                         m = 0xf; break;
 868                 default:
 869                         BUG(); return;
 870                 }
 871         }
 872
 873         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
 874 }
 875
 876 static void dispc_ovl_configure_burst_type(enum omap_plane plane,
 877                 enum omap_dss_rotation_type rotation_type)
 878 {
 879         if (dss_has_feature(FEAT_BURST_2D) == 0)
 880                 return;
 881
 882         if (rotation_type == OMAP_DSS_ROT_TILER)
 883                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
 884         else
 885                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
 886 }
 887
 888 void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
 889 {
 890         int shift;
 891         u32 val;
 892         int chan = 0, chan2 = 0;
 893
 894         switch (plane) {
 895         case OMAP_DSS_GFX:
 896                 shift = 8;
 897                 break;
 898         case OMAP_DSS_VIDEO1:
 899         case OMAP_DSS_VIDEO2:
 900         case OMAP_DSS_VIDEO3:
 901                 shift = 16;
 902                 break;
 903         default:
 904                 BUG();
 905                 return;
 906         }
 907
 908         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
 909         if (dss_has_feature(FEAT_MGR_LCD2)) {
 910                 switch (channel) {
 911                 case OMAP_DSS_CHANNEL_LCD:
 912                         chan = 0;
 913                         chan2 = 0;
 914                         break;
 915                 case OMAP_DSS_CHANNEL_DIGIT:
 916                         chan = 1;
 917                         chan2 = 0;
 918                         break;
 919                 case OMAP_DSS_CHANNEL_LCD2:
 920                         chan = 0;
 921                         chan2 = 1;
 922                         break;
 923                 case OMAP_DSS_CHANNEL_LCD3:
 924                         if (dss_has_feature(FEAT_MGR_LCD3)) {
 925                                 chan = 0;
 926                                 chan2 = 2;
 927                         } else {
 928                                 BUG();
 929                                 return;
 930                         }
 931                         break;
 932                 default:
 933                         BUG();
 934                         return;
 935                 }
 936
 937                 val = FLD_MOD(val, chan, shift, shift);
 938                 val = FLD_MOD(val, chan2, 31, 30);
 939         } else {
 940                 val = FLD_MOD(val, channel, shift, shift);
 941         }
 942         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
 943 }
 944
 945 static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
 946 {
 947         int shift;
 948         u32 val;
 949         enum omap_channel channel;
 950
 951         switch (plane) {
 952         case OMAP_DSS_GFX:
 953                 shift = 8;
 954                 break;
 955         case OMAP_DSS_VIDEO1:
 956         case OMAP_DSS_VIDEO2:
 957         case OMAP_DSS_VIDEO3:
 958                 shift = 16;
 959                 break;
 960         default:
 961                 BUG();
 962                 return 0;
 963         }
 964
 965         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
 966
 967         if (dss_has_feature(FEAT_MGR_LCD3)) {
 968                 if (FLD_GET(val, 31, 30) == 0)
 969                         channel = FLD_GET(val, shift, shift);
 970                 else if (FLD_GET(val, 31, 30) == 1)
 971                         channel = OMAP_DSS_CHANNEL_LCD2;
 972                 else
 973                         channel = OMAP_DSS_CHANNEL_LCD3;
 974         } else if (dss_has_feature(FEAT_MGR_LCD2)) {
 975                 if (FLD_GET(val, 31, 30) == 0)
 976                         channel = FLD_GET(val, shift, shift);
 977                 else
 978                         channel = OMAP_DSS_CHANNEL_LCD2;
 979         } else {
 980                 channel = FLD_GET(val, shift, shift);
 981         }
 982
 983         return channel;
 984 }
 985
 986 void dispc_wb_set_channel_in(enum dss_writeback_channel channel)
 987 {
 988         enum omap_plane plane = OMAP_DSS_WB;
 989
 990         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), channel, 18, 16);
 991 }
 992
 993 static void dispc_ovl_set_burst_size(enum omap_plane plane,
 994                 enum omap_burst_size burst_size)
 995 {
 996         static const unsigned shifts[] = { 6, 14, 14, 14, };
 997         int shift;
 998
 999         shift = shifts[plane];
1000         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
1001 }
1002
1003 static void dispc_configure_burst_sizes(void)
1004 {
1005         int i;
1006         const int burst_size = BURST_SIZE_X8;
1007
1008         /* Configure burst size always to maximum size */
1009         for (i = 0; i < omap_dss_get_num_overlays(); ++i)
1010                 dispc_ovl_set_burst_size(i, burst_size);
1011 }
1012
1013 static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
1014 {
1015         unsigned unit = dss_feat_get_burst_size_unit();
1016         /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
1017         return unit * 8;
1018 }
1019
1020 void dispc_enable_gamma_table(bool enable)
1021 {
1022         /*
1023          * This is partially implemented to support only disabling of
1024          * the gamma table.
1025          */
1026         if (enable) {
1027                 DSSWARN("Gamma table enabling for TV not yet supported");
1028                 return;
1029         }
1030
1031         REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
1032 }
1033
1034 static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
1035 {
1036         if (channel == OMAP_DSS_CHANNEL_DIGIT)
1037                 return;
1038
1039         mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);
1040 }
1041
1042 static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
1043                 struct omap_dss_cpr_coefs *coefs)
1044 {
1045         u32 coef_r, coef_g, coef_b;
1046
1047         if (!dss_mgr_is_lcd(channel))
1048                 return;
1049
1050         coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1051                 FLD_VAL(coefs->rb, 9, 0);
1052         coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1053                 FLD_VAL(coefs->gb, 9, 0);
1054         coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1055                 FLD_VAL(coefs->bb, 9, 0);
1056
1057         dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1058         dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1059         dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1060 }
1061
1062 static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
1063 {
1064         u32 val;
1065
1066         BUG_ON(plane == OMAP_DSS_GFX);
1067
1068         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1069         val = FLD_MOD(val, enable, 9, 9);
1070         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
1071 }
1072
1073 static void dispc_ovl_enable_replication(enum omap_plane plane,
1074                 enum omap_overlay_caps caps, bool enable)
1075 {
1076         static const unsigned shifts[] = { 5, 10, 10, 10 };
1077         int shift;
1078
1079         if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0)
1080                 return;
1081
1082         shift = shifts[plane];
1083         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
1084 }
1085
1086 static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
1087                 u16 height)
1088 {
1089         u32 val;
1090
1091         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
1092         dispc_write_reg(DISPC_SIZE_MGR(channel), val);
1093 }
1094
1095 static void dispc_init_fifos(void)
1096 {
1097         u32 size;
1098         int fifo;
1099         u8 start, end;
1100         u32 unit;
1101
1102         unit = dss_feat_get_buffer_size_unit();
1103
1104         dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
1105
1106         for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1107                 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end);
1108                 size *= unit;
1109                 dispc.fifo_size[fifo] = size;
1110
1111                 /*
1112                  * By default fifos are mapped directly to overlays, fifo 0 to
1113                  * ovl 0, fifo 1 to ovl 1, etc.
1114                  */
1115                 dispc.fifo_assignment[fifo] = fifo;
1116         }
1117
1118         /*
1119          * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo
1120          * causes problems with certain use cases, like using the tiler in 2D
1121          * mode. The below hack swaps the fifos of GFX and WB planes, thus
1122          * giving GFX plane a larger fifo. WB but should work fine with a
1123          * smaller fifo.
1124          */
1125         if (dispc.feat->gfx_fifo_workaround) {
1126                 u32 v;
1127
1128                 v = dispc_read_reg(DISPC_GLOBAL_BUFFER);
1129
1130                 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */
1131                 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */
1132                 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */
1133                 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */
1134
1135                 dispc_write_reg(DISPC_GLOBAL_BUFFER, v);
1136
1137                 dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB;
1138                 dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX;
1139         }
1140 }
1141
1142 static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
1143 {
1144         int fifo;
1145         u32 size = 0;
1146
1147         for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1148                 if (dispc.fifo_assignment[fifo] == plane)
1149                         size += dispc.fifo_size[fifo];
1150         }
1151
1152         return size;
1153 }
1154
1155 void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
1156 {
1157         u8 hi_start, hi_end, lo_start, lo_end;
1158         u32 unit;
1159
1160         unit = dss_feat_get_buffer_size_unit();
1161
1162         WARN_ON(low % unit != 0);
1163         WARN_ON(high % unit != 0);
1164
1165         low /= unit;
1166         high /= unit;
1167
1168         dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1169         dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1170
1171         DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
1172                         plane,
1173                         REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1174                                 lo_start, lo_end) * unit,
1175                         REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1176                                 hi_start, hi_end) * unit,
1177                         low * unit, high * unit);
1178
1179         dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
1180                         FLD_VAL(high, hi_start, hi_end) |
1181                         FLD_VAL(low, lo_start, lo_end));
1182 }
1183
1184 void dispc_enable_fifomerge(bool enable)
1185 {
1186         if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1187                 WARN_ON(enable);
1188                 return;
1189         }
1190
1191         DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1192         REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1193 }
1194
1195 void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
1196                 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
1197                 bool manual_update)
1198 {
1199         /*
1200          * All sizes are in bytes. Both the buffer and burst are made of
1201          * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1202          */
1203
1204         unsigned buf_unit = dss_feat_get_buffer_size_unit();
1205         unsigned ovl_fifo_size, total_fifo_size, burst_size;
1206         int i;
1207
1208         burst_size = dispc_ovl_get_burst_size(plane);
1209         ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
1210
1211         if (use_fifomerge) {
1212                 total_fifo_size = 0;
1213                 for (i = 0; i < omap_dss_get_num_overlays(); ++i)
1214                         total_fifo_size += dispc_ovl_get_fifo_size(i);
1215         } else {
1216                 total_fifo_size = ovl_fifo_size;
1217         }
1218
1219         /*
1220          * We use the same low threshold for both fifomerge and non-fifomerge
1221          * cases, but for fifomerge we calculate the high threshold using the
1222          * combined fifo size
1223          */
1224
1225         if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
1226                 *fifo_low = ovl_fifo_size - burst_size * 2;
1227                 *fifo_high = total_fifo_size - burst_size;
1228         } else {
1229                 *fifo_low = ovl_fifo_size - burst_size;
1230                 *fifo_high = total_fifo_size - buf_unit;
1231         }
1232 }
1233
1234 static void dispc_ovl_set_fir(enum omap_plane plane,
1235                                 int hinc, int vinc,
1236                                 enum omap_color_component color_comp)
1237 {
1238         u32 val;
1239
1240         if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1241                 u8 hinc_start, hinc_end, vinc_start, vinc_end;
1242
1243                 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1244                                         &hinc_start, &hinc_end);
1245                 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1246                                         &vinc_start, &vinc_end);
1247                 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1248                                 FLD_VAL(hinc, hinc_start, hinc_end);
1249
1250                 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1251         } else {
1252                 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1253                 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1254         }
1255 }
1256
1257 static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1258 {
1259         u32 val;
1260         u8 hor_start, hor_end, vert_start, vert_end;
1261
1262         dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1263         dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1264
1265         val = FLD_VAL(vaccu, vert_start, vert_end) |
1266                         FLD_VAL(haccu, hor_start, hor_end);
1267
1268         dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
1269 }
1270
1271 static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1272 {
1273         u32 val;
1274         u8 hor_start, hor_end, vert_start, vert_end;
1275
1276         dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1277         dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1278
1279         val = FLD_VAL(vaccu, vert_start, vert_end) |
1280                         FLD_VAL(haccu, hor_start, hor_end);
1281
1282         dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
1283 }
1284
1285 static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1286                 int vaccu)
1287 {
1288         u32 val;
1289
1290         val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1291         dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1292 }
1293
1294 static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1295                 int vaccu)
1296 {
1297         u32 val;
1298
1299         val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1300         dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1301 }
1302
1303 static void dispc_ovl_set_scale_param(enum omap_plane plane,
1304                 u16 orig_width, u16 orig_height,
1305                 u16 out_width, u16 out_height,
1306                 bool five_taps, u8 rotation,
1307                 enum omap_color_component color_comp)
1308 {
1309         int fir_hinc, fir_vinc;
1310
1311         fir_hinc = 1024 * orig_width / out_width;
1312         fir_vinc = 1024 * orig_height / out_height;
1313
1314         dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1315                                 color_comp);
1316         dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
1317 }
1318
1319 static void dispc_ovl_set_accu_uv(enum omap_plane plane,
1320                 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
1321                 bool ilace, enum omap_color_mode color_mode, u8 rotation)
1322 {
1323         int h_accu2_0, h_accu2_1;
1324         int v_accu2_0, v_accu2_1;
1325         int chroma_hinc, chroma_vinc;
1326         int idx;
1327
1328         struct accu {
1329                 s8 h0_m, h0_n;
1330                 s8 h1_m, h1_n;
1331                 s8 v0_m, v0_n;
1332                 s8 v1_m, v1_n;
1333         };
1334
1335         const struct accu *accu_table;
1336         const struct accu *accu_val;
1337
1338         static const struct accu accu_nv12[4] = {
1339                 {  0, 1,  0, 1 , -1, 2, 0, 1 },
1340                 {  1, 2, -3, 4 ,  0, 1, 0, 1 },
1341                 { -1, 1,  0, 1 , -1, 2, 0, 1 },
1342                 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1343         };
1344
1345         static const struct accu accu_nv12_ilace[4] = {
1346                 {  0, 1,  0, 1 , -3, 4, -1, 4 },
1347                 { -1, 4, -3, 4 ,  0, 1,  0, 1 },
1348                 { -1, 1,  0, 1 , -1, 4, -3, 4 },
1349                 { -3, 4, -3, 4 , -1, 1,  0, 1 },
1350         };
1351
1352         static const struct accu accu_yuv[4] = {
1353                 {  0, 1, 0, 1,  0, 1, 0, 1 },
1354                 {  0, 1, 0, 1,  0, 1, 0, 1 },
1355                 { -1, 1, 0, 1,  0, 1, 0, 1 },
1356                 {  0, 1, 0, 1, -1, 1, 0, 1 },
1357         };
1358
1359         switch (rotation) {
1360         case OMAP_DSS_ROT_0:
1361                 idx = 0;
1362                 break;
1363         case OMAP_DSS_ROT_90:
1364                 idx = 1;
1365                 break;
1366         case OMAP_DSS_ROT_180:
1367                 idx = 2;
1368                 break;
1369         case OMAP_DSS_ROT_270:
1370                 idx = 3;
1371                 break;
1372         default:
1373                 BUG();
1374                 return;
1375         }
1376
1377         switch (color_mode) {
1378         case OMAP_DSS_COLOR_NV12:
1379                 if (ilace)
1380                         accu_table = accu_nv12_ilace;
1381                 else
1382                         accu_table = accu_nv12;
1383                 break;
1384         case OMAP_DSS_COLOR_YUV2:
1385         case OMAP_DSS_COLOR_UYVY:
1386                 accu_table = accu_yuv;
1387                 break;
1388         default:
1389                 BUG();
1390                 return;
1391         }
1392
1393         accu_val = &accu_table[idx];
1394
1395         chroma_hinc = 1024 * orig_width / out_width;
1396         chroma_vinc = 1024 * orig_height / out_height;
1397
1398         h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1399         h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1400         v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1401         v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1402
1403         dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
1404         dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
1405 }
1406
1407 static void dispc_ovl_set_scaling_common(enum omap_plane plane,
1408                 u16 orig_width, u16 orig_height,
1409                 u16 out_width, u16 out_height,
1410                 bool ilace, bool five_taps,
1411                 bool fieldmode, enum omap_color_mode color_mode,
1412                 u8 rotation)
1413 {
1414         int accu0 = 0;
1415         int accu1 = 0;
1416         u32 l;
1417
1418         dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1419                                 out_width, out_height, five_taps,
1420                                 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
1421         l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1422
1423         /* RESIZEENABLE and VERTICALTAPS */
1424         l &= ~((0x3 << 5) | (0x1 << 21));
1425         l |= (orig_width != out_width) ? (1 << 5) : 0;
1426         l |= (orig_height != out_height) ? (1 << 6) : 0;
1427         l |= five_taps ? (1 << 21) : 0;
1428
1429         /* VRESIZECONF and HRESIZECONF */
1430         if (dss_has_feature(FEAT_RESIZECONF)) {
1431                 l &= ~(0x3 << 7);
1432                 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1433                 l |= (orig_height <= out_height) ? 0 : (1 << 8);
1434         }
1435
1436         /* LINEBUFFERSPLIT */
1437         if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1438                 l &= ~(0x1 << 22);
1439                 l |= five_taps ? (1 << 22) : 0;
1440         }
1441
1442         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
1443
1444         /*
1445          * field 0 = even field = bottom field
1446          * field 1 = odd field = top field
1447          */
1448         if (ilace && !fieldmode) {
1449                 accu1 = 0;
1450                 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
1451                 if (accu0 >= 1024/2) {
1452                         accu1 = 1024/2;
1453                         accu0 -= accu1;
1454                 }
1455         }
1456
1457         dispc_ovl_set_vid_accu0(plane, 0, accu0);
1458         dispc_ovl_set_vid_accu1(plane, 0, accu1);
1459 }
1460
1461 static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
1462                 u16 orig_width, u16 orig_height,
1463                 u16 out_width, u16 out_height,
1464                 bool ilace, bool five_taps,
1465                 bool fieldmode, enum omap_color_mode color_mode,
1466                 u8 rotation)
1467 {
1468         int scale_x = out_width != orig_width;
1469         int scale_y = out_height != orig_height;
1470         bool chroma_upscale = plane != OMAP_DSS_WB ? true : false;
1471
1472         if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1473                 return;
1474         if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1475                         color_mode != OMAP_DSS_COLOR_UYVY &&
1476                         color_mode != OMAP_DSS_COLOR_NV12)) {
1477                 /* reset chroma resampling for RGB formats  */
1478                 if (plane != OMAP_DSS_WB)
1479                         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1480                 return;
1481         }
1482
1483         dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
1484                         out_height, ilace, color_mode, rotation);
1485
1486         switch (color_mode) {
1487         case OMAP_DSS_COLOR_NV12:
1488                 if (chroma_upscale) {
1489                         /* UV is subsampled by 2 horizontally and vertically */
1490                         orig_height >>= 1;
1491                         orig_width >>= 1;
1492                 } else {
1493                         /* UV is downsampled by 2 horizontally and vertically */
1494                         orig_height <<= 1;
1495                         orig_width <<= 1;
1496                 }
1497
1498                 break;
1499         case OMAP_DSS_COLOR_YUV2:
1500         case OMAP_DSS_COLOR_UYVY:
1501                 /* For YUV422 with 90/270 rotation, we don't upsample chroma */
1502                 if (rotation == OMAP_DSS_ROT_0 ||
1503                                 rotation == OMAP_DSS_ROT_180) {
1504                         if (chroma_upscale)
1505                                 /* UV is subsampled by 2 horizontally */
1506                                 orig_width >>= 1;
1507                         else
1508                                 /* UV is downsampled by 2 horizontally */
1509                                 orig_width <<= 1;
1510                 }
1511
1512                 /* must use FIR for YUV422 if rotated */
1513                 if (rotation != OMAP_DSS_ROT_0)
1514                         scale_x = scale_y = true;
1515
1516                 break;
1517         default:
1518                 BUG();
1519                 return;
1520         }
1521
1522         if (out_width != orig_width)
1523                 scale_x = true;
1524         if (out_height != orig_height)
1525                 scale_y = true;
1526
1527         dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1528                         out_width, out_height, five_taps,
1529                                 rotation, DISPC_COLOR_COMPONENT_UV);
1530
1531         if (plane != OMAP_DSS_WB)
1532                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1533                         (scale_x || scale_y) ? 1 : 0, 8, 8);
1534
1535         /* set H scaling */
1536         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1537         /* set V scaling */
1538         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1539 }
1540
1541 static void dispc_ovl_set_scaling(enum omap_plane plane,
1542                 u16 orig_width, u16 orig_height,
1543                 u16 out_width, u16 out_height,
1544                 bool ilace, bool five_taps,
1545                 bool fieldmode, enum omap_color_mode color_mode,
1546                 u8 rotation)
1547 {
1548         BUG_ON(plane == OMAP_DSS_GFX);
1549
1550         dispc_ovl_set_scaling_common(plane,
1551                         orig_width, orig_height,
1552                         out_width, out_height,
1553                         ilace, five_taps,
1554                         fieldmode, color_mode,
1555                         rotation);
1556
1557         dispc_ovl_set_scaling_uv(plane,
1558                 orig_width, orig_height,
1559                 out_width, out_height,
1560                 ilace, five_taps,
1561                 fieldmode, color_mode,
1562                 rotation);
1563 }
1564
1565 static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1566                 bool mirroring, enum omap_color_mode color_mode)
1567 {
1568         bool row_repeat = false;
1569         int vidrot = 0;
1570
1571         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1572                         color_mode == OMAP_DSS_COLOR_UYVY) {
1573
1574                 if (mirroring) {
1575                         switch (rotation) {
1576                         case OMAP_DSS_ROT_0:
1577                                 vidrot = 2;
1578                                 break;
1579                         case OMAP_DSS_ROT_90:
1580                                 vidrot = 1;
1581                                 break;
1582                         case OMAP_DSS_ROT_180:
1583                                 vidrot = 0;
1584                                 break;
1585                         case OMAP_DSS_ROT_270:
1586                                 vidrot = 3;
1587                                 break;
1588                         }
1589                 } else {
1590                         switch (rotation) {
1591                         case OMAP_DSS_ROT_0:
1592                                 vidrot = 0;
1593                                 break;
1594                         case OMAP_DSS_ROT_90:
1595                                 vidrot = 1;
1596                                 break;
1597                         case OMAP_DSS_ROT_180:
1598                                 vidrot = 2;
1599                                 break;
1600                         case OMAP_DSS_ROT_270:
1601                                 vidrot = 3;
1602                                 break;
1603                         }
1604                 }
1605
1606                 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1607                         row_repeat = true;
1608                 else
1609                         row_repeat = false;
1610         }
1611
1612         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
1613         if (dss_has_feature(FEAT_ROWREPEATENABLE))
1614                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1615                         row_repeat ? 1 : 0, 18, 18);
1616 }
1617
1618 static int color_mode_to_bpp(enum omap_color_mode color_mode)
1619 {
1620         switch (color_mode) {
1621         case OMAP_DSS_COLOR_CLUT1:
1622                 return 1;
1623         case OMAP_DSS_COLOR_CLUT2:
1624                 return 2;
1625         case OMAP_DSS_COLOR_CLUT4:
1626                 return 4;
1627         case OMAP_DSS_COLOR_CLUT8:
1628         case OMAP_DSS_COLOR_NV12:
1629                 return 8;
1630         case OMAP_DSS_COLOR_RGB12U:
1631         case OMAP_DSS_COLOR_RGB16:
1632         case OMAP_DSS_COLOR_ARGB16:
1633         case OMAP_DSS_COLOR_YUV2:
1634         case OMAP_DSS_COLOR_UYVY:
1635         case OMAP_DSS_COLOR_RGBA16:
1636         case OMAP_DSS_COLOR_RGBX16:
1637         case OMAP_DSS_COLOR_ARGB16_1555:
1638         case OMAP_DSS_COLOR_XRGB16_1555:
1639                 return 16;
1640         case OMAP_DSS_COLOR_RGB24P:
1641                 return 24;
1642         case OMAP_DSS_COLOR_RGB24U:
1643         case OMAP_DSS_COLOR_ARGB32:
1644         case OMAP_DSS_COLOR_RGBA32:
1645         case OMAP_DSS_COLOR_RGBX32:
1646                 return 32;
1647         default:
1648                 BUG();
1649                 return 0;
1650         }
1651 }
1652
1653 static s32 pixinc(int pixels, u8 ps)
1654 {
1655         if (pixels == 1)
1656                 return 1;
1657         else if (pixels > 1)
1658                 return 1 + (pixels - 1) * ps;
1659         else if (pixels < 0)
1660                 return 1 - (-pixels + 1) * ps;
1661         else
1662                 BUG();
1663                 return 0;
1664 }
1665
1666 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1667                 u16 screen_width,
1668                 u16 width, u16 height,
1669                 enum omap_color_mode color_mode, bool fieldmode,
1670                 unsigned int field_offset,
1671                 unsigned *offset0, unsigned *offset1,
1672                 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1673 {
1674         u8 ps;
1675
1676         /* FIXME CLUT formats */
1677         switch (color_mode) {
1678         case OMAP_DSS_COLOR_CLUT1:
1679         case OMAP_DSS_COLOR_CLUT2:
1680         case OMAP_DSS_COLOR_CLUT4:
1681         case OMAP_DSS_COLOR_CLUT8:
1682                 BUG();
1683                 return;
1684         case OMAP_DSS_COLOR_YUV2:
1685         case OMAP_DSS_COLOR_UYVY:
1686                 ps = 4;
1687                 break;
1688         default:
1689                 ps = color_mode_to_bpp(color_mode) / 8;
1690                 break;
1691         }
1692
1693         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1694                         width, height);
1695
1696         /*
1697          * field 0 = even field = bottom field
1698          * field 1 = odd field = top field
1699          */
1700         switch (rotation + mirror * 4) {
1701         case OMAP_DSS_ROT_0:
1702         case OMAP_DSS_ROT_180:
1703                 /*
1704                  * If the pixel format is YUV or UYVY divide the width
1705                  * of the image by 2 for 0 and 180 degree rotation.
1706                  */
1707                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1708                         color_mode == OMAP_DSS_COLOR_UYVY)
1709                         width = width >> 1;
1710         case OMAP_DSS_ROT_90:
1711         case OMAP_DSS_ROT_270:
1712                 *offset1 = 0;
1713                 if (field_offset)
1714                         *offset0 = field_offset * screen_width * ps;
1715                 else
1716                         *offset0 = 0;
1717
1718                 *row_inc = pixinc(1 +
1719                         (y_predecim * screen_width - x_predecim * width) +
1720                         (fieldmode ? screen_width : 0), ps);
1721                 *pix_inc = pixinc(x_predecim, ps);
1722                 break;
1723
1724         case OMAP_DSS_ROT_0 + 4:
1725         case OMAP_DSS_ROT_180 + 4:
1726                 /* If the pixel format is YUV or UYVY divide the width
1727                  * of the image by 2  for 0 degree and 180 degree
1728                  */
1729                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1730                         color_mode == OMAP_DSS_COLOR_UYVY)
1731                         width = width >> 1;
1732         case OMAP_DSS_ROT_90 + 4:
1733         case OMAP_DSS_ROT_270 + 4:
1734                 *offset1 = 0;
1735                 if (field_offset)
1736                         *offset0 = field_offset * screen_width * ps;
1737                 else
1738                         *offset0 = 0;
1739                 *row_inc = pixinc(1 -
1740                         (y_predecim * screen_width + x_predecim * width) -
1741                         (fieldmode ? screen_width : 0), ps);
1742                 *pix_inc = pixinc(x_predecim, ps);
1743                 break;
1744
1745         default:
1746                 BUG();
1747                 return;
1748         }
1749 }
1750
1751 static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1752                 u16 screen_width,
1753                 u16 width, u16 height,
1754                 enum omap_color_mode color_mode, bool fieldmode,
1755                 unsigned int field_offset,
1756                 unsigned *offset0, unsigned *offset1,
1757                 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1758 {
1759         u8 ps;
1760         u16 fbw, fbh;
1761
1762         /* FIXME CLUT formats */
1763         switch (color_mode) {
1764         case OMAP_DSS_COLOR_CLUT1:
1765         case OMAP_DSS_COLOR_CLUT2:
1766         case OMAP_DSS_COLOR_CLUT4:
1767         case OMAP_DSS_COLOR_CLUT8:
1768                 BUG();
1769                 return;
1770         default:
1771                 ps = color_mode_to_bpp(color_mode) / 8;
1772                 break;
1773         }
1774
1775         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1776                         width, height);
1777
1778         /* width & height are overlay sizes, convert to fb sizes */
1779
1780         if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1781                 fbw = width;
1782                 fbh = height;
1783         } else {
1784                 fbw = height;
1785                 fbh = width;
1786         }
1787
1788         /*
1789          * field 0 = even field = bottom field
1790          * field 1 = odd field = top field
1791          */
1792         switch (rotation + mirror * 4) {
1793         case OMAP_DSS_ROT_0:
1794                 *offset1 = 0;
1795                 if (field_offset)
1796                         *offset0 = *offset1 + field_offset * screen_width * ps;
1797                 else
1798                         *offset0 = *offset1;
1799                 *row_inc = pixinc(1 +
1800                         (y_predecim * screen_width - fbw * x_predecim) +
1801                         (fieldmode ? screen_width : 0), ps);
1802                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1803                         color_mode == OMAP_DSS_COLOR_UYVY)
1804                         *pix_inc = pixinc(x_predecim, 2 * ps);
1805                 else
1806                         *pix_inc = pixinc(x_predecim, ps);
1807                 break;
1808         case OMAP_DSS_ROT_90:
1809                 *offset1 = screen_width * (fbh - 1) * ps;
1810                 if (field_offset)
1811                         *offset0 = *offset1 + field_offset * ps;
1812                 else
1813                         *offset0 = *offset1;
1814                 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
1815                                 y_predecim + (fieldmode ? 1 : 0), ps);
1816                 *pix_inc = pixinc(-x_predecim * screen_width, ps);
1817                 break;
1818         case OMAP_DSS_ROT_180:
1819                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1820                 if (field_offset)
1821                         *offset0 = *offset1 - field_offset * screen_width * ps;
1822                 else
1823                         *offset0 = *offset1;
1824                 *row_inc = pixinc(-1 -
1825                         (y_predecim * screen_width - fbw * x_predecim) -
1826                         (fieldmode ? screen_width : 0), ps);
1827                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1828                         color_mode == OMAP_DSS_COLOR_UYVY)
1829                         *pix_inc = pixinc(-x_predecim, 2 * ps);
1830                 else
1831                         *pix_inc = pixinc(-x_predecim, ps);
1832                 break;
1833         case OMAP_DSS_ROT_270:
1834                 *offset1 = (fbw - 1) * ps;
1835                 if (field_offset)
1836                         *offset0 = *offset1 - field_offset * ps;
1837                 else
1838                         *offset0 = *offset1;
1839                 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
1840                                 y_predecim - (fieldmode ? 1 : 0), ps);
1841                 *pix_inc = pixinc(x_predecim * screen_width, ps);
1842                 break;
1843
1844         /* mirroring */
1845         case OMAP_DSS_ROT_0 + 4:
1846                 *offset1 = (fbw - 1) * ps;
1847                 if (field_offset)
1848                         *offset0 = *offset1 + field_offset * screen_width * ps;
1849                 else
1850                         *offset0 = *offset1;
1851                 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
1852                                 (fieldmode ? screen_width : 0),
1853                                 ps);
1854                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1855                         color_mode == OMAP_DSS_COLOR_UYVY)
1856                         *pix_inc = pixinc(-x_predecim, 2 * ps);
1857                 else
1858                         *pix_inc = pixinc(-x_predecim, ps);
1859                 break;
1860
1861         case OMAP_DSS_ROT_90 + 4:
1862                 *offset1 = 0;
1863                 if (field_offset)
1864                         *offset0 = *offset1 + field_offset * ps;
1865                 else
1866                         *offset0 = *offset1;
1867                 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
1868                                 y_predecim + (fieldmode ? 1 : 0),
1869                                 ps);
1870                 *pix_inc = pixinc(x_predecim * screen_width, ps);
1871                 break;
1872
1873         case OMAP_DSS_ROT_180 + 4:
1874                 *offset1 = screen_width * (fbh - 1) * ps;
1875                 if (field_offset)
1876                         *offset0 = *offset1 - field_offset * screen_width * ps;
1877                 else
1878                         *offset0 = *offset1;
1879                 *row_inc = pixinc(1 - y_predecim * screen_width * 2 -
1880                                 (fieldmode ? screen_width : 0),
1881                                 ps);
1882                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1883                         color_mode == OMAP_DSS_COLOR_UYVY)
1884                         *pix_inc = pixinc(x_predecim, 2 * ps);
1885                 else
1886                         *pix_inc = pixinc(x_predecim, ps);
1887                 break;
1888
1889         case OMAP_DSS_ROT_270 + 4:
1890                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1891                 if (field_offset)
1892                         *offset0 = *offset1 - field_offset * ps;
1893                 else
1894                         *offset0 = *offset1;
1895                 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
1896                                 y_predecim - (fieldmode ? 1 : 0),
1897                                 ps);
1898                 *pix_inc = pixinc(-x_predecim * screen_width, ps);
1899                 break;
1900
1901         default:
1902                 BUG();
1903                 return;
1904         }
1905 }
1906
1907 static void calc_tiler_rotation_offset(u16 screen_width, u16 width,
1908                 enum omap_color_mode color_mode, bool fieldmode,
1909                 unsigned int field_offset, unsigned *offset0, unsigned *offset1,
1910                 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1911 {
1912         u8 ps;
1913
1914         switch (color_mode) {
1915         case OMAP_DSS_COLOR_CLUT1:
1916         case OMAP_DSS_COLOR_CLUT2:
1917         case OMAP_DSS_COLOR_CLUT4:
1918         case OMAP_DSS_COLOR_CLUT8:
1919                 BUG();
1920                 return;
1921         default:
1922                 ps = color_mode_to_bpp(color_mode) / 8;
1923                 break;
1924         }
1925
1926         DSSDBG("scrw %d, width %d\n", screen_width, width);
1927
1928         /*
1929          * field 0 = even field = bottom field
1930          * field 1 = odd field = top field
1931          */
1932         *offset1 = 0;
1933         if (field_offset)
1934                 *offset0 = *offset1 + field_offset * screen_width * ps;
1935         else
1936                 *offset0 = *offset1;
1937         *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) +
1938                         (fieldmode ? screen_width : 0), ps);
1939         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1940                 color_mode == OMAP_DSS_COLOR_UYVY)
1941                 *pix_inc = pixinc(x_predecim, 2 * ps);
1942         else
1943                 *pix_inc = pixinc(x_predecim, ps);
1944 }
1945
1946 /*
1947  * This function is used to avoid synclosts in OMAP3, because of some
1948  * undocumented horizontal position and timing related limitations.
1949  */
1950 static int check_horiz_timing_omap3(enum omap_plane plane,
1951                 const struct omap_video_timings *t, u16 pos_x,
1952                 u16 width, u16 height, u16 out_width, u16 out_height)
1953 {
1954         int DS = DIV_ROUND_UP(height, out_height);
1955         unsigned long nonactive;
1956         static const u8 limits[3] = { 8, 10, 20 };
1957         u64 val, blank;
1958         unsigned long pclk = dispc_plane_pclk_rate(plane);
1959         unsigned long lclk = dispc_plane_lclk_rate(plane);
1960         int i;
1961
1962         nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
1963
1964         i = 0;
1965         if (out_height < height)
1966                 i++;
1967         if (out_width < width)
1968                 i++;
1969         blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
1970         DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
1971         if (blank <= limits[i])
1972                 return -EINVAL;
1973
1974         /*
1975          * Pixel data should be prepared before visible display point starts.
1976          * So, atleast DS-2 lines must have already been fetched by DISPC
1977          * during nonactive - pos_x period.
1978          */
1979         val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
1980         DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
1981                 val, max(0, DS - 2) * width);
1982         if (val < max(0, DS - 2) * width)
1983                 return -EINVAL;
1984
1985         /*
1986          * All lines need to be refilled during the nonactive period of which
1987          * only one line can be loaded during the active period. So, atleast
1988          * DS - 1 lines should be loaded during nonactive period.
1989          */
1990         val =  div_u64((u64)nonactive * lclk, pclk);
1991         DSSDBG("nonactive * pcd  = %llu, max(0, DS - 1) * width = %d\n",
1992                 val, max(0, DS - 1) * width);
1993         if (val < max(0, DS - 1) * width)
1994                 return -EINVAL;
1995
1996         return 0;
1997 }
1998
1999 static unsigned long calc_core_clk_five_taps(enum omap_plane plane,
2000                 const struct omap_video_timings *mgr_timings, u16 width,
2001                 u16 height, u16 out_width, u16 out_height,
2002                 enum omap_color_mode color_mode)
2003 {
2004         u32 core_clk = 0;
2005         u64 tmp;
2006         unsigned long pclk = dispc_plane_pclk_rate(plane);
2007
2008         if (height <= out_height && width <= out_width)
2009                 return (unsigned long) pclk;
2010
2011         if (height > out_height) {
2012                 unsigned int ppl = mgr_timings->x_res;
2013
2014                 tmp = pclk * height * out_width;
2015                 do_div(tmp, 2 * out_height * ppl);
2016                 core_clk = tmp;
2017
2018                 if (height > 2 * out_height) {
2019                         if (ppl == out_width)
2020                                 return 0;
2021
2022                         tmp = pclk * (height - 2 * out_height) * out_width;
2023                         do_div(tmp, 2 * out_height * (ppl - out_width));
2024                         core_clk = max_t(u32, core_clk, tmp);
2025                 }
2026         }
2027
2028         if (width > out_width) {
2029                 tmp = pclk * width;
2030                 do_div(tmp, out_width);
2031                 core_clk = max_t(u32, core_clk, tmp);
2032
2033                 if (color_mode == OMAP_DSS_COLOR_RGB24U)
2034                         core_clk <<= 1;
2035         }
2036
2037         return core_clk;
2038 }
2039
2040 static unsigned long calc_core_clk_24xx(enum omap_plane plane, u16 width,
2041                 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2042 {
2043         unsigned long pclk = dispc_plane_pclk_rate(plane);
2044
2045         if (height > out_height && width > out_width)
2046                 return pclk * 4;
2047         else
2048                 return pclk * 2;
2049 }
2050
2051 static unsigned long calc_core_clk_34xx(enum omap_plane plane, u16 width,
2052                 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2053 {
2054         unsigned int hf, vf;
2055         unsigned long pclk = dispc_plane_pclk_rate(plane);
2056
2057         /*
2058          * FIXME how to determine the 'A' factor
2059          * for the no downscaling case ?
2060          */
2061
2062         if (width > 3 * out_width)
2063                 hf = 4;
2064         else if (width > 2 * out_width)
2065                 hf = 3;
2066         else if (width > out_width)
2067                 hf = 2;
2068         else
2069                 hf = 1;
2070         if (height > out_height)
2071                 vf = 2;
2072         else
2073                 vf = 1;
2074
2075         return pclk * vf * hf;
2076 }
2077
2078 static unsigned long calc_core_clk_44xx(enum omap_plane plane, u16 width,
2079                 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2080 {
2081         unsigned long pclk;
2082
2083         /*
2084          * If the overlay/writeback is in mem to mem mode, there are no
2085          * downscaling limitations with respect to pixel clock, return 1 as
2086          * required core clock to represent that we have sufficient enough
2087          * core clock to do maximum downscaling
2088          */
2089         if (mem_to_mem)
2090                 return 1;
2091
2092         pclk = dispc_plane_pclk_rate(plane);
2093
2094         if (width > out_width)
2095                 return DIV_ROUND_UP(pclk, out_width) * width;
2096         else
2097                 return pclk;
2098 }
2099
2100 static int dispc_ovl_calc_scaling_24xx(enum omap_plane plane,
2101                 const struct omap_video_timings *mgr_timings,
2102                 u16 width, u16 height, u16 out_width, u16 out_height,
2103                 enum omap_color_mode color_mode, bool *five_taps,
2104                 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2105                 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2106 {
2107         int error;
2108         u16 in_width, in_height;
2109         int min_factor = min(*decim_x, *decim_y);
2110         const int maxsinglelinewidth =
2111                         dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2112
2113         *five_taps = false;
2114
2115         do {
2116                 in_height = DIV_ROUND_UP(height, *decim_y);
2117                 in_width = DIV_ROUND_UP(width, *decim_x);
2118                 *core_clk = dispc.feat->calc_core_clk(plane, in_width,
2119                                 in_height, out_width, out_height, mem_to_mem);
2120                 error = (in_width > maxsinglelinewidth || !*core_clk ||
2121                         *core_clk > dispc_core_clk_rate());
2122                 if (error) {
2123                         if (*decim_x == *decim_y) {
2124                                 *decim_x = min_factor;
2125                                 ++*decim_y;
2126                         } else {
2127                                 swap(*decim_x, *decim_y);
2128                                 if (*decim_x < *decim_y)
2129                                         ++*decim_x;
2130                         }
2131                 }
2132         } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2133
2134         if (in_width > maxsinglelinewidth) {
2135                 DSSERR("Cannot scale max input width exceeded");
2136                 return -EINVAL;
2137         }
2138         return 0;
2139 }
2140
2141 static int dispc_ovl_calc_scaling_34xx(enum omap_plane plane,
2142                 const struct omap_video_timings *mgr_timings,
2143                 u16 width, u16 height, u16 out_width, u16 out_height,
2144                 enum omap_color_mode color_mode, bool *five_taps,
2145                 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2146                 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2147 {
2148         int error;
2149         u16 in_width, in_height;
2150         int min_factor = min(*decim_x, *decim_y);
2151         const int maxsinglelinewidth =
2152                         dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2153
2154         do {
2155                 in_height = DIV_ROUND_UP(height, *decim_y);
2156                 in_width = DIV_ROUND_UP(width, *decim_x);
2157                 *core_clk = calc_core_clk_five_taps(plane, mgr_timings,
2158                         in_width, in_height, out_width, out_height, color_mode);
2159
2160                 error = check_horiz_timing_omap3(plane, mgr_timings,
2161                                 pos_x, in_width, in_height, out_width,
2162                                 out_height);
2163
2164                 if (in_width > maxsinglelinewidth)
2165                         if (in_height > out_height &&
2166                                                 in_height < out_height * 2)
2167                                 *five_taps = false;
2168                 if (!*five_taps)
2169                         *core_clk = dispc.feat->calc_core_clk(plane, in_width,
2170                                         in_height, out_width, out_height,
2171                                         mem_to_mem);
2172
2173                 error = (error || in_width > maxsinglelinewidth * 2 ||
2174                         (in_width > maxsinglelinewidth && *five_taps) ||
2175                         !*core_clk || *core_clk > dispc_core_clk_rate());
2176                 if (error) {
2177                         if (*decim_x == *decim_y) {
2178                                 *decim_x = min_factor;
2179                                 ++*decim_y;
2180                         } else {
2181                                 swap(*decim_x, *decim_y);
2182                                 if (*decim_x < *decim_y)
2183                                         ++*decim_x;
2184                         }
2185                 }
2186         } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2187
2188         if (check_horiz_timing_omap3(plane, mgr_timings, pos_x, width, height,
2189                 out_width, out_height)){
2190                         DSSERR("horizontal timing too tight\n");
2191                         return -EINVAL;
2192         }
2193
2194         if (in_width > (maxsinglelinewidth * 2)) {
2195                 DSSERR("Cannot setup scaling");
2196                 DSSERR("width exceeds maximum width possible");
2197                 return -EINVAL;
2198         }
2199
2200         if (in_width > maxsinglelinewidth && *five_taps) {
2201                 DSSERR("cannot setup scaling with five taps");
2202                 return -EINVAL;
2203         }
2204         return 0;
2205 }
2206
2207 static int dispc_ovl_calc_scaling_44xx(enum omap_plane plane,
2208                 const struct omap_video_timings *mgr_timings,
2209                 u16 width, u16 height, u16 out_width, u16 out_height,
2210                 enum omap_color_mode color_mode, bool *five_taps,
2211                 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2212                 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2213 {
2214         u16 in_width, in_width_max;
2215         int decim_x_min = *decim_x;
2216         u16 in_height = DIV_ROUND_UP(height, *decim_y);
2217         const int maxsinglelinewidth =
2218                                 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2219         unsigned long pclk = dispc_plane_pclk_rate(plane);
2220         const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
2221
2222         if (mem_to_mem)
2223                 in_width_max = DIV_ROUND_UP(out_width, maxdownscale);
2224         else
2225                 in_width_max = dispc_core_clk_rate() /
2226                                         DIV_ROUND_UP(pclk, out_width);
2227
2228         *decim_x = DIV_ROUND_UP(width, in_width_max);
2229
2230         *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min;
2231         if (*decim_x > *x_predecim)
2232                 return -EINVAL;
2233
2234         do {
2235                 in_width = DIV_ROUND_UP(width, *decim_x);
2236         } while (*decim_x <= *x_predecim &&
2237                         in_width > maxsinglelinewidth && ++*decim_x);
2238
2239         if (in_width > maxsinglelinewidth) {
2240                 DSSERR("Cannot scale width exceeds max line width");
2241                 return -EINVAL;
2242         }
2243
2244         *core_clk = dispc.feat->calc_core_clk(plane, in_width, in_height,
2245                                 out_width, out_height, mem_to_mem);
2246         return 0;
2247 }
2248
2249 static int dispc_ovl_calc_scaling(enum omap_plane plane,
2250                 enum omap_overlay_caps caps,
2251                 const struct omap_video_timings *mgr_timings,
2252                 u16 width, u16 height, u16 out_width, u16 out_height,
2253                 enum omap_color_mode color_mode, bool *five_taps,
2254                 int *x_predecim, int *y_predecim, u16 pos_x,
2255                 enum omap_dss_rotation_type rotation_type, bool mem_to_mem)
2256 {
2257         const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
2258         const int max_decim_limit = 16;
2259         unsigned long core_clk = 0;
2260         int decim_x, decim_y, ret;
2261
2262         if (width == out_width && height == out_height)
2263                 return 0;
2264
2265         if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
2266                 return -EINVAL;
2267
2268         *x_predecim = max_decim_limit;
2269         *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER &&
2270                         dss_has_feature(FEAT_BURST_2D)) ? 2 : max_decim_limit;
2271
2272         if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
2273             color_mode == OMAP_DSS_COLOR_CLUT2 ||
2274             color_mode == OMAP_DSS_COLOR_CLUT4 ||
2275             color_mode == OMAP_DSS_COLOR_CLUT8) {
2276                 *x_predecim = 1;
2277                 *y_predecim = 1;
2278                 *five_taps = false;
2279                 return 0;
2280         }
2281
2282         decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
2283         decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
2284
2285         if (decim_x > *x_predecim || out_width > width * 8)
2286                 return -EINVAL;
2287
2288         if (decim_y > *y_predecim || out_height > height * 8)
2289                 return -EINVAL;
2290
2291         ret = dispc.feat->calc_scaling(plane, mgr_timings, width, height,
2292                 out_width, out_height, color_mode, five_taps,
2293                 x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk,
2294                 mem_to_mem);
2295         if (ret)
2296                 return ret;
2297
2298         DSSDBG("required core clk rate = %lu Hz\n", core_clk);
2299         DSSDBG("current core clk rate = %lu Hz\n", dispc_core_clk_rate());
2300
2301         if (!core_clk || core_clk > dispc_core_clk_rate()) {
2302                 DSSERR("failed to set up scaling, "
2303                         "required core clk rate = %lu Hz, "
2304                         "current core clk rate = %lu Hz\n",
2305                         core_clk, dispc_core_clk_rate());
2306                 return -EINVAL;
2307         }
2308
2309         *x_predecim = decim_x;
2310         *y_predecim = decim_y;
2311         return 0;
2312 }
2313
2314 static int dispc_ovl_setup_common(enum omap_plane plane,
2315                 enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr,
2316                 u16 screen_width, int pos_x, int pos_y, u16 width, u16 height,
2317                 u16 out_width, u16 out_height, enum omap_color_mode color_mode,
2318                 u8 rotation, bool mirror, u8 zorder, u8 pre_mult_alpha,
2319                 u8 global_alpha, enum omap_dss_rotation_type rotation_type,
2320                 bool replication, const struct omap_video_timings *mgr_timings,
2321                 bool mem_to_mem)
2322 {
2323         bool five_taps = true;
2324         bool fieldmode = 0;
2325         int r, cconv = 0;
2326         unsigned offset0, offset1;
2327         s32 row_inc;
2328         s32 pix_inc;
2329         u16 frame_height = height;
2330         unsigned int field_offset = 0;
2331         u16 in_height = height;
2332         u16 in_width = width;
2333         int x_predecim = 1, y_predecim = 1;
2334         bool ilace = mgr_timings->interlace;
2335
2336         if (paddr == 0)
2337                 return -EINVAL;
2338
2339         out_width = out_width == 0 ? width : out_width;
2340         out_height = out_height == 0 ? height : out_height;
2341
2342         if (ilace && height == out_height)
2343                 fieldmode = 1;
2344
2345         if (ilace) {
2346                 if (fieldmode)
2347                         in_height /= 2;
2348                 pos_y /= 2;
2349                 out_height /= 2;
2350
2351                 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
2352                         "out_height %d\n", in_height, pos_y,
2353                         out_height);
2354         }
2355
2356         if (!dss_feat_color_mode_supported(plane, color_mode))
2357                 return -EINVAL;
2358
2359         r = dispc_ovl_calc_scaling(plane, caps, mgr_timings, in_width,
2360                         in_height, out_width, out_height, color_mode,
2361                         &five_taps, &x_predecim, &y_predecim, pos_x,
2362                         rotation_type, mem_to_mem);
2363         if (r)
2364                 return r;
2365
2366         in_width = DIV_ROUND_UP(in_width, x_predecim);
2367         in_height = DIV_ROUND_UP(in_height, y_predecim);
2368
2369         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2370                         color_mode == OMAP_DSS_COLOR_UYVY ||
2371                         color_mode == OMAP_DSS_COLOR_NV12)
2372                 cconv = 1;
2373
2374         if (ilace && !fieldmode) {
2375                 /*
2376                  * when downscaling the bottom field may have to start several
2377                  * source lines below the top field. Unfortunately ACCUI
2378                  * registers will only hold the fractional part of the offset
2379                  * so the integer part must be added to the base address of the
2380                  * bottom field.
2381                  */
2382                 if (!in_height || in_height == out_height)
2383                         field_offset = 0;
2384                 else
2385                         field_offset = in_height / out_height / 2;
2386         }
2387
2388         /* Fields are independent but interleaved in memory. */
2389         if (fieldmode)
2390                 field_offset = 1;
2391
2392         offset0 = 0;
2393         offset1 = 0;
2394         row_inc = 0;
2395         pix_inc = 0;
2396
2397         if (rotation_type == OMAP_DSS_ROT_TILER)
2398                 calc_tiler_rotation_offset(screen_width, in_width,
2399                                 color_mode, fieldmode, field_offset,
2400                                 &offset0, &offset1, &row_inc, &pix_inc,
2401                                 x_predecim, y_predecim);
2402         else if (rotation_type == OMAP_DSS_ROT_DMA)
2403                 calc_dma_rotation_offset(rotation, mirror,
2404                                 screen_width, in_width, frame_height,
2405                                 color_mode, fieldmode, field_offset,
2406                                 &offset0, &offset1, &row_inc, &pix_inc,
2407                                 x_predecim, y_predecim);
2408         else
2409                 calc_vrfb_rotation_offset(rotation, mirror,
2410                                 screen_width, in_width, frame_height,
2411                                 color_mode, fieldmode, field_offset,
2412                                 &offset0, &offset1, &row_inc, &pix_inc,
2413                                 x_predecim, y_predecim);
2414
2415         DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2416                         offset0, offset1, row_inc, pix_inc);
2417
2418         dispc_ovl_set_color_mode(plane, color_mode);
2419
2420         dispc_ovl_configure_burst_type(plane, rotation_type);
2421
2422         dispc_ovl_set_ba0(plane, paddr + offset0);
2423         dispc_ovl_set_ba1(plane, paddr + offset1);
2424
2425         if (OMAP_DSS_COLOR_NV12 == color_mode) {
2426                 dispc_ovl_set_ba0_uv(plane, p_uv_addr + offset0);
2427                 dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1);
2428         }
2429
2430         dispc_ovl_set_row_inc(plane, row_inc);
2431         dispc_ovl_set_pix_inc(plane, pix_inc);
2432
2433         DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width,
2434                         in_height, out_width, out_height);
2435
2436         dispc_ovl_set_pos(plane, caps, pos_x, pos_y);
2437
2438         dispc_ovl_set_input_size(plane, in_width, in_height);
2439
2440         if (caps & OMAP_DSS_OVL_CAP_SCALE) {
2441                 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2442                                    out_height, ilace, five_taps, fieldmode,
2443                                    color_mode, rotation);
2444                 dispc_ovl_set_output_size(plane, out_width, out_height);
2445                 dispc_ovl_set_vid_color_conv(plane, cconv);
2446         }
2447
2448         dispc_ovl_set_rotation_attrs(plane, rotation, mirror, color_mode);
2449
2450         dispc_ovl_set_zorder(plane, caps, zorder);
2451         dispc_ovl_set_pre_mult_alpha(plane, caps, pre_mult_alpha);
2452         dispc_ovl_setup_global_alpha(plane, caps, global_alpha);
2453
2454         dispc_ovl_enable_replication(plane, caps, replication);
2455
2456         return 0;
2457 }
2458
2459 int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
2460                 bool replication, const struct omap_video_timings *mgr_timings,
2461                 bool mem_to_mem)
2462 {
2463         int r;
2464         struct omap_overlay *ovl = omap_dss_get_overlay(plane);
2465         enum omap_channel channel;
2466
2467         channel = dispc_ovl_get_channel_out(plane);
2468
2469         DSSDBG("dispc_ovl_setup %d, pa %x, pa_uv %x, sw %d, %d,%d, %dx%d -> "
2470                 "%dx%d, cmode %x, rot %d, mir %d, chan %d repl %d\n",
2471                 plane, oi->paddr, oi->p_uv_addr, oi->screen_width, oi->pos_x,
2472                 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height,
2473                 oi->color_mode, oi->rotation, oi->mirror, channel, replication);
2474
2475         r = dispc_ovl_setup_common(plane, ovl->caps, oi->paddr, oi->p_uv_addr,
2476                 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2477                 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
2478                 oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha,
2479                 oi->rotation_type, replication, mgr_timings, mem_to_mem);
2480
2481         return r;
2482 }
2483
2484 int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
2485                 bool mem_to_mem, const struct omap_video_timings *mgr_timings)
2486 {
2487         int r;
2488         u32 l;
2489         enum omap_plane plane = OMAP_DSS_WB;
2490         const int pos_x = 0, pos_y = 0;
2491         const u8 zorder = 0, global_alpha = 0;
2492         const bool replication = false;
2493         bool truncation;
2494         int in_width = mgr_timings->x_res;
2495         int in_height = mgr_timings->y_res;
2496         enum omap_overlay_caps caps =
2497                 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA;
2498
2499         DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, "
2500                 "rot %d, mir %d\n", wi->paddr, wi->p_uv_addr, in_width,
2501                 in_height, wi->width, wi->height, wi->color_mode, wi->rotation,
2502                 wi->mirror);
2503
2504         r = dispc_ovl_setup_common(plane, caps, wi->paddr, wi->p_uv_addr,
2505                 wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width,
2506                 wi->height, wi->color_mode, wi->rotation, wi->mirror, zorder,
2507                 wi->pre_mult_alpha, global_alpha, wi->rotation_type,
2508                 replication, mgr_timings, mem_to_mem);
2509
2510         switch (wi->color_mode) {
2511         case OMAP_DSS_COLOR_RGB16:
2512         case OMAP_DSS_COLOR_RGB24P:
2513         case OMAP_DSS_COLOR_ARGB16:
2514         case OMAP_DSS_COLOR_RGBA16:
2515         case OMAP_DSS_COLOR_RGB12U:
2516         case OMAP_DSS_COLOR_ARGB16_1555:
2517         case OMAP_DSS_COLOR_XRGB16_1555:
2518         case OMAP_DSS_COLOR_RGBX16:
2519                 truncation = true;
2520                 break;
2521         default:
2522                 truncation = false;
2523                 break;
2524         }
2525
2526         /* setup extra DISPC_WB_ATTRIBUTES */
2527         l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2528         l = FLD_MOD(l, truncation, 10, 10);     /* TRUNCATIONENABLE */
2529         l = FLD_MOD(l, mem_to_mem, 19, 19);     /* WRITEBACKMODE */
2530         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
2531
2532         return r;
2533 }
2534
2535 int dispc_ovl_enable(enum omap_plane plane, bool enable)
2536 {
2537         DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2538
2539         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
2540
2541         return 0;
2542 }
2543
2544 static void dispc_disable_isr(void *data, u32 mask)
2545 {
2546         struct completion *compl = data;
2547         complete(compl);
2548 }
2549
2550 static void _enable_lcd_out(enum omap_channel channel, bool enable)
2551 {
2552         mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);
2553         /* flush posted write */
2554         mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2555 }
2556
2557 static void dispc_mgr_enable_lcd_out(enum omap_channel channel, bool enable)
2558 {
2559         struct completion frame_done_completion;
2560         bool is_on;
2561         int r;
2562         u32 irq;
2563
2564         /* When we disable LCD output, we need to wait until frame is done.
2565          * Otherwise the DSS is still working, and turning off the clocks
2566          * prevents DSS from going to OFF mode */
2567         is_on = mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2568
2569         irq = mgr_desc[channel].framedone_irq;
2570
2571         if (!enable && is_on) {
2572                 init_completion(&frame_done_completion);
2573
2574                 r = omap_dispc_register_isr(dispc_disable_isr,
2575                                 &frame_done_completion, irq);
2576
2577                 if (r)
2578                         DSSERR("failed to register FRAMEDONE isr\n");
2579         }
2580
2581         _enable_lcd_out(channel, enable);
2582
2583         if (!enable && is_on) {
2584                 if (!wait_for_completion_timeout(&frame_done_completion,
2585                                         msecs_to_jiffies(100)))
2586                         DSSERR("timeout waiting for FRAME DONE\n");
2587
2588                 r = omap_dispc_unregister_isr(dispc_disable_isr,
2589                                 &frame_done_completion, irq);
2590
2591                 if (r)
2592                         DSSERR("failed to unregister FRAMEDONE isr\n");
2593         }
2594 }
2595
2596 static void _enable_digit_out(bool enable)
2597 {
2598         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
2599         /* flush posted write */
2600         dispc_read_reg(DISPC_CONTROL);
2601 }
2602
2603 static void dispc_mgr_enable_digit_out(bool enable)
2604 {
2605         struct completion frame_done_completion;
2606         enum dss_hdmi_venc_clk_source_select src;
2607         int r, i;
2608         u32 irq_mask;
2609         int num_irqs;
2610
2611         if (REG_GET(DISPC_CONTROL, 1, 1) == enable)
2612                 return;
2613
2614         src = dss_get_hdmi_venc_clk_source();
2615
2616         if (enable) {
2617                 unsigned long flags;
2618                 /* When we enable digit output, we'll get an extra digit
2619                  * sync lost interrupt, that we need to ignore */
2620                 spin_lock_irqsave(&dispc.irq_lock, flags);
2621                 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
2622                 _omap_dispc_set_irqs();
2623                 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2624         }
2625
2626         /* When we disable digit output, we need to wait until fields are done.
2627          * Otherwise the DSS is still working, and turning off the clocks
2628          * prevents DSS from going to OFF mode. And when enabling, we need to
2629          * wait for the extra sync losts */
2630         init_completion(&frame_done_completion);
2631
2632         if (src == DSS_HDMI_M_PCLK && enable == false) {
2633                 irq_mask = DISPC_IRQ_FRAMEDONETV;
2634                 num_irqs = 1;
2635         } else {
2636                 irq_mask = DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD;
2637                 /* XXX I understand from TRM that we should only wait for the
2638                  * current field to complete. But it seems we have to wait for
2639                  * both fields */
2640                 num_irqs = 2;
2641         }
2642
2643         r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
2644                         irq_mask);
2645         if (r)
2646                 DSSERR("failed to register %x isr\n", irq_mask);
2647
2648         _enable_digit_out(enable);
2649
2650         for (i = 0; i < num_irqs; ++i) {
2651                 if (!wait_for_completion_timeout(&frame_done_completion,
2652                                         msecs_to_jiffies(100)))
2653                         DSSERR("timeout waiting for digit out to %s\n",
2654                                         enable ? "start" : "stop");
2655         }
2656
2657         r = omap_dispc_unregister_isr(dispc_disable_isr, &frame_done_completion,
2658                         irq_mask);
2659         if (r)
2660                 DSSERR("failed to unregister %x isr\n", irq_mask);
2661
2662         if (enable) {
2663                 unsigned long flags;
2664                 spin_lock_irqsave(&dispc.irq_lock, flags);
2665                 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST_DIGIT;
2666                 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
2667                 _omap_dispc_set_irqs();
2668                 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2669         }
2670 }
2671
2672 bool dispc_mgr_is_enabled(enum omap_channel channel)
2673 {
2674         return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2675 }
2676
2677 void dispc_mgr_enable(enum omap_channel channel, bool enable)
2678 {
2679         if (dss_mgr_is_lcd(channel))
2680                 dispc_mgr_enable_lcd_out(channel, enable);
2681         else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2682                 dispc_mgr_enable_digit_out(enable);
2683         else
2684                 BUG();
2685 }
2686
2687 void dispc_lcd_enable_signal_polarity(bool act_high)
2688 {
2689         if (!dss_has_feature(FEAT_LCDENABLEPOL))
2690                 return;
2691
2692         REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
2693 }
2694
2695 void dispc_lcd_enable_signal(bool enable)
2696 {
2697         if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2698                 return;
2699
2700         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
2701 }
2702
2703 void dispc_pck_free_enable(bool enable)
2704 {
2705         if (!dss_has_feature(FEAT_PCKFREEENABLE))
2706                 return;
2707
2708         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
2709 }
2710
2711 void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
2712 {
2713         mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
2714 }
2715
2716
2717 void dispc_mgr_set_lcd_type_tft(enum omap_channel channel)
2718 {
2719         mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1);
2720 }
2721
2722 void dispc_set_loadmode(enum omap_dss_load_mode mode)
2723 {
2724         REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
2725 }
2726
2727
2728 static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
2729 {
2730         dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
2731 }
2732
2733 static void dispc_mgr_set_trans_key(enum omap_channel ch,
2734                 enum omap_dss_trans_key_type type,
2735                 u32 trans_key)
2736 {
2737         mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type);
2738
2739         dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
2740 }
2741
2742 static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
2743 {
2744         mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable);
2745 }
2746
2747 static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2748                 bool enable)
2749 {
2750         if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
2751                 return;
2752
2753         if (ch == OMAP_DSS_CHANNEL_LCD)
2754                 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2755         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2756                 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2757 }
2758
2759 void dispc_mgr_setup(enum omap_channel channel,
2760                 struct omap_overlay_manager_info *info)
2761 {
2762         dispc_mgr_set_default_color(channel, info->default_color);
2763         dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
2764         dispc_mgr_enable_trans_key(channel, info->trans_enabled);
2765         dispc_mgr_enable_alpha_fixed_zorder(channel,
2766                         info->partial_alpha_enabled);
2767         if (dss_has_feature(FEAT_CPR)) {
2768                 dispc_mgr_enable_cpr(channel, info->cpr_enable);
2769                 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
2770         }
2771 }
2772
2773 void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
2774 {
2775         int code;
2776
2777         switch (data_lines) {
2778         case 12:
2779                 code = 0;
2780                 break;
2781         case 16:
2782                 code = 1;
2783                 break;
2784         case 18:
2785                 code = 2;
2786                 break;
2787         case 24:
2788                 code = 3;
2789                 break;
2790         default:
2791                 BUG();
2792                 return;
2793         }
2794
2795         mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code);
2796 }
2797
2798 void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
2799 {
2800         u32 l;
2801         int gpout0, gpout1;
2802
2803         switch (mode) {
2804         case DSS_IO_PAD_MODE_RESET:
2805                 gpout0 = 0;
2806                 gpout1 = 0;
2807                 break;
2808         case DSS_IO_PAD_MODE_RFBI:
2809                 gpout0 = 1;
2810                 gpout1 = 0;
2811                 break;
2812         case DSS_IO_PAD_MODE_BYPASS:
2813                 gpout0 = 1;
2814                 gpout1 = 1;
2815                 break;
2816         default:
2817                 BUG();
2818                 return;
2819         }
2820
2821         l = dispc_read_reg(DISPC_CONTROL);
2822         l = FLD_MOD(l, gpout0, 15, 15);
2823         l = FLD_MOD(l, gpout1, 16, 16);
2824         dispc_write_reg(DISPC_CONTROL, l);
2825 }
2826
2827 void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
2828 {
2829         mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);
2830 }
2831
2832 static bool _dispc_mgr_size_ok(u16 width, u16 height)
2833 {
2834         return width <= dss_feat_get_param_max(FEAT_PARAM_MGR_WIDTH) &&
2835                 height <= dss_feat_get_param_max(FEAT_PARAM_MGR_HEIGHT);
2836 }
2837
2838 static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2839                 int vsw, int vfp, int vbp)
2840 {
2841         if (hsw < 1 || hsw > dispc.feat->sw_max ||
2842                         hfp < 1 || hfp > dispc.feat->hp_max ||
2843                         hbp < 1 || hbp > dispc.feat->hp_max ||
2844                         vsw < 1 || vsw > dispc.feat->sw_max ||
2845                         vfp < 0 || vfp > dispc.feat->vp_max ||
2846                         vbp < 0 || vbp > dispc.feat->vp_max)
2847                 return false;
2848         return true;
2849 }
2850
2851 bool dispc_mgr_timings_ok(enum omap_channel channel,
2852                 const struct omap_video_timings *timings)
2853 {
2854         bool timings_ok;
2855
2856         timings_ok = _dispc_mgr_size_ok(timings->x_res, timings->y_res);
2857
2858         if (dss_mgr_is_lcd(channel))
2859                 timings_ok =  timings_ok && _dispc_lcd_timings_ok(timings->hsw,
2860                                                 timings->hfp, timings->hbp,
2861                                                 timings->vsw, timings->vfp,
2862                                                 timings->vbp);
2863
2864         return timings_ok;
2865 }
2866
2867 static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
2868                 int hfp, int hbp, int vsw, int vfp, int vbp,
2869                 enum omap_dss_signal_level vsync_level,
2870                 enum omap_dss_signal_level hsync_level,
2871                 enum omap_dss_signal_edge data_pclk_edge,
2872                 enum omap_dss_signal_level de_level,
2873                 enum omap_dss_signal_edge sync_pclk_edge)
2874
2875 {
2876         u32 timing_h, timing_v, l;
2877         bool onoff, rf, ipc;
2878
2879         timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) |
2880                         FLD_VAL(hfp-1, dispc.feat->fp_start, 8) |
2881                         FLD_VAL(hbp-1, dispc.feat->bp_start, 20);
2882         timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) |
2883                         FLD_VAL(vfp, dispc.feat->fp_start, 8) |
2884                         FLD_VAL(vbp, dispc.feat->bp_start, 20);
2885
2886         dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2887         dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
2888
2889         switch (data_pclk_edge) {
2890         case OMAPDSS_DRIVE_SIG_RISING_EDGE:
2891                 ipc = false;
2892                 break;
2893         case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
2894                 ipc = true;
2895                 break;
2896         case OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES:
2897         default:
2898                 BUG();
2899         }
2900
2901         switch (sync_pclk_edge) {
2902         case OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES:
2903                 onoff = false;
2904                 rf = false;
2905                 break;
2906         case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
2907                 onoff = true;
2908                 rf = false;
2909                 break;
2910         case OMAPDSS_DRIVE_SIG_RISING_EDGE:
2911                 onoff = true;
2912                 rf = true;
2913                 break;
2914         default:
2915                 BUG();
2916         };
2917
2918         l = dispc_read_reg(DISPC_POL_FREQ(channel));
2919         l |= FLD_VAL(onoff, 17, 17);
2920         l |= FLD_VAL(rf, 16, 16);
2921         l |= FLD_VAL(de_level, 15, 15);
2922         l |= FLD_VAL(ipc, 14, 14);
2923         l |= FLD_VAL(hsync_level, 13, 13);
2924         l |= FLD_VAL(vsync_level, 12, 12);
2925         dispc_write_reg(DISPC_POL_FREQ(channel), l);
2926 }
2927
2928 /* change name to mode? */
2929 void dispc_mgr_set_timings(enum omap_channel channel,
2930                 struct omap_video_timings *timings)
2931 {
2932         unsigned xtot, ytot;
2933         unsigned long ht, vt;
2934         struct omap_video_timings t = *timings;
2935
2936         DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res);
2937
2938         if (!dispc_mgr_timings_ok(channel, &t)) {
2939                 BUG();
2940                 return;
2941         }
2942
2943         if (dss_mgr_is_lcd(channel)) {
2944                 _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw,
2945                                 t.vfp, t.vbp, t.vsync_level, t.hsync_level,
2946                                 t.data_pclk_edge, t.de_level, t.sync_pclk_edge);
2947
2948                 xtot = t.x_res + t.hfp + t.hsw + t.hbp;
2949                 ytot = t.y_res + t.vfp + t.vsw + t.vbp;
2950
2951                 ht = (timings->pixel_clock * 1000) / xtot;
2952                 vt = (timings->pixel_clock * 1000) / xtot / ytot;
2953
2954                 DSSDBG("pck %u\n", timings->pixel_clock);
2955                 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2956                         t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
2957                 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
2958                         t.vsync_level, t.hsync_level, t.data_pclk_edge,
2959                         t.de_level, t.sync_pclk_edge);
2960
2961                 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2962         } else {
2963                 if (t.interlace == true)
2964                         t.y_res /= 2;
2965         }
2966
2967         dispc_mgr_set_size(channel, t.x_res, t.y_res);
2968 }
2969
2970 static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
2971                 u16 pck_div)
2972 {
2973         BUG_ON(lck_div < 1);
2974         BUG_ON(pck_div < 1);
2975
2976         dispc_write_reg(DISPC_DIVISORo(channel),
2977                         FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
2978 }
2979
2980 static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2981                 int *pck_div)
2982 {
2983         u32 l;
2984         l = dispc_read_reg(DISPC_DIVISORo(channel));
2985         *lck_div = FLD_GET(l, 23, 16);
2986         *pck_div = FLD_GET(l, 7, 0);
2987 }
2988
2989 unsigned long dispc_fclk_rate(void)
2990 {
2991         struct platform_device *dsidev;
2992         unsigned long r = 0;
2993
2994         switch (dss_get_dispc_clk_source()) {
2995         case OMAP_DSS_CLK_SRC_FCK:
2996                 r = clk_get_rate(dispc.dss_clk);
2997                 break;
2998         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
2999                 dsidev = dsi_get_dsidev_from_id(0);
3000                 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
3001                 break;
3002         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3003                 dsidev = dsi_get_dsidev_from_id(1);
3004                 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
3005                 break;
3006         default:
3007                 BUG();
3008                 return 0;
3009         }
3010
3011         return r;
3012 }
3013
3014 unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
3015 {
3016         struct platform_device *dsidev;
3017         int lcd;
3018         unsigned long r;
3019         u32 l;
3020
3021         l = dispc_read_reg(DISPC_DIVISORo(channel));
3022
3023         lcd = FLD_GET(l, 23, 16);
3024
3025         switch (dss_get_lcd_clk_source(channel)) {
3026         case OMAP_DSS_CLK_SRC_FCK:
3027                 r = clk_get_rate(dispc.dss_clk);
3028                 break;
3029         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
3030                 dsidev = dsi_get_dsidev_from_id(0);
3031                 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
3032                 break;
3033         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3034                 dsidev = dsi_get_dsidev_from_id(1);
3035                 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
3036                 break;
3037         default:
3038                 BUG();
3039                 return 0;
3040         }
3041
3042         return r / lcd;
3043 }
3044
3045 unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
3046 {
3047         unsigned long r;
3048
3049         if (dss_mgr_is_lcd(channel)) {
3050                 int pcd;
3051                 u32 l;
3052
3053                 l = dispc_read_reg(DISPC_DIVISORo(channel));
3054
3055                 pcd = FLD_GET(l, 7, 0);
3056
3057                 r = dispc_mgr_lclk_rate(channel);
3058
3059                 return r / pcd;
3060         } else {
3061                 enum dss_hdmi_venc_clk_source_select source;
3062
3063                 source = dss_get_hdmi_venc_clk_source();
3064
3065                 switch (source) {
3066                 case DSS_VENC_TV_CLK:
3067                         return venc_get_pixel_clock();
3068                 case DSS_HDMI_M_PCLK:
3069                         return hdmi_get_pixel_clock();
3070                 default:
3071                         BUG();
3072                         return 0;
3073                 }
3074         }
3075 }
3076
3077 unsigned long dispc_core_clk_rate(void)
3078 {
3079         int lcd;
3080         unsigned long fclk = dispc_fclk_rate();
3081
3082         if (dss_has_feature(FEAT_CORE_CLK_DIV))
3083                 lcd = REG_GET(DISPC_DIVISOR, 23, 16);
3084         else
3085                 lcd = REG_GET(DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD), 23, 16);
3086
3087         return fclk / lcd;
3088 }
3089
3090 static unsigned long dispc_plane_pclk_rate(enum omap_plane plane)
3091 {
3092         enum omap_channel channel = dispc_ovl_get_channel_out(plane);
3093
3094         return dispc_mgr_pclk_rate(channel);
3095 }
3096
3097 static unsigned long dispc_plane_lclk_rate(enum omap_plane plane)
3098 {
3099         enum omap_channel channel = dispc_ovl_get_channel_out(plane);
3100
3101         if (dss_mgr_is_lcd(channel))
3102                 return dispc_mgr_lclk_rate(channel);
3103         else
3104                 return dispc_fclk_rate();
3105
3106 }
3107 static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel)
3108 {
3109         int lcd, pcd;
3110         enum omap_dss_clk_source lcd_clk_src;
3111
3112         seq_printf(s, "- %s -\n", mgr_desc[channel].name);
3113
3114         lcd_clk_src = dss_get_lcd_clk_source(channel);
3115
3116         seq_printf(s, "%s clk source = %s (%s)\n", mgr_desc[channel].name,
3117                 dss_get_generic_clk_source_name(lcd_clk_src),
3118                 dss_feat_get_clk_source_name(lcd_clk_src));
3119
3120         dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd);
3121
3122         seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3123                 dispc_mgr_lclk_rate(channel), lcd);
3124         seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
3125                 dispc_mgr_pclk_rate(channel), pcd);
3126 }
3127
3128 void dispc_dump_clocks(struct seq_file *s)
3129 {
3130         int lcd;
3131         u32 l;
3132         enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
3133
3134         if (dispc_runtime_get())
3135                 return;
3136
3137         seq_printf(s, "- DISPC -\n");
3138
3139         seq_printf(s, "dispc fclk source = %s (%s)\n",
3140                         dss_get_generic_clk_source_name(dispc_clk_src),
3141                         dss_feat_get_clk_source_name(dispc_clk_src));
3142
3143         seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
3144
3145         if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3146                 seq_printf(s, "- DISPC-CORE-CLK -\n");
3147                 l = dispc_read_reg(DISPC_DIVISOR);
3148                 lcd = FLD_GET(l, 23, 16);
3149
3150                 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3151                                 (dispc_fclk_rate()/lcd), lcd);
3152         }
3153
3154         dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD);
3155
3156         if (dss_has_feature(FEAT_MGR_LCD2))
3157                 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2);
3158         if (dss_has_feature(FEAT_MGR_LCD3))
3159                 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3);
3160
3161         dispc_runtime_put();
3162 }
3163
3164 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3165 void dispc_dump_irqs(struct seq_file *s)
3166 {
3167         unsigned long flags;
3168         struct dispc_irq_stats stats;
3169
3170         spin_lock_irqsave(&dispc.irq_stats_lock, flags);
3171
3172         stats = dispc.irq_stats;
3173         memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
3174         dispc.irq_stats.last_reset = jiffies;
3175
3176         spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
3177
3178         seq_printf(s, "period %u ms\n",
3179                         jiffies_to_msecs(jiffies - stats.last_reset));
3180
3181         seq_printf(s, "irqs %d\n", stats.irq_count);
3182 #define PIS(x) \
3183         seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
3184
3185         PIS(FRAMEDONE);
3186         PIS(VSYNC);
3187         PIS(EVSYNC_EVEN);
3188         PIS(EVSYNC_ODD);
3189         PIS(ACBIAS_COUNT_STAT);
3190         PIS(PROG_LINE_NUM);
3191         PIS(GFX_FIFO_UNDERFLOW);
3192         PIS(GFX_END_WIN);
3193         PIS(PAL_GAMMA_MASK);
3194         PIS(OCP_ERR);
3195         PIS(VID1_FIFO_UNDERFLOW);
3196         PIS(VID1_END_WIN);
3197         PIS(VID2_FIFO_UNDERFLOW);
3198         PIS(VID2_END_WIN);
3199         if (dss_feat_get_num_ovls() > 3) {
3200                 PIS(VID3_FIFO_UNDERFLOW);
3201                 PIS(VID3_END_WIN);
3202         }
3203         PIS(SYNC_LOST);
3204         PIS(SYNC_LOST_DIGIT);
3205         PIS(WAKEUP);
3206         if (dss_has_feature(FEAT_MGR_LCD2)) {
3207                 PIS(FRAMEDONE2);
3208                 PIS(VSYNC2);
3209                 PIS(ACBIAS_COUNT_STAT2);
3210                 PIS(SYNC_LOST2);
3211         }
3212         if (dss_has_feature(FEAT_MGR_LCD3)) {
3213                 PIS(FRAMEDONE3);
3214                 PIS(VSYNC3);
3215                 PIS(ACBIAS_COUNT_STAT3);
3216                 PIS(SYNC_LOST3);
3217         }
3218 #undef PIS
3219 }
3220 #endif
3221
3222 static void dispc_dump_regs(struct seq_file *s)
3223 {
3224         int i, j;
3225         const char *mgr_names[] = {
3226                 [OMAP_DSS_CHANNEL_LCD]          = "LCD",
3227                 [OMAP_DSS_CHANNEL_DIGIT]        = "TV",
3228                 [OMAP_DSS_CHANNEL_LCD2]         = "LCD2",
3229                 [OMAP_DSS_CHANNEL_LCD3]         = "LCD3",
3230         };
3231         const char *ovl_names[] = {
3232                 [OMAP_DSS_GFX]          = "GFX",
3233                 [OMAP_DSS_VIDEO1]       = "VID1",
3234                 [OMAP_DSS_VIDEO2]       = "VID2",
3235                 [OMAP_DSS_VIDEO3]       = "VID3",
3236         };
3237         const char **p_names;
3238
3239 #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
3240
3241         if (dispc_runtime_get())
3242                 return;
3243
3244         /* DISPC common registers */
3245         DUMPREG(DISPC_REVISION);
3246         DUMPREG(DISPC_SYSCONFIG);
3247         DUMPREG(DISPC_SYSSTATUS);
3248         DUMPREG(DISPC_IRQSTATUS);
3249         DUMPREG(DISPC_IRQENABLE);
3250         DUMPREG(DISPC_CONTROL);
3251         DUMPREG(DISPC_CONFIG);
3252         DUMPREG(DISPC_CAPABLE);
3253         DUMPREG(DISPC_LINE_STATUS);
3254         DUMPREG(DISPC_LINE_NUMBER);
3255         if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
3256                         dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
3257                 DUMPREG(DISPC_GLOBAL_ALPHA);
3258         if (dss_has_feature(FEAT_MGR_LCD2)) {
3259                 DUMPREG(DISPC_CONTROL2);
3260                 DUMPREG(DISPC_CONFIG2);
3261         }
3262         if (dss_has_feature(FEAT_MGR_LCD3)) {
3263                 DUMPREG(DISPC_CONTROL3);
3264                 DUMPREG(DISPC_CONFIG3);
3265         }
3266
3267 #undef DUMPREG
3268
3269 #define DISPC_REG(i, name) name(i)
3270 #define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
3271         48 - strlen(#r) - strlen(p_names[i]), " ", \
3272         dispc_read_reg(DISPC_REG(i, r)))
3273
3274         p_names = mgr_names;
3275
3276         /* DISPC channel specific registers */
3277         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
3278                 DUMPREG(i, DISPC_DEFAULT_COLOR);
3279                 DUMPREG(i, DISPC_TRANS_COLOR);
3280                 DUMPREG(i, DISPC_SIZE_MGR);
3281
3282                 if (i == OMAP_DSS_CHANNEL_DIGIT)
3283                         continue;
3284
3285                 DUMPREG(i, DISPC_DEFAULT_COLOR);
3286                 DUMPREG(i, DISPC_TRANS_COLOR);
3287                 DUMPREG(i, DISPC_TIMING_H);
3288                 DUMPREG(i, DISPC_TIMING_V);
3289                 DUMPREG(i, DISPC_POL_FREQ);
3290                 DUMPREG(i, DISPC_DIVISORo);
3291                 DUMPREG(i, DISPC_SIZE_MGR);
3292
3293                 DUMPREG(i, DISPC_DATA_CYCLE1);
3294                 DUMPREG(i, DISPC_DATA_CYCLE2);
3295                 DUMPREG(i, DISPC_DATA_CYCLE3);
3296
3297                 if (dss_has_feature(FEAT_CPR)) {
3298                         DUMPREG(i, DISPC_CPR_COEF_R);
3299                         DUMPREG(i, DISPC_CPR_COEF_G);
3300                         DUMPREG(i, DISPC_CPR_COEF_B);
3301                 }
3302         }
3303
3304         p_names = ovl_names;
3305
3306         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
3307                 DUMPREG(i, DISPC_OVL_BA0);
3308                 DUMPREG(i, DISPC_OVL_BA1);
3309                 DUMPREG(i, DISPC_OVL_POSITION);
3310                 DUMPREG(i, DISPC_OVL_SIZE);
3311                 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3312                 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3313                 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3314                 DUMPREG(i, DISPC_OVL_ROW_INC);
3315                 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3316                 if (dss_has_feature(FEAT_PRELOAD))
3317                         DUMPREG(i, DISPC_OVL_PRELOAD);
3318
3319                 if (i == OMAP_DSS_GFX) {
3320                         DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
3321                         DUMPREG(i, DISPC_OVL_TABLE_BA);
3322                         continue;
3323                 }
3324
3325                 DUMPREG(i, DISPC_OVL_FIR);
3326                 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3327                 DUMPREG(i, DISPC_OVL_ACCU0);
3328                 DUMPREG(i, DISPC_OVL_ACCU1);
3329                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3330                         DUMPREG(i, DISPC_OVL_BA0_UV);
3331                         DUMPREG(i, DISPC_OVL_BA1_UV);
3332                         DUMPREG(i, DISPC_OVL_FIR2);
3333                         DUMPREG(i, DISPC_OVL_ACCU2_0);
3334                         DUMPREG(i, DISPC_OVL_ACCU2_1);
3335                 }
3336                 if (dss_has_feature(FEAT_ATTR2))
3337                         DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3338                 if (dss_has_feature(FEAT_PRELOAD))
3339                         DUMPREG(i, DISPC_OVL_PRELOAD);
3340         }
3341
3342 #undef DISPC_REG
3343 #undef DUMPREG
3344
3345 #define DISPC_REG(plane, name, i) name(plane, i)
3346 #define DUMPREG(plane, name, i) \
3347         seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
3348         46 - strlen(#name) - strlen(p_names[plane]), " ", \
3349         dispc_read_reg(DISPC_REG(plane, name, i)))
3350
3351         /* Video pipeline coefficient registers */
3352
3353         /* start from OMAP_DSS_VIDEO1 */
3354         for (i = 1; i < dss_feat_get_num_ovls(); i++) {
3355                 for (j = 0; j < 8; j++)
3356                         DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
3357
3358                 for (j = 0; j < 8; j++)
3359                         DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
3360
3361                 for (j = 0; j < 5; j++)
3362                         DUMPREG(i, DISPC_OVL_CONV_COEF, j);
3363
3364                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
3365                         for (j = 0; j < 8; j++)
3366                                 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
3367                 }
3368
3369                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3370                         for (j = 0; j < 8; j++)
3371                                 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
3372
3373                         for (j = 0; j < 8; j++)
3374                                 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
3375
3376                         for (j = 0; j < 8; j++)
3377                                 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
3378                 }
3379         }
3380
3381         dispc_runtime_put();
3382
3383 #undef DISPC_REG
3384 #undef DUMPREG
3385 }
3386
3387 /* with fck as input clock rate, find dispc dividers that produce req_pck */
3388 void dispc_find_clk_divs(unsigned long req_pck, unsigned long fck,
3389                 struct dispc_clock_info *cinfo)
3390 {
3391         u16 pcd_min, pcd_max;
3392         unsigned long best_pck;
3393         u16 best_ld, cur_ld;
3394         u16 best_pd, cur_pd;
3395
3396         pcd_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
3397         pcd_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
3398
3399         best_pck = 0;
3400         best_ld = 0;
3401         best_pd = 0;
3402
3403         for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
3404                 unsigned long lck = fck / cur_ld;
3405
3406                 for (cur_pd = pcd_min; cur_pd <= pcd_max; ++cur_pd) {
3407                         unsigned long pck = lck / cur_pd;
3408                         long old_delta = abs(best_pck - req_pck);
3409                         long new_delta = abs(pck - req_pck);
3410
3411                         if (best_pck == 0 || new_delta < old_delta) {
3412                                 best_pck = pck;
3413                                 best_ld = cur_ld;
3414                                 best_pd = cur_pd;
3415
3416                                 if (pck == req_pck)
3417                                         goto found;
3418                         }
3419
3420                         if (pck < req_pck)
3421                                 break;
3422                 }
3423
3424                 if (lck / pcd_min < req_pck)
3425                         break;
3426         }
3427
3428 found:
3429         cinfo->lck_div = best_ld;
3430         cinfo->pck_div = best_pd;
3431         cinfo->lck = fck / cinfo->lck_div;
3432         cinfo->pck = cinfo->lck / cinfo->pck_div;
3433 }
3434
3435 /* calculate clock rates using dividers in cinfo */
3436 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
3437                 struct dispc_clock_info *cinfo)
3438 {
3439         if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3440                 return -EINVAL;
3441         if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
3442                 return -EINVAL;
3443
3444         cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3445         cinfo->pck = cinfo->lck / cinfo->pck_div;
3446
3447         return 0;
3448 }
3449
3450 void dispc_mgr_set_clock_div(enum omap_channel channel,
3451                 struct dispc_clock_info *cinfo)
3452 {
3453         DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3454         DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3455
3456         dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
3457 }
3458
3459 int dispc_mgr_get_clock_div(enum omap_channel channel,
3460                 struct dispc_clock_info *cinfo)
3461 {
3462         unsigned long fck;
3463
3464         fck = dispc_fclk_rate();
3465
3466         cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3467         cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
3468
3469         cinfo->lck = fck / cinfo->lck_div;
3470         cinfo->pck = cinfo->lck / cinfo->pck_div;
3471
3472         return 0;
3473 }
3474
3475 /* dispc.irq_lock has to be locked by the caller */
3476 static void _omap_dispc_set_irqs(void)
3477 {
3478         u32 mask;
3479         u32 old_mask;
3480         int i;
3481         struct omap_dispc_isr_data *isr_data;
3482
3483         mask = dispc.irq_error_mask;
3484
3485         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3486                 isr_data = &dispc.registered_isr[i];
3487
3488                 if (isr_data->isr == NULL)
3489                         continue;
3490
3491                 mask |= isr_data->mask;
3492         }
3493
3494         old_mask = dispc_read_reg(DISPC_IRQENABLE);
3495         /* clear the irqstatus for newly enabled irqs */
3496         dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
3497
3498         dispc_write_reg(DISPC_IRQENABLE, mask);
3499 }
3500
3501 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3502 {
3503         int i;
3504         int ret;
3505         unsigned long flags;
3506         struct omap_dispc_isr_data *isr_data;
3507
3508         if (isr == NULL)
3509                 return -EINVAL;
3510
3511         spin_lock_irqsave(&dispc.irq_lock, flags);
3512
3513         /* check for duplicate entry */
3514         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3515                 isr_data = &dispc.registered_isr[i];
3516                 if (isr_data->isr == isr && isr_data->arg == arg &&
3517                                 isr_data->mask == mask) {
3518                         ret = -EINVAL;
3519                         goto err;
3520                 }
3521         }
3522
3523         isr_data = NULL;
3524         ret = -EBUSY;
3525
3526         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3527                 isr_data = &dispc.registered_isr[i];
3528
3529                 if (isr_data->isr != NULL)
3530                         continue;
3531
3532                 isr_data->isr = isr;
3533                 isr_data->arg = arg;
3534                 isr_data->mask = mask;
3535                 ret = 0;
3536
3537                 break;
3538         }
3539
3540         if (ret)
3541                 goto err;
3542
3543         _omap_dispc_set_irqs();
3544
3545         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3546
3547         return 0;
3548 err:
3549         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3550
3551         return ret;
3552 }
3553 EXPORT_SYMBOL(omap_dispc_register_isr);
3554
3555 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3556 {
3557         int i;
3558         unsigned long flags;
3559         int ret = -EINVAL;
3560         struct omap_dispc_isr_data *isr_data;
3561
3562         spin_lock_irqsave(&dispc.irq_lock, flags);
3563
3564         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3565                 isr_data = &dispc.registered_isr[i];
3566                 if (isr_data->isr != isr || isr_data->arg != arg ||
3567                                 isr_data->mask != mask)
3568                         continue;
3569
3570                 /* found the correct isr */
3571
3572                 isr_data->isr = NULL;
3573                 isr_data->arg = NULL;
3574                 isr_data->mask = 0;
3575
3576                 ret = 0;
3577                 break;
3578         }
3579
3580         if (ret == 0)
3581                 _omap_dispc_set_irqs();
3582
3583         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3584
3585         return ret;
3586 }
3587 EXPORT_SYMBOL(omap_dispc_unregister_isr);
3588
3589 #ifdef DEBUG
3590 static void print_irq_status(u32 status)
3591 {
3592         if ((status & dispc.irq_error_mask) == 0)
3593                 return;
3594
3595         printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
3596
3597 #define PIS(x) \
3598         if (status & DISPC_IRQ_##x) \
3599                 printk(#x " ");
3600         PIS(GFX_FIFO_UNDERFLOW);
3601         PIS(OCP_ERR);
3602         PIS(VID1_FIFO_UNDERFLOW);
3603         PIS(VID2_FIFO_UNDERFLOW);
3604         if (dss_feat_get_num_ovls() > 3)
3605                 PIS(VID3_FIFO_UNDERFLOW);
3606         PIS(SYNC_LOST);
3607         PIS(SYNC_LOST_DIGIT);
3608         if (dss_has_feature(FEAT_MGR_LCD2))
3609                 PIS(SYNC_LOST2);
3610         if (dss_has_feature(FEAT_MGR_LCD3))
3611                 PIS(SYNC_LOST3);
3612 #undef PIS
3613
3614         printk("\n");
3615 }
3616 #endif
3617
3618 /* Called from dss.c. Note that we don't touch clocks here,
3619  * but we presume they are on because we got an IRQ. However,
3620  * an irq handler may turn the clocks off, so we may not have
3621  * clock later in the function. */
3622 static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
3623 {
3624         int i;
3625         u32 irqstatus, irqenable;
3626         u32 handledirqs = 0;
3627         u32 unhandled_errors;
3628         struct omap_dispc_isr_data *isr_data;
3629         struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
3630
3631         spin_lock(&dispc.irq_lock);
3632
3633         irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
3634         irqenable = dispc_read_reg(DISPC_IRQENABLE);
3635
3636         /* IRQ is not for us */
3637         if (!(irqstatus & irqenable)) {
3638                 spin_unlock(&dispc.irq_lock);
3639                 return IRQ_NONE;
3640         }
3641
3642 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3643         spin_lock(&dispc.irq_stats_lock);
3644         dispc.irq_stats.irq_count++;
3645         dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
3646         spin_unlock(&dispc.irq_stats_lock);
3647 #endif
3648
3649 #ifdef DEBUG
3650         if (dss_debug)
3651                 print_irq_status(irqstatus);
3652 #endif
3653         /* Ack the interrupt. Do it here before clocks are possibly turned
3654          * off */
3655         dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
3656         /* flush posted write */
3657         dispc_read_reg(DISPC_IRQSTATUS);
3658
3659         /* make a copy and unlock, so that isrs can unregister
3660          * themselves */
3661         memcpy(registered_isr, dispc.registered_isr,
3662                         sizeof(registered_isr));
3663
3664         spin_unlock(&dispc.irq_lock);
3665
3666         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3667                 isr_data = &registered_isr[i];
3668
3669                 if (!isr_data->isr)
3670                         continue;
3671
3672                 if (isr_data->mask & irqstatus) {
3673                         isr_data->isr(isr_data->arg, irqstatus);
3674                         handledirqs |= isr_data->mask;
3675                 }
3676         }
3677
3678         spin_lock(&dispc.irq_lock);
3679
3680         unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
3681
3682         if (unhandled_errors) {
3683                 dispc.error_irqs |= unhandled_errors;
3684
3685                 dispc.irq_error_mask &= ~unhandled_errors;
3686                 _omap_dispc_set_irqs();
3687
3688                 schedule_work(&dispc.error_work);
3689         }
3690
3691         spin_unlock(&dispc.irq_lock);
3692
3693         return IRQ_HANDLED;
3694 }
3695
3696 static void dispc_error_worker(struct work_struct *work)
3697 {
3698         int i;
3699         u32 errors;
3700         unsigned long flags;
3701         static const unsigned fifo_underflow_bits[] = {
3702                 DISPC_IRQ_GFX_FIFO_UNDERFLOW,
3703                 DISPC_IRQ_VID1_FIFO_UNDERFLOW,
3704                 DISPC_IRQ_VID2_FIFO_UNDERFLOW,
3705                 DISPC_IRQ_VID3_FIFO_UNDERFLOW,
3706         };
3707
3708         spin_lock_irqsave(&dispc.irq_lock, flags);
3709         errors = dispc.error_irqs;
3710         dispc.error_irqs = 0;
3711         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3712
3713         dispc_runtime_get();
3714
3715         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3716                 struct omap_overlay *ovl;
3717                 unsigned bit;
3718
3719                 ovl = omap_dss_get_overlay(i);
3720                 bit = fifo_underflow_bits[i];
3721
3722                 if (bit & errors) {
3723                         DSSERR("FIFO UNDERFLOW on %s, disabling the overlay\n",
3724                                         ovl->name);
3725                         dispc_ovl_enable(ovl->id, false);
3726                         dispc_mgr_go(ovl->manager->id);
3727                         msleep(50);
3728                 }
3729         }
3730
3731         for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3732                 struct omap_overlay_manager *mgr;
3733                 unsigned bit;
3734
3735                 mgr = omap_dss_get_overlay_manager(i);
3736                 bit = mgr_desc[i].sync_lost_irq;
3737
3738                 if (bit & errors) {
3739                         struct omap_dss_device *dssdev = mgr->get_device(mgr);
3740                         bool enable;
3741
3742                         DSSERR("SYNC_LOST on channel %s, restarting the output "
3743                                         "with video overlays disabled\n",
3744                                         mgr->name);
3745
3746                         enable = dssdev->state == OMAP_DSS_DISPLAY_ACTIVE;
3747                         dssdev->driver->disable(dssdev);
3748
3749                         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3750                                 struct omap_overlay *ovl;
3751                                 ovl = omap_dss_get_overlay(i);
3752
3753                                 if (ovl->id != OMAP_DSS_GFX &&
3754                                                 ovl->manager == mgr)
3755                                         dispc_ovl_enable(ovl->id, false);
3756                         }
3757
3758                         dispc_mgr_go(mgr->id);
3759                         msleep(50);
3760
3761                         if (enable)
3762                                 dssdev->driver->enable(dssdev);
3763                 }
3764         }
3765
3766         if (errors & DISPC_IRQ_OCP_ERR) {
3767                 DSSERR("OCP_ERR\n");
3768                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3769                         struct omap_overlay_manager *mgr;
3770                         struct omap_dss_device *dssdev;
3771
3772                         mgr = omap_dss_get_overlay_manager(i);
3773                         dssdev = mgr->get_device(mgr);
3774
3775                         if (dssdev && dssdev->driver)
3776                                 dssdev->driver->disable(dssdev);
3777                 }
3778         }
3779
3780         spin_lock_irqsave(&dispc.irq_lock, flags);
3781         dispc.irq_error_mask |= errors;
3782         _omap_dispc_set_irqs();
3783         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3784
3785         dispc_runtime_put();
3786 }
3787
3788 int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3789 {
3790         void dispc_irq_wait_handler(void *data, u32 mask)
3791         {
3792                 complete((struct completion *)data);
3793         }
3794
3795         int r;
3796         DECLARE_COMPLETION_ONSTACK(completion);
3797
3798         r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3799                         irqmask);
3800
3801         if (r)
3802                 return r;
3803
3804         timeout = wait_for_completion_timeout(&completion, timeout);
3805
3806         omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3807
3808         if (timeout == 0)
3809                 return -ETIMEDOUT;
3810
3811         if (timeout == -ERESTARTSYS)
3812                 return -ERESTARTSYS;
3813
3814         return 0;
3815 }
3816
3817 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3818                 unsigned long timeout)
3819 {
3820         void dispc_irq_wait_handler(void *data, u32 mask)
3821         {
3822                 complete((struct completion *)data);
3823         }
3824
3825         int r;
3826         DECLARE_COMPLETION_ONSTACK(completion);
3827
3828         r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3829                         irqmask);
3830
3831         if (r)
3832                 return r;
3833
3834         timeout = wait_for_completion_interruptible_timeout(&completion,
3835                         timeout);
3836
3837         omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3838
3839         if (timeout == 0)
3840                 return -ETIMEDOUT;
3841
3842         if (timeout == -ERESTARTSYS)
3843                 return -ERESTARTSYS;
3844
3845         return 0;
3846 }
3847
3848 static void _omap_dispc_initialize_irq(void)
3849 {
3850         unsigned long flags;
3851
3852         spin_lock_irqsave(&dispc.irq_lock, flags);
3853
3854         memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3855
3856         dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
3857         if (dss_has_feature(FEAT_MGR_LCD2))
3858                 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
3859         if (dss_has_feature(FEAT_MGR_LCD3))
3860                 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST3;
3861         if (dss_feat_get_num_ovls() > 3)
3862                 dispc.irq_error_mask |= DISPC_IRQ_VID3_FIFO_UNDERFLOW;
3863
3864         /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3865          * so clear it */
3866         dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3867
3868         _omap_dispc_set_irqs();
3869
3870         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3871 }
3872
3873 void dispc_enable_sidle(void)
3874 {
3875         REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3);  /* SIDLEMODE: smart idle */
3876 }
3877
3878 void dispc_disable_sidle(void)
3879 {
3880         REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3);  /* SIDLEMODE: no idle */
3881 }
3882
3883 static void _omap_dispc_initial_config(void)
3884 {
3885         u32 l;
3886
3887         /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3888         if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3889                 l = dispc_read_reg(DISPC_DIVISOR);
3890                 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3891                 l = FLD_MOD(l, 1, 0, 0);
3892                 l = FLD_MOD(l, 1, 23, 16);
3893                 dispc_write_reg(DISPC_DIVISOR, l);
3894         }
3895
3896         /* FUNCGATED */
3897         if (dss_has_feature(FEAT_FUNCGATED))
3898                 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3899
3900         _dispc_setup_color_conv_coef();
3901
3902         dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3903
3904         dispc_init_fifos();
3905
3906         dispc_configure_burst_sizes();
3907
3908         dispc_ovl_enable_zorder_planes();
3909 }
3910
3911 static const struct dispc_features omap24xx_dispc_feats __initconst = {
3912         .sw_start               =       5,
3913         .fp_start               =       15,
3914         .bp_start               =       27,
3915         .sw_max                 =       64,
3916         .vp_max                 =       255,
3917         .hp_max                 =       256,
3918         .calc_scaling           =       dispc_ovl_calc_scaling_24xx,
3919         .calc_core_clk          =       calc_core_clk_24xx,
3920         .num_fifos              =       3,
3921 };
3922
3923 static const struct dispc_features omap34xx_rev1_0_dispc_feats __initconst = {
3924         .sw_start               =       5,
3925         .fp_start               =       15,
3926         .bp_start               =       27,
3927         .sw_max                 =       64,
3928         .vp_max                 =       255,
3929         .hp_max                 =       256,
3930         .calc_scaling           =       dispc_ovl_calc_scaling_34xx,
3931         .calc_core_clk          =       calc_core_clk_34xx,
3932         .num_fifos              =       3,
3933 };
3934
3935 static const struct dispc_features omap34xx_rev3_0_dispc_feats __initconst = {
3936         .sw_start               =       7,
3937         .fp_start               =       19,
3938         .bp_start               =       31,
3939         .sw_max                 =       256,
3940         .vp_max                 =       4095,
3941         .hp_max                 =       4096,
3942         .calc_scaling           =       dispc_ovl_calc_scaling_34xx,
3943         .calc_core_clk          =       calc_core_clk_34xx,
3944         .num_fifos              =       3,
3945 };
3946
3947 static const struct dispc_features omap44xx_dispc_feats __initconst = {
3948         .sw_start               =       7,
3949         .fp_start               =       19,
3950         .bp_start               =       31,
3951         .sw_max                 =       256,
3952         .vp_max                 =       4095,
3953         .hp_max                 =       4096,
3954         .calc_scaling           =       dispc_ovl_calc_scaling_44xx,
3955         .calc_core_clk          =       calc_core_clk_44xx,
3956         .num_fifos              =       5,
3957         .gfx_fifo_workaround    =       true,
3958 };
3959
3960 static int __init dispc_init_features(struct device *dev)
3961 {
3962         const struct dispc_features *src;
3963         struct dispc_features *dst;
3964
3965         dst = devm_kzalloc(dev, sizeof(*dst), GFP_KERNEL);
3966         if (!dst) {
3967                 dev_err(dev, "Failed to allocate DISPC Features\n");
3968                 return -ENOMEM;
3969         }
3970
3971         if (cpu_is_omap24xx()) {
3972                 src = &omap24xx_dispc_feats;
3973         } else if (cpu_is_omap34xx()) {
3974                 if (omap_rev() < OMAP3430_REV_ES3_0)
3975                         src = &omap34xx_rev1_0_dispc_feats;
3976                 else
3977                         src = &omap34xx_rev3_0_dispc_feats;
3978         } else if (cpu_is_omap44xx()) {
3979                 src = &omap44xx_dispc_feats;
3980         } else if (soc_is_omap54xx()) {
3981                 src = &omap44xx_dispc_feats;
3982         } else {
3983                 return -ENODEV;
3984         }
3985
3986         memcpy(dst, src, sizeof(*dst));
3987         dispc.feat = dst;
3988
3989         return 0;
3990 }
3991
3992 /* DISPC HW IP initialisation */
3993 static int __init omap_dispchw_probe(struct platform_device *pdev)
3994 {
3995         u32 rev;
3996         int r = 0;
3997         struct resource *dispc_mem;
3998         struct clk *clk;
3999
4000         dispc.pdev = pdev;
4001
4002         r = dispc_init_features(&dispc.pdev->dev);
4003         if (r)
4004                 return r;
4005
4006         spin_lock_init(&dispc.irq_lock);
4007
4008 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
4009         spin_lock_init(&dispc.irq_stats_lock);
4010         dispc.irq_stats.last_reset = jiffies;
4011 #endif
4012
4013         INIT_WORK(&dispc.error_work, dispc_error_worker);
4014
4015         dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
4016         if (!dispc_mem) {
4017                 DSSERR("can't get IORESOURCE_MEM DISPC\n");
4018                 return -EINVAL;
4019         }
4020
4021         dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
4022                                   resource_size(dispc_mem));
4023         if (!dispc.base) {
4024                 DSSERR("can't ioremap DISPC\n");
4025                 return -ENOMEM;
4026         }
4027
4028         dispc.irq = platform_get_irq(dispc.pdev, 0);
4029         if (dispc.irq < 0) {
4030                 DSSERR("platform_get_irq failed\n");
4031                 return -ENODEV;
4032         }
4033
4034         r = devm_request_irq(&pdev->dev, dispc.irq, omap_dispc_irq_handler,
4035                              IRQF_SHARED, "OMAP DISPC", dispc.pdev);
4036         if (r < 0) {
4037                 DSSERR("request_irq failed\n");
4038                 return r;
4039         }
4040
4041         clk = clk_get(&pdev->dev, "fck");
4042         if (IS_ERR(clk)) {
4043                 DSSERR("can't get fck\n");
4044                 r = PTR_ERR(clk);
4045                 return r;
4046         }
4047
4048         dispc.dss_clk = clk;
4049
4050         pm_runtime_enable(&pdev->dev);
4051
4052         r = dispc_runtime_get();
4053         if (r)
4054                 goto err_runtime_get;
4055
4056         _omap_dispc_initial_config();
4057
4058         _omap_dispc_initialize_irq();
4059
4060         rev = dispc_read_reg(DISPC_REVISION);
4061         dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
4062                FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
4063
4064         dispc_runtime_put();
4065
4066         dss_debugfs_create_file("dispc", dispc_dump_regs);
4067
4068 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
4069         dss_debugfs_create_file("dispc_irq", dispc_dump_irqs);
4070 #endif
4071         return 0;
4072
4073 err_runtime_get:
4074         pm_runtime_disable(&pdev->dev);
4075         clk_put(dispc.dss_clk);
4076         return r;
4077 }
4078
4079 static int __exit omap_dispchw_remove(struct platform_device *pdev)
4080 {
4081         pm_runtime_disable(&pdev->dev);
4082
4083         clk_put(dispc.dss_clk);
4084
4085         return 0;
4086 }
4087
4088 static int dispc_runtime_suspend(struct device *dev)
4089 {
4090         dispc_save_context();
4091
4092         return 0;
4093 }
4094
4095 static int dispc_runtime_resume(struct device *dev)
4096 {
4097         dispc_restore_context();
4098
4099         return 0;
4100 }
4101
4102 static const struct dev_pm_ops dispc_pm_ops = {
4103         .runtime_suspend = dispc_runtime_suspend,
4104         .runtime_resume = dispc_runtime_resume,
4105 };
4106
4107 static struct platform_driver omap_dispchw_driver = {
4108         .remove         = __exit_p(omap_dispchw_remove),
4109         .driver         = {
4110                 .name   = "omapdss_dispc",
4111                 .owner  = THIS_MODULE,
4112                 .pm     = &dispc_pm_ops,
4113         },
4114 };
4115
4116 int __init dispc_init_platform_driver(void)
4117 {
4118         return platform_driver_probe(&omap_dispchw_driver, omap_dispchw_probe);
4119 }
4120
4121 void __exit dispc_uninit_platform_driver(void)
4122 {
4123         platform_driver_unregister(&omap_dispchw_driver);
4124 }