2 * linux/drivers/video/omap2/dss/dispc.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * Some code and ideas taken from drivers/video/omap/ driver
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
23 #define DSS_SUBSYS_NAME "DISPC"
25 #include <linux/kernel.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/vmalloc.h>
28 #include <linux/export.h>
29 #include <linux/clk.h>
31 #include <linux/jiffies.h>
32 #include <linux/seq_file.h>
33 #include <linux/delay.h>
34 #include <linux/workqueue.h>
35 #include <linux/hardirq.h>
36 #include <linux/platform_device.h>
37 #include <linux/pm_runtime.h>
38 #include <linux/sizes.h>
40 #include <video/omapdss.h>
43 #include "dss_features.h"
47 #define DISPC_SZ_REGS SZ_4K
49 enum omap_burst_size {
55 #define REG_GET(idx, start, end) \
56 FLD_GET(dispc_read_reg(idx), start, end)
58 #define REG_FLD_MOD(idx, val, start, end) \
59 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
61 struct dispc_features {
72 unsigned long max_lcd_pclk;
73 unsigned long max_tv_pclk;
74 int (*calc_scaling) (unsigned long pclk, unsigned long lclk,
75 const struct omap_video_timings *mgr_timings,
76 u16 width, u16 height, u16 out_width, u16 out_height,
77 enum omap_color_mode color_mode, bool *five_taps,
78 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
79 u16 pos_x, unsigned long *core_clk, bool mem_to_mem);
80 unsigned long (*calc_core_clk) (unsigned long pclk,
81 u16 width, u16 height, u16 out_width, u16 out_height,
85 /* swap GFX & WB fifos */
86 bool gfx_fifo_workaround:1;
88 /* no DISPC_IRQ_FRAMEDONETV on this SoC */
89 bool no_framedone_tv:1;
91 /* revert to the OMAP4 mechanism of DISPC Smart Standby operation */
92 bool mstandby_workaround:1;
94 bool set_max_preload:1;
97 #define DISPC_MAX_NR_FIFOS 5
100 struct platform_device *pdev;
105 unsigned long core_clk_rate;
106 unsigned long tv_pclk_rate;
108 u32 fifo_size[DISPC_MAX_NR_FIFOS];
109 /* maps which plane is using a fifo. fifo-id -> plane-id */
110 int fifo_assignment[DISPC_MAX_NR_FIFOS];
113 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
115 const struct dispc_features *feat;
118 enum omap_color_component {
119 /* used for all color formats for OMAP3 and earlier
120 * and for RGB and Y color component on OMAP4
122 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
123 /* used for UV component for
124 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
125 * color formats on OMAP4
127 DISPC_COLOR_COMPONENT_UV = 1 << 1,
130 enum mgr_reg_fields {
131 DISPC_MGR_FLD_ENABLE,
132 DISPC_MGR_FLD_STNTFT,
134 DISPC_MGR_FLD_TFTDATALINES,
135 DISPC_MGR_FLD_STALLMODE,
136 DISPC_MGR_FLD_TCKENABLE,
137 DISPC_MGR_FLD_TCKSELECTION,
139 DISPC_MGR_FLD_FIFOHANDCHECK,
140 /* used to maintain a count of the above fields */
144 static const struct {
149 struct reg_field reg_desc[DISPC_MGR_FLD_NUM];
151 [OMAP_DSS_CHANNEL_LCD] = {
153 .vsync_irq = DISPC_IRQ_VSYNC,
154 .framedone_irq = DISPC_IRQ_FRAMEDONE,
155 .sync_lost_irq = DISPC_IRQ_SYNC_LOST,
157 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 },
158 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 },
159 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 },
160 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 },
161 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 },
162 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 10, 10 },
163 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 11, 11 },
164 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG, 15, 15 },
165 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
168 [OMAP_DSS_CHANNEL_DIGIT] = {
170 .vsync_irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
171 .framedone_irq = DISPC_IRQ_FRAMEDONETV,
172 .sync_lost_irq = DISPC_IRQ_SYNC_LOST_DIGIT,
174 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 },
175 [DISPC_MGR_FLD_STNTFT] = { },
176 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 },
177 [DISPC_MGR_FLD_TFTDATALINES] = { },
178 [DISPC_MGR_FLD_STALLMODE] = { },
179 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 12, 12 },
180 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 13, 13 },
181 [DISPC_MGR_FLD_CPR] = { },
182 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
185 [OMAP_DSS_CHANNEL_LCD2] = {
187 .vsync_irq = DISPC_IRQ_VSYNC2,
188 .framedone_irq = DISPC_IRQ_FRAMEDONE2,
189 .sync_lost_irq = DISPC_IRQ_SYNC_LOST2,
191 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL2, 0, 0 },
192 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL2, 3, 3 },
193 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 },
194 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL2, 9, 8 },
195 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL2, 11, 11 },
196 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG2, 10, 10 },
197 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG2, 11, 11 },
198 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG2, 15, 15 },
199 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG2, 16, 16 },
202 [OMAP_DSS_CHANNEL_LCD3] = {
204 .vsync_irq = DISPC_IRQ_VSYNC3,
205 .framedone_irq = DISPC_IRQ_FRAMEDONE3,
206 .sync_lost_irq = DISPC_IRQ_SYNC_LOST3,
208 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL3, 0, 0 },
209 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL3, 3, 3 },
210 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL3, 5, 5 },
211 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL3, 9, 8 },
212 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL3, 11, 11 },
213 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG3, 10, 10 },
214 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG3, 11, 11 },
215 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG3, 15, 15 },
216 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG3, 16, 16 },
221 struct color_conv_coef {
222 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
226 static unsigned long dispc_plane_pclk_rate(enum omap_plane plane);
227 static unsigned long dispc_plane_lclk_rate(enum omap_plane plane);
229 static inline void dispc_write_reg(const u16 idx, u32 val)
231 __raw_writel(val, dispc.base + idx);
234 static inline u32 dispc_read_reg(const u16 idx)
236 return __raw_readl(dispc.base + idx);
239 static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)
241 const struct reg_field rfld = mgr_desc[channel].reg_desc[regfld];
242 return REG_GET(rfld.reg, rfld.high, rfld.low);
245 static void mgr_fld_write(enum omap_channel channel,
246 enum mgr_reg_fields regfld, int val) {
247 const struct reg_field rfld = mgr_desc[channel].reg_desc[regfld];
248 REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
252 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
254 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
256 static void dispc_save_context(void)
260 DSSDBG("dispc_save_context\n");
266 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
267 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
269 if (dss_has_feature(FEAT_MGR_LCD2)) {
273 if (dss_has_feature(FEAT_MGR_LCD3)) {
278 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
279 SR(DEFAULT_COLOR(i));
282 if (i == OMAP_DSS_CHANNEL_DIGIT)
293 if (dss_has_feature(FEAT_CPR)) {
300 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
305 SR(OVL_ATTRIBUTES(i));
306 SR(OVL_FIFO_THRESHOLD(i));
308 SR(OVL_PIXEL_INC(i));
309 if (dss_has_feature(FEAT_PRELOAD))
311 if (i == OMAP_DSS_GFX) {
312 SR(OVL_WINDOW_SKIP(i));
317 SR(OVL_PICTURE_SIZE(i));
321 for (j = 0; j < 8; j++)
322 SR(OVL_FIR_COEF_H(i, j));
324 for (j = 0; j < 8; j++)
325 SR(OVL_FIR_COEF_HV(i, j));
327 for (j = 0; j < 5; j++)
328 SR(OVL_CONV_COEF(i, j));
330 if (dss_has_feature(FEAT_FIR_COEF_V)) {
331 for (j = 0; j < 8; j++)
332 SR(OVL_FIR_COEF_V(i, j));
335 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
342 for (j = 0; j < 8; j++)
343 SR(OVL_FIR_COEF_H2(i, j));
345 for (j = 0; j < 8; j++)
346 SR(OVL_FIR_COEF_HV2(i, j));
348 for (j = 0; j < 8; j++)
349 SR(OVL_FIR_COEF_V2(i, j));
351 if (dss_has_feature(FEAT_ATTR2))
352 SR(OVL_ATTRIBUTES2(i));
355 if (dss_has_feature(FEAT_CORE_CLK_DIV))
358 dispc.ctx_valid = true;
360 DSSDBG("context saved\n");
363 static void dispc_restore_context(void)
367 DSSDBG("dispc_restore_context\n");
369 if (!dispc.ctx_valid)
376 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
377 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
379 if (dss_has_feature(FEAT_MGR_LCD2))
381 if (dss_has_feature(FEAT_MGR_LCD3))
384 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
385 RR(DEFAULT_COLOR(i));
388 if (i == OMAP_DSS_CHANNEL_DIGIT)
399 if (dss_has_feature(FEAT_CPR)) {
406 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
411 RR(OVL_ATTRIBUTES(i));
412 RR(OVL_FIFO_THRESHOLD(i));
414 RR(OVL_PIXEL_INC(i));
415 if (dss_has_feature(FEAT_PRELOAD))
417 if (i == OMAP_DSS_GFX) {
418 RR(OVL_WINDOW_SKIP(i));
423 RR(OVL_PICTURE_SIZE(i));
427 for (j = 0; j < 8; j++)
428 RR(OVL_FIR_COEF_H(i, j));
430 for (j = 0; j < 8; j++)
431 RR(OVL_FIR_COEF_HV(i, j));
433 for (j = 0; j < 5; j++)
434 RR(OVL_CONV_COEF(i, j));
436 if (dss_has_feature(FEAT_FIR_COEF_V)) {
437 for (j = 0; j < 8; j++)
438 RR(OVL_FIR_COEF_V(i, j));
441 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
448 for (j = 0; j < 8; j++)
449 RR(OVL_FIR_COEF_H2(i, j));
451 for (j = 0; j < 8; j++)
452 RR(OVL_FIR_COEF_HV2(i, j));
454 for (j = 0; j < 8; j++)
455 RR(OVL_FIR_COEF_V2(i, j));
457 if (dss_has_feature(FEAT_ATTR2))
458 RR(OVL_ATTRIBUTES2(i));
461 if (dss_has_feature(FEAT_CORE_CLK_DIV))
464 /* enable last, because LCD & DIGIT enable are here */
466 if (dss_has_feature(FEAT_MGR_LCD2))
468 if (dss_has_feature(FEAT_MGR_LCD3))
470 /* clear spurious SYNC_LOST_DIGIT interrupts */
471 dispc_clear_irqstatus(DISPC_IRQ_SYNC_LOST_DIGIT);
474 * enable last so IRQs won't trigger before
475 * the context is fully restored
479 DSSDBG("context restored\n");
485 int dispc_runtime_get(void)
489 DSSDBG("dispc_runtime_get\n");
491 r = pm_runtime_get_sync(&dispc.pdev->dev);
493 return r < 0 ? r : 0;
495 EXPORT_SYMBOL(dispc_runtime_get);
497 void dispc_runtime_put(void)
501 DSSDBG("dispc_runtime_put\n");
503 r = pm_runtime_put_sync(&dispc.pdev->dev);
504 WARN_ON(r < 0 && r != -ENOSYS);
506 EXPORT_SYMBOL(dispc_runtime_put);
508 u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
510 return mgr_desc[channel].vsync_irq;
512 EXPORT_SYMBOL(dispc_mgr_get_vsync_irq);
514 u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
516 if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv)
519 return mgr_desc[channel].framedone_irq;
521 EXPORT_SYMBOL(dispc_mgr_get_framedone_irq);
523 u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel)
525 return mgr_desc[channel].sync_lost_irq;
527 EXPORT_SYMBOL(dispc_mgr_get_sync_lost_irq);
529 u32 dispc_wb_get_framedone_irq(void)
531 return DISPC_IRQ_FRAMEDONEWB;
534 bool dispc_mgr_go_busy(enum omap_channel channel)
536 return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
538 EXPORT_SYMBOL(dispc_mgr_go_busy);
540 void dispc_mgr_go(enum omap_channel channel)
542 WARN_ON(dispc_mgr_is_enabled(channel) == false);
543 WARN_ON(dispc_mgr_go_busy(channel));
545 DSSDBG("GO %s\n", mgr_desc[channel].name);
547 mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
549 EXPORT_SYMBOL(dispc_mgr_go);
551 bool dispc_wb_go_busy(void)
553 return REG_GET(DISPC_CONTROL2, 6, 6) == 1;
556 void dispc_wb_go(void)
558 enum omap_plane plane = OMAP_DSS_WB;
561 enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1;
566 go = REG_GET(DISPC_CONTROL2, 6, 6) == 1;
568 DSSERR("GO bit not down for WB\n");
572 REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6);
575 static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
577 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
580 static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
582 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
585 static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
587 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
590 static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
592 BUG_ON(plane == OMAP_DSS_GFX);
594 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
597 static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
600 BUG_ON(plane == OMAP_DSS_GFX);
602 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
605 static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
607 BUG_ON(plane == OMAP_DSS_GFX);
609 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
612 static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
613 int fir_vinc, int five_taps,
614 enum omap_color_component color_comp)
616 const struct dispc_coef *h_coef, *v_coef;
619 h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
620 v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
622 for (i = 0; i < 8; i++) {
625 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
626 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
627 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
628 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
629 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
630 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
631 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
632 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
634 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
635 dispc_ovl_write_firh_reg(plane, i, h);
636 dispc_ovl_write_firhv_reg(plane, i, hv);
638 dispc_ovl_write_firh2_reg(plane, i, h);
639 dispc_ovl_write_firhv2_reg(plane, i, hv);
645 for (i = 0; i < 8; i++) {
647 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
648 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
649 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
650 dispc_ovl_write_firv_reg(plane, i, v);
652 dispc_ovl_write_firv2_reg(plane, i, v);
658 static void dispc_ovl_write_color_conv_coef(enum omap_plane plane,
659 const struct color_conv_coef *ct)
661 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
663 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry));
664 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb));
665 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr));
666 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by));
667 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb));
669 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);
674 static void dispc_setup_color_conv_coef(void)
677 int num_ovl = dss_feat_get_num_ovls();
678 int num_wb = dss_feat_get_num_wbs();
679 const struct color_conv_coef ctbl_bt601_5_ovl = {
680 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
682 const struct color_conv_coef ctbl_bt601_5_wb = {
683 66, 112, -38, 129, -94, -74, 25, -18, 112, 0,
686 for (i = 1; i < num_ovl; i++)
687 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_ovl);
689 for (; i < num_wb; i++)
690 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_wb);
693 static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
695 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
698 static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
700 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
703 static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
705 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
708 static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
710 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
713 static void dispc_ovl_set_pos(enum omap_plane plane,
714 enum omap_overlay_caps caps, int x, int y)
718 if ((caps & OMAP_DSS_OVL_CAP_POS) == 0)
721 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
723 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
726 static void dispc_ovl_set_input_size(enum omap_plane plane, int width,
729 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
731 if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB)
732 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
734 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
737 static void dispc_ovl_set_output_size(enum omap_plane plane, int width,
742 BUG_ON(plane == OMAP_DSS_GFX);
744 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
746 if (plane == OMAP_DSS_WB)
747 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
749 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
752 static void dispc_ovl_set_zorder(enum omap_plane plane,
753 enum omap_overlay_caps caps, u8 zorder)
755 if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
758 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
761 static void dispc_ovl_enable_zorder_planes(void)
765 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
768 for (i = 0; i < dss_feat_get_num_ovls(); i++)
769 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
772 static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane,
773 enum omap_overlay_caps caps, bool enable)
775 if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
778 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
781 static void dispc_ovl_setup_global_alpha(enum omap_plane plane,
782 enum omap_overlay_caps caps, u8 global_alpha)
784 static const unsigned shifts[] = { 0, 8, 16, 24, };
787 if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
790 shift = shifts[plane];
791 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
794 static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
796 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
799 static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
801 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
804 static void dispc_ovl_set_color_mode(enum omap_plane plane,
805 enum omap_color_mode color_mode)
808 if (plane != OMAP_DSS_GFX) {
809 switch (color_mode) {
810 case OMAP_DSS_COLOR_NV12:
812 case OMAP_DSS_COLOR_RGBX16:
814 case OMAP_DSS_COLOR_RGBA16:
816 case OMAP_DSS_COLOR_RGB12U:
818 case OMAP_DSS_COLOR_ARGB16:
820 case OMAP_DSS_COLOR_RGB16:
822 case OMAP_DSS_COLOR_ARGB16_1555:
824 case OMAP_DSS_COLOR_RGB24U:
826 case OMAP_DSS_COLOR_RGB24P:
828 case OMAP_DSS_COLOR_YUV2:
830 case OMAP_DSS_COLOR_UYVY:
832 case OMAP_DSS_COLOR_ARGB32:
834 case OMAP_DSS_COLOR_RGBA32:
836 case OMAP_DSS_COLOR_RGBX32:
838 case OMAP_DSS_COLOR_XRGB16_1555:
844 switch (color_mode) {
845 case OMAP_DSS_COLOR_CLUT1:
847 case OMAP_DSS_COLOR_CLUT2:
849 case OMAP_DSS_COLOR_CLUT4:
851 case OMAP_DSS_COLOR_CLUT8:
853 case OMAP_DSS_COLOR_RGB12U:
855 case OMAP_DSS_COLOR_ARGB16:
857 case OMAP_DSS_COLOR_RGB16:
859 case OMAP_DSS_COLOR_ARGB16_1555:
861 case OMAP_DSS_COLOR_RGB24U:
863 case OMAP_DSS_COLOR_RGB24P:
865 case OMAP_DSS_COLOR_RGBX16:
867 case OMAP_DSS_COLOR_RGBA16:
869 case OMAP_DSS_COLOR_ARGB32:
871 case OMAP_DSS_COLOR_RGBA32:
873 case OMAP_DSS_COLOR_RGBX32:
875 case OMAP_DSS_COLOR_XRGB16_1555:
882 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
885 static void dispc_ovl_configure_burst_type(enum omap_plane plane,
886 enum omap_dss_rotation_type rotation_type)
888 if (dss_has_feature(FEAT_BURST_2D) == 0)
891 if (rotation_type == OMAP_DSS_ROT_TILER)
892 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
894 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
897 void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
901 int chan = 0, chan2 = 0;
907 case OMAP_DSS_VIDEO1:
908 case OMAP_DSS_VIDEO2:
909 case OMAP_DSS_VIDEO3:
917 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
918 if (dss_has_feature(FEAT_MGR_LCD2)) {
920 case OMAP_DSS_CHANNEL_LCD:
924 case OMAP_DSS_CHANNEL_DIGIT:
928 case OMAP_DSS_CHANNEL_LCD2:
932 case OMAP_DSS_CHANNEL_LCD3:
933 if (dss_has_feature(FEAT_MGR_LCD3)) {
946 val = FLD_MOD(val, chan, shift, shift);
947 val = FLD_MOD(val, chan2, 31, 30);
949 val = FLD_MOD(val, channel, shift, shift);
951 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
953 EXPORT_SYMBOL(dispc_ovl_set_channel_out);
955 static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
959 enum omap_channel channel;
965 case OMAP_DSS_VIDEO1:
966 case OMAP_DSS_VIDEO2:
967 case OMAP_DSS_VIDEO3:
975 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
977 if (dss_has_feature(FEAT_MGR_LCD3)) {
978 if (FLD_GET(val, 31, 30) == 0)
979 channel = FLD_GET(val, shift, shift);
980 else if (FLD_GET(val, 31, 30) == 1)
981 channel = OMAP_DSS_CHANNEL_LCD2;
983 channel = OMAP_DSS_CHANNEL_LCD3;
984 } else if (dss_has_feature(FEAT_MGR_LCD2)) {
985 if (FLD_GET(val, 31, 30) == 0)
986 channel = FLD_GET(val, shift, shift);
988 channel = OMAP_DSS_CHANNEL_LCD2;
990 channel = FLD_GET(val, shift, shift);
996 void dispc_wb_set_channel_in(enum dss_writeback_channel channel)
998 enum omap_plane plane = OMAP_DSS_WB;
1000 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), channel, 18, 16);
1003 static void dispc_ovl_set_burst_size(enum omap_plane plane,
1004 enum omap_burst_size burst_size)
1006 static const unsigned shifts[] = { 6, 14, 14, 14, 14, };
1009 shift = shifts[plane];
1010 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
1013 static void dispc_configure_burst_sizes(void)
1016 const int burst_size = BURST_SIZE_X8;
1018 /* Configure burst size always to maximum size */
1019 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
1020 dispc_ovl_set_burst_size(i, burst_size);
1023 static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
1025 unsigned unit = dss_feat_get_burst_size_unit();
1026 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
1030 void dispc_enable_gamma_table(bool enable)
1033 * This is partially implemented to support only disabling of
1037 DSSWARN("Gamma table enabling for TV not yet supported");
1041 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
1044 static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
1046 if (channel == OMAP_DSS_CHANNEL_DIGIT)
1049 mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);
1052 static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
1053 const struct omap_dss_cpr_coefs *coefs)
1055 u32 coef_r, coef_g, coef_b;
1057 if (!dss_mgr_is_lcd(channel))
1060 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1061 FLD_VAL(coefs->rb, 9, 0);
1062 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1063 FLD_VAL(coefs->gb, 9, 0);
1064 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1065 FLD_VAL(coefs->bb, 9, 0);
1067 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1068 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1069 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1072 static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
1076 BUG_ON(plane == OMAP_DSS_GFX);
1078 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1079 val = FLD_MOD(val, enable, 9, 9);
1080 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
1083 static void dispc_ovl_enable_replication(enum omap_plane plane,
1084 enum omap_overlay_caps caps, bool enable)
1086 static const unsigned shifts[] = { 5, 10, 10, 10 };
1089 if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0)
1092 shift = shifts[plane];
1093 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
1096 static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
1101 val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) |
1102 FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0);
1104 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
1107 static void dispc_init_fifos(void)
1114 unit = dss_feat_get_buffer_size_unit();
1116 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
1118 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1119 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end);
1121 dispc.fifo_size[fifo] = size;
1124 * By default fifos are mapped directly to overlays, fifo 0 to
1125 * ovl 0, fifo 1 to ovl 1, etc.
1127 dispc.fifo_assignment[fifo] = fifo;
1131 * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo
1132 * causes problems with certain use cases, like using the tiler in 2D
1133 * mode. The below hack swaps the fifos of GFX and WB planes, thus
1134 * giving GFX plane a larger fifo. WB but should work fine with a
1137 if (dispc.feat->gfx_fifo_workaround) {
1140 v = dispc_read_reg(DISPC_GLOBAL_BUFFER);
1142 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */
1143 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */
1144 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */
1145 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */
1147 dispc_write_reg(DISPC_GLOBAL_BUFFER, v);
1149 dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB;
1150 dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX;
1154 static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
1159 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1160 if (dispc.fifo_assignment[fifo] == plane)
1161 size += dispc.fifo_size[fifo];
1167 void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
1169 u8 hi_start, hi_end, lo_start, lo_end;
1172 unit = dss_feat_get_buffer_size_unit();
1174 WARN_ON(low % unit != 0);
1175 WARN_ON(high % unit != 0);
1180 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1181 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1183 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
1185 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1186 lo_start, lo_end) * unit,
1187 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1188 hi_start, hi_end) * unit,
1189 low * unit, high * unit);
1191 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
1192 FLD_VAL(high, hi_start, hi_end) |
1193 FLD_VAL(low, lo_start, lo_end));
1196 * configure the preload to the pipeline's high threhold, if HT it's too
1197 * large for the preload field, set the threshold to the maximum value
1198 * that can be held by the preload register
1200 if (dss_has_feature(FEAT_PRELOAD) && dispc.feat->set_max_preload &&
1201 plane != OMAP_DSS_WB)
1202 dispc_write_reg(DISPC_OVL_PRELOAD(plane), min(high, 0xfffu));
1204 EXPORT_SYMBOL(dispc_ovl_set_fifo_threshold);
1206 void dispc_enable_fifomerge(bool enable)
1208 if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1213 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1214 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1217 void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
1218 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
1222 * All sizes are in bytes. Both the buffer and burst are made of
1223 * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1226 unsigned buf_unit = dss_feat_get_buffer_size_unit();
1227 unsigned ovl_fifo_size, total_fifo_size, burst_size;
1230 burst_size = dispc_ovl_get_burst_size(plane);
1231 ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
1233 if (use_fifomerge) {
1234 total_fifo_size = 0;
1235 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
1236 total_fifo_size += dispc_ovl_get_fifo_size(i);
1238 total_fifo_size = ovl_fifo_size;
1242 * We use the same low threshold for both fifomerge and non-fifomerge
1243 * cases, but for fifomerge we calculate the high threshold using the
1244 * combined fifo size
1247 if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
1248 *fifo_low = ovl_fifo_size - burst_size * 2;
1249 *fifo_high = total_fifo_size - burst_size;
1250 } else if (plane == OMAP_DSS_WB) {
1252 * Most optimal configuration for writeback is to push out data
1253 * to the interconnect the moment writeback pushes enough pixels
1254 * in the FIFO to form a burst
1257 *fifo_high = burst_size;
1259 *fifo_low = ovl_fifo_size - burst_size;
1260 *fifo_high = total_fifo_size - buf_unit;
1263 EXPORT_SYMBOL(dispc_ovl_compute_fifo_thresholds);
1265 static void dispc_ovl_set_fir(enum omap_plane plane,
1267 enum omap_color_component color_comp)
1271 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1272 u8 hinc_start, hinc_end, vinc_start, vinc_end;
1274 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1275 &hinc_start, &hinc_end);
1276 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1277 &vinc_start, &vinc_end);
1278 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1279 FLD_VAL(hinc, hinc_start, hinc_end);
1281 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1283 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1284 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1288 static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1291 u8 hor_start, hor_end, vert_start, vert_end;
1293 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1294 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1296 val = FLD_VAL(vaccu, vert_start, vert_end) |
1297 FLD_VAL(haccu, hor_start, hor_end);
1299 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
1302 static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1305 u8 hor_start, hor_end, vert_start, vert_end;
1307 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1308 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1310 val = FLD_VAL(vaccu, vert_start, vert_end) |
1311 FLD_VAL(haccu, hor_start, hor_end);
1313 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
1316 static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1321 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1322 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1325 static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1330 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1331 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1334 static void dispc_ovl_set_scale_param(enum omap_plane plane,
1335 u16 orig_width, u16 orig_height,
1336 u16 out_width, u16 out_height,
1337 bool five_taps, u8 rotation,
1338 enum omap_color_component color_comp)
1340 int fir_hinc, fir_vinc;
1342 fir_hinc = 1024 * orig_width / out_width;
1343 fir_vinc = 1024 * orig_height / out_height;
1345 dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1347 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
1350 static void dispc_ovl_set_accu_uv(enum omap_plane plane,
1351 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
1352 bool ilace, enum omap_color_mode color_mode, u8 rotation)
1354 int h_accu2_0, h_accu2_1;
1355 int v_accu2_0, v_accu2_1;
1356 int chroma_hinc, chroma_vinc;
1366 const struct accu *accu_table;
1367 const struct accu *accu_val;
1369 static const struct accu accu_nv12[4] = {
1370 { 0, 1, 0, 1 , -1, 2, 0, 1 },
1371 { 1, 2, -3, 4 , 0, 1, 0, 1 },
1372 { -1, 1, 0, 1 , -1, 2, 0, 1 },
1373 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1376 static const struct accu accu_nv12_ilace[4] = {
1377 { 0, 1, 0, 1 , -3, 4, -1, 4 },
1378 { -1, 4, -3, 4 , 0, 1, 0, 1 },
1379 { -1, 1, 0, 1 , -1, 4, -3, 4 },
1380 { -3, 4, -3, 4 , -1, 1, 0, 1 },
1383 static const struct accu accu_yuv[4] = {
1384 { 0, 1, 0, 1, 0, 1, 0, 1 },
1385 { 0, 1, 0, 1, 0, 1, 0, 1 },
1386 { -1, 1, 0, 1, 0, 1, 0, 1 },
1387 { 0, 1, 0, 1, -1, 1, 0, 1 },
1391 case OMAP_DSS_ROT_0:
1394 case OMAP_DSS_ROT_90:
1397 case OMAP_DSS_ROT_180:
1400 case OMAP_DSS_ROT_270:
1408 switch (color_mode) {
1409 case OMAP_DSS_COLOR_NV12:
1411 accu_table = accu_nv12_ilace;
1413 accu_table = accu_nv12;
1415 case OMAP_DSS_COLOR_YUV2:
1416 case OMAP_DSS_COLOR_UYVY:
1417 accu_table = accu_yuv;
1424 accu_val = &accu_table[idx];
1426 chroma_hinc = 1024 * orig_width / out_width;
1427 chroma_vinc = 1024 * orig_height / out_height;
1429 h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1430 h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1431 v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1432 v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1434 dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
1435 dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
1438 static void dispc_ovl_set_scaling_common(enum omap_plane plane,
1439 u16 orig_width, u16 orig_height,
1440 u16 out_width, u16 out_height,
1441 bool ilace, bool five_taps,
1442 bool fieldmode, enum omap_color_mode color_mode,
1449 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1450 out_width, out_height, five_taps,
1451 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
1452 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1454 /* RESIZEENABLE and VERTICALTAPS */
1455 l &= ~((0x3 << 5) | (0x1 << 21));
1456 l |= (orig_width != out_width) ? (1 << 5) : 0;
1457 l |= (orig_height != out_height) ? (1 << 6) : 0;
1458 l |= five_taps ? (1 << 21) : 0;
1460 /* VRESIZECONF and HRESIZECONF */
1461 if (dss_has_feature(FEAT_RESIZECONF)) {
1463 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1464 l |= (orig_height <= out_height) ? 0 : (1 << 8);
1467 /* LINEBUFFERSPLIT */
1468 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1470 l |= five_taps ? (1 << 22) : 0;
1473 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
1476 * field 0 = even field = bottom field
1477 * field 1 = odd field = top field
1479 if (ilace && !fieldmode) {
1481 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
1482 if (accu0 >= 1024/2) {
1488 dispc_ovl_set_vid_accu0(plane, 0, accu0);
1489 dispc_ovl_set_vid_accu1(plane, 0, accu1);
1492 static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
1493 u16 orig_width, u16 orig_height,
1494 u16 out_width, u16 out_height,
1495 bool ilace, bool five_taps,
1496 bool fieldmode, enum omap_color_mode color_mode,
1499 int scale_x = out_width != orig_width;
1500 int scale_y = out_height != orig_height;
1501 bool chroma_upscale = plane != OMAP_DSS_WB ? true : false;
1503 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1505 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1506 color_mode != OMAP_DSS_COLOR_UYVY &&
1507 color_mode != OMAP_DSS_COLOR_NV12)) {
1508 /* reset chroma resampling for RGB formats */
1509 if (plane != OMAP_DSS_WB)
1510 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1514 dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
1515 out_height, ilace, color_mode, rotation);
1517 switch (color_mode) {
1518 case OMAP_DSS_COLOR_NV12:
1519 if (chroma_upscale) {
1520 /* UV is subsampled by 2 horizontally and vertically */
1524 /* UV is downsampled by 2 horizontally and vertically */
1530 case OMAP_DSS_COLOR_YUV2:
1531 case OMAP_DSS_COLOR_UYVY:
1532 /* For YUV422 with 90/270 rotation, we don't upsample chroma */
1533 if (rotation == OMAP_DSS_ROT_0 ||
1534 rotation == OMAP_DSS_ROT_180) {
1536 /* UV is subsampled by 2 horizontally */
1539 /* UV is downsampled by 2 horizontally */
1543 /* must use FIR for YUV422 if rotated */
1544 if (rotation != OMAP_DSS_ROT_0)
1545 scale_x = scale_y = true;
1553 if (out_width != orig_width)
1555 if (out_height != orig_height)
1558 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1559 out_width, out_height, five_taps,
1560 rotation, DISPC_COLOR_COMPONENT_UV);
1562 if (plane != OMAP_DSS_WB)
1563 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1564 (scale_x || scale_y) ? 1 : 0, 8, 8);
1567 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1569 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1572 static void dispc_ovl_set_scaling(enum omap_plane plane,
1573 u16 orig_width, u16 orig_height,
1574 u16 out_width, u16 out_height,
1575 bool ilace, bool five_taps,
1576 bool fieldmode, enum omap_color_mode color_mode,
1579 BUG_ON(plane == OMAP_DSS_GFX);
1581 dispc_ovl_set_scaling_common(plane,
1582 orig_width, orig_height,
1583 out_width, out_height,
1585 fieldmode, color_mode,
1588 dispc_ovl_set_scaling_uv(plane,
1589 orig_width, orig_height,
1590 out_width, out_height,
1592 fieldmode, color_mode,
1596 static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1597 enum omap_dss_rotation_type rotation_type,
1598 bool mirroring, enum omap_color_mode color_mode)
1600 bool row_repeat = false;
1603 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1604 color_mode == OMAP_DSS_COLOR_UYVY) {
1608 case OMAP_DSS_ROT_0:
1611 case OMAP_DSS_ROT_90:
1614 case OMAP_DSS_ROT_180:
1617 case OMAP_DSS_ROT_270:
1623 case OMAP_DSS_ROT_0:
1626 case OMAP_DSS_ROT_90:
1629 case OMAP_DSS_ROT_180:
1632 case OMAP_DSS_ROT_270:
1638 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1644 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
1645 if (dss_has_feature(FEAT_ROWREPEATENABLE))
1646 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1647 row_repeat ? 1 : 0, 18, 18);
1649 if (color_mode == OMAP_DSS_COLOR_NV12) {
1650 bool doublestride = (rotation_type == OMAP_DSS_ROT_TILER) &&
1651 (rotation == OMAP_DSS_ROT_0 ||
1652 rotation == OMAP_DSS_ROT_180);
1654 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), doublestride, 22, 22);
1659 static int color_mode_to_bpp(enum omap_color_mode color_mode)
1661 switch (color_mode) {
1662 case OMAP_DSS_COLOR_CLUT1:
1664 case OMAP_DSS_COLOR_CLUT2:
1666 case OMAP_DSS_COLOR_CLUT4:
1668 case OMAP_DSS_COLOR_CLUT8:
1669 case OMAP_DSS_COLOR_NV12:
1671 case OMAP_DSS_COLOR_RGB12U:
1672 case OMAP_DSS_COLOR_RGB16:
1673 case OMAP_DSS_COLOR_ARGB16:
1674 case OMAP_DSS_COLOR_YUV2:
1675 case OMAP_DSS_COLOR_UYVY:
1676 case OMAP_DSS_COLOR_RGBA16:
1677 case OMAP_DSS_COLOR_RGBX16:
1678 case OMAP_DSS_COLOR_ARGB16_1555:
1679 case OMAP_DSS_COLOR_XRGB16_1555:
1681 case OMAP_DSS_COLOR_RGB24P:
1683 case OMAP_DSS_COLOR_RGB24U:
1684 case OMAP_DSS_COLOR_ARGB32:
1685 case OMAP_DSS_COLOR_RGBA32:
1686 case OMAP_DSS_COLOR_RGBX32:
1694 static s32 pixinc(int pixels, u8 ps)
1698 else if (pixels > 1)
1699 return 1 + (pixels - 1) * ps;
1700 else if (pixels < 0)
1701 return 1 - (-pixels + 1) * ps;
1707 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1709 u16 width, u16 height,
1710 enum omap_color_mode color_mode, bool fieldmode,
1711 unsigned int field_offset,
1712 unsigned *offset0, unsigned *offset1,
1713 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1717 /* FIXME CLUT formats */
1718 switch (color_mode) {
1719 case OMAP_DSS_COLOR_CLUT1:
1720 case OMAP_DSS_COLOR_CLUT2:
1721 case OMAP_DSS_COLOR_CLUT4:
1722 case OMAP_DSS_COLOR_CLUT8:
1725 case OMAP_DSS_COLOR_YUV2:
1726 case OMAP_DSS_COLOR_UYVY:
1730 ps = color_mode_to_bpp(color_mode) / 8;
1734 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1738 * field 0 = even field = bottom field
1739 * field 1 = odd field = top field
1741 switch (rotation + mirror * 4) {
1742 case OMAP_DSS_ROT_0:
1743 case OMAP_DSS_ROT_180:
1745 * If the pixel format is YUV or UYVY divide the width
1746 * of the image by 2 for 0 and 180 degree rotation.
1748 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1749 color_mode == OMAP_DSS_COLOR_UYVY)
1751 case OMAP_DSS_ROT_90:
1752 case OMAP_DSS_ROT_270:
1755 *offset0 = field_offset * screen_width * ps;
1759 *row_inc = pixinc(1 +
1760 (y_predecim * screen_width - x_predecim * width) +
1761 (fieldmode ? screen_width : 0), ps);
1762 *pix_inc = pixinc(x_predecim, ps);
1765 case OMAP_DSS_ROT_0 + 4:
1766 case OMAP_DSS_ROT_180 + 4:
1767 /* If the pixel format is YUV or UYVY divide the width
1768 * of the image by 2 for 0 degree and 180 degree
1770 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1771 color_mode == OMAP_DSS_COLOR_UYVY)
1773 case OMAP_DSS_ROT_90 + 4:
1774 case OMAP_DSS_ROT_270 + 4:
1777 *offset0 = field_offset * screen_width * ps;
1780 *row_inc = pixinc(1 -
1781 (y_predecim * screen_width + x_predecim * width) -
1782 (fieldmode ? screen_width : 0), ps);
1783 *pix_inc = pixinc(x_predecim, ps);
1792 static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1794 u16 width, u16 height,
1795 enum omap_color_mode color_mode, bool fieldmode,
1796 unsigned int field_offset,
1797 unsigned *offset0, unsigned *offset1,
1798 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1803 /* FIXME CLUT formats */
1804 switch (color_mode) {
1805 case OMAP_DSS_COLOR_CLUT1:
1806 case OMAP_DSS_COLOR_CLUT2:
1807 case OMAP_DSS_COLOR_CLUT4:
1808 case OMAP_DSS_COLOR_CLUT8:
1812 ps = color_mode_to_bpp(color_mode) / 8;
1816 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1819 /* width & height are overlay sizes, convert to fb sizes */
1821 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1830 * field 0 = even field = bottom field
1831 * field 1 = odd field = top field
1833 switch (rotation + mirror * 4) {
1834 case OMAP_DSS_ROT_0:
1837 *offset0 = *offset1 + field_offset * screen_width * ps;
1839 *offset0 = *offset1;
1840 *row_inc = pixinc(1 +
1841 (y_predecim * screen_width - fbw * x_predecim) +
1842 (fieldmode ? screen_width : 0), ps);
1843 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1844 color_mode == OMAP_DSS_COLOR_UYVY)
1845 *pix_inc = pixinc(x_predecim, 2 * ps);
1847 *pix_inc = pixinc(x_predecim, ps);
1849 case OMAP_DSS_ROT_90:
1850 *offset1 = screen_width * (fbh - 1) * ps;
1852 *offset0 = *offset1 + field_offset * ps;
1854 *offset0 = *offset1;
1855 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
1856 y_predecim + (fieldmode ? 1 : 0), ps);
1857 *pix_inc = pixinc(-x_predecim * screen_width, ps);
1859 case OMAP_DSS_ROT_180:
1860 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1862 *offset0 = *offset1 - field_offset * screen_width * ps;
1864 *offset0 = *offset1;
1865 *row_inc = pixinc(-1 -
1866 (y_predecim * screen_width - fbw * x_predecim) -
1867 (fieldmode ? screen_width : 0), ps);
1868 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1869 color_mode == OMAP_DSS_COLOR_UYVY)
1870 *pix_inc = pixinc(-x_predecim, 2 * ps);
1872 *pix_inc = pixinc(-x_predecim, ps);
1874 case OMAP_DSS_ROT_270:
1875 *offset1 = (fbw - 1) * ps;
1877 *offset0 = *offset1 - field_offset * ps;
1879 *offset0 = *offset1;
1880 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
1881 y_predecim - (fieldmode ? 1 : 0), ps);
1882 *pix_inc = pixinc(x_predecim * screen_width, ps);
1886 case OMAP_DSS_ROT_0 + 4:
1887 *offset1 = (fbw - 1) * ps;
1889 *offset0 = *offset1 + field_offset * screen_width * ps;
1891 *offset0 = *offset1;
1892 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
1893 (fieldmode ? screen_width : 0),
1895 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1896 color_mode == OMAP_DSS_COLOR_UYVY)
1897 *pix_inc = pixinc(-x_predecim, 2 * ps);
1899 *pix_inc = pixinc(-x_predecim, ps);
1902 case OMAP_DSS_ROT_90 + 4:
1905 *offset0 = *offset1 + field_offset * ps;
1907 *offset0 = *offset1;
1908 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
1909 y_predecim + (fieldmode ? 1 : 0),
1911 *pix_inc = pixinc(x_predecim * screen_width, ps);
1914 case OMAP_DSS_ROT_180 + 4:
1915 *offset1 = screen_width * (fbh - 1) * ps;
1917 *offset0 = *offset1 - field_offset * screen_width * ps;
1919 *offset0 = *offset1;
1920 *row_inc = pixinc(1 - y_predecim * screen_width * 2 -
1921 (fieldmode ? screen_width : 0),
1923 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1924 color_mode == OMAP_DSS_COLOR_UYVY)
1925 *pix_inc = pixinc(x_predecim, 2 * ps);
1927 *pix_inc = pixinc(x_predecim, ps);
1930 case OMAP_DSS_ROT_270 + 4:
1931 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1933 *offset0 = *offset1 - field_offset * ps;
1935 *offset0 = *offset1;
1936 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
1937 y_predecim - (fieldmode ? 1 : 0),
1939 *pix_inc = pixinc(-x_predecim * screen_width, ps);
1948 static void calc_tiler_rotation_offset(u16 screen_width, u16 width,
1949 enum omap_color_mode color_mode, bool fieldmode,
1950 unsigned int field_offset, unsigned *offset0, unsigned *offset1,
1951 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1955 switch (color_mode) {
1956 case OMAP_DSS_COLOR_CLUT1:
1957 case OMAP_DSS_COLOR_CLUT2:
1958 case OMAP_DSS_COLOR_CLUT4:
1959 case OMAP_DSS_COLOR_CLUT8:
1963 ps = color_mode_to_bpp(color_mode) / 8;
1967 DSSDBG("scrw %d, width %d\n", screen_width, width);
1970 * field 0 = even field = bottom field
1971 * field 1 = odd field = top field
1975 *offset0 = *offset1 + field_offset * screen_width * ps;
1977 *offset0 = *offset1;
1978 *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) +
1979 (fieldmode ? screen_width : 0), ps);
1980 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1981 color_mode == OMAP_DSS_COLOR_UYVY)
1982 *pix_inc = pixinc(x_predecim, 2 * ps);
1984 *pix_inc = pixinc(x_predecim, ps);
1988 * This function is used to avoid synclosts in OMAP3, because of some
1989 * undocumented horizontal position and timing related limitations.
1991 static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk,
1992 const struct omap_video_timings *t, u16 pos_x,
1993 u16 width, u16 height, u16 out_width, u16 out_height,
1996 const int ds = DIV_ROUND_UP(height, out_height);
1997 unsigned long nonactive;
1998 static const u8 limits[3] = { 8, 10, 20 };
2002 nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
2005 if (out_height < height)
2007 if (out_width < width)
2009 blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
2010 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
2011 if (blank <= limits[i])
2014 /* FIXME add checks for 3-tap filter once the limitations are known */
2019 * Pixel data should be prepared before visible display point starts.
2020 * So, atleast DS-2 lines must have already been fetched by DISPC
2021 * during nonactive - pos_x period.
2023 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
2024 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
2025 val, max(0, ds - 2) * width);
2026 if (val < max(0, ds - 2) * width)
2030 * All lines need to be refilled during the nonactive period of which
2031 * only one line can be loaded during the active period. So, atleast
2032 * DS - 1 lines should be loaded during nonactive period.
2034 val = div_u64((u64)nonactive * lclk, pclk);
2035 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n",
2036 val, max(0, ds - 1) * width);
2037 if (val < max(0, ds - 1) * width)
2043 static unsigned long calc_core_clk_five_taps(unsigned long pclk,
2044 const struct omap_video_timings *mgr_timings, u16 width,
2045 u16 height, u16 out_width, u16 out_height,
2046 enum omap_color_mode color_mode)
2051 if (height <= out_height && width <= out_width)
2052 return (unsigned long) pclk;
2054 if (height > out_height) {
2055 unsigned int ppl = mgr_timings->x_res;
2057 tmp = pclk * height * out_width;
2058 do_div(tmp, 2 * out_height * ppl);
2061 if (height > 2 * out_height) {
2062 if (ppl == out_width)
2065 tmp = pclk * (height - 2 * out_height) * out_width;
2066 do_div(tmp, 2 * out_height * (ppl - out_width));
2067 core_clk = max_t(u32, core_clk, tmp);
2071 if (width > out_width) {
2073 do_div(tmp, out_width);
2074 core_clk = max_t(u32, core_clk, tmp);
2076 if (color_mode == OMAP_DSS_COLOR_RGB24U)
2083 static unsigned long calc_core_clk_24xx(unsigned long pclk, u16 width,
2084 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2086 if (height > out_height && width > out_width)
2092 static unsigned long calc_core_clk_34xx(unsigned long pclk, u16 width,
2093 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2095 unsigned int hf, vf;
2098 * FIXME how to determine the 'A' factor
2099 * for the no downscaling case ?
2102 if (width > 3 * out_width)
2104 else if (width > 2 * out_width)
2106 else if (width > out_width)
2110 if (height > out_height)
2115 return pclk * vf * hf;
2118 static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width,
2119 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2122 * If the overlay/writeback is in mem to mem mode, there are no
2123 * downscaling limitations with respect to pixel clock, return 1 as
2124 * required core clock to represent that we have sufficient enough
2125 * core clock to do maximum downscaling
2130 if (width > out_width)
2131 return DIV_ROUND_UP(pclk, out_width) * width;
2136 static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk,
2137 const struct omap_video_timings *mgr_timings,
2138 u16 width, u16 height, u16 out_width, u16 out_height,
2139 enum omap_color_mode color_mode, bool *five_taps,
2140 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2141 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2144 u16 in_width, in_height;
2145 int min_factor = min(*decim_x, *decim_y);
2146 const int maxsinglelinewidth =
2147 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2152 in_height = height / *decim_y;
2153 in_width = width / *decim_x;
2154 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
2155 in_height, out_width, out_height, mem_to_mem);
2156 error = (in_width > maxsinglelinewidth || !*core_clk ||
2157 *core_clk > dispc_core_clk_rate());
2159 if (*decim_x == *decim_y) {
2160 *decim_x = min_factor;
2163 swap(*decim_x, *decim_y);
2164 if (*decim_x < *decim_y)
2168 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2170 if (in_width > maxsinglelinewidth) {
2171 DSSERR("Cannot scale max input width exceeded");
2177 static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk,
2178 const struct omap_video_timings *mgr_timings,
2179 u16 width, u16 height, u16 out_width, u16 out_height,
2180 enum omap_color_mode color_mode, bool *five_taps,
2181 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2182 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2185 u16 in_width, in_height;
2186 int min_factor = min(*decim_x, *decim_y);
2187 const int maxsinglelinewidth =
2188 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2191 in_height = height / *decim_y;
2192 in_width = width / *decim_x;
2193 *five_taps = in_height > out_height;
2195 if (in_width > maxsinglelinewidth)
2196 if (in_height > out_height &&
2197 in_height < out_height * 2)
2201 *core_clk = calc_core_clk_five_taps(pclk, mgr_timings,
2202 in_width, in_height, out_width,
2203 out_height, color_mode);
2205 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
2206 in_height, out_width, out_height,
2209 error = check_horiz_timing_omap3(pclk, lclk, mgr_timings,
2210 pos_x, in_width, in_height, out_width,
2211 out_height, *five_taps);
2212 if (error && *five_taps) {
2217 error = (error || in_width > maxsinglelinewidth * 2 ||
2218 (in_width > maxsinglelinewidth && *five_taps) ||
2219 !*core_clk || *core_clk > dispc_core_clk_rate());
2221 if (*decim_x == *decim_y) {
2222 *decim_x = min_factor;
2225 swap(*decim_x, *decim_y);
2226 if (*decim_x < *decim_y)
2230 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2232 if (check_horiz_timing_omap3(pclk, lclk, mgr_timings, pos_x, width,
2233 height, out_width, out_height, *five_taps)) {
2234 DSSERR("horizontal timing too tight\n");
2238 if (in_width > (maxsinglelinewidth * 2)) {
2239 DSSERR("Cannot setup scaling");
2240 DSSERR("width exceeds maximum width possible");
2244 if (in_width > maxsinglelinewidth && *five_taps) {
2245 DSSERR("cannot setup scaling with five taps");
2251 static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk,
2252 const struct omap_video_timings *mgr_timings,
2253 u16 width, u16 height, u16 out_width, u16 out_height,
2254 enum omap_color_mode color_mode, bool *five_taps,
2255 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2256 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2258 u16 in_width, in_width_max;
2259 int decim_x_min = *decim_x;
2260 u16 in_height = height / *decim_y;
2261 const int maxsinglelinewidth =
2262 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2263 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
2266 in_width_max = out_width * maxdownscale;
2268 in_width_max = dispc_core_clk_rate() /
2269 DIV_ROUND_UP(pclk, out_width);
2272 *decim_x = DIV_ROUND_UP(width, in_width_max);
2274 *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min;
2275 if (*decim_x > *x_predecim)
2279 in_width = width / *decim_x;
2280 } while (*decim_x <= *x_predecim &&
2281 in_width > maxsinglelinewidth && ++*decim_x);
2283 if (in_width > maxsinglelinewidth) {
2284 DSSERR("Cannot scale width exceeds max line width");
2288 *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in_height,
2289 out_width, out_height, mem_to_mem);
2293 static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk,
2294 enum omap_overlay_caps caps,
2295 const struct omap_video_timings *mgr_timings,
2296 u16 width, u16 height, u16 out_width, u16 out_height,
2297 enum omap_color_mode color_mode, bool *five_taps,
2298 int *x_predecim, int *y_predecim, u16 pos_x,
2299 enum omap_dss_rotation_type rotation_type, bool mem_to_mem)
2301 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
2302 const int max_decim_limit = 16;
2303 unsigned long core_clk = 0;
2304 int decim_x, decim_y, ret;
2306 if (width == out_width && height == out_height)
2309 if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
2313 *x_predecim = *y_predecim = 1;
2315 *x_predecim = max_decim_limit;
2316 *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER &&
2317 dss_has_feature(FEAT_BURST_2D)) ?
2318 2 : max_decim_limit;
2321 if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
2322 color_mode == OMAP_DSS_COLOR_CLUT2 ||
2323 color_mode == OMAP_DSS_COLOR_CLUT4 ||
2324 color_mode == OMAP_DSS_COLOR_CLUT8) {
2331 decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
2332 decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
2334 if (decim_x > *x_predecim || out_width > width * 8)
2337 if (decim_y > *y_predecim || out_height > height * 8)
2340 ret = dispc.feat->calc_scaling(pclk, lclk, mgr_timings, width, height,
2341 out_width, out_height, color_mode, five_taps,
2342 x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk,
2347 DSSDBG("required core clk rate = %lu Hz\n", core_clk);
2348 DSSDBG("current core clk rate = %lu Hz\n", dispc_core_clk_rate());
2350 if (!core_clk || core_clk > dispc_core_clk_rate()) {
2351 DSSERR("failed to set up scaling, "
2352 "required core clk rate = %lu Hz, "
2353 "current core clk rate = %lu Hz\n",
2354 core_clk, dispc_core_clk_rate());
2358 *x_predecim = decim_x;
2359 *y_predecim = decim_y;
2363 int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel,
2364 const struct omap_overlay_info *oi,
2365 const struct omap_video_timings *timings,
2366 int *x_predecim, int *y_predecim)
2368 enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
2369 bool five_taps = true;
2370 bool fieldmode = false;
2371 u16 in_height = oi->height;
2372 u16 in_width = oi->width;
2373 bool ilace = timings->interlace;
2374 u16 out_width, out_height;
2375 int pos_x = oi->pos_x;
2376 unsigned long pclk = dispc_mgr_pclk_rate(channel);
2377 unsigned long lclk = dispc_mgr_lclk_rate(channel);
2379 out_width = oi->out_width == 0 ? oi->width : oi->out_width;
2380 out_height = oi->out_height == 0 ? oi->height : oi->out_height;
2382 if (ilace && oi->height == out_height)
2390 DSSDBG("adjusting for ilace: height %d, out_height %d\n",
2391 in_height, out_height);
2394 if (!dss_feat_color_mode_supported(plane, oi->color_mode))
2397 return dispc_ovl_calc_scaling(pclk, lclk, caps, timings, in_width,
2398 in_height, out_width, out_height, oi->color_mode,
2399 &five_taps, x_predecim, y_predecim, pos_x,
2400 oi->rotation_type, false);
2402 EXPORT_SYMBOL(dispc_ovl_check);
2404 static int dispc_ovl_setup_common(enum omap_plane plane,
2405 enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr,
2406 u16 screen_width, int pos_x, int pos_y, u16 width, u16 height,
2407 u16 out_width, u16 out_height, enum omap_color_mode color_mode,
2408 u8 rotation, bool mirror, u8 zorder, u8 pre_mult_alpha,
2409 u8 global_alpha, enum omap_dss_rotation_type rotation_type,
2410 bool replication, const struct omap_video_timings *mgr_timings,
2413 bool five_taps = true;
2414 bool fieldmode = false;
2416 unsigned offset0, offset1;
2419 u16 frame_width, frame_height;
2420 unsigned int field_offset = 0;
2421 u16 in_height = height;
2422 u16 in_width = width;
2423 int x_predecim = 1, y_predecim = 1;
2424 bool ilace = mgr_timings->interlace;
2425 unsigned long pclk = dispc_plane_pclk_rate(plane);
2426 unsigned long lclk = dispc_plane_lclk_rate(plane);
2431 out_width = out_width == 0 ? width : out_width;
2432 out_height = out_height == 0 ? height : out_height;
2434 if (ilace && height == out_height)
2443 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
2444 "out_height %d\n", in_height, pos_y,
2448 if (!dss_feat_color_mode_supported(plane, color_mode))
2451 r = dispc_ovl_calc_scaling(pclk, lclk, caps, mgr_timings, in_width,
2452 in_height, out_width, out_height, color_mode,
2453 &five_taps, &x_predecim, &y_predecim, pos_x,
2454 rotation_type, mem_to_mem);
2458 in_width = in_width / x_predecim;
2459 in_height = in_height / y_predecim;
2461 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2462 color_mode == OMAP_DSS_COLOR_UYVY ||
2463 color_mode == OMAP_DSS_COLOR_NV12)
2466 if (ilace && !fieldmode) {
2468 * when downscaling the bottom field may have to start several
2469 * source lines below the top field. Unfortunately ACCUI
2470 * registers will only hold the fractional part of the offset
2471 * so the integer part must be added to the base address of the
2474 if (!in_height || in_height == out_height)
2477 field_offset = in_height / out_height / 2;
2480 /* Fields are independent but interleaved in memory. */
2489 if (plane == OMAP_DSS_WB) {
2490 frame_width = out_width;
2491 frame_height = out_height;
2493 frame_width = in_width;
2494 frame_height = height;
2497 if (rotation_type == OMAP_DSS_ROT_TILER)
2498 calc_tiler_rotation_offset(screen_width, frame_width,
2499 color_mode, fieldmode, field_offset,
2500 &offset0, &offset1, &row_inc, &pix_inc,
2501 x_predecim, y_predecim);
2502 else if (rotation_type == OMAP_DSS_ROT_DMA)
2503 calc_dma_rotation_offset(rotation, mirror, screen_width,
2504 frame_width, frame_height,
2505 color_mode, fieldmode, field_offset,
2506 &offset0, &offset1, &row_inc, &pix_inc,
2507 x_predecim, y_predecim);
2509 calc_vrfb_rotation_offset(rotation, mirror,
2510 screen_width, frame_width, frame_height,
2511 color_mode, fieldmode, field_offset,
2512 &offset0, &offset1, &row_inc, &pix_inc,
2513 x_predecim, y_predecim);
2515 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2516 offset0, offset1, row_inc, pix_inc);
2518 dispc_ovl_set_color_mode(plane, color_mode);
2520 dispc_ovl_configure_burst_type(plane, rotation_type);
2522 dispc_ovl_set_ba0(plane, paddr + offset0);
2523 dispc_ovl_set_ba1(plane, paddr + offset1);
2525 if (OMAP_DSS_COLOR_NV12 == color_mode) {
2526 dispc_ovl_set_ba0_uv(plane, p_uv_addr + offset0);
2527 dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1);
2530 dispc_ovl_set_row_inc(plane, row_inc);
2531 dispc_ovl_set_pix_inc(plane, pix_inc);
2533 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width,
2534 in_height, out_width, out_height);
2536 dispc_ovl_set_pos(plane, caps, pos_x, pos_y);
2538 dispc_ovl_set_input_size(plane, in_width, in_height);
2540 if (caps & OMAP_DSS_OVL_CAP_SCALE) {
2541 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2542 out_height, ilace, five_taps, fieldmode,
2543 color_mode, rotation);
2544 dispc_ovl_set_output_size(plane, out_width, out_height);
2545 dispc_ovl_set_vid_color_conv(plane, cconv);
2548 dispc_ovl_set_rotation_attrs(plane, rotation, rotation_type, mirror,
2551 dispc_ovl_set_zorder(plane, caps, zorder);
2552 dispc_ovl_set_pre_mult_alpha(plane, caps, pre_mult_alpha);
2553 dispc_ovl_setup_global_alpha(plane, caps, global_alpha);
2555 dispc_ovl_enable_replication(plane, caps, replication);
2560 int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
2561 bool replication, const struct omap_video_timings *mgr_timings,
2565 enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
2566 enum omap_channel channel;
2568 channel = dispc_ovl_get_channel_out(plane);
2570 DSSDBG("dispc_ovl_setup %d, pa %x, pa_uv %x, sw %d, %d,%d, %dx%d -> "
2571 "%dx%d, cmode %x, rot %d, mir %d, chan %d repl %d\n",
2572 plane, oi->paddr, oi->p_uv_addr, oi->screen_width, oi->pos_x,
2573 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height,
2574 oi->color_mode, oi->rotation, oi->mirror, channel, replication);
2576 r = dispc_ovl_setup_common(plane, caps, oi->paddr, oi->p_uv_addr,
2577 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2578 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
2579 oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha,
2580 oi->rotation_type, replication, mgr_timings, mem_to_mem);
2584 EXPORT_SYMBOL(dispc_ovl_setup);
2586 int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
2587 bool mem_to_mem, const struct omap_video_timings *mgr_timings)
2591 enum omap_plane plane = OMAP_DSS_WB;
2592 const int pos_x = 0, pos_y = 0;
2593 const u8 zorder = 0, global_alpha = 0;
2594 const bool replication = false;
2596 int in_width = mgr_timings->x_res;
2597 int in_height = mgr_timings->y_res;
2598 enum omap_overlay_caps caps =
2599 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA;
2601 DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, "
2602 "rot %d, mir %d\n", wi->paddr, wi->p_uv_addr, in_width,
2603 in_height, wi->width, wi->height, wi->color_mode, wi->rotation,
2606 r = dispc_ovl_setup_common(plane, caps, wi->paddr, wi->p_uv_addr,
2607 wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width,
2608 wi->height, wi->color_mode, wi->rotation, wi->mirror, zorder,
2609 wi->pre_mult_alpha, global_alpha, wi->rotation_type,
2610 replication, mgr_timings, mem_to_mem);
2612 switch (wi->color_mode) {
2613 case OMAP_DSS_COLOR_RGB16:
2614 case OMAP_DSS_COLOR_RGB24P:
2615 case OMAP_DSS_COLOR_ARGB16:
2616 case OMAP_DSS_COLOR_RGBA16:
2617 case OMAP_DSS_COLOR_RGB12U:
2618 case OMAP_DSS_COLOR_ARGB16_1555:
2619 case OMAP_DSS_COLOR_XRGB16_1555:
2620 case OMAP_DSS_COLOR_RGBX16:
2628 /* setup extra DISPC_WB_ATTRIBUTES */
2629 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2630 l = FLD_MOD(l, truncation, 10, 10); /* TRUNCATIONENABLE */
2631 l = FLD_MOD(l, mem_to_mem, 19, 19); /* WRITEBACKMODE */
2632 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
2637 int dispc_ovl_enable(enum omap_plane plane, bool enable)
2639 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2641 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
2645 EXPORT_SYMBOL(dispc_ovl_enable);
2647 bool dispc_ovl_enabled(enum omap_plane plane)
2649 return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0);
2651 EXPORT_SYMBOL(dispc_ovl_enabled);
2653 void dispc_mgr_enable(enum omap_channel channel, bool enable)
2655 mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);
2656 /* flush posted write */
2657 mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2659 EXPORT_SYMBOL(dispc_mgr_enable);
2661 bool dispc_mgr_is_enabled(enum omap_channel channel)
2663 return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2665 EXPORT_SYMBOL(dispc_mgr_is_enabled);
2667 void dispc_wb_enable(bool enable)
2669 dispc_ovl_enable(OMAP_DSS_WB, enable);
2672 bool dispc_wb_is_enabled(void)
2674 return dispc_ovl_enabled(OMAP_DSS_WB);
2677 static void dispc_lcd_enable_signal_polarity(bool act_high)
2679 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2682 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
2685 void dispc_lcd_enable_signal(bool enable)
2687 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2690 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
2693 void dispc_pck_free_enable(bool enable)
2695 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2698 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
2701 static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
2703 mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
2707 static void dispc_mgr_set_lcd_type_tft(enum omap_channel channel)
2709 mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1);
2712 void dispc_set_loadmode(enum omap_dss_load_mode mode)
2714 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
2718 static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
2720 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
2723 static void dispc_mgr_set_trans_key(enum omap_channel ch,
2724 enum omap_dss_trans_key_type type,
2727 mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type);
2729 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
2732 static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
2734 mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable);
2737 static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2740 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
2743 if (ch == OMAP_DSS_CHANNEL_LCD)
2744 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2745 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2746 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2749 void dispc_mgr_setup(enum omap_channel channel,
2750 const struct omap_overlay_manager_info *info)
2752 dispc_mgr_set_default_color(channel, info->default_color);
2753 dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
2754 dispc_mgr_enable_trans_key(channel, info->trans_enabled);
2755 dispc_mgr_enable_alpha_fixed_zorder(channel,
2756 info->partial_alpha_enabled);
2757 if (dss_has_feature(FEAT_CPR)) {
2758 dispc_mgr_enable_cpr(channel, info->cpr_enable);
2759 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
2762 EXPORT_SYMBOL(dispc_mgr_setup);
2764 static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
2768 switch (data_lines) {
2786 mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code);
2789 static void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
2795 case DSS_IO_PAD_MODE_RESET:
2799 case DSS_IO_PAD_MODE_RFBI:
2803 case DSS_IO_PAD_MODE_BYPASS:
2812 l = dispc_read_reg(DISPC_CONTROL);
2813 l = FLD_MOD(l, gpout0, 15, 15);
2814 l = FLD_MOD(l, gpout1, 16, 16);
2815 dispc_write_reg(DISPC_CONTROL, l);
2818 static void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
2820 mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);
2823 void dispc_mgr_set_lcd_config(enum omap_channel channel,
2824 const struct dss_lcd_mgr_config *config)
2826 dispc_mgr_set_io_pad_mode(config->io_pad_mode);
2828 dispc_mgr_enable_stallmode(channel, config->stallmode);
2829 dispc_mgr_enable_fifohandcheck(channel, config->fifohandcheck);
2831 dispc_mgr_set_clock_div(channel, &config->clock_info);
2833 dispc_mgr_set_tft_data_lines(channel, config->video_port_width);
2835 dispc_lcd_enable_signal_polarity(config->lcden_sig_polarity);
2837 dispc_mgr_set_lcd_type_tft(channel);
2839 EXPORT_SYMBOL(dispc_mgr_set_lcd_config);
2841 static bool _dispc_mgr_size_ok(u16 width, u16 height)
2843 return width <= dispc.feat->mgr_width_max &&
2844 height <= dispc.feat->mgr_height_max;
2847 static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2848 int vsw, int vfp, int vbp)
2850 if (hsw < 1 || hsw > dispc.feat->sw_max ||
2851 hfp < 1 || hfp > dispc.feat->hp_max ||
2852 hbp < 1 || hbp > dispc.feat->hp_max ||
2853 vsw < 1 || vsw > dispc.feat->sw_max ||
2854 vfp < 0 || vfp > dispc.feat->vp_max ||
2855 vbp < 0 || vbp > dispc.feat->vp_max)
2860 static bool _dispc_mgr_pclk_ok(enum omap_channel channel,
2863 if (dss_mgr_is_lcd(channel))
2864 return pclk <= dispc.feat->max_lcd_pclk ? true : false;
2866 return pclk <= dispc.feat->max_tv_pclk ? true : false;
2869 bool dispc_mgr_timings_ok(enum omap_channel channel,
2870 const struct omap_video_timings *timings)
2874 timings_ok = _dispc_mgr_size_ok(timings->x_res, timings->y_res);
2876 timings_ok &= _dispc_mgr_pclk_ok(channel, timings->pixelclock);
2878 if (dss_mgr_is_lcd(channel)) {
2879 timings_ok &= _dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2880 timings->hbp, timings->vsw, timings->vfp,
2887 static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
2888 int hfp, int hbp, int vsw, int vfp, int vbp,
2889 enum omap_dss_signal_level vsync_level,
2890 enum omap_dss_signal_level hsync_level,
2891 enum omap_dss_signal_edge data_pclk_edge,
2892 enum omap_dss_signal_level de_level,
2893 enum omap_dss_signal_edge sync_pclk_edge)
2896 u32 timing_h, timing_v, l;
2897 bool onoff, rf, ipc;
2899 timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) |
2900 FLD_VAL(hfp-1, dispc.feat->fp_start, 8) |
2901 FLD_VAL(hbp-1, dispc.feat->bp_start, 20);
2902 timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) |
2903 FLD_VAL(vfp, dispc.feat->fp_start, 8) |
2904 FLD_VAL(vbp, dispc.feat->bp_start, 20);
2906 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2907 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
2909 switch (data_pclk_edge) {
2910 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
2913 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
2916 case OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES:
2921 switch (sync_pclk_edge) {
2922 case OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES:
2926 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
2930 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
2938 l = dispc_read_reg(DISPC_POL_FREQ(channel));
2939 l |= FLD_VAL(onoff, 17, 17);
2940 l |= FLD_VAL(rf, 16, 16);
2941 l |= FLD_VAL(de_level, 15, 15);
2942 l |= FLD_VAL(ipc, 14, 14);
2943 l |= FLD_VAL(hsync_level, 13, 13);
2944 l |= FLD_VAL(vsync_level, 12, 12);
2945 dispc_write_reg(DISPC_POL_FREQ(channel), l);
2948 /* change name to mode? */
2949 void dispc_mgr_set_timings(enum omap_channel channel,
2950 const struct omap_video_timings *timings)
2952 unsigned xtot, ytot;
2953 unsigned long ht, vt;
2954 struct omap_video_timings t = *timings;
2956 DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res);
2958 if (!dispc_mgr_timings_ok(channel, &t)) {
2963 if (dss_mgr_is_lcd(channel)) {
2964 _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw,
2965 t.vfp, t.vbp, t.vsync_level, t.hsync_level,
2966 t.data_pclk_edge, t.de_level, t.sync_pclk_edge);
2968 xtot = t.x_res + t.hfp + t.hsw + t.hbp;
2969 ytot = t.y_res + t.vfp + t.vsw + t.vbp;
2971 ht = timings->pixelclock / xtot;
2972 vt = timings->pixelclock / xtot / ytot;
2974 DSSDBG("pck %u\n", timings->pixelclock);
2975 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2976 t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
2977 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
2978 t.vsync_level, t.hsync_level, t.data_pclk_edge,
2979 t.de_level, t.sync_pclk_edge);
2981 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2983 if (t.interlace == true)
2987 dispc_mgr_set_size(channel, t.x_res, t.y_res);
2989 EXPORT_SYMBOL(dispc_mgr_set_timings);
2991 static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
2994 BUG_ON(lck_div < 1);
2995 BUG_ON(pck_div < 1);
2997 dispc_write_reg(DISPC_DIVISORo(channel),
2998 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
3000 if (dss_has_feature(FEAT_CORE_CLK_DIV) == false &&
3001 channel == OMAP_DSS_CHANNEL_LCD)
3002 dispc.core_clk_rate = dispc_fclk_rate() / lck_div;
3005 static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
3009 l = dispc_read_reg(DISPC_DIVISORo(channel));
3010 *lck_div = FLD_GET(l, 23, 16);
3011 *pck_div = FLD_GET(l, 7, 0);
3014 unsigned long dispc_fclk_rate(void)
3016 struct platform_device *dsidev;
3017 unsigned long r = 0;
3019 switch (dss_get_dispc_clk_source()) {
3020 case OMAP_DSS_CLK_SRC_FCK:
3021 r = dss_get_dispc_clk_rate();
3023 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
3024 dsidev = dsi_get_dsidev_from_id(0);
3025 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
3027 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3028 dsidev = dsi_get_dsidev_from_id(1);
3029 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
3039 unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
3041 struct platform_device *dsidev;
3046 if (dss_mgr_is_lcd(channel)) {
3047 l = dispc_read_reg(DISPC_DIVISORo(channel));
3049 lcd = FLD_GET(l, 23, 16);
3051 switch (dss_get_lcd_clk_source(channel)) {
3052 case OMAP_DSS_CLK_SRC_FCK:
3053 r = dss_get_dispc_clk_rate();
3055 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
3056 dsidev = dsi_get_dsidev_from_id(0);
3057 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
3059 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3060 dsidev = dsi_get_dsidev_from_id(1);
3061 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
3070 return dispc_fclk_rate();
3074 unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
3078 if (dss_mgr_is_lcd(channel)) {
3082 l = dispc_read_reg(DISPC_DIVISORo(channel));
3084 pcd = FLD_GET(l, 7, 0);
3086 r = dispc_mgr_lclk_rate(channel);
3090 return dispc.tv_pclk_rate;
3094 void dispc_set_tv_pclk(unsigned long pclk)
3096 dispc.tv_pclk_rate = pclk;
3099 unsigned long dispc_core_clk_rate(void)
3101 return dispc.core_clk_rate;
3104 static unsigned long dispc_plane_pclk_rate(enum omap_plane plane)
3106 enum omap_channel channel;
3108 if (plane == OMAP_DSS_WB)
3111 channel = dispc_ovl_get_channel_out(plane);
3113 return dispc_mgr_pclk_rate(channel);
3116 static unsigned long dispc_plane_lclk_rate(enum omap_plane plane)
3118 enum omap_channel channel;
3120 if (plane == OMAP_DSS_WB)
3123 channel = dispc_ovl_get_channel_out(plane);
3125 return dispc_mgr_lclk_rate(channel);
3128 static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel)
3131 enum omap_dss_clk_source lcd_clk_src;
3133 seq_printf(s, "- %s -\n", mgr_desc[channel].name);
3135 lcd_clk_src = dss_get_lcd_clk_source(channel);
3137 seq_printf(s, "%s clk source = %s (%s)\n", mgr_desc[channel].name,
3138 dss_get_generic_clk_source_name(lcd_clk_src),
3139 dss_feat_get_clk_source_name(lcd_clk_src));
3141 dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd);
3143 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3144 dispc_mgr_lclk_rate(channel), lcd);
3145 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
3146 dispc_mgr_pclk_rate(channel), pcd);
3149 void dispc_dump_clocks(struct seq_file *s)
3153 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
3155 if (dispc_runtime_get())
3158 seq_printf(s, "- DISPC -\n");
3160 seq_printf(s, "dispc fclk source = %s (%s)\n",
3161 dss_get_generic_clk_source_name(dispc_clk_src),
3162 dss_feat_get_clk_source_name(dispc_clk_src));
3164 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
3166 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3167 seq_printf(s, "- DISPC-CORE-CLK -\n");
3168 l = dispc_read_reg(DISPC_DIVISOR);
3169 lcd = FLD_GET(l, 23, 16);
3171 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3172 (dispc_fclk_rate()/lcd), lcd);
3175 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD);
3177 if (dss_has_feature(FEAT_MGR_LCD2))
3178 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2);
3179 if (dss_has_feature(FEAT_MGR_LCD3))
3180 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3);
3182 dispc_runtime_put();
3185 static void dispc_dump_regs(struct seq_file *s)
3188 const char *mgr_names[] = {
3189 [OMAP_DSS_CHANNEL_LCD] = "LCD",
3190 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
3191 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
3192 [OMAP_DSS_CHANNEL_LCD3] = "LCD3",
3194 const char *ovl_names[] = {
3195 [OMAP_DSS_GFX] = "GFX",
3196 [OMAP_DSS_VIDEO1] = "VID1",
3197 [OMAP_DSS_VIDEO2] = "VID2",
3198 [OMAP_DSS_VIDEO3] = "VID3",
3200 const char **p_names;
3202 #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
3204 if (dispc_runtime_get())
3207 /* DISPC common registers */
3208 DUMPREG(DISPC_REVISION);
3209 DUMPREG(DISPC_SYSCONFIG);
3210 DUMPREG(DISPC_SYSSTATUS);
3211 DUMPREG(DISPC_IRQSTATUS);
3212 DUMPREG(DISPC_IRQENABLE);
3213 DUMPREG(DISPC_CONTROL);
3214 DUMPREG(DISPC_CONFIG);
3215 DUMPREG(DISPC_CAPABLE);
3216 DUMPREG(DISPC_LINE_STATUS);
3217 DUMPREG(DISPC_LINE_NUMBER);
3218 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
3219 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
3220 DUMPREG(DISPC_GLOBAL_ALPHA);
3221 if (dss_has_feature(FEAT_MGR_LCD2)) {
3222 DUMPREG(DISPC_CONTROL2);
3223 DUMPREG(DISPC_CONFIG2);
3225 if (dss_has_feature(FEAT_MGR_LCD3)) {
3226 DUMPREG(DISPC_CONTROL3);
3227 DUMPREG(DISPC_CONFIG3);
3229 if (dss_has_feature(FEAT_MFLAG))
3230 DUMPREG(DISPC_GLOBAL_MFLAG_ATTRIBUTE);
3234 #define DISPC_REG(i, name) name(i)
3235 #define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
3236 (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \
3237 dispc_read_reg(DISPC_REG(i, r)))
3239 p_names = mgr_names;
3241 /* DISPC channel specific registers */
3242 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
3243 DUMPREG(i, DISPC_DEFAULT_COLOR);
3244 DUMPREG(i, DISPC_TRANS_COLOR);
3245 DUMPREG(i, DISPC_SIZE_MGR);
3247 if (i == OMAP_DSS_CHANNEL_DIGIT)
3250 DUMPREG(i, DISPC_DEFAULT_COLOR);
3251 DUMPREG(i, DISPC_TRANS_COLOR);
3252 DUMPREG(i, DISPC_TIMING_H);
3253 DUMPREG(i, DISPC_TIMING_V);
3254 DUMPREG(i, DISPC_POL_FREQ);
3255 DUMPREG(i, DISPC_DIVISORo);
3256 DUMPREG(i, DISPC_SIZE_MGR);
3258 DUMPREG(i, DISPC_DATA_CYCLE1);
3259 DUMPREG(i, DISPC_DATA_CYCLE2);
3260 DUMPREG(i, DISPC_DATA_CYCLE3);
3262 if (dss_has_feature(FEAT_CPR)) {
3263 DUMPREG(i, DISPC_CPR_COEF_R);
3264 DUMPREG(i, DISPC_CPR_COEF_G);
3265 DUMPREG(i, DISPC_CPR_COEF_B);
3269 p_names = ovl_names;
3271 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
3272 DUMPREG(i, DISPC_OVL_BA0);
3273 DUMPREG(i, DISPC_OVL_BA1);
3274 DUMPREG(i, DISPC_OVL_POSITION);
3275 DUMPREG(i, DISPC_OVL_SIZE);
3276 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3277 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3278 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3279 DUMPREG(i, DISPC_OVL_ROW_INC);
3280 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3281 if (dss_has_feature(FEAT_PRELOAD))
3282 DUMPREG(i, DISPC_OVL_PRELOAD);
3284 if (i == OMAP_DSS_GFX) {
3285 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
3286 DUMPREG(i, DISPC_OVL_TABLE_BA);
3290 DUMPREG(i, DISPC_OVL_FIR);
3291 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3292 DUMPREG(i, DISPC_OVL_ACCU0);
3293 DUMPREG(i, DISPC_OVL_ACCU1);
3294 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3295 DUMPREG(i, DISPC_OVL_BA0_UV);
3296 DUMPREG(i, DISPC_OVL_BA1_UV);
3297 DUMPREG(i, DISPC_OVL_FIR2);
3298 DUMPREG(i, DISPC_OVL_ACCU2_0);
3299 DUMPREG(i, DISPC_OVL_ACCU2_1);
3301 if (dss_has_feature(FEAT_ATTR2))
3302 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3303 if (dss_has_feature(FEAT_PRELOAD))
3304 DUMPREG(i, DISPC_OVL_PRELOAD);
3305 if (dss_has_feature(FEAT_MFLAG))
3306 DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
3312 #define DISPC_REG(plane, name, i) name(plane, i)
3313 #define DUMPREG(plane, name, i) \
3314 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
3315 (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \
3316 dispc_read_reg(DISPC_REG(plane, name, i)))
3318 /* Video pipeline coefficient registers */
3320 /* start from OMAP_DSS_VIDEO1 */
3321 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
3322 for (j = 0; j < 8; j++)
3323 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
3325 for (j = 0; j < 8; j++)
3326 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
3328 for (j = 0; j < 5; j++)
3329 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
3331 if (dss_has_feature(FEAT_FIR_COEF_V)) {
3332 for (j = 0; j < 8; j++)
3333 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
3336 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3337 for (j = 0; j < 8; j++)
3338 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
3340 for (j = 0; j < 8; j++)
3341 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
3343 for (j = 0; j < 8; j++)
3344 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
3348 dispc_runtime_put();
3354 /* calculate clock rates using dividers in cinfo */
3355 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
3356 struct dispc_clock_info *cinfo)
3358 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3360 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
3363 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3364 cinfo->pck = cinfo->lck / cinfo->pck_div;
3369 bool dispc_div_calc(unsigned long dispc,
3370 unsigned long pck_min, unsigned long pck_max,
3371 dispc_div_calc_func func, void *data)
3373 int lckd, lckd_start, lckd_stop;
3374 int pckd, pckd_start, pckd_stop;
3375 unsigned long pck, lck;
3376 unsigned long lck_max;
3377 unsigned long pckd_hw_min, pckd_hw_max;
3378 unsigned min_fck_per_pck;
3381 #ifdef CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK
3382 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
3384 min_fck_per_pck = 0;
3387 pckd_hw_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
3388 pckd_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
3390 lck_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
3392 pck_min = pck_min ? pck_min : 1;
3393 pck_max = pck_max ? pck_max : ULONG_MAX;
3395 lckd_start = max(DIV_ROUND_UP(dispc, lck_max), 1ul);
3396 lckd_stop = min(dispc / pck_min, 255ul);
3398 for (lckd = lckd_start; lckd <= lckd_stop; ++lckd) {
3401 pckd_start = max(DIV_ROUND_UP(lck, pck_max), pckd_hw_min);
3402 pckd_stop = min(lck / pck_min, pckd_hw_max);
3404 for (pckd = pckd_start; pckd <= pckd_stop; ++pckd) {
3408 * For OMAP2/3 the DISPC fclk is the same as LCD's logic
3409 * clock, which means we're configuring DISPC fclk here
3410 * also. Thus we need to use the calculated lck. For
3411 * OMAP4+ the DISPC fclk is a separate clock.
3413 if (dss_has_feature(FEAT_CORE_CLK_DIV))
3414 fck = dispc_core_clk_rate();
3418 if (fck < pck * min_fck_per_pck)
3421 if (func(lckd, pckd, lck, pck, data))
3429 void dispc_mgr_set_clock_div(enum omap_channel channel,
3430 const struct dispc_clock_info *cinfo)
3432 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3433 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3435 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
3438 int dispc_mgr_get_clock_div(enum omap_channel channel,
3439 struct dispc_clock_info *cinfo)
3443 fck = dispc_fclk_rate();
3445 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3446 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
3448 cinfo->lck = fck / cinfo->lck_div;
3449 cinfo->pck = cinfo->lck / cinfo->pck_div;
3454 u32 dispc_read_irqstatus(void)
3456 return dispc_read_reg(DISPC_IRQSTATUS);
3458 EXPORT_SYMBOL(dispc_read_irqstatus);
3460 void dispc_clear_irqstatus(u32 mask)
3462 dispc_write_reg(DISPC_IRQSTATUS, mask);
3464 EXPORT_SYMBOL(dispc_clear_irqstatus);
3466 u32 dispc_read_irqenable(void)
3468 return dispc_read_reg(DISPC_IRQENABLE);
3470 EXPORT_SYMBOL(dispc_read_irqenable);
3472 void dispc_write_irqenable(u32 mask)
3474 u32 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3476 /* clear the irqstatus for newly enabled irqs */
3477 dispc_clear_irqstatus((mask ^ old_mask) & mask);
3479 dispc_write_reg(DISPC_IRQENABLE, mask);
3481 EXPORT_SYMBOL(dispc_write_irqenable);
3483 void dispc_enable_sidle(void)
3485 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3488 void dispc_disable_sidle(void)
3490 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3493 static void _omap_dispc_initial_config(void)
3497 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3498 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3499 l = dispc_read_reg(DISPC_DIVISOR);
3500 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3501 l = FLD_MOD(l, 1, 0, 0);
3502 l = FLD_MOD(l, 1, 23, 16);
3503 dispc_write_reg(DISPC_DIVISOR, l);
3505 dispc.core_clk_rate = dispc_fclk_rate();
3509 if (dss_has_feature(FEAT_FUNCGATED))
3510 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3512 dispc_setup_color_conv_coef();
3514 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3518 dispc_configure_burst_sizes();
3520 dispc_ovl_enable_zorder_planes();
3522 if (dispc.feat->mstandby_workaround)
3523 REG_FLD_MOD(DISPC_MSTANDBY_CTRL, 1, 0, 0);
3526 static const struct dispc_features omap24xx_dispc_feats __initconst = {
3533 .mgr_width_start = 10,
3534 .mgr_height_start = 26,
3535 .mgr_width_max = 2048,
3536 .mgr_height_max = 2048,
3537 .max_lcd_pclk = 66500000,
3538 .calc_scaling = dispc_ovl_calc_scaling_24xx,
3539 .calc_core_clk = calc_core_clk_24xx,
3541 .no_framedone_tv = true,
3542 .set_max_preload = false,
3545 static const struct dispc_features omap34xx_rev1_0_dispc_feats __initconst = {
3552 .mgr_width_start = 10,
3553 .mgr_height_start = 26,
3554 .mgr_width_max = 2048,
3555 .mgr_height_max = 2048,
3556 .max_lcd_pclk = 173000000,
3557 .max_tv_pclk = 59000000,
3558 .calc_scaling = dispc_ovl_calc_scaling_34xx,
3559 .calc_core_clk = calc_core_clk_34xx,
3561 .no_framedone_tv = true,
3562 .set_max_preload = false,
3565 static const struct dispc_features omap34xx_rev3_0_dispc_feats __initconst = {
3572 .mgr_width_start = 10,
3573 .mgr_height_start = 26,
3574 .mgr_width_max = 2048,
3575 .mgr_height_max = 2048,
3576 .max_lcd_pclk = 173000000,
3577 .max_tv_pclk = 59000000,
3578 .calc_scaling = dispc_ovl_calc_scaling_34xx,
3579 .calc_core_clk = calc_core_clk_34xx,
3581 .no_framedone_tv = true,
3582 .set_max_preload = false,
3585 static const struct dispc_features omap44xx_dispc_feats __initconst = {
3592 .mgr_width_start = 10,
3593 .mgr_height_start = 26,
3594 .mgr_width_max = 2048,
3595 .mgr_height_max = 2048,
3596 .max_lcd_pclk = 170000000,
3597 .max_tv_pclk = 185625000,
3598 .calc_scaling = dispc_ovl_calc_scaling_44xx,
3599 .calc_core_clk = calc_core_clk_44xx,
3601 .gfx_fifo_workaround = true,
3602 .set_max_preload = true,
3605 static const struct dispc_features omap54xx_dispc_feats __initconst = {
3612 .mgr_width_start = 11,
3613 .mgr_height_start = 27,
3614 .mgr_width_max = 4096,
3615 .mgr_height_max = 4096,
3616 .max_lcd_pclk = 170000000,
3617 .max_tv_pclk = 186000000,
3618 .calc_scaling = dispc_ovl_calc_scaling_44xx,
3619 .calc_core_clk = calc_core_clk_44xx,
3621 .gfx_fifo_workaround = true,
3622 .mstandby_workaround = true,
3623 .set_max_preload = true,
3626 static int __init dispc_init_features(struct platform_device *pdev)
3628 const struct dispc_features *src;
3629 struct dispc_features *dst;
3631 dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL);
3633 dev_err(&pdev->dev, "Failed to allocate DISPC Features\n");
3637 switch (omapdss_get_version()) {
3638 case OMAPDSS_VER_OMAP24xx:
3639 src = &omap24xx_dispc_feats;
3642 case OMAPDSS_VER_OMAP34xx_ES1:
3643 src = &omap34xx_rev1_0_dispc_feats;
3646 case OMAPDSS_VER_OMAP34xx_ES3:
3647 case OMAPDSS_VER_OMAP3630:
3648 case OMAPDSS_VER_AM35xx:
3649 src = &omap34xx_rev3_0_dispc_feats;
3652 case OMAPDSS_VER_OMAP4430_ES1:
3653 case OMAPDSS_VER_OMAP4430_ES2:
3654 case OMAPDSS_VER_OMAP4:
3655 src = &omap44xx_dispc_feats;
3658 case OMAPDSS_VER_OMAP5:
3659 src = &omap54xx_dispc_feats;
3666 memcpy(dst, src, sizeof(*dst));
3672 int dispc_request_irq(irq_handler_t handler, void *dev_id)
3674 return devm_request_irq(&dispc.pdev->dev, dispc.irq, handler,
3675 IRQF_SHARED, "OMAP DISPC", dev_id);
3677 EXPORT_SYMBOL(dispc_request_irq);
3679 void dispc_free_irq(void *dev_id)
3681 devm_free_irq(&dispc.pdev->dev, dispc.irq, dev_id);
3683 EXPORT_SYMBOL(dispc_free_irq);
3685 /* DISPC HW IP initialisation */
3686 static int __init omap_dispchw_probe(struct platform_device *pdev)
3690 struct resource *dispc_mem;
3694 r = dispc_init_features(dispc.pdev);
3698 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3700 DSSERR("can't get IORESOURCE_MEM DISPC\n");
3704 dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
3705 resource_size(dispc_mem));
3707 DSSERR("can't ioremap DISPC\n");
3711 dispc.irq = platform_get_irq(dispc.pdev, 0);
3712 if (dispc.irq < 0) {
3713 DSSERR("platform_get_irq failed\n");
3717 pm_runtime_enable(&pdev->dev);
3719 r = dispc_runtime_get();
3721 goto err_runtime_get;
3723 _omap_dispc_initial_config();
3725 rev = dispc_read_reg(DISPC_REVISION);
3726 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
3727 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3729 dispc_runtime_put();
3731 dss_init_overlay_managers();
3733 dss_debugfs_create_file("dispc", dispc_dump_regs);
3738 pm_runtime_disable(&pdev->dev);
3742 static int __exit omap_dispchw_remove(struct platform_device *pdev)
3744 pm_runtime_disable(&pdev->dev);
3746 dss_uninit_overlay_managers();
3751 static int dispc_runtime_suspend(struct device *dev)
3753 dispc_save_context();
3758 static int dispc_runtime_resume(struct device *dev)
3761 * The reset value for load mode is 0 (OMAP_DSS_LOAD_CLUT_AND_FRAME)
3762 * but we always initialize it to 2 (OMAP_DSS_LOAD_FRAME_ONLY) in
3763 * _omap_dispc_initial_config(). We can thus use it to detect if
3764 * we have lost register context.
3766 if (REG_GET(DISPC_CONFIG, 2, 1) == OMAP_DSS_LOAD_FRAME_ONLY)
3769 _omap_dispc_initial_config();
3771 dispc_restore_context();
3776 static const struct dev_pm_ops dispc_pm_ops = {
3777 .runtime_suspend = dispc_runtime_suspend,
3778 .runtime_resume = dispc_runtime_resume,
3781 static struct platform_driver omap_dispchw_driver = {
3782 .remove = __exit_p(omap_dispchw_remove),
3784 .name = "omapdss_dispc",
3785 .owner = THIS_MODULE,
3786 .pm = &dispc_pm_ops,
3790 int __init dispc_init_platform_driver(void)
3792 return platform_driver_probe(&omap_dispchw_driver, omap_dispchw_probe);
3795 void __exit dispc_uninit_platform_driver(void)
3797 platform_driver_unregister(&omap_dispchw_driver);