drivers/video/omap2/dss/dispc.h

   1 /*
   2  * linux/drivers/video/omap2/dss/dispc.h
   3  *
   4  * Copyright (C) 2011 Texas Instruments
   5  * Author: Archit Taneja <archit@ti.com>
   6  *
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of the GNU General Public License version 2 as published by
  10  * the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program.  If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #ifndef __OMAP2_DISPC_REG_H
  22 #define __OMAP2_DISPC_REG_H
  23
  24 /* DISPC common registers */
  25 #define DISPC_REVISION                  0x0000
  26 #define DISPC_SYSCONFIG                 0x0010
  27 #define DISPC_SYSSTATUS                 0x0014
  28 #define DISPC_IRQSTATUS                 0x0018
  29 #define DISPC_IRQENABLE                 0x001C
  30 #define DISPC_CONTROL                   0x0040
  31 #define DISPC_CONFIG                    0x0044
  32 #define DISPC_CAPABLE                   0x0048
  33 #define DISPC_LINE_STATUS               0x005C
  34 #define DISPC_LINE_NUMBER               0x0060
  35 #define DISPC_GLOBAL_ALPHA              0x0074
  36 #define DISPC_CONTROL2                  0x0238
  37 #define DISPC_CONFIG2                   0x0620
  38 #define DISPC_DIVISOR                   0x0804
  39
  40 /* DISPC overlay registers */
  41 #define DISPC_OVL_BA0(n)                (DISPC_OVL_BASE(n) + \
  42                                         DISPC_BA0_OFFSET(n))
  43 #define DISPC_OVL_BA1(n)                (DISPC_OVL_BASE(n) + \
  44                                         DISPC_BA1_OFFSET(n))
  45 #define DISPC_OVL_BA0_UV(n)             (DISPC_OVL_BASE(n) + \
  46                                         DISPC_BA0_UV_OFFSET(n))
  47 #define DISPC_OVL_BA1_UV(n)             (DISPC_OVL_BASE(n) + \
  48                                         DISPC_BA1_UV_OFFSET(n))
  49 #define DISPC_OVL_POSITION(n)           (DISPC_OVL_BASE(n) + \
  50                                         DISPC_POS_OFFSET(n))
  51 #define DISPC_OVL_SIZE(n)               (DISPC_OVL_BASE(n) + \
  52                                         DISPC_SIZE_OFFSET(n))
  53 #define DISPC_OVL_ATTRIBUTES(n)         (DISPC_OVL_BASE(n) + \
  54                                         DISPC_ATTR_OFFSET(n))
  55 #define DISPC_OVL_ATTRIBUTES2(n)        (DISPC_OVL_BASE(n) + \
  56                                         DISPC_ATTR2_OFFSET(n))
  57 #define DISPC_OVL_FIFO_THRESHOLD(n)     (DISPC_OVL_BASE(n) + \
  58                                         DISPC_FIFO_THRESH_OFFSET(n))
  59 #define DISPC_OVL_FIFO_SIZE_STATUS(n)   (DISPC_OVL_BASE(n) + \
  60                                         DISPC_FIFO_SIZE_STATUS_OFFSET(n))
  61 #define DISPC_OVL_ROW_INC(n)            (DISPC_OVL_BASE(n) + \
  62                                         DISPC_ROW_INC_OFFSET(n))
  63 #define DISPC_OVL_PIXEL_INC(n)          (DISPC_OVL_BASE(n) + \
  64                                         DISPC_PIX_INC_OFFSET(n))
  65 #define DISPC_OVL_WINDOW_SKIP(n)        (DISPC_OVL_BASE(n) + \
  66                                         DISPC_WINDOW_SKIP_OFFSET(n))
  67 #define DISPC_OVL_TABLE_BA(n)           (DISPC_OVL_BASE(n) + \
  68                                         DISPC_TABLE_BA_OFFSET(n))
  69 #define DISPC_OVL_FIR(n)                (DISPC_OVL_BASE(n) + \
  70                                         DISPC_FIR_OFFSET(n))
  71 #define DISPC_OVL_FIR2(n)               (DISPC_OVL_BASE(n) + \
  72                                         DISPC_FIR2_OFFSET(n))
  73 #define DISPC_OVL_PICTURE_SIZE(n)       (DISPC_OVL_BASE(n) + \
  74                                         DISPC_PIC_SIZE_OFFSET(n))
  75 #define DISPC_OVL_ACCU0(n)              (DISPC_OVL_BASE(n) + \
  76                                         DISPC_ACCU0_OFFSET(n))
  77 #define DISPC_OVL_ACCU1(n)              (DISPC_OVL_BASE(n) + \
  78                                         DISPC_ACCU1_OFFSET(n))
  79 #define DISPC_OVL_ACCU2_0(n)            (DISPC_OVL_BASE(n) + \
  80                                         DISPC_ACCU2_0_OFFSET(n))
  81 #define DISPC_OVL_ACCU2_1(n)            (DISPC_OVL_BASE(n) + \
  82                                         DISPC_ACCU2_1_OFFSET(n))
  83 #define DISPC_OVL_FIR_COEF_H(n, i)      (DISPC_OVL_BASE(n) + \
  84                                         DISPC_FIR_COEF_H_OFFSET(n, i))
  85 #define DISPC_OVL_FIR_COEF_HV(n, i)     (DISPC_OVL_BASE(n) + \
  86                                         DISPC_FIR_COEF_HV_OFFSET(n, i))
  87 #define DISPC_OVL_FIR_COEF_H2(n, i)     (DISPC_OVL_BASE(n) + \
  88                                         DISPC_FIR_COEF_H2_OFFSET(n, i))
  89 #define DISPC_OVL_FIR_COEF_HV2(n, i)    (DISPC_OVL_BASE(n) + \
  90                                         DISPC_FIR_COEF_HV2_OFFSET(n, i))
  91 #define DISPC_OVL_CONV_COEF(n, i)       (DISPC_OVL_BASE(n) + \
  92                                         DISPC_CONV_COEF_OFFSET(n, i))
  93 #define DISPC_OVL_FIR_COEF_V(n, i)      (DISPC_OVL_BASE(n) + \
  94                                         DISPC_FIR_COEF_V_OFFSET(n, i))
  95 #define DISPC_OVL_FIR_COEF_V2(n, i)     (DISPC_OVL_BASE(n) + \
  96                                         DISPC_FIR_COEF_V2_OFFSET(n, i))
  97 #define DISPC_OVL_PRELOAD(n)            (DISPC_OVL_BASE(n) + \
  98                                         DISPC_PRELOAD_OFFSET(n))
  99
 100 /* DISPC manager/channel specific registers */
 101 static inline u16 DISPC_DEFAULT_COLOR(enum omap_channel channel)
 102 {
 103         switch (channel) {
 104         case OMAP_DSS_CHANNEL_LCD:
 105                 return 0x004C;
 106         case OMAP_DSS_CHANNEL_DIGIT:
 107                 return 0x0050;
 108         case OMAP_DSS_CHANNEL_LCD2:
 109                 return 0x03AC;
 110         default:
 111                 BUG();
 112         }
 113 }
 114
 115 static inline u16 DISPC_TRANS_COLOR(enum omap_channel channel)
 116 {
 117         switch (channel) {
 118         case OMAP_DSS_CHANNEL_LCD:
 119                 return 0x0054;
 120         case OMAP_DSS_CHANNEL_DIGIT:
 121                 return 0x0058;
 122         case OMAP_DSS_CHANNEL_LCD2:
 123                 return 0x03B0;
 124         default:
 125                 BUG();
 126         }
 127 }
 128
 129 static inline u16 DISPC_TIMING_H(enum omap_channel channel)
 130 {
 131         switch (channel) {
 132         case OMAP_DSS_CHANNEL_LCD:
 133                 return 0x0064;
 134         case OMAP_DSS_CHANNEL_DIGIT:
 135                 BUG();
 136         case OMAP_DSS_CHANNEL_LCD2:
 137                 return 0x0400;
 138         default:
 139                 BUG();
 140         }
 141 }
 142
 143 static inline u16 DISPC_TIMING_V(enum omap_channel channel)
 144 {
 145         switch (channel) {
 146         case OMAP_DSS_CHANNEL_LCD:
 147                 return 0x0068;
 148         case OMAP_DSS_CHANNEL_DIGIT:
 149                 BUG();
 150         case OMAP_DSS_CHANNEL_LCD2:
 151                 return 0x0404;
 152         default:
 153                 BUG();
 154         }
 155 }
 156
 157 static inline u16 DISPC_POL_FREQ(enum omap_channel channel)
 158 {
 159         switch (channel) {
 160         case OMAP_DSS_CHANNEL_LCD:
 161                 return 0x006C;
 162         case OMAP_DSS_CHANNEL_DIGIT:
 163                 BUG();
 164         case OMAP_DSS_CHANNEL_LCD2:
 165                 return 0x0408;
 166         default:
 167                 BUG();
 168         }
 169 }
 170
 171 static inline u16 DISPC_DIVISORo(enum omap_channel channel)
 172 {
 173         switch (channel) {
 174         case OMAP_DSS_CHANNEL_LCD:
 175                 return 0x0070;
 176         case OMAP_DSS_CHANNEL_DIGIT:
 177                 BUG();
 178         case OMAP_DSS_CHANNEL_LCD2:
 179                 return 0x040C;
 180         default:
 181                 BUG();
 182         }
 183 }
 184
 185 /* Named as DISPC_SIZE_LCD, DISPC_SIZE_DIGIT and DISPC_SIZE_LCD2 in TRM */
 186 static inline u16 DISPC_SIZE_MGR(enum omap_channel channel)
 187 {
 188         switch (channel) {
 189         case OMAP_DSS_CHANNEL_LCD:
 190                 return 0x007C;
 191         case OMAP_DSS_CHANNEL_DIGIT:
 192                 return 0x0078;
 193         case OMAP_DSS_CHANNEL_LCD2:
 194                 return 0x03CC;
 195         default:
 196                 BUG();
 197         }
 198 }
 199
 200 static inline u16 DISPC_DATA_CYCLE1(enum omap_channel channel)
 201 {
 202         switch (channel) {
 203         case OMAP_DSS_CHANNEL_LCD:
 204                 return 0x01D4;
 205         case OMAP_DSS_CHANNEL_DIGIT:
 206                 BUG();
 207         case OMAP_DSS_CHANNEL_LCD2:
 208                 return 0x03C0;
 209         default:
 210                 BUG();
 211         }
 212 }
 213
 214 static inline u16 DISPC_DATA_CYCLE2(enum omap_channel channel)
 215 {
 216         switch (channel) {
 217         case OMAP_DSS_CHANNEL_LCD:
 218                 return 0x01D8;
 219         case OMAP_DSS_CHANNEL_DIGIT:
 220                 BUG();
 221         case OMAP_DSS_CHANNEL_LCD2:
 222                 return 0x03C4;
 223         default:
 224                 BUG();
 225         }
 226 }
 227
 228 static inline u16 DISPC_DATA_CYCLE3(enum omap_channel channel)
 229 {
 230         switch (channel) {
 231         case OMAP_DSS_CHANNEL_LCD:
 232                 return 0x01DC;
 233         case OMAP_DSS_CHANNEL_DIGIT:
 234                 BUG();
 235         case OMAP_DSS_CHANNEL_LCD2:
 236                 return 0x03C8;
 237         default:
 238                 BUG();
 239         }
 240 }
 241
 242 static inline u16 DISPC_CPR_COEF_R(enum omap_channel channel)
 243 {
 244         switch (channel) {
 245         case OMAP_DSS_CHANNEL_LCD:
 246                 return 0x0220;
 247         case OMAP_DSS_CHANNEL_DIGIT:
 248                 BUG();
 249         case OMAP_DSS_CHANNEL_LCD2:
 250                 return 0x03BC;
 251         default:
 252                 BUG();
 253         }
 254 }
 255
 256 static inline u16 DISPC_CPR_COEF_G(enum omap_channel channel)
 257 {
 258         switch (channel) {
 259         case OMAP_DSS_CHANNEL_LCD:
 260                 return 0x0224;
 261         case OMAP_DSS_CHANNEL_DIGIT:
 262                 BUG();
 263         case OMAP_DSS_CHANNEL_LCD2:
 264                 return 0x03B8;
 265         default:
 266                 BUG();
 267         }
 268 }
 269
 270 static inline u16 DISPC_CPR_COEF_B(enum omap_channel channel)
 271 {
 272         switch (channel) {
 273         case OMAP_DSS_CHANNEL_LCD:
 274                 return 0x0228;
 275         case OMAP_DSS_CHANNEL_DIGIT:
 276                 BUG();
 277         case OMAP_DSS_CHANNEL_LCD2:
 278                 return 0x03B4;
 279         default:
 280                 BUG();
 281         }
 282 }
 283
 284 /* DISPC overlay register base addresses */
 285 static inline u16 DISPC_OVL_BASE(enum omap_plane plane)
 286 {
 287         switch (plane) {
 288         case OMAP_DSS_GFX:
 289                 return 0x0080;
 290         case OMAP_DSS_VIDEO1:
 291                 return 0x00BC;
 292         case OMAP_DSS_VIDEO2:
 293                 return 0x014C;
 294         default:
 295                 BUG();
 296         }
 297 }
 298
 299 /* DISPC overlay register offsets */
 300 static inline u16 DISPC_BA0_OFFSET(enum omap_plane plane)
 301 {
 302         switch (plane) {
 303         case OMAP_DSS_GFX:
 304         case OMAP_DSS_VIDEO1:
 305         case OMAP_DSS_VIDEO2:
 306                 return 0x0000;
 307         default:
 308                 BUG();
 309         }
 310 }
 311
 312 static inline u16 DISPC_BA1_OFFSET(enum omap_plane plane)
 313 {
 314         switch (plane) {
 315         case OMAP_DSS_GFX:
 316         case OMAP_DSS_VIDEO1:
 317         case OMAP_DSS_VIDEO2:
 318                 return 0x0004;
 319         default:
 320                 BUG();
 321         }
 322 }
 323
 324 static inline u16 DISPC_BA0_UV_OFFSET(enum omap_plane plane)
 325 {
 326         switch (plane) {
 327         case OMAP_DSS_GFX:
 328                 BUG();
 329         case OMAP_DSS_VIDEO1:
 330                 return 0x0544;
 331         case OMAP_DSS_VIDEO2:
 332                 return 0x04BC;
 333         default:
 334                 BUG();
 335         }
 336 }
 337
 338 static inline u16 DISPC_BA1_UV_OFFSET(enum omap_plane plane)
 339 {
 340         switch (plane) {
 341         case OMAP_DSS_GFX:
 342                 BUG();
 343         case OMAP_DSS_VIDEO1:
 344                 return 0x0548;
 345         case OMAP_DSS_VIDEO2:
 346                 return 0x04C0;
 347         default:
 348                 BUG();
 349         }
 350 }
 351
 352 static inline u16 DISPC_POS_OFFSET(enum omap_plane plane)
 353 {
 354         switch (plane) {
 355         case OMAP_DSS_GFX:
 356         case OMAP_DSS_VIDEO1:
 357         case OMAP_DSS_VIDEO2:
 358                 return 0x0008;
 359         default:
 360                 BUG();
 361         }
 362 }
 363
 364 static inline u16 DISPC_SIZE_OFFSET(enum omap_plane plane)
 365 {
 366         switch (plane) {
 367         case OMAP_DSS_GFX:
 368         case OMAP_DSS_VIDEO1:
 369         case OMAP_DSS_VIDEO2:
 370                 return 0x000C;
 371         default:
 372                 BUG();
 373         }
 374 }
 375
 376 static inline u16 DISPC_ATTR_OFFSET(enum omap_plane plane)
 377 {
 378         switch (plane) {
 379         case OMAP_DSS_GFX:
 380                 return 0x0020;
 381         case OMAP_DSS_VIDEO1:
 382         case OMAP_DSS_VIDEO2:
 383                 return 0x0010;
 384         default:
 385                 BUG();
 386         }
 387 }
 388
 389 static inline u16 DISPC_ATTR2_OFFSET(enum omap_plane plane)
 390 {
 391         switch (plane) {
 392         case OMAP_DSS_GFX:
 393                 BUG();
 394         case OMAP_DSS_VIDEO1:
 395                 return 0x0568;
 396         case OMAP_DSS_VIDEO2:
 397                 return 0x04DC;
 398         default:
 399                 BUG();
 400         }
 401 }
 402
 403 static inline u16 DISPC_FIFO_THRESH_OFFSET(enum omap_plane plane)
 404 {
 405         switch (plane) {
 406         case OMAP_DSS_GFX:
 407                 return 0x0024;
 408         case OMAP_DSS_VIDEO1:
 409         case OMAP_DSS_VIDEO2:
 410                 return 0x0014;
 411         default:
 412                 BUG();
 413         }
 414 }
 415
 416 static inline u16 DISPC_FIFO_SIZE_STATUS_OFFSET(enum omap_plane plane)
 417 {
 418         switch (plane) {
 419         case OMAP_DSS_GFX:
 420                 return 0x0028;
 421         case OMAP_DSS_VIDEO1:
 422         case OMAP_DSS_VIDEO2:
 423                 return 0x0018;
 424         default:
 425                 BUG();
 426         }
 427 }
 428
 429 static inline u16 DISPC_ROW_INC_OFFSET(enum omap_plane plane)
 430 {
 431         switch (plane) {
 432         case OMAP_DSS_GFX:
 433                 return 0x002C;
 434         case OMAP_DSS_VIDEO1:
 435         case OMAP_DSS_VIDEO2:
 436                 return 0x001C;
 437         default:
 438                 BUG();
 439         }
 440 }
 441
 442 static inline u16 DISPC_PIX_INC_OFFSET(enum omap_plane plane)
 443 {
 444         switch (plane) {
 445         case OMAP_DSS_GFX:
 446                 return 0x0030;
 447         case OMAP_DSS_VIDEO1:
 448         case OMAP_DSS_VIDEO2:
 449                 return 0x0020;
 450         default:
 451                 BUG();
 452         }
 453 }
 454
 455 static inline u16 DISPC_WINDOW_SKIP_OFFSET(enum omap_plane plane)
 456 {
 457         switch (plane) {
 458         case OMAP_DSS_GFX:
 459                 return 0x0034;
 460         case OMAP_DSS_VIDEO1:
 461         case OMAP_DSS_VIDEO2:
 462                 BUG();
 463         default:
 464                 BUG();
 465         }
 466 }
 467
 468 static inline u16 DISPC_TABLE_BA_OFFSET(enum omap_plane plane)
 469 {
 470         switch (plane) {
 471         case OMAP_DSS_GFX:
 472                 return 0x0038;
 473         case OMAP_DSS_VIDEO1:
 474         case OMAP_DSS_VIDEO2:
 475                 BUG();
 476         default:
 477                 BUG();
 478         }
 479 }
 480
 481 static inline u16 DISPC_FIR_OFFSET(enum omap_plane plane)
 482 {
 483         switch (plane) {
 484         case OMAP_DSS_GFX:
 485                 BUG();
 486         case OMAP_DSS_VIDEO1:
 487         case OMAP_DSS_VIDEO2:
 488                 return 0x0024;
 489         default:
 490                 BUG();
 491         }
 492 }
 493
 494 static inline u16 DISPC_FIR2_OFFSET(enum omap_plane plane)
 495 {
 496         switch (plane) {
 497         case OMAP_DSS_GFX:
 498                 BUG();
 499         case OMAP_DSS_VIDEO1:
 500                 return 0x0580;
 501         case OMAP_DSS_VIDEO2:
 502                 return 0x055C;
 503         default:
 504                 BUG();
 505         }
 506 }
 507
 508 static inline u16 DISPC_PIC_SIZE_OFFSET(enum omap_plane plane)
 509 {
 510         switch (plane) {
 511         case OMAP_DSS_GFX:
 512                 BUG();
 513         case OMAP_DSS_VIDEO1:
 514         case OMAP_DSS_VIDEO2:
 515                 return 0x0028;
 516         default:
 517                 BUG();
 518         }
 519 }
 520
 521
 522 static inline u16 DISPC_ACCU0_OFFSET(enum omap_plane plane)
 523 {
 524         switch (plane) {
 525         case OMAP_DSS_GFX:
 526                 BUG();
 527         case OMAP_DSS_VIDEO1:
 528         case OMAP_DSS_VIDEO2:
 529                 return 0x002C;
 530         default:
 531                 BUG();
 532         }
 533 }
 534
 535 static inline u16 DISPC_ACCU2_0_OFFSET(enum omap_plane plane)
 536 {
 537         switch (plane) {
 538         case OMAP_DSS_GFX:
 539                 BUG();
 540         case OMAP_DSS_VIDEO1:
 541                 return 0x0584;
 542         case OMAP_DSS_VIDEO2:
 543                 return 0x0560;
 544         default:
 545                 BUG();
 546         }
 547 }
 548
 549 static inline u16 DISPC_ACCU1_OFFSET(enum omap_plane plane)
 550 {
 551         switch (plane) {
 552         case OMAP_DSS_GFX:
 553                 BUG();
 554         case OMAP_DSS_VIDEO1:
 555         case OMAP_DSS_VIDEO2:
 556                 return 0x0030;
 557         default:
 558                 BUG();
 559         }
 560 }
 561
 562 static inline u16 DISPC_ACCU2_1_OFFSET(enum omap_plane plane)
 563 {
 564         switch (plane) {
 565         case OMAP_DSS_GFX:
 566                 BUG();
 567         case OMAP_DSS_VIDEO1:
 568                 return 0x0588;
 569         case OMAP_DSS_VIDEO2:
 570                 return 0x0564;
 571         default:
 572                 BUG();
 573         }
 574 }
 575
 576 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 577 static inline u16 DISPC_FIR_COEF_H_OFFSET(enum omap_plane plane, u16 i)
 578 {
 579         switch (plane) {
 580         case OMAP_DSS_GFX:
 581                 BUG();
 582         case OMAP_DSS_VIDEO1:
 583         case OMAP_DSS_VIDEO2:
 584                 return 0x0034 + i * 0x8;
 585         default:
 586                 BUG();
 587         }
 588 }
 589
 590 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 591 static inline u16 DISPC_FIR_COEF_H2_OFFSET(enum omap_plane plane, u16 i)
 592 {
 593         switch (plane) {
 594         case OMAP_DSS_GFX:
 595                 BUG();
 596         case OMAP_DSS_VIDEO1:
 597                 return 0x058C + i * 0x8;
 598         case OMAP_DSS_VIDEO2:
 599                 return 0x0568 + i * 0x8;
 600         default:
 601                 BUG();
 602         }
 603 }
 604
 605 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 606 static inline u16 DISPC_FIR_COEF_HV_OFFSET(enum omap_plane plane, u16 i)
 607 {
 608         switch (plane) {
 609         case OMAP_DSS_GFX:
 610                 BUG();
 611         case OMAP_DSS_VIDEO1:
 612         case OMAP_DSS_VIDEO2:
 613                 return 0x0038 + i * 0x8;
 614         default:
 615                 BUG();
 616         }
 617 }
 618
 619 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 620 static inline u16 DISPC_FIR_COEF_HV2_OFFSET(enum omap_plane plane, u16 i)
 621 {
 622         switch (plane) {
 623         case OMAP_DSS_GFX:
 624                 BUG();
 625         case OMAP_DSS_VIDEO1:
 626                 return 0x0590 + i * 8;
 627         case OMAP_DSS_VIDEO2:
 628                 return 0x056C + i * 0x8;
 629         default:
 630                 BUG();
 631         }
 632 }
 633
 634 /* coef index i = {0, 1, 2, 3, 4,} */
 635 static inline u16 DISPC_CONV_COEF_OFFSET(enum omap_plane plane, u16 i)
 636 {
 637         switch (plane) {
 638         case OMAP_DSS_GFX:
 639                 BUG();
 640         case OMAP_DSS_VIDEO1:
 641         case OMAP_DSS_VIDEO2:
 642                 return 0x0074 + i * 0x4;
 643         default:
 644                 BUG();
 645         }
 646 }
 647
 648 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 649 static inline u16 DISPC_FIR_COEF_V_OFFSET(enum omap_plane plane, u16 i)
 650 {
 651         switch (plane) {
 652         case OMAP_DSS_GFX:
 653                 BUG();
 654         case OMAP_DSS_VIDEO1:
 655                 return 0x0124 + i * 0x4;
 656         case OMAP_DSS_VIDEO2:
 657                 return 0x00B4 + i * 0x4;
 658         default:
 659                 BUG();
 660         }
 661 }
 662
 663 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 664 static inline u16 DISPC_FIR_COEF_V2_OFFSET(enum omap_plane plane, u16 i)
 665 {
 666         switch (plane) {
 667         case OMAP_DSS_GFX:
 668                 BUG();
 669         case OMAP_DSS_VIDEO1:
 670                 return 0x05CC + i * 0x4;
 671         case OMAP_DSS_VIDEO2:
 672                 return 0x05A8 + i * 0x4;
 673         default:
 674                 BUG();
 675         }
 676 }
 677
 678 static inline u16 DISPC_PRELOAD_OFFSET(enum omap_plane plane)
 679 {
 680         switch (plane) {
 681         case OMAP_DSS_GFX:
 682                 return 0x01AC;
 683         case OMAP_DSS_VIDEO1:
 684                 return 0x0174;
 685         case OMAP_DSS_VIDEO2:
 686                 return 0x00E8;
 687         default:
 688                 BUG();
 689         }
 690 }
 691 #endif