drivers/video/omap2/dss/dispc.h

   1 /*
   2  * linux/drivers/video/omap2/dss/dispc.h
   3  *
   4  * Copyright (C) 2011 Texas Instruments
   5  * Author: Archit Taneja <archit@ti.com>
   6  *
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of the GNU General Public License version 2 as published by
  10  * the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program.  If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #ifndef __OMAP2_DISPC_REG_H
  22 #define __OMAP2_DISPC_REG_H
  23
  24 /* DISPC common registers */
  25 #define DISPC_REVISION                  0x0000
  26 #define DISPC_SYSCONFIG                 0x0010
  27 #define DISPC_SYSSTATUS                 0x0014
  28 #define DISPC_IRQSTATUS                 0x0018
  29 #define DISPC_IRQENABLE                 0x001C
  30 #define DISPC_CONTROL                   0x0040
  31 #define DISPC_CONFIG                    0x0044
  32 #define DISPC_CAPABLE                   0x0048
  33 #define DISPC_LINE_STATUS               0x005C
  34 #define DISPC_LINE_NUMBER               0x0060
  35 #define DISPC_GLOBAL_ALPHA              0x0074
  36 #define DISPC_CONTROL2                  0x0238
  37 #define DISPC_CONFIG2                   0x0620
  38 #define DISPC_DIVISOR                   0x0804
  39 #define DISPC_CONTROL3                  0x0848
  40 #define DISPC_CONFIG3                   0x084C
  41
  42 /* DISPC overlay registers */
  43 #define DISPC_OVL_BA0(n)                (DISPC_OVL_BASE(n) + \
  44                                         DISPC_BA0_OFFSET(n))
  45 #define DISPC_OVL_BA1(n)                (DISPC_OVL_BASE(n) + \
  46                                         DISPC_BA1_OFFSET(n))
  47 #define DISPC_OVL_BA0_UV(n)             (DISPC_OVL_BASE(n) + \
  48                                         DISPC_BA0_UV_OFFSET(n))
  49 #define DISPC_OVL_BA1_UV(n)             (DISPC_OVL_BASE(n) + \
  50                                         DISPC_BA1_UV_OFFSET(n))
  51 #define DISPC_OVL_POSITION(n)           (DISPC_OVL_BASE(n) + \
  52                                         DISPC_POS_OFFSET(n))
  53 #define DISPC_OVL_SIZE(n)               (DISPC_OVL_BASE(n) + \
  54                                         DISPC_SIZE_OFFSET(n))
  55 #define DISPC_OVL_ATTRIBUTES(n)         (DISPC_OVL_BASE(n) + \
  56                                         DISPC_ATTR_OFFSET(n))
  57 #define DISPC_OVL_ATTRIBUTES2(n)        (DISPC_OVL_BASE(n) + \
  58                                         DISPC_ATTR2_OFFSET(n))
  59 #define DISPC_OVL_FIFO_THRESHOLD(n)     (DISPC_OVL_BASE(n) + \
  60                                         DISPC_FIFO_THRESH_OFFSET(n))
  61 #define DISPC_OVL_FIFO_SIZE_STATUS(n)   (DISPC_OVL_BASE(n) + \
  62                                         DISPC_FIFO_SIZE_STATUS_OFFSET(n))
  63 #define DISPC_OVL_ROW_INC(n)            (DISPC_OVL_BASE(n) + \
  64                                         DISPC_ROW_INC_OFFSET(n))
  65 #define DISPC_OVL_PIXEL_INC(n)          (DISPC_OVL_BASE(n) + \
  66                                         DISPC_PIX_INC_OFFSET(n))
  67 #define DISPC_OVL_WINDOW_SKIP(n)        (DISPC_OVL_BASE(n) + \
  68                                         DISPC_WINDOW_SKIP_OFFSET(n))
  69 #define DISPC_OVL_TABLE_BA(n)           (DISPC_OVL_BASE(n) + \
  70                                         DISPC_TABLE_BA_OFFSET(n))
  71 #define DISPC_OVL_FIR(n)                (DISPC_OVL_BASE(n) + \
  72                                         DISPC_FIR_OFFSET(n))
  73 #define DISPC_OVL_FIR2(n)               (DISPC_OVL_BASE(n) + \
  74                                         DISPC_FIR2_OFFSET(n))
  75 #define DISPC_OVL_PICTURE_SIZE(n)       (DISPC_OVL_BASE(n) + \
  76                                         DISPC_PIC_SIZE_OFFSET(n))
  77 #define DISPC_OVL_ACCU0(n)              (DISPC_OVL_BASE(n) + \
  78                                         DISPC_ACCU0_OFFSET(n))
  79 #define DISPC_OVL_ACCU1(n)              (DISPC_OVL_BASE(n) + \
  80                                         DISPC_ACCU1_OFFSET(n))
  81 #define DISPC_OVL_ACCU2_0(n)            (DISPC_OVL_BASE(n) + \
  82                                         DISPC_ACCU2_0_OFFSET(n))
  83 #define DISPC_OVL_ACCU2_1(n)            (DISPC_OVL_BASE(n) + \
  84                                         DISPC_ACCU2_1_OFFSET(n))
  85 #define DISPC_OVL_FIR_COEF_H(n, i)      (DISPC_OVL_BASE(n) + \
  86                                         DISPC_FIR_COEF_H_OFFSET(n, i))
  87 #define DISPC_OVL_FIR_COEF_HV(n, i)     (DISPC_OVL_BASE(n) + \
  88                                         DISPC_FIR_COEF_HV_OFFSET(n, i))
  89 #define DISPC_OVL_FIR_COEF_H2(n, i)     (DISPC_OVL_BASE(n) + \
  90                                         DISPC_FIR_COEF_H2_OFFSET(n, i))
  91 #define DISPC_OVL_FIR_COEF_HV2(n, i)    (DISPC_OVL_BASE(n) + \
  92                                         DISPC_FIR_COEF_HV2_OFFSET(n, i))
  93 #define DISPC_OVL_CONV_COEF(n, i)       (DISPC_OVL_BASE(n) + \
  94                                         DISPC_CONV_COEF_OFFSET(n, i))
  95 #define DISPC_OVL_FIR_COEF_V(n, i)      (DISPC_OVL_BASE(n) + \
  96                                         DISPC_FIR_COEF_V_OFFSET(n, i))
  97 #define DISPC_OVL_FIR_COEF_V2(n, i)     (DISPC_OVL_BASE(n) + \
  98                                         DISPC_FIR_COEF_V2_OFFSET(n, i))
  99 #define DISPC_OVL_PRELOAD(n)            (DISPC_OVL_BASE(n) + \
 100                                         DISPC_PRELOAD_OFFSET(n))
 101
 102 /* DISPC up/downsampling FIR filter coefficient structure */
 103 struct dispc_coef {
 104         s8 hc4_vc22;
 105         s8 hc3_vc2;
 106         u8 hc2_vc1;
 107         s8 hc1_vc0;
 108         s8 hc0_vc00;
 109 };
 110
 111 const struct dispc_coef *dispc_ovl_get_scale_coef(int inc, int five_taps);
 112
 113 /* DISPC manager/channel specific registers */
 114 static inline u16 DISPC_DEFAULT_COLOR(enum omap_channel channel)
 115 {
 116         switch (channel) {
 117         case OMAP_DSS_CHANNEL_LCD:
 118                 return 0x004C;
 119         case OMAP_DSS_CHANNEL_DIGIT:
 120                 return 0x0050;
 121         case OMAP_DSS_CHANNEL_LCD2:
 122                 return 0x03AC;
 123         case OMAP_DSS_CHANNEL_LCD3:
 124                 return 0x0814;
 125         default:
 126                 BUG();
 127                 return 0;
 128         }
 129 }
 130
 131 static inline u16 DISPC_TRANS_COLOR(enum omap_channel channel)
 132 {
 133         switch (channel) {
 134         case OMAP_DSS_CHANNEL_LCD:
 135                 return 0x0054;
 136         case OMAP_DSS_CHANNEL_DIGIT:
 137                 return 0x0058;
 138         case OMAP_DSS_CHANNEL_LCD2:
 139                 return 0x03B0;
 140         case OMAP_DSS_CHANNEL_LCD3:
 141                 return 0x0818;
 142         default:
 143                 BUG();
 144                 return 0;
 145         }
 146 }
 147
 148 static inline u16 DISPC_TIMING_H(enum omap_channel channel)
 149 {
 150         switch (channel) {
 151         case OMAP_DSS_CHANNEL_LCD:
 152                 return 0x0064;
 153         case OMAP_DSS_CHANNEL_DIGIT:
 154                 BUG();
 155                 return 0;
 156         case OMAP_DSS_CHANNEL_LCD2:
 157                 return 0x0400;
 158         case OMAP_DSS_CHANNEL_LCD3:
 159                 return 0x0840;
 160         default:
 161                 BUG();
 162                 return 0;
 163         }
 164 }
 165
 166 static inline u16 DISPC_TIMING_V(enum omap_channel channel)
 167 {
 168         switch (channel) {
 169         case OMAP_DSS_CHANNEL_LCD:
 170                 return 0x0068;
 171         case OMAP_DSS_CHANNEL_DIGIT:
 172                 BUG();
 173                 return 0;
 174         case OMAP_DSS_CHANNEL_LCD2:
 175                 return 0x0404;
 176         case OMAP_DSS_CHANNEL_LCD3:
 177                 return 0x0844;
 178         default:
 179                 BUG();
 180                 return 0;
 181         }
 182 }
 183
 184 static inline u16 DISPC_POL_FREQ(enum omap_channel channel)
 185 {
 186         switch (channel) {
 187         case OMAP_DSS_CHANNEL_LCD:
 188                 return 0x006C;
 189         case OMAP_DSS_CHANNEL_DIGIT:
 190                 BUG();
 191                 return 0;
 192         case OMAP_DSS_CHANNEL_LCD2:
 193                 return 0x0408;
 194         case OMAP_DSS_CHANNEL_LCD3:
 195                 return 0x083C;
 196         default:
 197                 BUG();
 198                 return 0;
 199         }
 200 }
 201
 202 static inline u16 DISPC_DIVISORo(enum omap_channel channel)
 203 {
 204         switch (channel) {
 205         case OMAP_DSS_CHANNEL_LCD:
 206                 return 0x0070;
 207         case OMAP_DSS_CHANNEL_DIGIT:
 208                 BUG();
 209                 return 0;
 210         case OMAP_DSS_CHANNEL_LCD2:
 211                 return 0x040C;
 212         case OMAP_DSS_CHANNEL_LCD3:
 213                 return 0x0838;
 214         default:
 215                 BUG();
 216                 return 0;
 217         }
 218 }
 219
 220 /* Named as DISPC_SIZE_LCD, DISPC_SIZE_DIGIT and DISPC_SIZE_LCD2 in TRM */
 221 static inline u16 DISPC_SIZE_MGR(enum omap_channel channel)
 222 {
 223         switch (channel) {
 224         case OMAP_DSS_CHANNEL_LCD:
 225                 return 0x007C;
 226         case OMAP_DSS_CHANNEL_DIGIT:
 227                 return 0x0078;
 228         case OMAP_DSS_CHANNEL_LCD2:
 229                 return 0x03CC;
 230         case OMAP_DSS_CHANNEL_LCD3:
 231                 return 0x0834;
 232         default:
 233                 BUG();
 234                 return 0;
 235         }
 236 }
 237
 238 static inline u16 DISPC_DATA_CYCLE1(enum omap_channel channel)
 239 {
 240         switch (channel) {
 241         case OMAP_DSS_CHANNEL_LCD:
 242                 return 0x01D4;
 243         case OMAP_DSS_CHANNEL_DIGIT:
 244                 BUG();
 245                 return 0;
 246         case OMAP_DSS_CHANNEL_LCD2:
 247                 return 0x03C0;
 248         case OMAP_DSS_CHANNEL_LCD3:
 249                 return 0x0828;
 250         default:
 251                 BUG();
 252                 return 0;
 253         }
 254 }
 255
 256 static inline u16 DISPC_DATA_CYCLE2(enum omap_channel channel)
 257 {
 258         switch (channel) {
 259         case OMAP_DSS_CHANNEL_LCD:
 260                 return 0x01D8;
 261         case OMAP_DSS_CHANNEL_DIGIT:
 262                 BUG();
 263                 return 0;
 264         case OMAP_DSS_CHANNEL_LCD2:
 265                 return 0x03C4;
 266         case OMAP_DSS_CHANNEL_LCD3:
 267                 return 0x082C;
 268         default:
 269                 BUG();
 270                 return 0;
 271         }
 272 }
 273
 274 static inline u16 DISPC_DATA_CYCLE3(enum omap_channel channel)
 275 {
 276         switch (channel) {
 277         case OMAP_DSS_CHANNEL_LCD:
 278                 return 0x01DC;
 279         case OMAP_DSS_CHANNEL_DIGIT:
 280                 BUG();
 281                 return 0;
 282         case OMAP_DSS_CHANNEL_LCD2:
 283                 return 0x03C8;
 284         case OMAP_DSS_CHANNEL_LCD3:
 285                 return 0x0830;
 286         default:
 287                 BUG();
 288                 return 0;
 289         }
 290 }
 291
 292 static inline u16 DISPC_CPR_COEF_R(enum omap_channel channel)
 293 {
 294         switch (channel) {
 295         case OMAP_DSS_CHANNEL_LCD:
 296                 return 0x0220;
 297         case OMAP_DSS_CHANNEL_DIGIT:
 298                 BUG();
 299                 return 0;
 300         case OMAP_DSS_CHANNEL_LCD2:
 301                 return 0x03BC;
 302         case OMAP_DSS_CHANNEL_LCD3:
 303                 return 0x0824;
 304         default:
 305                 BUG();
 306                 return 0;
 307         }
 308 }
 309
 310 static inline u16 DISPC_CPR_COEF_G(enum omap_channel channel)
 311 {
 312         switch (channel) {
 313         case OMAP_DSS_CHANNEL_LCD:
 314                 return 0x0224;
 315         case OMAP_DSS_CHANNEL_DIGIT:
 316                 BUG();
 317                 return 0;
 318         case OMAP_DSS_CHANNEL_LCD2:
 319                 return 0x03B8;
 320         case OMAP_DSS_CHANNEL_LCD3:
 321                 return 0x0820;
 322         default:
 323                 BUG();
 324                 return 0;
 325         }
 326 }
 327
 328 static inline u16 DISPC_CPR_COEF_B(enum omap_channel channel)
 329 {
 330         switch (channel) {
 331         case OMAP_DSS_CHANNEL_LCD:
 332                 return 0x0228;
 333         case OMAP_DSS_CHANNEL_DIGIT:
 334                 BUG();
 335                 return 0;
 336         case OMAP_DSS_CHANNEL_LCD2:
 337                 return 0x03B4;
 338         case OMAP_DSS_CHANNEL_LCD3:
 339                 return 0x081C;
 340         default:
 341                 BUG();
 342                 return 0;
 343         }
 344 }
 345
 346 /* DISPC overlay register base addresses */
 347 static inline u16 DISPC_OVL_BASE(enum omap_plane plane)
 348 {
 349         switch (plane) {
 350         case OMAP_DSS_GFX:
 351                 return 0x0080;
 352         case OMAP_DSS_VIDEO1:
 353                 return 0x00BC;
 354         case OMAP_DSS_VIDEO2:
 355                 return 0x014C;
 356         case OMAP_DSS_VIDEO3:
 357                 return 0x0300;
 358         default:
 359                 BUG();
 360                 return 0;
 361         }
 362 }
 363
 364 /* DISPC overlay register offsets */
 365 static inline u16 DISPC_BA0_OFFSET(enum omap_plane plane)
 366 {
 367         switch (plane) {
 368         case OMAP_DSS_GFX:
 369         case OMAP_DSS_VIDEO1:
 370         case OMAP_DSS_VIDEO2:
 371                 return 0x0000;
 372         case OMAP_DSS_VIDEO3:
 373                 return 0x0008;
 374         default:
 375                 BUG();
 376                 return 0;
 377         }
 378 }
 379
 380 static inline u16 DISPC_BA1_OFFSET(enum omap_plane plane)
 381 {
 382         switch (plane) {
 383         case OMAP_DSS_GFX:
 384         case OMAP_DSS_VIDEO1:
 385         case OMAP_DSS_VIDEO2:
 386                 return 0x0004;
 387         case OMAP_DSS_VIDEO3:
 388                 return 0x000C;
 389         default:
 390                 BUG();
 391                 return 0;
 392         }
 393 }
 394
 395 static inline u16 DISPC_BA0_UV_OFFSET(enum omap_plane plane)
 396 {
 397         switch (plane) {
 398         case OMAP_DSS_GFX:
 399                 BUG();
 400                 return 0;
 401         case OMAP_DSS_VIDEO1:
 402                 return 0x0544;
 403         case OMAP_DSS_VIDEO2:
 404                 return 0x04BC;
 405         case OMAP_DSS_VIDEO3:
 406                 return 0x0310;
 407         default:
 408                 BUG();
 409                 return 0;
 410         }
 411 }
 412
 413 static inline u16 DISPC_BA1_UV_OFFSET(enum omap_plane plane)
 414 {
 415         switch (plane) {
 416         case OMAP_DSS_GFX:
 417                 BUG();
 418                 return 0;
 419         case OMAP_DSS_VIDEO1:
 420                 return 0x0548;
 421         case OMAP_DSS_VIDEO2:
 422                 return 0x04C0;
 423         case OMAP_DSS_VIDEO3:
 424                 return 0x0314;
 425         default:
 426                 BUG();
 427                 return 0;
 428         }
 429 }
 430
 431 static inline u16 DISPC_POS_OFFSET(enum omap_plane plane)
 432 {
 433         switch (plane) {
 434         case OMAP_DSS_GFX:
 435         case OMAP_DSS_VIDEO1:
 436         case OMAP_DSS_VIDEO2:
 437                 return 0x0008;
 438         case OMAP_DSS_VIDEO3:
 439                 return 0x009C;
 440         default:
 441                 BUG();
 442                 return 0;
 443         }
 444 }
 445
 446 static inline u16 DISPC_SIZE_OFFSET(enum omap_plane plane)
 447 {
 448         switch (plane) {
 449         case OMAP_DSS_GFX:
 450         case OMAP_DSS_VIDEO1:
 451         case OMAP_DSS_VIDEO2:
 452                 return 0x000C;
 453         case OMAP_DSS_VIDEO3:
 454                 return 0x00A8;
 455         default:
 456                 BUG();
 457                 return 0;
 458         }
 459 }
 460
 461 static inline u16 DISPC_ATTR_OFFSET(enum omap_plane plane)
 462 {
 463         switch (plane) {
 464         case OMAP_DSS_GFX:
 465                 return 0x0020;
 466         case OMAP_DSS_VIDEO1:
 467         case OMAP_DSS_VIDEO2:
 468                 return 0x0010;
 469         case OMAP_DSS_VIDEO3:
 470                 return 0x0070;
 471         default:
 472                 BUG();
 473                 return 0;
 474         }
 475 }
 476
 477 static inline u16 DISPC_ATTR2_OFFSET(enum omap_plane plane)
 478 {
 479         switch (plane) {
 480         case OMAP_DSS_GFX:
 481                 BUG();
 482                 return 0;
 483         case OMAP_DSS_VIDEO1:
 484                 return 0x0568;
 485         case OMAP_DSS_VIDEO2:
 486                 return 0x04DC;
 487         case OMAP_DSS_VIDEO3:
 488                 return 0x032C;
 489         default:
 490                 BUG();
 491                 return 0;
 492         }
 493 }
 494
 495 static inline u16 DISPC_FIFO_THRESH_OFFSET(enum omap_plane plane)
 496 {
 497         switch (plane) {
 498         case OMAP_DSS_GFX:
 499                 return 0x0024;
 500         case OMAP_DSS_VIDEO1:
 501         case OMAP_DSS_VIDEO2:
 502                 return 0x0014;
 503         case OMAP_DSS_VIDEO3:
 504                 return 0x008C;
 505         default:
 506                 BUG();
 507                 return 0;
 508         }
 509 }
 510
 511 static inline u16 DISPC_FIFO_SIZE_STATUS_OFFSET(enum omap_plane plane)
 512 {
 513         switch (plane) {
 514         case OMAP_DSS_GFX:
 515                 return 0x0028;
 516         case OMAP_DSS_VIDEO1:
 517         case OMAP_DSS_VIDEO2:
 518                 return 0x0018;
 519         case OMAP_DSS_VIDEO3:
 520                 return 0x0088;
 521         default:
 522                 BUG();
 523                 return 0;
 524         }
 525 }
 526
 527 static inline u16 DISPC_ROW_INC_OFFSET(enum omap_plane plane)
 528 {
 529         switch (plane) {
 530         case OMAP_DSS_GFX:
 531                 return 0x002C;
 532         case OMAP_DSS_VIDEO1:
 533         case OMAP_DSS_VIDEO2:
 534                 return 0x001C;
 535         case OMAP_DSS_VIDEO3:
 536                 return 0x00A4;
 537         default:
 538                 BUG();
 539                 return 0;
 540         }
 541 }
 542
 543 static inline u16 DISPC_PIX_INC_OFFSET(enum omap_plane plane)
 544 {
 545         switch (plane) {
 546         case OMAP_DSS_GFX:
 547                 return 0x0030;
 548         case OMAP_DSS_VIDEO1:
 549         case OMAP_DSS_VIDEO2:
 550                 return 0x0020;
 551         case OMAP_DSS_VIDEO3:
 552                 return 0x0098;
 553         default:
 554                 BUG();
 555                 return 0;
 556         }
 557 }
 558
 559 static inline u16 DISPC_WINDOW_SKIP_OFFSET(enum omap_plane plane)
 560 {
 561         switch (plane) {
 562         case OMAP_DSS_GFX:
 563                 return 0x0034;
 564         case OMAP_DSS_VIDEO1:
 565         case OMAP_DSS_VIDEO2:
 566         case OMAP_DSS_VIDEO3:
 567                 BUG();
 568                 return 0;
 569         default:
 570                 BUG();
 571                 return 0;
 572         }
 573 }
 574
 575 static inline u16 DISPC_TABLE_BA_OFFSET(enum omap_plane plane)
 576 {
 577         switch (plane) {
 578         case OMAP_DSS_GFX:
 579                 return 0x0038;
 580         case OMAP_DSS_VIDEO1:
 581         case OMAP_DSS_VIDEO2:
 582         case OMAP_DSS_VIDEO3:
 583                 BUG();
 584                 return 0;
 585         default:
 586                 BUG();
 587                 return 0;
 588         }
 589 }
 590
 591 static inline u16 DISPC_FIR_OFFSET(enum omap_plane plane)
 592 {
 593         switch (plane) {
 594         case OMAP_DSS_GFX:
 595                 BUG();
 596                 return 0;
 597         case OMAP_DSS_VIDEO1:
 598         case OMAP_DSS_VIDEO2:
 599                 return 0x0024;
 600         case OMAP_DSS_VIDEO3:
 601                 return 0x0090;
 602         default:
 603                 BUG();
 604                 return 0;
 605         }
 606 }
 607
 608 static inline u16 DISPC_FIR2_OFFSET(enum omap_plane plane)
 609 {
 610         switch (plane) {
 611         case OMAP_DSS_GFX:
 612                 BUG();
 613                 return 0;
 614         case OMAP_DSS_VIDEO1:
 615                 return 0x0580;
 616         case OMAP_DSS_VIDEO2:
 617                 return 0x055C;
 618         case OMAP_DSS_VIDEO3:
 619                 return 0x0424;
 620         default:
 621                 BUG();
 622                 return 0;
 623         }
 624 }
 625
 626 static inline u16 DISPC_PIC_SIZE_OFFSET(enum omap_plane plane)
 627 {
 628         switch (plane) {
 629         case OMAP_DSS_GFX:
 630                 BUG();
 631                 return 0;
 632         case OMAP_DSS_VIDEO1:
 633         case OMAP_DSS_VIDEO2:
 634                 return 0x0028;
 635         case OMAP_DSS_VIDEO3:
 636                 return 0x0094;
 637         default:
 638                 BUG();
 639                 return 0;
 640         }
 641 }
 642
 643
 644 static inline u16 DISPC_ACCU0_OFFSET(enum omap_plane plane)
 645 {
 646         switch (plane) {
 647         case OMAP_DSS_GFX:
 648                 BUG();
 649                 return 0;
 650         case OMAP_DSS_VIDEO1:
 651         case OMAP_DSS_VIDEO2:
 652                 return 0x002C;
 653         case OMAP_DSS_VIDEO3:
 654                 return 0x0000;
 655         default:
 656                 BUG();
 657                 return 0;
 658         }
 659 }
 660
 661 static inline u16 DISPC_ACCU2_0_OFFSET(enum omap_plane plane)
 662 {
 663         switch (plane) {
 664         case OMAP_DSS_GFX:
 665                 BUG();
 666                 return 0;
 667         case OMAP_DSS_VIDEO1:
 668                 return 0x0584;
 669         case OMAP_DSS_VIDEO2:
 670                 return 0x0560;
 671         case OMAP_DSS_VIDEO3:
 672                 return 0x0428;
 673         default:
 674                 BUG();
 675                 return 0;
 676         }
 677 }
 678
 679 static inline u16 DISPC_ACCU1_OFFSET(enum omap_plane plane)
 680 {
 681         switch (plane) {
 682         case OMAP_DSS_GFX:
 683                 BUG();
 684                 return 0;
 685         case OMAP_DSS_VIDEO1:
 686         case OMAP_DSS_VIDEO2:
 687                 return 0x0030;
 688         case OMAP_DSS_VIDEO3:
 689                 return 0x0004;
 690         default:
 691                 BUG();
 692                 return 0;
 693         }
 694 }
 695
 696 static inline u16 DISPC_ACCU2_1_OFFSET(enum omap_plane plane)
 697 {
 698         switch (plane) {
 699         case OMAP_DSS_GFX:
 700                 BUG();
 701                 return 0;
 702         case OMAP_DSS_VIDEO1:
 703                 return 0x0588;
 704         case OMAP_DSS_VIDEO2:
 705                 return 0x0564;
 706         case OMAP_DSS_VIDEO3:
 707                 return 0x042C;
 708         default:
 709                 BUG();
 710                 return 0;
 711         }
 712 }
 713
 714 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 715 static inline u16 DISPC_FIR_COEF_H_OFFSET(enum omap_plane plane, u16 i)
 716 {
 717         switch (plane) {
 718         case OMAP_DSS_GFX:
 719                 BUG();
 720                 return 0;
 721         case OMAP_DSS_VIDEO1:
 722         case OMAP_DSS_VIDEO2:
 723                 return 0x0034 + i * 0x8;
 724         case OMAP_DSS_VIDEO3:
 725                 return 0x0010 + i * 0x8;
 726         default:
 727                 BUG();
 728                 return 0;
 729         }
 730 }
 731
 732 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 733 static inline u16 DISPC_FIR_COEF_H2_OFFSET(enum omap_plane plane, u16 i)
 734 {
 735         switch (plane) {
 736         case OMAP_DSS_GFX:
 737                 BUG();
 738                 return 0;
 739         case OMAP_DSS_VIDEO1:
 740                 return 0x058C + i * 0x8;
 741         case OMAP_DSS_VIDEO2:
 742                 return 0x0568 + i * 0x8;
 743         case OMAP_DSS_VIDEO3:
 744                 return 0x0430 + i * 0x8;
 745         default:
 746                 BUG();
 747                 return 0;
 748         }
 749 }
 750
 751 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 752 static inline u16 DISPC_FIR_COEF_HV_OFFSET(enum omap_plane plane, u16 i)
 753 {
 754         switch (plane) {
 755         case OMAP_DSS_GFX:
 756                 BUG();
 757                 return 0;
 758         case OMAP_DSS_VIDEO1:
 759         case OMAP_DSS_VIDEO2:
 760                 return 0x0038 + i * 0x8;
 761         case OMAP_DSS_VIDEO3:
 762                 return 0x0014 + i * 0x8;
 763         default:
 764                 BUG();
 765                 return 0;
 766         }
 767 }
 768
 769 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 770 static inline u16 DISPC_FIR_COEF_HV2_OFFSET(enum omap_plane plane, u16 i)
 771 {
 772         switch (plane) {
 773         case OMAP_DSS_GFX:
 774                 BUG();
 775                 return 0;
 776         case OMAP_DSS_VIDEO1:
 777                 return 0x0590 + i * 8;
 778         case OMAP_DSS_VIDEO2:
 779                 return 0x056C + i * 0x8;
 780         case OMAP_DSS_VIDEO3:
 781                 return 0x0434 + i * 0x8;
 782         default:
 783                 BUG();
 784                 return 0;
 785         }
 786 }
 787
 788 /* coef index i = {0, 1, 2, 3, 4,} */
 789 static inline u16 DISPC_CONV_COEF_OFFSET(enum omap_plane plane, u16 i)
 790 {
 791         switch (plane) {
 792         case OMAP_DSS_GFX:
 793                 BUG();
 794                 return 0;
 795         case OMAP_DSS_VIDEO1:
 796         case OMAP_DSS_VIDEO2:
 797         case OMAP_DSS_VIDEO3:
 798                 return 0x0074 + i * 0x4;
 799         default:
 800                 BUG();
 801                 return 0;
 802         }
 803 }
 804
 805 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 806 static inline u16 DISPC_FIR_COEF_V_OFFSET(enum omap_plane plane, u16 i)
 807 {
 808         switch (plane) {
 809         case OMAP_DSS_GFX:
 810                 BUG();
 811                 return 0;
 812         case OMAP_DSS_VIDEO1:
 813                 return 0x0124 + i * 0x4;
 814         case OMAP_DSS_VIDEO2:
 815                 return 0x00B4 + i * 0x4;
 816         case OMAP_DSS_VIDEO3:
 817                 return 0x0050 + i * 0x4;
 818         default:
 819                 BUG();
 820                 return 0;
 821         }
 822 }
 823
 824 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 825 static inline u16 DISPC_FIR_COEF_V2_OFFSET(enum omap_plane plane, u16 i)
 826 {
 827         switch (plane) {
 828         case OMAP_DSS_GFX:
 829                 BUG();
 830                 return 0;
 831         case OMAP_DSS_VIDEO1:
 832                 return 0x05CC + i * 0x4;
 833         case OMAP_DSS_VIDEO2:
 834                 return 0x05A8 + i * 0x4;
 835         case OMAP_DSS_VIDEO3:
 836                 return 0x0470 + i * 0x4;
 837         default:
 838                 BUG();
 839                 return 0;
 840         }
 841 }
 842
 843 static inline u16 DISPC_PRELOAD_OFFSET(enum omap_plane plane)
 844 {
 845         switch (plane) {
 846         case OMAP_DSS_GFX:
 847                 return 0x01AC;
 848         case OMAP_DSS_VIDEO1:
 849                 return 0x0174;
 850         case OMAP_DSS_VIDEO2:
 851                 return 0x00E8;
 852         case OMAP_DSS_VIDEO3:
 853                 return 0x00A0;
 854         default:
 855                 BUG();
 856                 return 0;
 857         }
 858 }
 859 #endif