2 * linux/drivers/video/omap2/dss/dpi.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * Some code and ideas taken from drivers/video/omap/ driver
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
23 #define DSS_SUBSYS_NAME "DPI"
25 #include <linux/kernel.h>
26 #include <linux/delay.h>
27 #include <linux/err.h>
28 #include <linux/errno.h>
29 #include <linux/platform_device.h>
30 #include <linux/regulator/consumer.h>
32 #include <video/omapdss.h>
38 struct regulator *vdds_dsi_reg;
39 struct platform_device *dsidev;
42 static struct platform_device *dpi_get_dsidev(enum omap_dss_clk_source clk)
46 dsi_module = clk == OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC ? 0 : 1;
48 return dsi_get_dsidev_from_id(dsi_module);
51 static bool dpi_use_dsi_pll(struct omap_dss_device *dssdev)
53 if (dssdev->clocks.dispc.dispc_fclk_src ==
54 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC ||
55 dssdev->clocks.dispc.dispc_fclk_src ==
56 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC ||
57 dssdev->clocks.dispc.channel.lcd_clk_src ==
58 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC ||
59 dssdev->clocks.dispc.channel.lcd_clk_src ==
60 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC)
66 static int dpi_set_dsi_clk(struct omap_dss_device *dssdev, bool is_tft,
67 unsigned long pck_req, unsigned long *fck, int *lck_div,
70 struct dsi_clock_info dsi_cinfo;
71 struct dispc_clock_info dispc_cinfo;
74 r = dsi_pll_calc_clock_div_pck(dpi.dsidev, is_tft, pck_req,
75 &dsi_cinfo, &dispc_cinfo);
79 r = dsi_pll_set_clock_div(dpi.dsidev, &dsi_cinfo);
83 dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);
85 r = dispc_mgr_set_clock_div(dssdev->manager->id, &dispc_cinfo);
87 dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
91 *fck = dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
92 *lck_div = dispc_cinfo.lck_div;
93 *pck_div = dispc_cinfo.pck_div;
98 static int dpi_set_dispc_clk(struct omap_dss_device *dssdev, bool is_tft,
99 unsigned long pck_req, unsigned long *fck, int *lck_div,
102 struct dss_clock_info dss_cinfo;
103 struct dispc_clock_info dispc_cinfo;
106 r = dss_calc_clock_div(is_tft, pck_req, &dss_cinfo, &dispc_cinfo);
110 r = dss_set_clock_div(&dss_cinfo);
114 r = dispc_mgr_set_clock_div(dssdev->manager->id, &dispc_cinfo);
118 *fck = dss_cinfo.fck;
119 *lck_div = dispc_cinfo.lck_div;
120 *pck_div = dispc_cinfo.pck_div;
125 static int dpi_set_mode(struct omap_dss_device *dssdev)
127 struct omap_video_timings *t = &dssdev->panel.timings;
128 int lck_div = 0, pck_div = 0;
129 unsigned long fck = 0;
134 dispc_mgr_set_pol_freq(dssdev->manager->id, dssdev->panel.config,
135 dssdev->panel.acbi, dssdev->panel.acb);
137 is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
139 if (dpi_use_dsi_pll(dssdev))
140 r = dpi_set_dsi_clk(dssdev, is_tft, t->pixel_clock * 1000,
141 &fck, &lck_div, &pck_div);
143 r = dpi_set_dispc_clk(dssdev, is_tft, t->pixel_clock * 1000,
144 &fck, &lck_div, &pck_div);
148 pck = fck / lck_div / pck_div / 1000;
150 if (pck != t->pixel_clock) {
151 DSSWARN("Could not find exact pixel clock. "
152 "Requested %d kHz, got %lu kHz\n",
153 t->pixel_clock, pck);
155 t->pixel_clock = pck;
158 dispc_mgr_set_lcd_timings(dssdev->manager->id, t);
163 static void dpi_basic_init(struct omap_dss_device *dssdev)
167 is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
169 dispc_mgr_set_io_pad_mode(DSS_IO_PAD_MODE_BYPASS);
170 dispc_mgr_enable_stallmode(dssdev->manager->id, false);
172 dispc_mgr_set_lcd_display_type(dssdev->manager->id, is_tft ?
173 OMAP_DSS_LCD_DISPLAY_TFT : OMAP_DSS_LCD_DISPLAY_STN);
174 dispc_mgr_set_tft_data_lines(dssdev->manager->id,
175 dssdev->phy.dpi.data_lines);
178 int omapdss_dpi_display_enable(struct omap_dss_device *dssdev)
182 if (dssdev->manager == NULL) {
183 DSSERR("failed to enable display: no manager\n");
187 r = omap_dss_start_device(dssdev);
189 DSSERR("failed to start device\n");
193 if (cpu_is_omap34xx()) {
194 r = regulator_enable(dpi.vdds_dsi_reg);
199 r = dss_runtime_get();
203 r = dispc_runtime_get();
207 dpi_basic_init(dssdev);
209 if (dpi_use_dsi_pll(dssdev)) {
210 r = dsi_runtime_get(dpi.dsidev);
214 r = dsi_pll_init(dpi.dsidev, 0, 1);
216 goto err_dsi_pll_init;
219 r = dpi_set_mode(dssdev);
225 dssdev->manager->enable(dssdev->manager);
230 if (dpi_use_dsi_pll(dssdev))
231 dsi_pll_uninit(dpi.dsidev, true);
233 if (dpi_use_dsi_pll(dssdev))
234 dsi_runtime_put(dpi.dsidev);
240 if (cpu_is_omap34xx())
241 regulator_disable(dpi.vdds_dsi_reg);
243 omap_dss_stop_device(dssdev);
247 EXPORT_SYMBOL(omapdss_dpi_display_enable);
249 void omapdss_dpi_display_disable(struct omap_dss_device *dssdev)
251 dssdev->manager->disable(dssdev->manager);
253 if (dpi_use_dsi_pll(dssdev)) {
254 dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
255 dsi_pll_uninit(dpi.dsidev, true);
256 dsi_runtime_put(dpi.dsidev);
262 if (cpu_is_omap34xx())
263 regulator_disable(dpi.vdds_dsi_reg);
265 omap_dss_stop_device(dssdev);
267 EXPORT_SYMBOL(omapdss_dpi_display_disable);
269 void dpi_set_timings(struct omap_dss_device *dssdev,
270 struct omap_video_timings *timings)
274 DSSDBG("dpi_set_timings\n");
275 dssdev->panel.timings = *timings;
276 if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) {
277 r = dss_runtime_get();
281 r = dispc_runtime_get();
287 dpi_set_mode(dssdev);
288 dispc_mgr_go(dssdev->manager->id);
294 EXPORT_SYMBOL(dpi_set_timings);
296 int dpi_check_timings(struct omap_dss_device *dssdev,
297 struct omap_video_timings *timings)
301 int lck_div, pck_div;
304 struct dispc_clock_info dispc_cinfo;
306 if (!dispc_lcd_timings_ok(timings))
309 if (timings->pixel_clock == 0)
312 is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
314 if (dpi_use_dsi_pll(dssdev)) {
315 struct dsi_clock_info dsi_cinfo;
316 r = dsi_pll_calc_clock_div_pck(dpi.dsidev, is_tft,
317 timings->pixel_clock * 1000,
318 &dsi_cinfo, &dispc_cinfo);
323 fck = dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
325 struct dss_clock_info dss_cinfo;
326 r = dss_calc_clock_div(is_tft, timings->pixel_clock * 1000,
327 &dss_cinfo, &dispc_cinfo);
335 lck_div = dispc_cinfo.lck_div;
336 pck_div = dispc_cinfo.pck_div;
338 pck = fck / lck_div / pck_div / 1000;
340 timings->pixel_clock = pck;
344 EXPORT_SYMBOL(dpi_check_timings);
346 int dpi_init_display(struct omap_dss_device *dssdev)
348 DSSDBG("init_display\n");
350 if (cpu_is_omap34xx() && dpi.vdds_dsi_reg == NULL) {
351 struct regulator *vdds_dsi;
353 vdds_dsi = dss_get_vdds_dsi();
355 if (IS_ERR(vdds_dsi)) {
356 DSSERR("can't get VDDS_DSI regulator\n");
357 return PTR_ERR(vdds_dsi);
360 dpi.vdds_dsi_reg = vdds_dsi;
363 if (dpi_use_dsi_pll(dssdev)) {
364 enum omap_dss_clk_source dispc_fclk_src =
365 dssdev->clocks.dispc.dispc_fclk_src;
366 dpi.dsidev = dpi_get_dsidev(dispc_fclk_src);