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[karo-tx-linux.git] / drivers / video / omap2 / dss / dpi.c
1 /*
2  * linux/drivers/video/omap2/dss/dpi.c
3  *
4  * Copyright (C) 2009 Nokia Corporation
5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6  *
7  * Some code and ideas taken from drivers/video/omap/ driver
8  * by Imre Deak.
9  *
10  * This program is free software; you can redistribute it and/or modify it
11  * under the terms of the GNU General Public License version 2 as published by
12  * the Free Software Foundation.
13  *
14  * This program is distributed in the hope that it will be useful, but WITHOUT
15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
17  * more details.
18  *
19  * You should have received a copy of the GNU General Public License along with
20  * this program.  If not, see <http://www.gnu.org/licenses/>.
21  */
22
23 #define DSS_SUBSYS_NAME "DPI"
24
25 #include <linux/kernel.h>
26 #include <linux/delay.h>
27 #include <linux/export.h>
28 #include <linux/err.h>
29 #include <linux/errno.h>
30 #include <linux/platform_device.h>
31 #include <linux/regulator/consumer.h>
32 #include <linux/string.h>
33
34 #include <video/omapdss.h>
35
36 #include "dss.h"
37 #include "dss_features.h"
38
39 static struct {
40         struct platform_device *pdev;
41
42         struct regulator *vdds_dsi_reg;
43         struct platform_device *dsidev;
44
45         struct mutex lock;
46
47         struct omap_video_timings timings;
48         struct dss_lcd_mgr_config mgr_config;
49         int data_lines;
50
51         struct omap_dss_device output;
52 } dpi;
53
54 static struct platform_device *dpi_get_dsidev(enum omap_channel channel)
55 {
56         /*
57          * XXX we can't currently use DSI PLL for DPI with OMAP3, as the DSI PLL
58          * would also be used for DISPC fclk. Meaning, when the DPI output is
59          * disabled, DISPC clock will be disabled, and TV out will stop.
60          */
61         switch (omapdss_get_version()) {
62         case OMAPDSS_VER_OMAP24xx:
63         case OMAPDSS_VER_OMAP34xx_ES1:
64         case OMAPDSS_VER_OMAP34xx_ES3:
65         case OMAPDSS_VER_OMAP3630:
66         case OMAPDSS_VER_AM35xx:
67                 return NULL;
68
69         case OMAPDSS_VER_OMAP4430_ES1:
70         case OMAPDSS_VER_OMAP4430_ES2:
71         case OMAPDSS_VER_OMAP4:
72                 switch (channel) {
73                 case OMAP_DSS_CHANNEL_LCD:
74                         return dsi_get_dsidev_from_id(0);
75                 case OMAP_DSS_CHANNEL_LCD2:
76                         return dsi_get_dsidev_from_id(1);
77                 default:
78                         return NULL;
79                 }
80
81         case OMAPDSS_VER_OMAP5:
82                 switch (channel) {
83                 case OMAP_DSS_CHANNEL_LCD:
84                         return dsi_get_dsidev_from_id(0);
85                 case OMAP_DSS_CHANNEL_LCD3:
86                         return dsi_get_dsidev_from_id(1);
87                 default:
88                         return NULL;
89                 }
90
91         default:
92                 return NULL;
93         }
94 }
95
96 static enum omap_dss_clk_source dpi_get_alt_clk_src(enum omap_channel channel)
97 {
98         switch (channel) {
99         case OMAP_DSS_CHANNEL_LCD:
100                 return OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC;
101         case OMAP_DSS_CHANNEL_LCD2:
102                 return OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC;
103         default:
104                 /* this shouldn't happen */
105                 WARN_ON(1);
106                 return OMAP_DSS_CLK_SRC_FCK;
107         }
108 }
109
110 struct dpi_clk_calc_ctx {
111         struct platform_device *dsidev;
112
113         /* inputs */
114
115         unsigned long pck_min, pck_max;
116
117         /* outputs */
118
119         struct dsi_clock_info dsi_cinfo;
120         unsigned long fck;
121         struct dispc_clock_info dispc_cinfo;
122 };
123
124 static bool dpi_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
125                 unsigned long pck, void *data)
126 {
127         struct dpi_clk_calc_ctx *ctx = data;
128
129         /*
130          * Odd dividers give us uneven duty cycle, causing problem when level
131          * shifted. So skip all odd dividers when the pixel clock is on the
132          * higher side.
133          */
134         if (ctx->pck_min >= 100000000) {
135                 if (lckd > 1 && lckd % 2 != 0)
136                         return false;
137
138                 if (pckd > 1 && pckd % 2 != 0)
139                         return false;
140         }
141
142         ctx->dispc_cinfo.lck_div = lckd;
143         ctx->dispc_cinfo.pck_div = pckd;
144         ctx->dispc_cinfo.lck = lck;
145         ctx->dispc_cinfo.pck = pck;
146
147         return true;
148 }
149
150
151 static bool dpi_calc_hsdiv_cb(int regm_dispc, unsigned long dispc,
152                 void *data)
153 {
154         struct dpi_clk_calc_ctx *ctx = data;
155
156         /*
157          * Odd dividers give us uneven duty cycle, causing problem when level
158          * shifted. So skip all odd dividers when the pixel clock is on the
159          * higher side.
160          */
161         if (regm_dispc > 1 && regm_dispc % 2 != 0 && ctx->pck_min >= 100000000)
162                 return false;
163
164         ctx->dsi_cinfo.regm_dispc = regm_dispc;
165         ctx->dsi_cinfo.dsi_pll_hsdiv_dispc_clk = dispc;
166
167         return dispc_div_calc(dispc, ctx->pck_min, ctx->pck_max,
168                         dpi_calc_dispc_cb, ctx);
169 }
170
171
172 static bool dpi_calc_pll_cb(int regn, int regm, unsigned long fint,
173                 unsigned long pll,
174                 void *data)
175 {
176         struct dpi_clk_calc_ctx *ctx = data;
177
178         ctx->dsi_cinfo.regn = regn;
179         ctx->dsi_cinfo.regm = regm;
180         ctx->dsi_cinfo.fint = fint;
181         ctx->dsi_cinfo.clkin4ddr = pll;
182
183         return dsi_hsdiv_calc(ctx->dsidev, pll, ctx->pck_min,
184                         dpi_calc_hsdiv_cb, ctx);
185 }
186
187 static bool dpi_calc_dss_cb(unsigned long fck, void *data)
188 {
189         struct dpi_clk_calc_ctx *ctx = data;
190
191         ctx->fck = fck;
192
193         return dispc_div_calc(fck, ctx->pck_min, ctx->pck_max,
194                         dpi_calc_dispc_cb, ctx);
195 }
196
197 static bool dpi_dsi_clk_calc(unsigned long pck, struct dpi_clk_calc_ctx *ctx)
198 {
199         unsigned long clkin;
200         unsigned long pll_min, pll_max;
201
202         clkin = dsi_get_pll_clkin(dpi.dsidev);
203
204         memset(ctx, 0, sizeof(*ctx));
205         ctx->dsidev = dpi.dsidev;
206         ctx->pck_min = pck - 1000;
207         ctx->pck_max = pck + 1000;
208         ctx->dsi_cinfo.clkin = clkin;
209
210         pll_min = 0;
211         pll_max = 0;
212
213         return dsi_pll_calc(dpi.dsidev, clkin,
214                         pll_min, pll_max,
215                         dpi_calc_pll_cb, ctx);
216 }
217
218 static bool dpi_dss_clk_calc(unsigned long pck, struct dpi_clk_calc_ctx *ctx)
219 {
220         int i;
221
222         /*
223          * DSS fck gives us very few possibilities, so finding a good pixel
224          * clock may not be possible. We try multiple times to find the clock,
225          * each time widening the pixel clock range we look for, up to
226          * +/- ~15MHz.
227          */
228
229         for (i = 0; i < 25; ++i) {
230                 bool ok;
231
232                 memset(ctx, 0, sizeof(*ctx));
233                 if (pck > 1000 * i * i * i)
234                         ctx->pck_min = max(pck - 1000 * i * i * i, 0lu);
235                 else
236                         ctx->pck_min = 0;
237                 ctx->pck_max = pck + 1000 * i * i * i;
238
239                 ok = dss_div_calc(pck, ctx->pck_min, dpi_calc_dss_cb, ctx);
240                 if (ok)
241                         return ok;
242         }
243
244         return false;
245 }
246
247
248
249 static int dpi_set_dsi_clk(enum omap_channel channel,
250                 unsigned long pck_req, unsigned long *fck, int *lck_div,
251                 int *pck_div)
252 {
253         struct dpi_clk_calc_ctx ctx;
254         int r;
255         bool ok;
256
257         ok = dpi_dsi_clk_calc(pck_req, &ctx);
258         if (!ok)
259                 return -EINVAL;
260
261         r = dsi_pll_set_clock_div(dpi.dsidev, &ctx.dsi_cinfo);
262         if (r)
263                 return r;
264
265         dss_select_lcd_clk_source(channel,
266                         dpi_get_alt_clk_src(channel));
267
268         dpi.mgr_config.clock_info = ctx.dispc_cinfo;
269
270         *fck = ctx.dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
271         *lck_div = ctx.dispc_cinfo.lck_div;
272         *pck_div = ctx.dispc_cinfo.pck_div;
273
274         return 0;
275 }
276
277 static int dpi_set_dispc_clk(unsigned long pck_req, unsigned long *fck,
278                 int *lck_div, int *pck_div)
279 {
280         struct dpi_clk_calc_ctx ctx;
281         int r;
282         bool ok;
283
284         ok = dpi_dss_clk_calc(pck_req, &ctx);
285         if (!ok)
286                 return -EINVAL;
287
288         r = dss_set_fck_rate(ctx.fck);
289         if (r)
290                 return r;
291
292         dpi.mgr_config.clock_info = ctx.dispc_cinfo;
293
294         *fck = ctx.fck;
295         *lck_div = ctx.dispc_cinfo.lck_div;
296         *pck_div = ctx.dispc_cinfo.pck_div;
297
298         return 0;
299 }
300
301 static int dpi_set_mode(struct omap_overlay_manager *mgr)
302 {
303         struct omap_video_timings *t = &dpi.timings;
304         int lck_div = 0, pck_div = 0;
305         unsigned long fck = 0;
306         unsigned long pck;
307         int r = 0;
308
309         if (dpi.dsidev)
310                 r = dpi_set_dsi_clk(mgr->id, t->pixelclock, &fck,
311                                 &lck_div, &pck_div);
312         else
313                 r = dpi_set_dispc_clk(t->pixelclock, &fck,
314                                 &lck_div, &pck_div);
315         if (r)
316                 return r;
317
318         pck = fck / lck_div / pck_div;
319
320         if (pck != t->pixelclock) {
321                 DSSWARN("Could not find exact pixel clock. Requested %d Hz, got %lu Hz\n",
322                         t->pixelclock, pck);
323
324                 t->pixelclock = pck;
325         }
326
327         dss_mgr_set_timings(mgr, t);
328
329         return 0;
330 }
331
332 static void dpi_config_lcd_manager(struct omap_overlay_manager *mgr)
333 {
334         dpi.mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
335
336         dpi.mgr_config.stallmode = false;
337         dpi.mgr_config.fifohandcheck = false;
338
339         dpi.mgr_config.video_port_width = dpi.data_lines;
340
341         dpi.mgr_config.lcden_sig_polarity = 0;
342
343         dss_mgr_set_lcd_config(mgr, &dpi.mgr_config);
344 }
345
346 static int dpi_display_enable(struct omap_dss_device *dssdev)
347 {
348         struct omap_dss_device *out = &dpi.output;
349         int r;
350
351         mutex_lock(&dpi.lock);
352
353         if (dss_has_feature(FEAT_DPI_USES_VDDS_DSI) && !dpi.vdds_dsi_reg) {
354                 DSSERR("no VDSS_DSI regulator\n");
355                 r = -ENODEV;
356                 goto err_no_reg;
357         }
358
359         if (out == NULL || out->manager == NULL) {
360                 DSSERR("failed to enable display: no output/manager\n");
361                 r = -ENODEV;
362                 goto err_no_out_mgr;
363         }
364
365         if (dss_has_feature(FEAT_DPI_USES_VDDS_DSI)) {
366                 r = regulator_enable(dpi.vdds_dsi_reg);
367                 if (r)
368                         goto err_reg_enable;
369         }
370
371         r = dispc_runtime_get();
372         if (r)
373                 goto err_get_dispc;
374
375         r = dss_dpi_select_source(out->manager->id);
376         if (r)
377                 goto err_src_sel;
378
379         if (dpi.dsidev) {
380                 r = dsi_runtime_get(dpi.dsidev);
381                 if (r)
382                         goto err_get_dsi;
383
384                 r = dsi_pll_init(dpi.dsidev, 0, 1);
385                 if (r)
386                         goto err_dsi_pll_init;
387         }
388
389         r = dpi_set_mode(out->manager);
390         if (r)
391                 goto err_set_mode;
392
393         dpi_config_lcd_manager(out->manager);
394
395         mdelay(2);
396
397         r = dss_mgr_enable(out->manager);
398         if (r)
399                 goto err_mgr_enable;
400
401         mutex_unlock(&dpi.lock);
402
403         return 0;
404
405 err_mgr_enable:
406 err_set_mode:
407         if (dpi.dsidev)
408                 dsi_pll_uninit(dpi.dsidev, true);
409 err_dsi_pll_init:
410         if (dpi.dsidev)
411                 dsi_runtime_put(dpi.dsidev);
412 err_get_dsi:
413 err_src_sel:
414         dispc_runtime_put();
415 err_get_dispc:
416         if (dss_has_feature(FEAT_DPI_USES_VDDS_DSI))
417                 regulator_disable(dpi.vdds_dsi_reg);
418 err_reg_enable:
419 err_no_out_mgr:
420 err_no_reg:
421         mutex_unlock(&dpi.lock);
422         return r;
423 }
424
425 static void dpi_display_disable(struct omap_dss_device *dssdev)
426 {
427         struct omap_overlay_manager *mgr = dpi.output.manager;
428
429         mutex_lock(&dpi.lock);
430
431         dss_mgr_disable(mgr);
432
433         if (dpi.dsidev) {
434                 dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK);
435                 dsi_pll_uninit(dpi.dsidev, true);
436                 dsi_runtime_put(dpi.dsidev);
437         }
438
439         dispc_runtime_put();
440
441         if (dss_has_feature(FEAT_DPI_USES_VDDS_DSI))
442                 regulator_disable(dpi.vdds_dsi_reg);
443
444         mutex_unlock(&dpi.lock);
445 }
446
447 static void dpi_set_timings(struct omap_dss_device *dssdev,
448                 struct omap_video_timings *timings)
449 {
450         DSSDBG("dpi_set_timings\n");
451
452         mutex_lock(&dpi.lock);
453
454         dpi.timings = *timings;
455
456         mutex_unlock(&dpi.lock);
457 }
458
459 static void dpi_get_timings(struct omap_dss_device *dssdev,
460                 struct omap_video_timings *timings)
461 {
462         mutex_lock(&dpi.lock);
463
464         *timings = dpi.timings;
465
466         mutex_unlock(&dpi.lock);
467 }
468
469 static int dpi_check_timings(struct omap_dss_device *dssdev,
470                         struct omap_video_timings *timings)
471 {
472         struct omap_overlay_manager *mgr = dpi.output.manager;
473         int lck_div, pck_div;
474         unsigned long fck;
475         unsigned long pck;
476         struct dpi_clk_calc_ctx ctx;
477         bool ok;
478
479         if (mgr && !dispc_mgr_timings_ok(mgr->id, timings))
480                 return -EINVAL;
481
482         if (timings->pixelclock == 0)
483                 return -EINVAL;
484
485         if (dpi.dsidev) {
486                 ok = dpi_dsi_clk_calc(timings->pixelclock, &ctx);
487                 if (!ok)
488                         return -EINVAL;
489
490                 fck = ctx.dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
491         } else {
492                 ok = dpi_dss_clk_calc(timings->pixelclock, &ctx);
493                 if (!ok)
494                         return -EINVAL;
495
496                 fck = ctx.fck;
497         }
498
499         lck_div = ctx.dispc_cinfo.lck_div;
500         pck_div = ctx.dispc_cinfo.pck_div;
501
502         pck = fck / lck_div / pck_div;
503
504         timings->pixelclock = pck;
505
506         return 0;
507 }
508
509 static void dpi_set_data_lines(struct omap_dss_device *dssdev, int data_lines)
510 {
511         mutex_lock(&dpi.lock);
512
513         dpi.data_lines = data_lines;
514
515         mutex_unlock(&dpi.lock);
516 }
517
518 static int dpi_verify_dsi_pll(struct platform_device *dsidev)
519 {
520         int r;
521
522         /* do initial setup with the PLL to see if it is operational */
523
524         r = dsi_runtime_get(dsidev);
525         if (r)
526                 return r;
527
528         r = dsi_pll_init(dsidev, 0, 1);
529         if (r) {
530                 dsi_runtime_put(dsidev);
531                 return r;
532         }
533
534         dsi_pll_uninit(dsidev, true);
535         dsi_runtime_put(dsidev);
536
537         return 0;
538 }
539
540 static int dpi_init_regulator(void)
541 {
542         struct regulator *vdds_dsi;
543
544         if (!dss_has_feature(FEAT_DPI_USES_VDDS_DSI))
545                 return 0;
546
547         if (dpi.vdds_dsi_reg)
548                 return 0;
549
550         vdds_dsi = devm_regulator_get(&dpi.pdev->dev, "vdds_dsi");
551         if (IS_ERR(vdds_dsi)) {
552                 if (PTR_ERR(vdds_dsi) != -EPROBE_DEFER)
553                         DSSERR("can't get VDDS_DSI regulator\n");
554                 return PTR_ERR(vdds_dsi);
555         }
556
557         dpi.vdds_dsi_reg = vdds_dsi;
558
559         return 0;
560 }
561
562 static void dpi_init_pll(void)
563 {
564         struct platform_device *dsidev;
565
566         if (dpi.dsidev)
567                 return;
568
569         dsidev = dpi_get_dsidev(dpi.output.dispc_channel);
570         if (!dsidev)
571                 return;
572
573         if (dpi_verify_dsi_pll(dsidev)) {
574                 DSSWARN("DSI PLL not operational\n");
575                 return;
576         }
577
578         dpi.dsidev = dsidev;
579 }
580
581 /*
582  * Return a hardcoded channel for the DPI output. This should work for
583  * current use cases, but this can be later expanded to either resolve
584  * the channel in some more dynamic manner, or get the channel as a user
585  * parameter.
586  */
587 static enum omap_channel dpi_get_channel(void)
588 {
589         switch (omapdss_get_version()) {
590         case OMAPDSS_VER_OMAP24xx:
591         case OMAPDSS_VER_OMAP34xx_ES1:
592         case OMAPDSS_VER_OMAP34xx_ES3:
593         case OMAPDSS_VER_OMAP3630:
594         case OMAPDSS_VER_AM35xx:
595                 return OMAP_DSS_CHANNEL_LCD;
596
597         case OMAPDSS_VER_OMAP4430_ES1:
598         case OMAPDSS_VER_OMAP4430_ES2:
599         case OMAPDSS_VER_OMAP4:
600                 return OMAP_DSS_CHANNEL_LCD2;
601
602         case OMAPDSS_VER_OMAP5:
603                 return OMAP_DSS_CHANNEL_LCD3;
604
605         default:
606                 DSSWARN("unsupported DSS version\n");
607                 return OMAP_DSS_CHANNEL_LCD;
608         }
609 }
610
611 static int dpi_connect(struct omap_dss_device *dssdev,
612                 struct omap_dss_device *dst)
613 {
614         struct omap_overlay_manager *mgr;
615         int r;
616
617         r = dpi_init_regulator();
618         if (r)
619                 return r;
620
621         dpi_init_pll();
622
623         mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel);
624         if (!mgr)
625                 return -ENODEV;
626
627         r = dss_mgr_connect(mgr, dssdev);
628         if (r)
629                 return r;
630
631         r = omapdss_output_set_device(dssdev, dst);
632         if (r) {
633                 DSSERR("failed to connect output to new device: %s\n",
634                                 dst->name);
635                 dss_mgr_disconnect(mgr, dssdev);
636                 return r;
637         }
638
639         return 0;
640 }
641
642 static void dpi_disconnect(struct omap_dss_device *dssdev,
643                 struct omap_dss_device *dst)
644 {
645         WARN_ON(dst != dssdev->dst);
646
647         if (dst != dssdev->dst)
648                 return;
649
650         omapdss_output_unset_device(dssdev);
651
652         if (dssdev->manager)
653                 dss_mgr_disconnect(dssdev->manager, dssdev);
654 }
655
656 static const struct omapdss_dpi_ops dpi_ops = {
657         .connect = dpi_connect,
658         .disconnect = dpi_disconnect,
659
660         .enable = dpi_display_enable,
661         .disable = dpi_display_disable,
662
663         .check_timings = dpi_check_timings,
664         .set_timings = dpi_set_timings,
665         .get_timings = dpi_get_timings,
666
667         .set_data_lines = dpi_set_data_lines,
668 };
669
670 static void dpi_init_output(struct platform_device *pdev)
671 {
672         struct omap_dss_device *out = &dpi.output;
673
674         out->dev = &pdev->dev;
675         out->id = OMAP_DSS_OUTPUT_DPI;
676         out->output_type = OMAP_DISPLAY_TYPE_DPI;
677         out->name = "dpi.0";
678         out->dispc_channel = dpi_get_channel();
679         out->ops.dpi = &dpi_ops;
680         out->owner = THIS_MODULE;
681
682         omapdss_register_output(out);
683 }
684
685 static void __exit dpi_uninit_output(struct platform_device *pdev)
686 {
687         struct omap_dss_device *out = &dpi.output;
688
689         omapdss_unregister_output(out);
690 }
691
692 static int omap_dpi_probe(struct platform_device *pdev)
693 {
694         dpi.pdev = pdev;
695
696         mutex_init(&dpi.lock);
697
698         dpi_init_output(pdev);
699
700         return 0;
701 }
702
703 static int __exit omap_dpi_remove(struct platform_device *pdev)
704 {
705         dpi_uninit_output(pdev);
706
707         return 0;
708 }
709
710 static struct platform_driver omap_dpi_driver = {
711         .probe          = omap_dpi_probe,
712         .remove         = __exit_p(omap_dpi_remove),
713         .driver         = {
714                 .name   = "omapdss_dpi",
715                 .owner  = THIS_MODULE,
716         },
717 };
718
719 int __init dpi_init_platform_driver(void)
720 {
721         return platform_driver_register(&omap_dpi_driver);
722 }
723
724 void __exit dpi_uninit_platform_driver(void)
725 {
726         platform_driver_unregister(&omap_dpi_driver);
727 }