2 * linux/drivers/video/omap2/dss/dsi.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #define DSS_SUBSYS_NAME "DSI"
22 #include <linux/kernel.h>
24 #include <linux/clk.h>
25 #include <linux/device.h>
26 #include <linux/err.h>
27 #include <linux/interrupt.h>
28 #include <linux/delay.h>
29 #include <linux/mutex.h>
30 #include <linux/module.h>
31 #include <linux/semaphore.h>
32 #include <linux/seq_file.h>
33 #include <linux/platform_device.h>
34 #include <linux/regulator/consumer.h>
35 #include <linux/wait.h>
36 #include <linux/workqueue.h>
37 #include <linux/sched.h>
38 #include <linux/slab.h>
39 #include <linux/debugfs.h>
40 #include <linux/pm_runtime.h>
42 #include <linux/of_platform.h>
44 #include <video/omapdss.h>
45 #include <video/mipi_display.h>
48 #include "dss_features.h"
50 #define DSI_CATCH_MISSING_TE
52 struct dsi_reg { u16 module; u16 idx; };
54 #define DSI_REG(mod, idx) ((const struct dsi_reg) { mod, idx })
56 /* DSI Protocol Engine */
59 #define DSI_PROTO_SZ 0x200
61 #define DSI_REVISION DSI_REG(DSI_PROTO, 0x0000)
62 #define DSI_SYSCONFIG DSI_REG(DSI_PROTO, 0x0010)
63 #define DSI_SYSSTATUS DSI_REG(DSI_PROTO, 0x0014)
64 #define DSI_IRQSTATUS DSI_REG(DSI_PROTO, 0x0018)
65 #define DSI_IRQENABLE DSI_REG(DSI_PROTO, 0x001C)
66 #define DSI_CTRL DSI_REG(DSI_PROTO, 0x0040)
67 #define DSI_GNQ DSI_REG(DSI_PROTO, 0x0044)
68 #define DSI_COMPLEXIO_CFG1 DSI_REG(DSI_PROTO, 0x0048)
69 #define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(DSI_PROTO, 0x004C)
70 #define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(DSI_PROTO, 0x0050)
71 #define DSI_CLK_CTRL DSI_REG(DSI_PROTO, 0x0054)
72 #define DSI_TIMING1 DSI_REG(DSI_PROTO, 0x0058)
73 #define DSI_TIMING2 DSI_REG(DSI_PROTO, 0x005C)
74 #define DSI_VM_TIMING1 DSI_REG(DSI_PROTO, 0x0060)
75 #define DSI_VM_TIMING2 DSI_REG(DSI_PROTO, 0x0064)
76 #define DSI_VM_TIMING3 DSI_REG(DSI_PROTO, 0x0068)
77 #define DSI_CLK_TIMING DSI_REG(DSI_PROTO, 0x006C)
78 #define DSI_TX_FIFO_VC_SIZE DSI_REG(DSI_PROTO, 0x0070)
79 #define DSI_RX_FIFO_VC_SIZE DSI_REG(DSI_PROTO, 0x0074)
80 #define DSI_COMPLEXIO_CFG2 DSI_REG(DSI_PROTO, 0x0078)
81 #define DSI_RX_FIFO_VC_FULLNESS DSI_REG(DSI_PROTO, 0x007C)
82 #define DSI_VM_TIMING4 DSI_REG(DSI_PROTO, 0x0080)
83 #define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(DSI_PROTO, 0x0084)
84 #define DSI_VM_TIMING5 DSI_REG(DSI_PROTO, 0x0088)
85 #define DSI_VM_TIMING6 DSI_REG(DSI_PROTO, 0x008C)
86 #define DSI_VM_TIMING7 DSI_REG(DSI_PROTO, 0x0090)
87 #define DSI_STOPCLK_TIMING DSI_REG(DSI_PROTO, 0x0094)
88 #define DSI_VC_CTRL(n) DSI_REG(DSI_PROTO, 0x0100 + (n * 0x20))
89 #define DSI_VC_TE(n) DSI_REG(DSI_PROTO, 0x0104 + (n * 0x20))
90 #define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(DSI_PROTO, 0x0108 + (n * 0x20))
91 #define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(DSI_PROTO, 0x010C + (n * 0x20))
92 #define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(DSI_PROTO, 0x0110 + (n * 0x20))
93 #define DSI_VC_IRQSTATUS(n) DSI_REG(DSI_PROTO, 0x0118 + (n * 0x20))
94 #define DSI_VC_IRQENABLE(n) DSI_REG(DSI_PROTO, 0x011C + (n * 0x20))
99 #define DSI_PHY_OFFSET 0x200
100 #define DSI_PHY_SZ 0x40
102 #define DSI_DSIPHY_CFG0 DSI_REG(DSI_PHY, 0x0000)
103 #define DSI_DSIPHY_CFG1 DSI_REG(DSI_PHY, 0x0004)
104 #define DSI_DSIPHY_CFG2 DSI_REG(DSI_PHY, 0x0008)
105 #define DSI_DSIPHY_CFG5 DSI_REG(DSI_PHY, 0x0014)
106 #define DSI_DSIPHY_CFG10 DSI_REG(DSI_PHY, 0x0028)
108 /* DSI_PLL_CTRL_SCP */
111 #define DSI_PLL_OFFSET 0x300
112 #define DSI_PLL_SZ 0x20
114 #define DSI_PLL_CONTROL DSI_REG(DSI_PLL, 0x0000)
115 #define DSI_PLL_STATUS DSI_REG(DSI_PLL, 0x0004)
116 #define DSI_PLL_GO DSI_REG(DSI_PLL, 0x0008)
117 #define DSI_PLL_CONFIGURATION1 DSI_REG(DSI_PLL, 0x000C)
118 #define DSI_PLL_CONFIGURATION2 DSI_REG(DSI_PLL, 0x0010)
120 #define REG_GET(dsidev, idx, start, end) \
121 FLD_GET(dsi_read_reg(dsidev, idx), start, end)
123 #define REG_FLD_MOD(dsidev, idx, val, start, end) \
124 dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end))
126 /* Global interrupts */
127 #define DSI_IRQ_VC0 (1 << 0)
128 #define DSI_IRQ_VC1 (1 << 1)
129 #define DSI_IRQ_VC2 (1 << 2)
130 #define DSI_IRQ_VC3 (1 << 3)
131 #define DSI_IRQ_WAKEUP (1 << 4)
132 #define DSI_IRQ_RESYNC (1 << 5)
133 #define DSI_IRQ_PLL_LOCK (1 << 7)
134 #define DSI_IRQ_PLL_UNLOCK (1 << 8)
135 #define DSI_IRQ_PLL_RECALL (1 << 9)
136 #define DSI_IRQ_COMPLEXIO_ERR (1 << 10)
137 #define DSI_IRQ_HS_TX_TIMEOUT (1 << 14)
138 #define DSI_IRQ_LP_RX_TIMEOUT (1 << 15)
139 #define DSI_IRQ_TE_TRIGGER (1 << 16)
140 #define DSI_IRQ_ACK_TRIGGER (1 << 17)
141 #define DSI_IRQ_SYNC_LOST (1 << 18)
142 #define DSI_IRQ_LDO_POWER_GOOD (1 << 19)
143 #define DSI_IRQ_TA_TIMEOUT (1 << 20)
144 #define DSI_IRQ_ERROR_MASK \
145 (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
146 DSI_IRQ_TA_TIMEOUT | DSI_IRQ_SYNC_LOST)
147 #define DSI_IRQ_CHANNEL_MASK 0xf
149 /* Virtual channel interrupts */
150 #define DSI_VC_IRQ_CS (1 << 0)
151 #define DSI_VC_IRQ_ECC_CORR (1 << 1)
152 #define DSI_VC_IRQ_PACKET_SENT (1 << 2)
153 #define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3)
154 #define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4)
155 #define DSI_VC_IRQ_BTA (1 << 5)
156 #define DSI_VC_IRQ_ECC_NO_CORR (1 << 6)
157 #define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7)
158 #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
159 #define DSI_VC_IRQ_ERROR_MASK \
160 (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
161 DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
162 DSI_VC_IRQ_FIFO_TX_UDF)
164 /* ComplexIO interrupts */
165 #define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0)
166 #define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1)
167 #define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2)
168 #define DSI_CIO_IRQ_ERRSYNCESC4 (1 << 3)
169 #define DSI_CIO_IRQ_ERRSYNCESC5 (1 << 4)
170 #define DSI_CIO_IRQ_ERRESC1 (1 << 5)
171 #define DSI_CIO_IRQ_ERRESC2 (1 << 6)
172 #define DSI_CIO_IRQ_ERRESC3 (1 << 7)
173 #define DSI_CIO_IRQ_ERRESC4 (1 << 8)
174 #define DSI_CIO_IRQ_ERRESC5 (1 << 9)
175 #define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10)
176 #define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11)
177 #define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12)
178 #define DSI_CIO_IRQ_ERRCONTROL4 (1 << 13)
179 #define DSI_CIO_IRQ_ERRCONTROL5 (1 << 14)
180 #define DSI_CIO_IRQ_STATEULPS1 (1 << 15)
181 #define DSI_CIO_IRQ_STATEULPS2 (1 << 16)
182 #define DSI_CIO_IRQ_STATEULPS3 (1 << 17)
183 #define DSI_CIO_IRQ_STATEULPS4 (1 << 18)
184 #define DSI_CIO_IRQ_STATEULPS5 (1 << 19)
185 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20)
186 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21)
187 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22)
188 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23)
189 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24)
190 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25)
191 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_4 (1 << 26)
192 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_4 (1 << 27)
193 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_5 (1 << 28)
194 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_5 (1 << 29)
195 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30)
196 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31)
197 #define DSI_CIO_IRQ_ERROR_MASK \
198 (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
199 DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \
200 DSI_CIO_IRQ_ERRSYNCESC5 | \
201 DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
202 DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \
203 DSI_CIO_IRQ_ERRESC5 | \
204 DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \
205 DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \
206 DSI_CIO_IRQ_ERRCONTROL5 | \
207 DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
208 DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
209 DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \
210 DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \
211 DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5)
213 typedef void (*omap_dsi_isr_t) (void *arg, u32 mask);
215 static int dsi_display_init_dispc(struct platform_device *dsidev,
216 struct omap_overlay_manager *mgr);
217 static void dsi_display_uninit_dispc(struct platform_device *dsidev,
218 struct omap_overlay_manager *mgr);
220 static int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel);
222 #define DSI_MAX_NR_ISRS 2
223 #define DSI_MAX_NR_LANES 5
225 enum dsi_lane_function {
234 struct dsi_lane_config {
235 enum dsi_lane_function function;
239 struct dsi_isr_data {
247 DSI_FIFO_SIZE_32 = 1,
248 DSI_FIFO_SIZE_64 = 2,
249 DSI_FIFO_SIZE_96 = 3,
250 DSI_FIFO_SIZE_128 = 4,
254 DSI_VC_SOURCE_L4 = 0,
258 struct dsi_irq_stats {
259 unsigned long last_reset;
261 unsigned dsi_irqs[32];
262 unsigned vc_irqs[4][32];
263 unsigned cio_irqs[32];
266 struct dsi_isr_tables {
267 struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS];
268 struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS];
269 struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS];
272 struct dsi_clk_calc_ctx {
273 struct platform_device *dsidev;
277 const struct omap_dss_dsi_config *config;
279 unsigned long req_pck_min, req_pck_nom, req_pck_max;
283 struct dsi_clock_info dsi_cinfo;
284 struct dispc_clock_info dispc_cinfo;
286 struct omap_video_timings dispc_vm;
287 struct omap_dss_dsi_videomode_timings dsi_vm;
291 struct platform_device *pdev;
292 void __iomem *proto_base;
293 void __iomem *phy_base;
294 void __iomem *pll_base;
303 struct dispc_clock_info user_dispc_cinfo;
304 struct dsi_clock_info user_dsi_cinfo;
306 struct dsi_clock_info current_cinfo;
308 bool vdds_dsi_enabled;
309 struct regulator *vdds_dsi_reg;
312 enum dsi_vc_source source;
313 struct omap_dss_device *dssdev;
314 enum fifo_size tx_fifo_size;
315 enum fifo_size rx_fifo_size;
320 struct semaphore bus_lock;
325 struct dsi_isr_tables isr_tables;
326 /* space for a copy used by the interrupt handler */
327 struct dsi_isr_tables isr_tables_copy;
330 #ifdef DSI_PERF_MEASURE
331 unsigned update_bytes;
337 void (*framedone_callback)(int, void *);
338 void *framedone_data;
340 struct delayed_work framedone_timeout_work;
342 #ifdef DSI_CATCH_MISSING_TE
343 struct timer_list te_timer;
346 unsigned long cache_req_pck;
347 unsigned long cache_clk_freq;
348 struct dsi_clock_info cache_cinfo;
351 spinlock_t errors_lock;
352 #ifdef DSI_PERF_MEASURE
353 ktime_t perf_setup_time;
354 ktime_t perf_start_time;
359 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
360 spinlock_t irq_stats_lock;
361 struct dsi_irq_stats irq_stats;
363 /* DSI PLL Parameter Ranges */
364 unsigned long regm_max, regn_max;
365 unsigned long regm_dispc_max, regm_dsi_max;
366 unsigned long fint_min, fint_max;
367 unsigned long lpdiv_max;
369 unsigned num_lanes_supported;
370 unsigned line_buffer_size;
372 struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
373 unsigned num_lanes_used;
375 unsigned scp_clk_refcount;
377 struct dss_lcd_mgr_config mgr_config;
378 struct omap_video_timings timings;
379 enum omap_dss_dsi_pixel_format pix_fmt;
380 enum omap_dss_dsi_mode mode;
381 struct omap_dss_dsi_videomode_timings vm_timings;
383 struct omap_dss_device output;
386 struct dsi_packet_sent_handler_data {
387 struct platform_device *dsidev;
388 struct completion *completion;
391 struct dsi_module_id_data {
396 static const struct of_device_id dsi_of_match[];
398 #ifdef DSI_PERF_MEASURE
399 static bool dsi_perf;
400 module_param(dsi_perf, bool, 0644);
403 static inline struct dsi_data *dsi_get_dsidrv_data(struct platform_device *dsidev)
405 return dev_get_drvdata(&dsidev->dev);
408 static inline struct platform_device *dsi_get_dsidev_from_dssdev(struct omap_dss_device *dssdev)
410 return to_platform_device(dssdev->dev);
413 struct platform_device *dsi_get_dsidev_from_id(int module)
415 struct omap_dss_device *out;
416 enum omap_dss_output_id id;
420 id = OMAP_DSS_OUTPUT_DSI1;
423 id = OMAP_DSS_OUTPUT_DSI2;
429 out = omap_dss_get_output(id);
431 return out ? to_platform_device(out->dev) : NULL;
434 static inline void dsi_write_reg(struct platform_device *dsidev,
435 const struct dsi_reg idx, u32 val)
437 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
441 case DSI_PROTO: base = dsi->proto_base; break;
442 case DSI_PHY: base = dsi->phy_base; break;
443 case DSI_PLL: base = dsi->pll_base; break;
447 __raw_writel(val, base + idx.idx);
450 static inline u32 dsi_read_reg(struct platform_device *dsidev,
451 const struct dsi_reg idx)
453 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
457 case DSI_PROTO: base = dsi->proto_base; break;
458 case DSI_PHY: base = dsi->phy_base; break;
459 case DSI_PLL: base = dsi->pll_base; break;
463 return __raw_readl(base + idx.idx);
466 static void dsi_bus_lock(struct omap_dss_device *dssdev)
468 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
469 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
471 down(&dsi->bus_lock);
474 static void dsi_bus_unlock(struct omap_dss_device *dssdev)
476 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
477 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
482 static bool dsi_bus_is_locked(struct platform_device *dsidev)
484 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
486 return dsi->bus_lock.count == 0;
489 static void dsi_completion_handler(void *data, u32 mask)
491 complete((struct completion *)data);
494 static inline int wait_for_bit_change(struct platform_device *dsidev,
495 const struct dsi_reg idx, int bitnum, int value)
497 unsigned long timeout;
501 /* first busyloop to see if the bit changes right away */
504 if (REG_GET(dsidev, idx, bitnum, bitnum) == value)
508 /* then loop for 500ms, sleeping for 1ms in between */
509 timeout = jiffies + msecs_to_jiffies(500);
510 while (time_before(jiffies, timeout)) {
511 if (REG_GET(dsidev, idx, bitnum, bitnum) == value)
514 wait = ns_to_ktime(1000 * 1000);
515 set_current_state(TASK_UNINTERRUPTIBLE);
516 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
522 u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
525 case OMAP_DSS_DSI_FMT_RGB888:
526 case OMAP_DSS_DSI_FMT_RGB666:
528 case OMAP_DSS_DSI_FMT_RGB666_PACKED:
530 case OMAP_DSS_DSI_FMT_RGB565:
538 #ifdef DSI_PERF_MEASURE
539 static void dsi_perf_mark_setup(struct platform_device *dsidev)
541 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
542 dsi->perf_setup_time = ktime_get();
545 static void dsi_perf_mark_start(struct platform_device *dsidev)
547 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
548 dsi->perf_start_time = ktime_get();
551 static void dsi_perf_show(struct platform_device *dsidev, const char *name)
553 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
554 ktime_t t, setup_time, trans_time;
556 u32 setup_us, trans_us, total_us;
563 setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time);
564 setup_us = (u32)ktime_to_us(setup_time);
568 trans_time = ktime_sub(t, dsi->perf_start_time);
569 trans_us = (u32)ktime_to_us(trans_time);
573 total_us = setup_us + trans_us;
575 total_bytes = dsi->update_bytes;
577 printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), "
578 "%u bytes, %u kbytes/sec\n",
583 1000*1000 / total_us,
585 total_bytes * 1000 / total_us);
588 static inline void dsi_perf_mark_setup(struct platform_device *dsidev)
592 static inline void dsi_perf_mark_start(struct platform_device *dsidev)
596 static inline void dsi_perf_show(struct platform_device *dsidev,
602 static int verbose_irq;
604 static void print_irq_status(u32 status)
609 if (!verbose_irq && (status & ~DSI_IRQ_CHANNEL_MASK) == 0)
612 #define PIS(x) (status & DSI_IRQ_##x) ? (#x " ") : ""
614 pr_debug("DSI IRQ: 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
616 verbose_irq ? PIS(VC0) : "",
617 verbose_irq ? PIS(VC1) : "",
618 verbose_irq ? PIS(VC2) : "",
619 verbose_irq ? PIS(VC3) : "",
636 static void print_irq_status_vc(int channel, u32 status)
641 if (!verbose_irq && (status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
644 #define PIS(x) (status & DSI_VC_IRQ_##x) ? (#x " ") : ""
646 pr_debug("DSI VC(%d) IRQ 0x%x: %s%s%s%s%s%s%s%s%s\n",
652 verbose_irq ? PIS(PACKET_SENT) : "",
657 PIS(PP_BUSY_CHANGE));
661 static void print_irq_status_cio(u32 status)
666 #define PIS(x) (status & DSI_CIO_IRQ_##x) ? (#x " ") : ""
668 pr_debug("DSI CIO IRQ 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
682 PIS(ERRCONTENTIONLP0_1),
683 PIS(ERRCONTENTIONLP1_1),
684 PIS(ERRCONTENTIONLP0_2),
685 PIS(ERRCONTENTIONLP1_2),
686 PIS(ERRCONTENTIONLP0_3),
687 PIS(ERRCONTENTIONLP1_3),
688 PIS(ULPSACTIVENOT_ALL0),
689 PIS(ULPSACTIVENOT_ALL1));
693 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
694 static void dsi_collect_irq_stats(struct platform_device *dsidev, u32 irqstatus,
695 u32 *vcstatus, u32 ciostatus)
697 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
700 spin_lock(&dsi->irq_stats_lock);
702 dsi->irq_stats.irq_count++;
703 dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs);
705 for (i = 0; i < 4; ++i)
706 dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]);
708 dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs);
710 spin_unlock(&dsi->irq_stats_lock);
713 #define dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus)
716 static int debug_irq;
718 static void dsi_handle_irq_errors(struct platform_device *dsidev, u32 irqstatus,
719 u32 *vcstatus, u32 ciostatus)
721 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
724 if (irqstatus & DSI_IRQ_ERROR_MASK) {
725 DSSERR("DSI error, irqstatus %x\n", irqstatus);
726 print_irq_status(irqstatus);
727 spin_lock(&dsi->errors_lock);
728 dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK;
729 spin_unlock(&dsi->errors_lock);
730 } else if (debug_irq) {
731 print_irq_status(irqstatus);
734 for (i = 0; i < 4; ++i) {
735 if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) {
736 DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
738 print_irq_status_vc(i, vcstatus[i]);
739 } else if (debug_irq) {
740 print_irq_status_vc(i, vcstatus[i]);
744 if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) {
745 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
746 print_irq_status_cio(ciostatus);
747 } else if (debug_irq) {
748 print_irq_status_cio(ciostatus);
752 static void dsi_call_isrs(struct dsi_isr_data *isr_array,
753 unsigned isr_array_size, u32 irqstatus)
755 struct dsi_isr_data *isr_data;
758 for (i = 0; i < isr_array_size; i++) {
759 isr_data = &isr_array[i];
760 if (isr_data->isr && isr_data->mask & irqstatus)
761 isr_data->isr(isr_data->arg, irqstatus);
765 static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables,
766 u32 irqstatus, u32 *vcstatus, u32 ciostatus)
770 dsi_call_isrs(isr_tables->isr_table,
771 ARRAY_SIZE(isr_tables->isr_table),
774 for (i = 0; i < 4; ++i) {
775 if (vcstatus[i] == 0)
777 dsi_call_isrs(isr_tables->isr_table_vc[i],
778 ARRAY_SIZE(isr_tables->isr_table_vc[i]),
783 dsi_call_isrs(isr_tables->isr_table_cio,
784 ARRAY_SIZE(isr_tables->isr_table_cio),
788 static irqreturn_t omap_dsi_irq_handler(int irq, void *arg)
790 struct platform_device *dsidev;
791 struct dsi_data *dsi;
792 u32 irqstatus, vcstatus[4], ciostatus;
795 dsidev = (struct platform_device *) arg;
796 dsi = dsi_get_dsidrv_data(dsidev);
798 spin_lock(&dsi->irq_lock);
800 irqstatus = dsi_read_reg(dsidev, DSI_IRQSTATUS);
802 /* IRQ is not for us */
804 spin_unlock(&dsi->irq_lock);
808 dsi_write_reg(dsidev, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
809 /* flush posted write */
810 dsi_read_reg(dsidev, DSI_IRQSTATUS);
812 for (i = 0; i < 4; ++i) {
813 if ((irqstatus & (1 << i)) == 0) {
818 vcstatus[i] = dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
820 dsi_write_reg(dsidev, DSI_VC_IRQSTATUS(i), vcstatus[i]);
821 /* flush posted write */
822 dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
825 if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
826 ciostatus = dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
828 dsi_write_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
829 /* flush posted write */
830 dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
835 #ifdef DSI_CATCH_MISSING_TE
836 if (irqstatus & DSI_IRQ_TE_TRIGGER)
837 del_timer(&dsi->te_timer);
840 /* make a copy and unlock, so that isrs can unregister
842 memcpy(&dsi->isr_tables_copy, &dsi->isr_tables,
843 sizeof(dsi->isr_tables));
845 spin_unlock(&dsi->irq_lock);
847 dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus);
849 dsi_handle_irq_errors(dsidev, irqstatus, vcstatus, ciostatus);
851 dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus);
856 /* dsi->irq_lock has to be locked by the caller */
857 static void _omap_dsi_configure_irqs(struct platform_device *dsidev,
858 struct dsi_isr_data *isr_array,
859 unsigned isr_array_size, u32 default_mask,
860 const struct dsi_reg enable_reg,
861 const struct dsi_reg status_reg)
863 struct dsi_isr_data *isr_data;
870 for (i = 0; i < isr_array_size; i++) {
871 isr_data = &isr_array[i];
873 if (isr_data->isr == NULL)
876 mask |= isr_data->mask;
879 old_mask = dsi_read_reg(dsidev, enable_reg);
880 /* clear the irqstatus for newly enabled irqs */
881 dsi_write_reg(dsidev, status_reg, (mask ^ old_mask) & mask);
882 dsi_write_reg(dsidev, enable_reg, mask);
884 /* flush posted writes */
885 dsi_read_reg(dsidev, enable_reg);
886 dsi_read_reg(dsidev, status_reg);
889 /* dsi->irq_lock has to be locked by the caller */
890 static void _omap_dsi_set_irqs(struct platform_device *dsidev)
892 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
893 u32 mask = DSI_IRQ_ERROR_MASK;
894 #ifdef DSI_CATCH_MISSING_TE
895 mask |= DSI_IRQ_TE_TRIGGER;
897 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table,
898 ARRAY_SIZE(dsi->isr_tables.isr_table), mask,
899 DSI_IRQENABLE, DSI_IRQSTATUS);
902 /* dsi->irq_lock has to be locked by the caller */
903 static void _omap_dsi_set_irqs_vc(struct platform_device *dsidev, int vc)
905 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
907 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_vc[vc],
908 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]),
909 DSI_VC_IRQ_ERROR_MASK,
910 DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc));
913 /* dsi->irq_lock has to be locked by the caller */
914 static void _omap_dsi_set_irqs_cio(struct platform_device *dsidev)
916 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
918 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_cio,
919 ARRAY_SIZE(dsi->isr_tables.isr_table_cio),
920 DSI_CIO_IRQ_ERROR_MASK,
921 DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS);
924 static void _dsi_initialize_irq(struct platform_device *dsidev)
926 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
930 spin_lock_irqsave(&dsi->irq_lock, flags);
932 memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables));
934 _omap_dsi_set_irqs(dsidev);
935 for (vc = 0; vc < 4; ++vc)
936 _omap_dsi_set_irqs_vc(dsidev, vc);
937 _omap_dsi_set_irqs_cio(dsidev);
939 spin_unlock_irqrestore(&dsi->irq_lock, flags);
942 static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
943 struct dsi_isr_data *isr_array, unsigned isr_array_size)
945 struct dsi_isr_data *isr_data;
951 /* check for duplicate entry and find a free slot */
953 for (i = 0; i < isr_array_size; i++) {
954 isr_data = &isr_array[i];
956 if (isr_data->isr == isr && isr_data->arg == arg &&
957 isr_data->mask == mask) {
961 if (isr_data->isr == NULL && free_idx == -1)
968 isr_data = &isr_array[free_idx];
971 isr_data->mask = mask;
976 static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
977 struct dsi_isr_data *isr_array, unsigned isr_array_size)
979 struct dsi_isr_data *isr_data;
982 for (i = 0; i < isr_array_size; i++) {
983 isr_data = &isr_array[i];
984 if (isr_data->isr != isr || isr_data->arg != arg ||
985 isr_data->mask != mask)
988 isr_data->isr = NULL;
989 isr_data->arg = NULL;
998 static int dsi_register_isr(struct platform_device *dsidev, omap_dsi_isr_t isr,
1001 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1002 unsigned long flags;
1005 spin_lock_irqsave(&dsi->irq_lock, flags);
1007 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table,
1008 ARRAY_SIZE(dsi->isr_tables.isr_table));
1011 _omap_dsi_set_irqs(dsidev);
1013 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1018 static int dsi_unregister_isr(struct platform_device *dsidev,
1019 omap_dsi_isr_t isr, void *arg, u32 mask)
1021 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1022 unsigned long flags;
1025 spin_lock_irqsave(&dsi->irq_lock, flags);
1027 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table,
1028 ARRAY_SIZE(dsi->isr_tables.isr_table));
1031 _omap_dsi_set_irqs(dsidev);
1033 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1038 static int dsi_register_isr_vc(struct platform_device *dsidev, int channel,
1039 omap_dsi_isr_t isr, void *arg, u32 mask)
1041 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1042 unsigned long flags;
1045 spin_lock_irqsave(&dsi->irq_lock, flags);
1047 r = _dsi_register_isr(isr, arg, mask,
1048 dsi->isr_tables.isr_table_vc[channel],
1049 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
1052 _omap_dsi_set_irqs_vc(dsidev, channel);
1054 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1059 static int dsi_unregister_isr_vc(struct platform_device *dsidev, int channel,
1060 omap_dsi_isr_t isr, void *arg, u32 mask)
1062 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1063 unsigned long flags;
1066 spin_lock_irqsave(&dsi->irq_lock, flags);
1068 r = _dsi_unregister_isr(isr, arg, mask,
1069 dsi->isr_tables.isr_table_vc[channel],
1070 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
1073 _omap_dsi_set_irqs_vc(dsidev, channel);
1075 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1080 static int dsi_register_isr_cio(struct platform_device *dsidev,
1081 omap_dsi_isr_t isr, void *arg, u32 mask)
1083 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1084 unsigned long flags;
1087 spin_lock_irqsave(&dsi->irq_lock, flags);
1089 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1090 ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1093 _omap_dsi_set_irqs_cio(dsidev);
1095 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1100 static int dsi_unregister_isr_cio(struct platform_device *dsidev,
1101 omap_dsi_isr_t isr, void *arg, u32 mask)
1103 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1104 unsigned long flags;
1107 spin_lock_irqsave(&dsi->irq_lock, flags);
1109 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1110 ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1113 _omap_dsi_set_irqs_cio(dsidev);
1115 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1120 static u32 dsi_get_errors(struct platform_device *dsidev)
1122 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1123 unsigned long flags;
1125 spin_lock_irqsave(&dsi->errors_lock, flags);
1128 spin_unlock_irqrestore(&dsi->errors_lock, flags);
1132 int dsi_runtime_get(struct platform_device *dsidev)
1135 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1137 DSSDBG("dsi_runtime_get\n");
1139 r = pm_runtime_get_sync(&dsi->pdev->dev);
1141 return r < 0 ? r : 0;
1144 void dsi_runtime_put(struct platform_device *dsidev)
1146 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1149 DSSDBG("dsi_runtime_put\n");
1151 r = pm_runtime_put_sync(&dsi->pdev->dev);
1152 WARN_ON(r < 0 && r != -ENOSYS);
1155 static int dsi_regulator_init(struct platform_device *dsidev)
1157 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1158 struct regulator *vdds_dsi;
1160 if (dsi->vdds_dsi_reg != NULL)
1163 vdds_dsi = devm_regulator_get(&dsi->pdev->dev, "vdd");
1165 if (IS_ERR(vdds_dsi)) {
1166 if (PTR_ERR(vdds_dsi) != -EPROBE_DEFER)
1167 DSSERR("can't get DSI VDD regulator\n");
1168 return PTR_ERR(vdds_dsi);
1171 dsi->vdds_dsi_reg = vdds_dsi;
1176 /* source clock for DSI PLL. this could also be PCLKFREE */
1177 static inline void dsi_enable_pll_clock(struct platform_device *dsidev,
1180 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1183 clk_prepare_enable(dsi->sys_clk);
1185 clk_disable_unprepare(dsi->sys_clk);
1187 if (enable && dsi->pll_locked) {
1188 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1)
1189 DSSERR("cannot lock PLL when enabling clocks\n");
1193 static void _dsi_print_reset_status(struct platform_device *dsidev)
1198 /* A dummy read using the SCP interface to any DSIPHY register is
1199 * required after DSIPHY reset to complete the reset of the DSI complex
1201 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
1203 if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) {
1213 #define DSI_FLD_GET(fld, start, end)\
1214 FLD_GET(dsi_read_reg(dsidev, DSI_##fld), start, end)
1216 pr_debug("DSI resets: PLL (%d) CIO (%d) PHY (%x%x%x, %d, %d, %d)\n",
1217 DSI_FLD_GET(PLL_STATUS, 0, 0),
1218 DSI_FLD_GET(COMPLEXIO_CFG1, 29, 29),
1219 DSI_FLD_GET(DSIPHY_CFG5, b0, b0),
1220 DSI_FLD_GET(DSIPHY_CFG5, b1, b1),
1221 DSI_FLD_GET(DSIPHY_CFG5, b2, b2),
1222 DSI_FLD_GET(DSIPHY_CFG5, 29, 29),
1223 DSI_FLD_GET(DSIPHY_CFG5, 30, 30),
1224 DSI_FLD_GET(DSIPHY_CFG5, 31, 31));
1229 static inline int dsi_if_enable(struct platform_device *dsidev, bool enable)
1231 DSSDBG("dsi_if_enable(%d)\n", enable);
1233 enable = enable ? 1 : 0;
1234 REG_FLD_MOD(dsidev, DSI_CTRL, enable, 0, 0); /* IF_EN */
1236 if (wait_for_bit_change(dsidev, DSI_CTRL, 0, enable) != enable) {
1237 DSSERR("Failed to set dsi_if_enable to %d\n", enable);
1244 unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
1246 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1248 return dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk;
1251 static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct platform_device *dsidev)
1253 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1255 return dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk;
1258 static unsigned long dsi_get_txbyteclkhs(struct platform_device *dsidev)
1260 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1262 return dsi->current_cinfo.clkin4ddr / 16;
1265 static unsigned long dsi_fclk_rate(struct platform_device *dsidev)
1268 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1270 if (dss_get_dsi_clk_source(dsi->module_id) == OMAP_DSS_CLK_SRC_FCK) {
1271 /* DSI FCLK source is DSS_CLK_FCK */
1272 r = clk_get_rate(dsi->dss_clk);
1274 /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */
1275 r = dsi_get_pll_hsdiv_dsi_rate(dsidev);
1281 static int dsi_lp_clock_calc(struct dsi_clock_info *cinfo,
1282 unsigned long lp_clk_min, unsigned long lp_clk_max)
1284 unsigned long dsi_fclk = cinfo->dsi_pll_hsdiv_dsi_clk;
1285 unsigned lp_clk_div;
1286 unsigned long lp_clk;
1288 lp_clk_div = DIV_ROUND_UP(dsi_fclk, lp_clk_max * 2);
1289 lp_clk = dsi_fclk / 2 / lp_clk_div;
1291 if (lp_clk < lp_clk_min || lp_clk > lp_clk_max)
1294 cinfo->lp_clk_div = lp_clk_div;
1295 cinfo->lp_clk = lp_clk;
1300 static int dsi_set_lp_clk_divisor(struct platform_device *dsidev)
1302 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1303 unsigned long dsi_fclk;
1304 unsigned lp_clk_div;
1305 unsigned long lp_clk;
1307 lp_clk_div = dsi->user_dsi_cinfo.lp_clk_div;
1309 if (lp_clk_div == 0 || lp_clk_div > dsi->lpdiv_max)
1312 dsi_fclk = dsi_fclk_rate(dsidev);
1314 lp_clk = dsi_fclk / 2 / lp_clk_div;
1316 DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
1317 dsi->current_cinfo.lp_clk = lp_clk;
1318 dsi->current_cinfo.lp_clk_div = lp_clk_div;
1320 /* LP_CLK_DIVISOR */
1321 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0);
1323 /* LP_RX_SYNCHRO_ENABLE */
1324 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21);
1329 static void dsi_enable_scp_clk(struct platform_device *dsidev)
1331 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1333 if (dsi->scp_clk_refcount++ == 0)
1334 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */
1337 static void dsi_disable_scp_clk(struct platform_device *dsidev)
1339 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1341 WARN_ON(dsi->scp_clk_refcount == 0);
1342 if (--dsi->scp_clk_refcount == 0)
1343 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */
1346 enum dsi_pll_power_state {
1347 DSI_PLL_POWER_OFF = 0x0,
1348 DSI_PLL_POWER_ON_HSCLK = 0x1,
1349 DSI_PLL_POWER_ON_ALL = 0x2,
1350 DSI_PLL_POWER_ON_DIV = 0x3,
1353 static int dsi_pll_power(struct platform_device *dsidev,
1354 enum dsi_pll_power_state state)
1358 /* DSI-PLL power command 0x3 is not working */
1359 if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG) &&
1360 state == DSI_PLL_POWER_ON_DIV)
1361 state = DSI_PLL_POWER_ON_ALL;
1364 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30);
1366 /* PLL_PWR_STATUS */
1367 while (FLD_GET(dsi_read_reg(dsidev, DSI_CLK_CTRL), 29, 28) != state) {
1369 DSSERR("Failed to set DSI PLL power mode to %d\n",
1379 unsigned long dsi_get_pll_clkin(struct platform_device *dsidev)
1381 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1382 return clk_get_rate(dsi->sys_clk);
1385 bool dsi_hsdiv_calc(struct platform_device *dsidev, unsigned long pll,
1386 unsigned long out_min, dsi_hsdiv_calc_func func, void *data)
1388 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1389 int regm, regm_start, regm_stop;
1390 unsigned long out_max;
1393 out_min = out_min ? out_min : 1;
1394 out_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
1396 regm_start = max(DIV_ROUND_UP(pll, out_max), 1ul);
1397 regm_stop = min(pll / out_min, dsi->regm_dispc_max);
1399 for (regm = regm_start; regm <= regm_stop; ++regm) {
1402 if (func(regm, out, data))
1409 bool dsi_pll_calc(struct platform_device *dsidev, unsigned long clkin,
1410 unsigned long pll_min, unsigned long pll_max,
1411 dsi_pll_calc_func func, void *data)
1413 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1414 int regn, regn_start, regn_stop;
1415 int regm, regm_start, regm_stop;
1416 unsigned long fint, pll;
1417 const unsigned long pll_hw_max = 1800000000;
1418 unsigned long fint_hw_min, fint_hw_max;
1420 fint_hw_min = dsi->fint_min;
1421 fint_hw_max = dsi->fint_max;
1423 regn_start = max(DIV_ROUND_UP(clkin, fint_hw_max), 1ul);
1424 regn_stop = min(clkin / fint_hw_min, dsi->regn_max);
1426 pll_max = pll_max ? pll_max : ULONG_MAX;
1428 for (regn = regn_start; regn <= regn_stop; ++regn) {
1429 fint = clkin / regn;
1431 regm_start = max(DIV_ROUND_UP(DIV_ROUND_UP(pll_min, fint), 2),
1433 regm_stop = min3(pll_max / fint / 2,
1434 pll_hw_max / fint / 2,
1437 for (regm = regm_start; regm <= regm_stop; ++regm) {
1438 pll = 2 * regm * fint;
1440 if (func(regn, regm, fint, pll, data))
1448 /* calculate clock rates using dividers in cinfo */
1449 static int dsi_calc_clock_rates(struct platform_device *dsidev,
1450 struct dsi_clock_info *cinfo)
1452 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1454 if (cinfo->regn == 0 || cinfo->regn > dsi->regn_max)
1457 if (cinfo->regm == 0 || cinfo->regm > dsi->regm_max)
1460 if (cinfo->regm_dispc > dsi->regm_dispc_max)
1463 if (cinfo->regm_dsi > dsi->regm_dsi_max)
1466 cinfo->clkin = clk_get_rate(dsi->sys_clk);
1467 cinfo->fint = cinfo->clkin / cinfo->regn;
1469 if (cinfo->fint > dsi->fint_max || cinfo->fint < dsi->fint_min)
1472 cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint;
1474 if (cinfo->clkin4ddr > 1800 * 1000 * 1000)
1477 if (cinfo->regm_dispc > 0)
1478 cinfo->dsi_pll_hsdiv_dispc_clk =
1479 cinfo->clkin4ddr / cinfo->regm_dispc;
1481 cinfo->dsi_pll_hsdiv_dispc_clk = 0;
1483 if (cinfo->regm_dsi > 0)
1484 cinfo->dsi_pll_hsdiv_dsi_clk =
1485 cinfo->clkin4ddr / cinfo->regm_dsi;
1487 cinfo->dsi_pll_hsdiv_dsi_clk = 0;
1492 static void dsi_pll_calc_dsi_fck(struct dsi_clock_info *cinfo)
1494 unsigned long max_dsi_fck;
1496 max_dsi_fck = dss_feat_get_param_max(FEAT_PARAM_DSI_FCK);
1498 cinfo->regm_dsi = DIV_ROUND_UP(cinfo->clkin4ddr, max_dsi_fck);
1499 cinfo->dsi_pll_hsdiv_dsi_clk = cinfo->clkin4ddr / cinfo->regm_dsi;
1502 int dsi_pll_set_clock_div(struct platform_device *dsidev,
1503 struct dsi_clock_info *cinfo)
1505 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1509 u8 regn_start, regn_end, regm_start, regm_end;
1510 u8 regm_dispc_start, regm_dispc_end, regm_dsi_start, regm_dsi_end;
1512 DSSDBG("DSI PLL clock config starts");
1514 dsi->current_cinfo.clkin = cinfo->clkin;
1515 dsi->current_cinfo.fint = cinfo->fint;
1516 dsi->current_cinfo.clkin4ddr = cinfo->clkin4ddr;
1517 dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk =
1518 cinfo->dsi_pll_hsdiv_dispc_clk;
1519 dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk =
1520 cinfo->dsi_pll_hsdiv_dsi_clk;
1522 dsi->current_cinfo.regn = cinfo->regn;
1523 dsi->current_cinfo.regm = cinfo->regm;
1524 dsi->current_cinfo.regm_dispc = cinfo->regm_dispc;
1525 dsi->current_cinfo.regm_dsi = cinfo->regm_dsi;
1527 DSSDBG("DSI Fint %ld\n", cinfo->fint);
1529 DSSDBG("clkin rate %ld\n", cinfo->clkin);
1531 /* DSIPHY == CLKIN4DDR */
1532 DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu = %lu\n",
1538 DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
1539 cinfo->clkin4ddr / 1000 / 1000 / 2);
1541 DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4);
1543 DSSDBG("regm_dispc = %d, %s (%s) = %lu\n", cinfo->regm_dispc,
1544 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1545 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1546 cinfo->dsi_pll_hsdiv_dispc_clk);
1547 DSSDBG("regm_dsi = %d, %s (%s) = %lu\n", cinfo->regm_dsi,
1548 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1549 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1550 cinfo->dsi_pll_hsdiv_dsi_clk);
1552 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGN, ®n_start, ®n_end);
1553 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM, ®m_start, ®m_end);
1554 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DISPC, ®m_dispc_start,
1556 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DSI, ®m_dsi_start,
1559 /* DSI_PLL_AUTOMODE = manual */
1560 REG_FLD_MOD(dsidev, DSI_PLL_CONTROL, 0, 0, 0);
1562 l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION1);
1563 l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */
1565 l = FLD_MOD(l, cinfo->regn - 1, regn_start, regn_end);
1567 l = FLD_MOD(l, cinfo->regm, regm_start, regm_end);
1569 l = FLD_MOD(l, cinfo->regm_dispc > 0 ? cinfo->regm_dispc - 1 : 0,
1570 regm_dispc_start, regm_dispc_end);
1571 /* DSIPROTO_CLOCK_DIV */
1572 l = FLD_MOD(l, cinfo->regm_dsi > 0 ? cinfo->regm_dsi - 1 : 0,
1573 regm_dsi_start, regm_dsi_end);
1574 dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION1, l);
1576 BUG_ON(cinfo->fint < dsi->fint_min || cinfo->fint > dsi->fint_max);
1578 l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
1580 if (dss_has_feature(FEAT_DSI_PLL_FREQSEL)) {
1581 f = cinfo->fint < 1000000 ? 0x3 :
1582 cinfo->fint < 1250000 ? 0x4 :
1583 cinfo->fint < 1500000 ? 0x5 :
1584 cinfo->fint < 1750000 ? 0x6 :
1587 l = FLD_MOD(l, f, 4, 1); /* DSI_PLL_FREQSEL */
1588 } else if (dss_has_feature(FEAT_DSI_PLL_SELFREQDCO)) {
1589 f = cinfo->clkin4ddr < 1000000000 ? 0x2 : 0x4;
1591 l = FLD_MOD(l, f, 4, 1); /* PLL_SELFREQDCO */
1594 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1595 l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */
1596 l = FLD_MOD(l, 1, 20, 20); /* DSI_HSDIVBYPASS */
1597 if (dss_has_feature(FEAT_DSI_PLL_REFSEL))
1598 l = FLD_MOD(l, 3, 22, 21); /* REF_SYSCLK = sysclk */
1599 dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
1601 REG_FLD_MOD(dsidev, DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */
1603 if (wait_for_bit_change(dsidev, DSI_PLL_GO, 0, 0) != 0) {
1604 DSSERR("dsi pll go bit not going down.\n");
1609 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1) {
1610 DSSERR("cannot lock PLL\n");
1615 dsi->pll_locked = 1;
1617 l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
1618 l = FLD_MOD(l, 0, 0, 0); /* DSI_PLL_IDLE */
1619 l = FLD_MOD(l, 0, 5, 5); /* DSI_PLL_PLLLPMODE */
1620 l = FLD_MOD(l, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */
1621 l = FLD_MOD(l, 0, 7, 7); /* DSI_PLL_TIGHTPHASELOCK */
1622 l = FLD_MOD(l, 0, 8, 8); /* DSI_PLL_DRIFTGUARDEN */
1623 l = FLD_MOD(l, 0, 10, 9); /* DSI_PLL_LOCKSEL */
1624 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1625 l = FLD_MOD(l, 1, 14, 14); /* DSIPHY_CLKINEN */
1626 l = FLD_MOD(l, 0, 15, 15); /* DSI_BYPASSEN */
1627 l = FLD_MOD(l, 1, 16, 16); /* DSS_CLOCK_EN */
1628 l = FLD_MOD(l, 0, 17, 17); /* DSS_CLOCK_PWDN */
1629 l = FLD_MOD(l, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */
1630 l = FLD_MOD(l, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */
1631 l = FLD_MOD(l, 0, 20, 20); /* DSI_HSDIVBYPASS */
1632 dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
1634 DSSDBG("PLL config done\n");
1639 int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk,
1642 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1644 enum dsi_pll_power_state pwstate;
1646 DSSDBG("PLL init\n");
1649 * It seems that on many OMAPs we need to enable both to have a
1650 * functional HSDivider.
1652 enable_hsclk = enable_hsdiv = true;
1654 r = dsi_regulator_init(dsidev);
1658 dsi_enable_pll_clock(dsidev, 1);
1660 * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4.
1662 dsi_enable_scp_clk(dsidev);
1664 if (!dsi->vdds_dsi_enabled) {
1665 r = regulator_enable(dsi->vdds_dsi_reg);
1668 dsi->vdds_dsi_enabled = true;
1671 /* XXX PLL does not come out of reset without this... */
1672 dispc_pck_free_enable(1);
1674 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 0, 1) != 1) {
1675 DSSERR("PLL not coming out of reset.\n");
1677 dispc_pck_free_enable(0);
1681 /* XXX ... but if left on, we get problems when planes do not
1682 * fill the whole display. No idea about this */
1683 dispc_pck_free_enable(0);
1685 if (enable_hsclk && enable_hsdiv)
1686 pwstate = DSI_PLL_POWER_ON_ALL;
1687 else if (enable_hsclk)
1688 pwstate = DSI_PLL_POWER_ON_HSCLK;
1689 else if (enable_hsdiv)
1690 pwstate = DSI_PLL_POWER_ON_DIV;
1692 pwstate = DSI_PLL_POWER_OFF;
1694 r = dsi_pll_power(dsidev, pwstate);
1699 DSSDBG("PLL init done\n");
1703 if (dsi->vdds_dsi_enabled) {
1704 regulator_disable(dsi->vdds_dsi_reg);
1705 dsi->vdds_dsi_enabled = false;
1708 dsi_disable_scp_clk(dsidev);
1709 dsi_enable_pll_clock(dsidev, 0);
1713 void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes)
1715 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1717 dsi->pll_locked = 0;
1718 dsi_pll_power(dsidev, DSI_PLL_POWER_OFF);
1719 if (disconnect_lanes) {
1720 WARN_ON(!dsi->vdds_dsi_enabled);
1721 regulator_disable(dsi->vdds_dsi_reg);
1722 dsi->vdds_dsi_enabled = false;
1725 dsi_disable_scp_clk(dsidev);
1726 dsi_enable_pll_clock(dsidev, 0);
1728 DSSDBG("PLL uninit done\n");
1731 static void dsi_dump_dsidev_clocks(struct platform_device *dsidev,
1734 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1735 struct dsi_clock_info *cinfo = &dsi->current_cinfo;
1736 enum omap_dss_clk_source dispc_clk_src, dsi_clk_src;
1737 int dsi_module = dsi->module_id;
1739 dispc_clk_src = dss_get_dispc_clk_source();
1740 dsi_clk_src = dss_get_dsi_clk_source(dsi_module);
1742 if (dsi_runtime_get(dsidev))
1745 seq_printf(s, "- DSI%d PLL -\n", dsi_module + 1);
1747 seq_printf(s, "dsi pll clkin\t%lu\n", cinfo->clkin);
1749 seq_printf(s, "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn);
1751 seq_printf(s, "CLKIN4DDR\t%-16luregm %u\n",
1752 cinfo->clkin4ddr, cinfo->regm);
1754 seq_printf(s, "DSI_PLL_HSDIV_DISPC (%s)\t%-16luregm_dispc %u\t(%s)\n",
1755 dss_feat_get_clk_source_name(dsi_module == 0 ?
1756 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC :
1757 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC),
1758 cinfo->dsi_pll_hsdiv_dispc_clk,
1760 dispc_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1763 seq_printf(s, "DSI_PLL_HSDIV_DSI (%s)\t%-16luregm_dsi %u\t(%s)\n",
1764 dss_feat_get_clk_source_name(dsi_module == 0 ?
1765 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI :
1766 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI),
1767 cinfo->dsi_pll_hsdiv_dsi_clk,
1769 dsi_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1772 seq_printf(s, "- DSI%d -\n", dsi_module + 1);
1774 seq_printf(s, "dsi fclk source = %s (%s)\n",
1775 dss_get_generic_clk_source_name(dsi_clk_src),
1776 dss_feat_get_clk_source_name(dsi_clk_src));
1778 seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsidev));
1780 seq_printf(s, "DDR_CLK\t\t%lu\n",
1781 cinfo->clkin4ddr / 4);
1783 seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsidev));
1785 seq_printf(s, "LP_CLK\t\t%lu\n", cinfo->lp_clk);
1787 dsi_runtime_put(dsidev);
1790 void dsi_dump_clocks(struct seq_file *s)
1792 struct platform_device *dsidev;
1795 for (i = 0; i < MAX_NUM_DSI; i++) {
1796 dsidev = dsi_get_dsidev_from_id(i);
1798 dsi_dump_dsidev_clocks(dsidev, s);
1802 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
1803 static void dsi_dump_dsidev_irqs(struct platform_device *dsidev,
1806 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1807 unsigned long flags;
1808 struct dsi_irq_stats stats;
1810 spin_lock_irqsave(&dsi->irq_stats_lock, flags);
1812 stats = dsi->irq_stats;
1813 memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats));
1814 dsi->irq_stats.last_reset = jiffies;
1816 spin_unlock_irqrestore(&dsi->irq_stats_lock, flags);
1818 seq_printf(s, "period %u ms\n",
1819 jiffies_to_msecs(jiffies - stats.last_reset));
1821 seq_printf(s, "irqs %d\n", stats.irq_count);
1823 seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);
1825 seq_printf(s, "-- DSI%d interrupts --\n", dsi->module_id + 1);
1841 PIS(LDO_POWER_GOOD);
1846 seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
1847 stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
1848 stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
1849 stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
1850 stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
1852 seq_printf(s, "-- VC interrupts --\n");
1861 PIS(PP_BUSY_CHANGE);
1865 seq_printf(s, "%-20s %10d\n", #x, \
1866 stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
1868 seq_printf(s, "-- CIO interrupts --\n");
1881 PIS(ERRCONTENTIONLP0_1);
1882 PIS(ERRCONTENTIONLP1_1);
1883 PIS(ERRCONTENTIONLP0_2);
1884 PIS(ERRCONTENTIONLP1_2);
1885 PIS(ERRCONTENTIONLP0_3);
1886 PIS(ERRCONTENTIONLP1_3);
1887 PIS(ULPSACTIVENOT_ALL0);
1888 PIS(ULPSACTIVENOT_ALL1);
1892 static void dsi1_dump_irqs(struct seq_file *s)
1894 struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
1896 dsi_dump_dsidev_irqs(dsidev, s);
1899 static void dsi2_dump_irqs(struct seq_file *s)
1901 struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
1903 dsi_dump_dsidev_irqs(dsidev, s);
1907 static void dsi_dump_dsidev_regs(struct platform_device *dsidev,
1910 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r))
1912 if (dsi_runtime_get(dsidev))
1914 dsi_enable_scp_clk(dsidev);
1916 DUMPREG(DSI_REVISION);
1917 DUMPREG(DSI_SYSCONFIG);
1918 DUMPREG(DSI_SYSSTATUS);
1919 DUMPREG(DSI_IRQSTATUS);
1920 DUMPREG(DSI_IRQENABLE);
1922 DUMPREG(DSI_COMPLEXIO_CFG1);
1923 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
1924 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
1925 DUMPREG(DSI_CLK_CTRL);
1926 DUMPREG(DSI_TIMING1);
1927 DUMPREG(DSI_TIMING2);
1928 DUMPREG(DSI_VM_TIMING1);
1929 DUMPREG(DSI_VM_TIMING2);
1930 DUMPREG(DSI_VM_TIMING3);
1931 DUMPREG(DSI_CLK_TIMING);
1932 DUMPREG(DSI_TX_FIFO_VC_SIZE);
1933 DUMPREG(DSI_RX_FIFO_VC_SIZE);
1934 DUMPREG(DSI_COMPLEXIO_CFG2);
1935 DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
1936 DUMPREG(DSI_VM_TIMING4);
1937 DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
1938 DUMPREG(DSI_VM_TIMING5);
1939 DUMPREG(DSI_VM_TIMING6);
1940 DUMPREG(DSI_VM_TIMING7);
1941 DUMPREG(DSI_STOPCLK_TIMING);
1943 DUMPREG(DSI_VC_CTRL(0));
1944 DUMPREG(DSI_VC_TE(0));
1945 DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
1946 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
1947 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
1948 DUMPREG(DSI_VC_IRQSTATUS(0));
1949 DUMPREG(DSI_VC_IRQENABLE(0));
1951 DUMPREG(DSI_VC_CTRL(1));
1952 DUMPREG(DSI_VC_TE(1));
1953 DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
1954 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
1955 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
1956 DUMPREG(DSI_VC_IRQSTATUS(1));
1957 DUMPREG(DSI_VC_IRQENABLE(1));
1959 DUMPREG(DSI_VC_CTRL(2));
1960 DUMPREG(DSI_VC_TE(2));
1961 DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
1962 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
1963 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
1964 DUMPREG(DSI_VC_IRQSTATUS(2));
1965 DUMPREG(DSI_VC_IRQENABLE(2));
1967 DUMPREG(DSI_VC_CTRL(3));
1968 DUMPREG(DSI_VC_TE(3));
1969 DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
1970 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
1971 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
1972 DUMPREG(DSI_VC_IRQSTATUS(3));
1973 DUMPREG(DSI_VC_IRQENABLE(3));
1975 DUMPREG(DSI_DSIPHY_CFG0);
1976 DUMPREG(DSI_DSIPHY_CFG1);
1977 DUMPREG(DSI_DSIPHY_CFG2);
1978 DUMPREG(DSI_DSIPHY_CFG5);
1980 DUMPREG(DSI_PLL_CONTROL);
1981 DUMPREG(DSI_PLL_STATUS);
1982 DUMPREG(DSI_PLL_GO);
1983 DUMPREG(DSI_PLL_CONFIGURATION1);
1984 DUMPREG(DSI_PLL_CONFIGURATION2);
1986 dsi_disable_scp_clk(dsidev);
1987 dsi_runtime_put(dsidev);
1991 static void dsi1_dump_regs(struct seq_file *s)
1993 struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
1995 dsi_dump_dsidev_regs(dsidev, s);
1998 static void dsi2_dump_regs(struct seq_file *s)
2000 struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
2002 dsi_dump_dsidev_regs(dsidev, s);
2005 enum dsi_cio_power_state {
2006 DSI_COMPLEXIO_POWER_OFF = 0x0,
2007 DSI_COMPLEXIO_POWER_ON = 0x1,
2008 DSI_COMPLEXIO_POWER_ULPS = 0x2,
2011 static int dsi_cio_power(struct platform_device *dsidev,
2012 enum dsi_cio_power_state state)
2017 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG1, state, 28, 27);
2020 while (FLD_GET(dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1),
2023 DSSERR("failed to set complexio power state to "
2033 static unsigned dsi_get_line_buf_size(struct platform_device *dsidev)
2037 /* line buffer on OMAP3 is 1024 x 24bits */
2038 /* XXX: for some reason using full buffer size causes
2039 * considerable TX slowdown with update sizes that fill the
2041 if (!dss_has_feature(FEAT_DSI_GNQ))
2044 val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */
2048 return 512 * 3; /* 512x24 bits */
2050 return 682 * 3; /* 682x24 bits */
2052 return 853 * 3; /* 853x24 bits */
2054 return 1024 * 3; /* 1024x24 bits */
2056 return 1194 * 3; /* 1194x24 bits */
2058 return 1365 * 3; /* 1365x24 bits */
2060 return 1920 * 3; /* 1920x24 bits */
2067 static int dsi_set_lane_config(struct platform_device *dsidev)
2069 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2070 static const u8 offsets[] = { 0, 4, 8, 12, 16 };
2071 static const enum dsi_lane_function functions[] = {
2081 r = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
2083 for (i = 0; i < dsi->num_lanes_used; ++i) {
2084 unsigned offset = offsets[i];
2085 unsigned polarity, lane_number;
2088 for (t = 0; t < dsi->num_lanes_supported; ++t)
2089 if (dsi->lanes[t].function == functions[i])
2092 if (t == dsi->num_lanes_supported)
2096 polarity = dsi->lanes[t].polarity;
2098 r = FLD_MOD(r, lane_number + 1, offset + 2, offset);
2099 r = FLD_MOD(r, polarity, offset + 3, offset + 3);
2102 /* clear the unused lanes */
2103 for (; i < dsi->num_lanes_supported; ++i) {
2104 unsigned offset = offsets[i];
2106 r = FLD_MOD(r, 0, offset + 2, offset);
2107 r = FLD_MOD(r, 0, offset + 3, offset + 3);
2110 dsi_write_reg(dsidev, DSI_COMPLEXIO_CFG1, r);
2115 static inline unsigned ns2ddr(struct platform_device *dsidev, unsigned ns)
2117 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2119 /* convert time in ns to ddr ticks, rounding up */
2120 unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
2121 return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
2124 static inline unsigned ddr2ns(struct platform_device *dsidev, unsigned ddr)
2126 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2128 unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
2129 return ddr * 1000 * 1000 / (ddr_clk / 1000);
2132 static void dsi_cio_timings(struct platform_device *dsidev)
2135 u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
2136 u32 tlpx_half, tclk_trail, tclk_zero;
2139 /* calculate timings */
2141 /* 1 * DDR_CLK = 2 * UI */
2143 /* min 40ns + 4*UI max 85ns + 6*UI */
2144 ths_prepare = ns2ddr(dsidev, 70) + 2;
2146 /* min 145ns + 10*UI */
2147 ths_prepare_ths_zero = ns2ddr(dsidev, 175) + 2;
2149 /* min max(8*UI, 60ns+4*UI) */
2150 ths_trail = ns2ddr(dsidev, 60) + 5;
2153 ths_exit = ns2ddr(dsidev, 145);
2156 tlpx_half = ns2ddr(dsidev, 25);
2159 tclk_trail = ns2ddr(dsidev, 60) + 2;
2161 /* min 38ns, max 95ns */
2162 tclk_prepare = ns2ddr(dsidev, 65);
2164 /* min tclk-prepare + tclk-zero = 300ns */
2165 tclk_zero = ns2ddr(dsidev, 260);
2167 DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
2168 ths_prepare, ddr2ns(dsidev, ths_prepare),
2169 ths_prepare_ths_zero, ddr2ns(dsidev, ths_prepare_ths_zero));
2170 DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
2171 ths_trail, ddr2ns(dsidev, ths_trail),
2172 ths_exit, ddr2ns(dsidev, ths_exit));
2174 DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
2175 "tclk_zero %u (%uns)\n",
2176 tlpx_half, ddr2ns(dsidev, tlpx_half),
2177 tclk_trail, ddr2ns(dsidev, tclk_trail),
2178 tclk_zero, ddr2ns(dsidev, tclk_zero));
2179 DSSDBG("tclk_prepare %u (%uns)\n",
2180 tclk_prepare, ddr2ns(dsidev, tclk_prepare));
2182 /* program timings */
2184 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
2185 r = FLD_MOD(r, ths_prepare, 31, 24);
2186 r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
2187 r = FLD_MOD(r, ths_trail, 15, 8);
2188 r = FLD_MOD(r, ths_exit, 7, 0);
2189 dsi_write_reg(dsidev, DSI_DSIPHY_CFG0, r);
2191 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
2192 r = FLD_MOD(r, tlpx_half, 20, 16);
2193 r = FLD_MOD(r, tclk_trail, 15, 8);
2194 r = FLD_MOD(r, tclk_zero, 7, 0);
2196 if (dss_has_feature(FEAT_DSI_PHY_DCC)) {
2197 r = FLD_MOD(r, 0, 21, 21); /* DCCEN = disable */
2198 r = FLD_MOD(r, 1, 22, 22); /* CLKINP_DIVBY2EN = enable */
2199 r = FLD_MOD(r, 1, 23, 23); /* CLKINP_SEL = enable */
2202 dsi_write_reg(dsidev, DSI_DSIPHY_CFG1, r);
2204 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
2205 r = FLD_MOD(r, tclk_prepare, 7, 0);
2206 dsi_write_reg(dsidev, DSI_DSIPHY_CFG2, r);
2209 /* lane masks have lane 0 at lsb. mask_p for positive lines, n for negative */
2210 static void dsi_cio_enable_lane_override(struct platform_device *dsidev,
2211 unsigned mask_p, unsigned mask_n)
2213 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2216 u8 lptxscp_start = dsi->num_lanes_supported == 3 ? 22 : 26;
2220 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2221 unsigned p = dsi->lanes[i].polarity;
2223 if (mask_p & (1 << i))
2224 l |= 1 << (i * 2 + (p ? 0 : 1));
2226 if (mask_n & (1 << i))
2227 l |= 1 << (i * 2 + (p ? 1 : 0));
2231 * Bits in REGLPTXSCPDAT4TO0DXDY:
2239 /* Set the lane override configuration */
2241 /* REGLPTXSCPDAT4TO0DXDY */
2242 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, l, lptxscp_start, 17);
2244 /* Enable lane override */
2247 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 1, 27, 27);
2250 static void dsi_cio_disable_lane_override(struct platform_device *dsidev)
2252 /* Disable lane override */
2253 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */
2254 /* Reset the lane override configuration */
2255 /* REGLPTXSCPDAT4TO0DXDY */
2256 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 22, 17);
2259 static int dsi_cio_wait_tx_clk_esc_reset(struct platform_device *dsidev)
2261 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2263 bool in_use[DSI_MAX_NR_LANES];
2264 static const u8 offsets_old[] = { 28, 27, 26 };
2265 static const u8 offsets_new[] = { 24, 25, 26, 27, 28 };
2268 if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC))
2269 offsets = offsets_old;
2271 offsets = offsets_new;
2273 for (i = 0; i < dsi->num_lanes_supported; ++i)
2274 in_use[i] = dsi->lanes[i].function != DSI_LANE_UNUSED;
2281 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2284 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2285 if (!in_use[i] || (l & (1 << offsets[i])))
2289 if (ok == dsi->num_lanes_supported)
2293 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2294 if (!in_use[i] || (l & (1 << offsets[i])))
2297 DSSERR("CIO TXCLKESC%d domain not coming " \
2298 "out of reset\n", i);
2307 /* return bitmask of enabled lanes, lane0 being the lsb */
2308 static unsigned dsi_get_lane_mask(struct platform_device *dsidev)
2310 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2314 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2315 if (dsi->lanes[i].function != DSI_LANE_UNUSED)
2322 static int dsi_cio_init(struct platform_device *dsidev)
2324 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2328 DSSDBG("DSI CIO init starts");
2330 r = dss_dsi_enable_pads(dsi->module_id, dsi_get_lane_mask(dsidev));
2334 dsi_enable_scp_clk(dsidev);
2336 /* A dummy read using the SCP interface to any DSIPHY register is
2337 * required after DSIPHY reset to complete the reset of the DSI complex
2339 dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2341 if (wait_for_bit_change(dsidev, DSI_DSIPHY_CFG5, 30, 1) != 1) {
2342 DSSERR("CIO SCP Clock domain not coming out of reset.\n");
2344 goto err_scp_clk_dom;
2347 r = dsi_set_lane_config(dsidev);
2349 goto err_scp_clk_dom;
2351 /* set TX STOP MODE timer to maximum for this operation */
2352 l = dsi_read_reg(dsidev, DSI_TIMING1);
2353 l = FLD_MOD(l, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2354 l = FLD_MOD(l, 1, 14, 14); /* STOP_STATE_X16_IO */
2355 l = FLD_MOD(l, 1, 13, 13); /* STOP_STATE_X4_IO */
2356 l = FLD_MOD(l, 0x1fff, 12, 0); /* STOP_STATE_COUNTER_IO */
2357 dsi_write_reg(dsidev, DSI_TIMING1, l);
2359 if (dsi->ulps_enabled) {
2363 DSSDBG("manual ulps exit\n");
2365 /* ULPS is exited by Mark-1 state for 1ms, followed by
2366 * stop state. DSS HW cannot do this via the normal
2367 * ULPS exit sequence, as after reset the DSS HW thinks
2368 * that we are not in ULPS mode, and refuses to send the
2369 * sequence. So we need to send the ULPS exit sequence
2370 * manually by setting positive lines high and negative lines
2376 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2377 if (dsi->lanes[i].function == DSI_LANE_UNUSED)
2382 dsi_cio_enable_lane_override(dsidev, mask_p, 0);
2385 r = dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ON);
2389 if (wait_for_bit_change(dsidev, DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
2390 DSSERR("CIO PWR clock domain not coming out of reset.\n");
2392 goto err_cio_pwr_dom;
2395 dsi_if_enable(dsidev, true);
2396 dsi_if_enable(dsidev, false);
2397 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
2399 r = dsi_cio_wait_tx_clk_esc_reset(dsidev);
2401 goto err_tx_clk_esc_rst;
2403 if (dsi->ulps_enabled) {
2404 /* Keep Mark-1 state for 1ms (as per DSI spec) */
2405 ktime_t wait = ns_to_ktime(1000 * 1000);
2406 set_current_state(TASK_UNINTERRUPTIBLE);
2407 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
2409 /* Disable the override. The lanes should be set to Mark-11
2410 * state by the HW */
2411 dsi_cio_disable_lane_override(dsidev);
2414 /* FORCE_TX_STOP_MODE_IO */
2415 REG_FLD_MOD(dsidev, DSI_TIMING1, 0, 15, 15);
2417 dsi_cio_timings(dsidev);
2419 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
2420 /* DDR_CLK_ALWAYS_ON */
2421 REG_FLD_MOD(dsidev, DSI_CLK_CTRL,
2422 dsi->vm_timings.ddr_clk_always_on, 13, 13);
2425 dsi->ulps_enabled = false;
2427 DSSDBG("CIO init done\n");
2432 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */
2434 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2436 if (dsi->ulps_enabled)
2437 dsi_cio_disable_lane_override(dsidev);
2439 dsi_disable_scp_clk(dsidev);
2440 dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dsidev));
2444 static void dsi_cio_uninit(struct platform_device *dsidev)
2446 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2448 /* DDR_CLK_ALWAYS_ON */
2449 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
2451 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2452 dsi_disable_scp_clk(dsidev);
2453 dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dsidev));
2456 static void dsi_config_tx_fifo(struct platform_device *dsidev,
2457 enum fifo_size size1, enum fifo_size size2,
2458 enum fifo_size size3, enum fifo_size size4)
2460 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2465 dsi->vc[0].tx_fifo_size = size1;
2466 dsi->vc[1].tx_fifo_size = size2;
2467 dsi->vc[2].tx_fifo_size = size3;
2468 dsi->vc[3].tx_fifo_size = size4;
2470 for (i = 0; i < 4; i++) {
2472 int size = dsi->vc[i].tx_fifo_size;
2474 if (add + size > 4) {
2475 DSSERR("Illegal FIFO configuration\n");
2480 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2482 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
2486 dsi_write_reg(dsidev, DSI_TX_FIFO_VC_SIZE, r);
2489 static void dsi_config_rx_fifo(struct platform_device *dsidev,
2490 enum fifo_size size1, enum fifo_size size2,
2491 enum fifo_size size3, enum fifo_size size4)
2493 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2498 dsi->vc[0].rx_fifo_size = size1;
2499 dsi->vc[1].rx_fifo_size = size2;
2500 dsi->vc[2].rx_fifo_size = size3;
2501 dsi->vc[3].rx_fifo_size = size4;
2503 for (i = 0; i < 4; i++) {
2505 int size = dsi->vc[i].rx_fifo_size;
2507 if (add + size > 4) {
2508 DSSERR("Illegal FIFO configuration\n");
2513 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2515 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
2519 dsi_write_reg(dsidev, DSI_RX_FIFO_VC_SIZE, r);
2522 static int dsi_force_tx_stop_mode_io(struct platform_device *dsidev)
2526 r = dsi_read_reg(dsidev, DSI_TIMING1);
2527 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2528 dsi_write_reg(dsidev, DSI_TIMING1, r);
2530 if (wait_for_bit_change(dsidev, DSI_TIMING1, 15, 0) != 0) {
2531 DSSERR("TX_STOP bit not going down\n");
2538 static bool dsi_vc_is_enabled(struct platform_device *dsidev, int channel)
2540 return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0);
2543 static void dsi_packet_sent_handler_vp(void *data, u32 mask)
2545 struct dsi_packet_sent_handler_data *vp_data =
2546 (struct dsi_packet_sent_handler_data *) data;
2547 struct dsi_data *dsi = dsi_get_dsidrv_data(vp_data->dsidev);
2548 const int channel = dsi->update_channel;
2549 u8 bit = dsi->te_enabled ? 30 : 31;
2551 if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0)
2552 complete(vp_data->completion);
2555 static int dsi_sync_vc_vp(struct platform_device *dsidev, int channel)
2557 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2558 DECLARE_COMPLETION_ONSTACK(completion);
2559 struct dsi_packet_sent_handler_data vp_data = { dsidev, &completion };
2563 bit = dsi->te_enabled ? 30 : 31;
2565 r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2566 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2570 /* Wait for completion only if TE_EN/TE_START is still set */
2571 if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) {
2572 if (wait_for_completion_timeout(&completion,
2573 msecs_to_jiffies(10)) == 0) {
2574 DSSERR("Failed to complete previous frame transfer\n");
2580 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2581 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2585 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2586 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2591 static void dsi_packet_sent_handler_l4(void *data, u32 mask)
2593 struct dsi_packet_sent_handler_data *l4_data =
2594 (struct dsi_packet_sent_handler_data *) data;
2595 struct dsi_data *dsi = dsi_get_dsidrv_data(l4_data->dsidev);
2596 const int channel = dsi->update_channel;
2598 if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0)
2599 complete(l4_data->completion);
2602 static int dsi_sync_vc_l4(struct platform_device *dsidev, int channel)
2604 DECLARE_COMPLETION_ONSTACK(completion);
2605 struct dsi_packet_sent_handler_data l4_data = { dsidev, &completion };
2608 r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2609 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2613 /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */
2614 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) {
2615 if (wait_for_completion_timeout(&completion,
2616 msecs_to_jiffies(10)) == 0) {
2617 DSSERR("Failed to complete previous l4 transfer\n");
2623 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2624 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2628 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2629 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2634 static int dsi_sync_vc(struct platform_device *dsidev, int channel)
2636 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2638 WARN_ON(!dsi_bus_is_locked(dsidev));
2640 WARN_ON(in_interrupt());
2642 if (!dsi_vc_is_enabled(dsidev, channel))
2645 switch (dsi->vc[channel].source) {
2646 case DSI_VC_SOURCE_VP:
2647 return dsi_sync_vc_vp(dsidev, channel);
2648 case DSI_VC_SOURCE_L4:
2649 return dsi_sync_vc_l4(dsidev, channel);
2656 static int dsi_vc_enable(struct platform_device *dsidev, int channel,
2659 DSSDBG("dsi_vc_enable channel %d, enable %d\n",
2662 enable = enable ? 1 : 0;
2664 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 0, 0);
2666 if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel),
2667 0, enable) != enable) {
2668 DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
2675 static void dsi_vc_initial_config(struct platform_device *dsidev, int channel)
2677 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2680 DSSDBG("Initial config of virtual channel %d", channel);
2682 r = dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2684 if (FLD_GET(r, 15, 15)) /* VC_BUSY */
2685 DSSERR("VC(%d) busy when trying to configure it!\n",
2688 r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
2689 r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */
2690 r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
2691 r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
2692 r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
2693 r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
2694 r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
2695 if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH))
2696 r = FLD_MOD(r, 3, 11, 10); /* OCP_WIDTH = 32 bit */
2698 r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
2699 r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
2701 dsi_write_reg(dsidev, DSI_VC_CTRL(channel), r);
2703 dsi->vc[channel].source = DSI_VC_SOURCE_L4;
2706 static int dsi_vc_config_source(struct platform_device *dsidev, int channel,
2707 enum dsi_vc_source source)
2709 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2711 if (dsi->vc[channel].source == source)
2714 DSSDBG("Source config of virtual channel %d", channel);
2716 dsi_sync_vc(dsidev, channel);
2718 dsi_vc_enable(dsidev, channel, 0);
2721 if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 15, 0) != 0) {
2722 DSSERR("vc(%d) busy when trying to config for VP\n", channel);
2726 /* SOURCE, 0 = L4, 1 = video port */
2727 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), source, 1, 1);
2729 /* DCS_CMD_ENABLE */
2730 if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
2731 bool enable = source == DSI_VC_SOURCE_VP;
2732 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 30, 30);
2735 dsi_vc_enable(dsidev, channel, 1);
2737 dsi->vc[channel].source = source;
2742 static void dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
2745 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2746 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2748 DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
2750 WARN_ON(!dsi_bus_is_locked(dsidev));
2752 dsi_vc_enable(dsidev, channel, 0);
2753 dsi_if_enable(dsidev, 0);
2755 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 9, 9);
2757 dsi_vc_enable(dsidev, channel, 1);
2758 dsi_if_enable(dsidev, 1);
2760 dsi_force_tx_stop_mode_io(dsidev);
2762 /* start the DDR clock by sending a NULL packet */
2763 if (dsi->vm_timings.ddr_clk_always_on && enable)
2764 dsi_vc_send_null(dssdev, channel);
2767 static void dsi_vc_flush_long_data(struct platform_device *dsidev, int channel)
2769 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2771 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2772 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
2776 (val >> 24) & 0xff);
2780 static void dsi_show_rx_ack_with_err(u16 err)
2782 DSSERR("\tACK with ERROR (%#x):\n", err);
2784 DSSERR("\t\tSoT Error\n");
2786 DSSERR("\t\tSoT Sync Error\n");
2788 DSSERR("\t\tEoT Sync Error\n");
2790 DSSERR("\t\tEscape Mode Entry Command Error\n");
2792 DSSERR("\t\tLP Transmit Sync Error\n");
2794 DSSERR("\t\tHS Receive Timeout Error\n");
2796 DSSERR("\t\tFalse Control Error\n");
2798 DSSERR("\t\t(reserved7)\n");
2800 DSSERR("\t\tECC Error, single-bit (corrected)\n");
2802 DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
2803 if (err & (1 << 10))
2804 DSSERR("\t\tChecksum Error\n");
2805 if (err & (1 << 11))
2806 DSSERR("\t\tData type not recognized\n");
2807 if (err & (1 << 12))
2808 DSSERR("\t\tInvalid VC ID\n");
2809 if (err & (1 << 13))
2810 DSSERR("\t\tInvalid Transmission Length\n");
2811 if (err & (1 << 14))
2812 DSSERR("\t\t(reserved14)\n");
2813 if (err & (1 << 15))
2814 DSSERR("\t\tDSI Protocol Violation\n");
2817 static u16 dsi_vc_flush_receive_data(struct platform_device *dsidev,
2820 /* RX_FIFO_NOT_EMPTY */
2821 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2824 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2825 DSSERR("\trawval %#08x\n", val);
2826 dt = FLD_GET(val, 5, 0);
2827 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
2828 u16 err = FLD_GET(val, 23, 8);
2829 dsi_show_rx_ack_with_err(err);
2830 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) {
2831 DSSERR("\tDCS short response, 1 byte: %#x\n",
2832 FLD_GET(val, 23, 8));
2833 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) {
2834 DSSERR("\tDCS short response, 2 byte: %#x\n",
2835 FLD_GET(val, 23, 8));
2836 } else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) {
2837 DSSERR("\tDCS long response, len %d\n",
2838 FLD_GET(val, 23, 8));
2839 dsi_vc_flush_long_data(dsidev, channel);
2841 DSSERR("\tunknown datatype 0x%02x\n", dt);
2847 static int dsi_vc_send_bta(struct platform_device *dsidev, int channel)
2849 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2851 if (dsi->debug_write || dsi->debug_read)
2852 DSSDBG("dsi_vc_send_bta %d\n", channel);
2854 WARN_ON(!dsi_bus_is_locked(dsidev));
2856 /* RX_FIFO_NOT_EMPTY */
2857 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2858 DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
2859 dsi_vc_flush_receive_data(dsidev, channel);
2862 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
2864 /* flush posted write */
2865 dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2870 static int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel)
2872 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2873 DECLARE_COMPLETION_ONSTACK(completion);
2877 r = dsi_register_isr_vc(dsidev, channel, dsi_completion_handler,
2878 &completion, DSI_VC_IRQ_BTA);
2882 r = dsi_register_isr(dsidev, dsi_completion_handler, &completion,
2883 DSI_IRQ_ERROR_MASK);
2887 r = dsi_vc_send_bta(dsidev, channel);
2891 if (wait_for_completion_timeout(&completion,
2892 msecs_to_jiffies(500)) == 0) {
2893 DSSERR("Failed to receive BTA\n");
2898 err = dsi_get_errors(dsidev);
2900 DSSERR("Error while sending BTA: %x\n", err);
2905 dsi_unregister_isr(dsidev, dsi_completion_handler, &completion,
2906 DSI_IRQ_ERROR_MASK);
2908 dsi_unregister_isr_vc(dsidev, channel, dsi_completion_handler,
2909 &completion, DSI_VC_IRQ_BTA);
2914 static inline void dsi_vc_write_long_header(struct platform_device *dsidev,
2915 int channel, u8 data_type, u16 len, u8 ecc)
2917 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2921 WARN_ON(!dsi_bus_is_locked(dsidev));
2923 data_id = data_type | dsi->vc[channel].vc_id << 6;
2925 val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
2926 FLD_VAL(ecc, 31, 24);
2928 dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_HEADER(channel), val);
2931 static inline void dsi_vc_write_long_payload(struct platform_device *dsidev,
2932 int channel, u8 b1, u8 b2, u8 b3, u8 b4)
2936 val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0;
2938 /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
2939 b1, b2, b3, b4, val); */
2941 dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
2944 static int dsi_vc_send_long(struct platform_device *dsidev, int channel,
2945 u8 data_type, u8 *data, u16 len, u8 ecc)
2948 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2954 if (dsi->debug_write)
2955 DSSDBG("dsi_vc_send_long, %d bytes\n", len);
2958 if (dsi->vc[channel].tx_fifo_size * 32 * 4 < len + 4) {
2959 DSSERR("unable to send long packet: packet too long.\n");
2963 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
2965 dsi_vc_write_long_header(dsidev, channel, data_type, len, ecc);
2968 for (i = 0; i < len >> 2; i++) {
2969 if (dsi->debug_write)
2970 DSSDBG("\tsending full packet %d\n", i);
2977 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, b4);
2982 b1 = 0; b2 = 0; b3 = 0;
2984 if (dsi->debug_write)
2985 DSSDBG("\tsending remainder bytes %d\n", i);
3002 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, 0);
3008 static int dsi_vc_send_short(struct platform_device *dsidev, int channel,
3009 u8 data_type, u16 data, u8 ecc)
3011 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3015 WARN_ON(!dsi_bus_is_locked(dsidev));
3017 if (dsi->debug_write)
3018 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
3020 data_type, data & 0xff, (data >> 8) & 0xff);
3022 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
3024 if (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(channel)), 16, 16)) {
3025 DSSERR("ERROR FIFO FULL, aborting transfer\n");
3029 data_id = data_type | dsi->vc[channel].vc_id << 6;
3031 r = (data_id << 0) | (data << 8) | (ecc << 24);
3033 dsi_write_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel), r);
3038 static int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel)
3040 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3042 return dsi_vc_send_long(dsidev, channel, MIPI_DSI_NULL_PACKET, NULL,
3046 static int dsi_vc_write_nosync_common(struct platform_device *dsidev,
3047 int channel, u8 *data, int len, enum dss_dsi_content_type type)
3052 BUG_ON(type == DSS_DSI_CONTENT_DCS);
3053 r = dsi_vc_send_short(dsidev, channel,
3054 MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, 0, 0);
3055 } else if (len == 1) {
3056 r = dsi_vc_send_short(dsidev, channel,
3057 type == DSS_DSI_CONTENT_GENERIC ?
3058 MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM :
3059 MIPI_DSI_DCS_SHORT_WRITE, data[0], 0);
3060 } else if (len == 2) {
3061 r = dsi_vc_send_short(dsidev, channel,
3062 type == DSS_DSI_CONTENT_GENERIC ?
3063 MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM :
3064 MIPI_DSI_DCS_SHORT_WRITE_PARAM,
3065 data[0] | (data[1] << 8), 0);
3067 r = dsi_vc_send_long(dsidev, channel,
3068 type == DSS_DSI_CONTENT_GENERIC ?
3069 MIPI_DSI_GENERIC_LONG_WRITE :
3070 MIPI_DSI_DCS_LONG_WRITE, data, len, 0);
3076 static int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
3079 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3081 return dsi_vc_write_nosync_common(dsidev, channel, data, len,
3082 DSS_DSI_CONTENT_DCS);
3085 static int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
3088 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3090 return dsi_vc_write_nosync_common(dsidev, channel, data, len,
3091 DSS_DSI_CONTENT_GENERIC);
3094 static int dsi_vc_write_common(struct omap_dss_device *dssdev, int channel,
3095 u8 *data, int len, enum dss_dsi_content_type type)
3097 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3100 r = dsi_vc_write_nosync_common(dsidev, channel, data, len, type);
3104 r = dsi_vc_send_bta_sync(dssdev, channel);
3108 /* RX_FIFO_NOT_EMPTY */
3109 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
3110 DSSERR("rx fifo not empty after write, dumping data:\n");
3111 dsi_vc_flush_receive_data(dsidev, channel);
3118 DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n",
3119 channel, data[0], len);
3123 static int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
3126 return dsi_vc_write_common(dssdev, channel, data, len,
3127 DSS_DSI_CONTENT_DCS);
3130 static int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
3133 return dsi_vc_write_common(dssdev, channel, data, len,
3134 DSS_DSI_CONTENT_GENERIC);
3137 static int dsi_vc_dcs_send_read_request(struct platform_device *dsidev,
3138 int channel, u8 dcs_cmd)
3140 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3143 if (dsi->debug_read)
3144 DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n",
3147 r = dsi_vc_send_short(dsidev, channel, MIPI_DSI_DCS_READ, dcs_cmd, 0);
3149 DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)"
3150 " failed\n", channel, dcs_cmd);
3157 static int dsi_vc_generic_send_read_request(struct platform_device *dsidev,
3158 int channel, u8 *reqdata, int reqlen)
3160 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3165 if (dsi->debug_read)
3166 DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n",
3170 data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM;
3172 } else if (reqlen == 1) {
3173 data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM;
3175 } else if (reqlen == 2) {
3176 data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM;
3177 data = reqdata[0] | (reqdata[1] << 8);
3183 r = dsi_vc_send_short(dsidev, channel, data_type, data, 0);
3185 DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)"
3186 " failed\n", channel, reqlen);
3193 static int dsi_vc_read_rx_fifo(struct platform_device *dsidev, int channel,
3194 u8 *buf, int buflen, enum dss_dsi_content_type type)
3196 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3201 /* RX_FIFO_NOT_EMPTY */
3202 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) {
3203 DSSERR("RX fifo empty when trying to read.\n");
3208 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
3209 if (dsi->debug_read)
3210 DSSDBG("\theader: %08x\n", val);
3211 dt = FLD_GET(val, 5, 0);
3212 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
3213 u16 err = FLD_GET(val, 23, 8);
3214 dsi_show_rx_ack_with_err(err);
3218 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3219 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE :
3220 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)) {
3221 u8 data = FLD_GET(val, 15, 8);
3222 if (dsi->debug_read)
3223 DSSDBG("\t%s short response, 1 byte: %02x\n",
3224 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3235 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3236 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE :
3237 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE)) {
3238 u16 data = FLD_GET(val, 23, 8);
3239 if (dsi->debug_read)
3240 DSSDBG("\t%s short response, 2 byte: %04x\n",
3241 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3249 buf[0] = data & 0xff;
3250 buf[1] = (data >> 8) & 0xff;
3253 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3254 MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE :
3255 MIPI_DSI_RX_DCS_LONG_READ_RESPONSE)) {
3257 int len = FLD_GET(val, 23, 8);
3258 if (dsi->debug_read)
3259 DSSDBG("\t%s long response, len %d\n",
3260 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3268 /* two byte checksum ends the packet, not included in len */
3269 for (w = 0; w < len + 2;) {
3271 val = dsi_read_reg(dsidev,
3272 DSI_VC_SHORT_PACKET_HEADER(channel));
3273 if (dsi->debug_read)
3274 DSSDBG("\t\t%02x %02x %02x %02x\n",
3278 (val >> 24) & 0xff);
3280 for (b = 0; b < 4; ++b) {
3282 buf[w] = (val >> (b * 8)) & 0xff;
3283 /* we discard the 2 byte checksum */
3290 DSSERR("\tunknown datatype 0x%02x\n", dt);
3296 DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel,
3297 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS");
3302 static int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3303 u8 *buf, int buflen)
3305 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3308 r = dsi_vc_dcs_send_read_request(dsidev, channel, dcs_cmd);
3312 r = dsi_vc_send_bta_sync(dssdev, channel);
3316 r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3317 DSS_DSI_CONTENT_DCS);
3328 DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel, dcs_cmd);
3332 static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel,
3333 u8 *reqdata, int reqlen, u8 *buf, int buflen)
3335 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3338 r = dsi_vc_generic_send_read_request(dsidev, channel, reqdata, reqlen);
3342 r = dsi_vc_send_bta_sync(dssdev, channel);
3346 r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3347 DSS_DSI_CONTENT_GENERIC);
3359 static int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
3362 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3364 return dsi_vc_send_short(dsidev, channel,
3365 MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0);
3368 static int dsi_enter_ulps(struct platform_device *dsidev)
3370 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3371 DECLARE_COMPLETION_ONSTACK(completion);
3375 DSSDBG("Entering ULPS");
3377 WARN_ON(!dsi_bus_is_locked(dsidev));
3379 WARN_ON(dsi->ulps_enabled);
3381 if (dsi->ulps_enabled)
3384 /* DDR_CLK_ALWAYS_ON */
3385 if (REG_GET(dsidev, DSI_CLK_CTRL, 13, 13)) {
3386 dsi_if_enable(dsidev, 0);
3387 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
3388 dsi_if_enable(dsidev, 1);
3391 dsi_sync_vc(dsidev, 0);
3392 dsi_sync_vc(dsidev, 1);
3393 dsi_sync_vc(dsidev, 2);
3394 dsi_sync_vc(dsidev, 3);
3396 dsi_force_tx_stop_mode_io(dsidev);
3398 dsi_vc_enable(dsidev, 0, false);
3399 dsi_vc_enable(dsidev, 1, false);
3400 dsi_vc_enable(dsidev, 2, false);
3401 dsi_vc_enable(dsidev, 3, false);
3403 if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 16, 16)) { /* HS_BUSY */
3404 DSSERR("HS busy when enabling ULPS\n");
3408 if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 17, 17)) { /* LP_BUSY */
3409 DSSERR("LP busy when enabling ULPS\n");
3413 r = dsi_register_isr_cio(dsidev, dsi_completion_handler, &completion,
3414 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3420 for (i = 0; i < dsi->num_lanes_supported; ++i) {
3421 if (dsi->lanes[i].function == DSI_LANE_UNUSED)
3425 /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */
3426 /* LANEx_ULPS_SIG2 */
3427 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, mask, 9, 5);
3429 /* flush posted write and wait for SCP interface to finish the write */
3430 dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
3432 if (wait_for_completion_timeout(&completion,
3433 msecs_to_jiffies(1000)) == 0) {
3434 DSSERR("ULPS enable timeout\n");
3439 dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3440 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3442 /* Reset LANEx_ULPS_SIG2 */
3443 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, 0, 9, 5);
3445 /* flush posted write and wait for SCP interface to finish the write */
3446 dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
3448 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ULPS);
3450 dsi_if_enable(dsidev, false);
3452 dsi->ulps_enabled = true;
3457 dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3458 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3462 static void dsi_set_lp_rx_timeout(struct platform_device *dsidev,
3463 unsigned ticks, bool x4, bool x16)
3466 unsigned long total_ticks;
3469 BUG_ON(ticks > 0x1fff);
3471 /* ticks in DSI_FCK */
3472 fck = dsi_fclk_rate(dsidev);
3474 r = dsi_read_reg(dsidev, DSI_TIMING2);
3475 r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */
3476 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */
3477 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */
3478 r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */
3479 dsi_write_reg(dsidev, DSI_TIMING2, r);
3481 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3483 DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3485 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3486 (total_ticks * 1000) / (fck / 1000 / 1000));
3489 static void dsi_set_ta_timeout(struct platform_device *dsidev, unsigned ticks,
3493 unsigned long total_ticks;
3496 BUG_ON(ticks > 0x1fff);
3498 /* ticks in DSI_FCK */
3499 fck = dsi_fclk_rate(dsidev);
3501 r = dsi_read_reg(dsidev, DSI_TIMING1);
3502 r = FLD_MOD(r, 1, 31, 31); /* TA_TO */
3503 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */
3504 r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */
3505 r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */
3506 dsi_write_reg(dsidev, DSI_TIMING1, r);
3508 total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1);
3510 DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n",
3512 ticks, x8 ? " x8" : "", x16 ? " x16" : "",
3513 (total_ticks * 1000) / (fck / 1000 / 1000));
3516 static void dsi_set_stop_state_counter(struct platform_device *dsidev,
3517 unsigned ticks, bool x4, bool x16)
3520 unsigned long total_ticks;
3523 BUG_ON(ticks > 0x1fff);
3525 /* ticks in DSI_FCK */
3526 fck = dsi_fclk_rate(dsidev);
3528 r = dsi_read_reg(dsidev, DSI_TIMING1);
3529 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
3530 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */
3531 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */
3532 r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */
3533 dsi_write_reg(dsidev, DSI_TIMING1, r);
3535 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3537 DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n",
3539 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3540 (total_ticks * 1000) / (fck / 1000 / 1000));
3543 static void dsi_set_hs_tx_timeout(struct platform_device *dsidev,
3544 unsigned ticks, bool x4, bool x16)
3547 unsigned long total_ticks;
3550 BUG_ON(ticks > 0x1fff);
3552 /* ticks in TxByteClkHS */
3553 fck = dsi_get_txbyteclkhs(dsidev);
3555 r = dsi_read_reg(dsidev, DSI_TIMING2);
3556 r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */
3557 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */
3558 r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */
3559 r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */
3560 dsi_write_reg(dsidev, DSI_TIMING2, r);
3562 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3564 DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3566 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3567 (total_ticks * 1000) / (fck / 1000 / 1000));
3570 static void dsi_config_vp_num_line_buffers(struct platform_device *dsidev)
3572 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3573 int num_line_buffers;
3575 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3576 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3577 struct omap_video_timings *timings = &dsi->timings;
3579 * Don't use line buffers if width is greater than the video
3580 * port's line buffer size
3582 if (dsi->line_buffer_size <= timings->x_res * bpp / 8)
3583 num_line_buffers = 0;
3585 num_line_buffers = 2;
3587 /* Use maximum number of line buffers in command mode */
3588 num_line_buffers = 2;
3592 REG_FLD_MOD(dsidev, DSI_CTRL, num_line_buffers, 13, 12);
3595 static void dsi_config_vp_sync_events(struct platform_device *dsidev)
3597 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3601 if (dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE)
3606 r = dsi_read_reg(dsidev, DSI_CTRL);
3607 r = FLD_MOD(r, 1, 9, 9); /* VP_DE_POL */
3608 r = FLD_MOD(r, 1, 10, 10); /* VP_HSYNC_POL */
3609 r = FLD_MOD(r, 1, 11, 11); /* VP_VSYNC_POL */
3610 r = FLD_MOD(r, 1, 15, 15); /* VP_VSYNC_START */
3611 r = FLD_MOD(r, sync_end, 16, 16); /* VP_VSYNC_END */
3612 r = FLD_MOD(r, 1, 17, 17); /* VP_HSYNC_START */
3613 r = FLD_MOD(r, sync_end, 18, 18); /* VP_HSYNC_END */
3614 dsi_write_reg(dsidev, DSI_CTRL, r);
3617 static void dsi_config_blanking_modes(struct platform_device *dsidev)
3619 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3620 int blanking_mode = dsi->vm_timings.blanking_mode;
3621 int hfp_blanking_mode = dsi->vm_timings.hfp_blanking_mode;
3622 int hbp_blanking_mode = dsi->vm_timings.hbp_blanking_mode;
3623 int hsa_blanking_mode = dsi->vm_timings.hsa_blanking_mode;
3627 * 0 = TX FIFO packets sent or LPS in corresponding blanking periods
3628 * 1 = Long blanking packets are sent in corresponding blanking periods
3630 r = dsi_read_reg(dsidev, DSI_CTRL);
3631 r = FLD_MOD(r, blanking_mode, 20, 20); /* BLANKING_MODE */
3632 r = FLD_MOD(r, hfp_blanking_mode, 21, 21); /* HFP_BLANKING */
3633 r = FLD_MOD(r, hbp_blanking_mode, 22, 22); /* HBP_BLANKING */
3634 r = FLD_MOD(r, hsa_blanking_mode, 23, 23); /* HSA_BLANKING */
3635 dsi_write_reg(dsidev, DSI_CTRL, r);
3639 * According to section 'HS Command Mode Interleaving' in OMAP TRM, Scenario 3
3640 * results in maximum transition time for data and clock lanes to enter and
3641 * exit HS mode. Hence, this is the scenario where the least amount of command
3642 * mode data can be interleaved. We program the minimum amount of TXBYTECLKHS
3643 * clock cycles that can be used to interleave command mode data in HS so that
3644 * all scenarios are satisfied.
3646 static int dsi_compute_interleave_hs(int blank, bool ddr_alwon, int enter_hs,
3647 int exit_hs, int exiths_clk, int ddr_pre, int ddr_post)
3652 * If DDR_CLK_ALWAYS_ON is set, we need to consider HS mode transition
3653 * time of data lanes only, if it isn't set, we need to consider HS
3654 * transition time of both data and clock lanes. HS transition time
3655 * of Scenario 3 is considered.
3658 transition = enter_hs + exit_hs + max(enter_hs, 2) + 1;
3661 trans1 = ddr_pre + enter_hs + exit_hs + max(enter_hs, 2) + 1;
3662 trans2 = ddr_pre + enter_hs + exiths_clk + ddr_post + ddr_pre +
3664 transition = max(trans1, trans2);
3667 return blank > transition ? blank - transition : 0;
3671 * According to section 'LP Command Mode Interleaving' in OMAP TRM, Scenario 1
3672 * results in maximum transition time for data lanes to enter and exit LP mode.
3673 * Hence, this is the scenario where the least amount of command mode data can
3674 * be interleaved. We program the minimum amount of bytes that can be
3675 * interleaved in LP so that all scenarios are satisfied.
3677 static int dsi_compute_interleave_lp(int blank, int enter_hs, int exit_hs,
3678 int lp_clk_div, int tdsi_fclk)
3680 int trans_lp; /* time required for a LP transition, in TXBYTECLKHS */
3681 int tlp_avail; /* time left for interleaving commands, in CLKIN4DDR */
3682 int ttxclkesc; /* period of LP transmit escape clock, in CLKIN4DDR */
3683 int thsbyte_clk = 16; /* Period of TXBYTECLKHS clock, in CLKIN4DDR */
3684 int lp_inter; /* cmd mode data that can be interleaved, in bytes */
3686 /* maximum LP transition time according to Scenario 1 */
3687 trans_lp = exit_hs + max(enter_hs, 2) + 1;
3689 /* CLKIN4DDR = 16 * TXBYTECLKHS */
3690 tlp_avail = thsbyte_clk * (blank - trans_lp);
3692 ttxclkesc = tdsi_fclk * lp_clk_div;
3694 lp_inter = ((tlp_avail - 8 * thsbyte_clk - 5 * tdsi_fclk) / ttxclkesc -
3697 return max(lp_inter, 0);
3700 static void dsi_config_cmd_mode_interleaving(struct platform_device *dsidev)
3702 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3704 int hfp_blanking_mode, hbp_blanking_mode, hsa_blanking_mode;
3705 int hsa, hfp, hbp, width_bytes, bllp, lp_clk_div;
3706 int ddr_clk_pre, ddr_clk_post, enter_hs_mode_lat, exit_hs_mode_lat;
3707 int tclk_trail, ths_exit, exiths_clk;
3709 struct omap_video_timings *timings = &dsi->timings;
3710 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3711 int ndl = dsi->num_lanes_used - 1;
3712 int dsi_fclk_hsdiv = dsi->user_dsi_cinfo.regm_dsi + 1;
3713 int hsa_interleave_hs = 0, hsa_interleave_lp = 0;
3714 int hfp_interleave_hs = 0, hfp_interleave_lp = 0;
3715 int hbp_interleave_hs = 0, hbp_interleave_lp = 0;
3716 int bl_interleave_hs = 0, bl_interleave_lp = 0;
3719 r = dsi_read_reg(dsidev, DSI_CTRL);
3720 blanking_mode = FLD_GET(r, 20, 20);
3721 hfp_blanking_mode = FLD_GET(r, 21, 21);
3722 hbp_blanking_mode = FLD_GET(r, 22, 22);
3723 hsa_blanking_mode = FLD_GET(r, 23, 23);
3725 r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
3726 hbp = FLD_GET(r, 11, 0);
3727 hfp = FLD_GET(r, 23, 12);
3728 hsa = FLD_GET(r, 31, 24);
3730 r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
3731 ddr_clk_post = FLD_GET(r, 7, 0);
3732 ddr_clk_pre = FLD_GET(r, 15, 8);
3734 r = dsi_read_reg(dsidev, DSI_VM_TIMING7);
3735 exit_hs_mode_lat = FLD_GET(r, 15, 0);
3736 enter_hs_mode_lat = FLD_GET(r, 31, 16);
3738 r = dsi_read_reg(dsidev, DSI_CLK_CTRL);
3739 lp_clk_div = FLD_GET(r, 12, 0);
3740 ddr_alwon = FLD_GET(r, 13, 13);
3742 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
3743 ths_exit = FLD_GET(r, 7, 0);
3745 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
3746 tclk_trail = FLD_GET(r, 15, 8);
3748 exiths_clk = ths_exit + tclk_trail;
3750 width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8);
3751 bllp = hbp + hfp + hsa + DIV_ROUND_UP(width_bytes + 6, ndl);
3753 if (!hsa_blanking_mode) {
3754 hsa_interleave_hs = dsi_compute_interleave_hs(hsa, ddr_alwon,
3755 enter_hs_mode_lat, exit_hs_mode_lat,
3756 exiths_clk, ddr_clk_pre, ddr_clk_post);
3757 hsa_interleave_lp = dsi_compute_interleave_lp(hsa,
3758 enter_hs_mode_lat, exit_hs_mode_lat,
3759 lp_clk_div, dsi_fclk_hsdiv);
3762 if (!hfp_blanking_mode) {
3763 hfp_interleave_hs = dsi_compute_interleave_hs(hfp, ddr_alwon,
3764 enter_hs_mode_lat, exit_hs_mode_lat,
3765 exiths_clk, ddr_clk_pre, ddr_clk_post);
3766 hfp_interleave_lp = dsi_compute_interleave_lp(hfp,
3767 enter_hs_mode_lat, exit_hs_mode_lat,
3768 lp_clk_div, dsi_fclk_hsdiv);
3771 if (!hbp_blanking_mode) {
3772 hbp_interleave_hs = dsi_compute_interleave_hs(hbp, ddr_alwon,
3773 enter_hs_mode_lat, exit_hs_mode_lat,
3774 exiths_clk, ddr_clk_pre, ddr_clk_post);
3776 hbp_interleave_lp = dsi_compute_interleave_lp(hbp,
3777 enter_hs_mode_lat, exit_hs_mode_lat,
3778 lp_clk_div, dsi_fclk_hsdiv);
3781 if (!blanking_mode) {
3782 bl_interleave_hs = dsi_compute_interleave_hs(bllp, ddr_alwon,
3783 enter_hs_mode_lat, exit_hs_mode_lat,
3784 exiths_clk, ddr_clk_pre, ddr_clk_post);
3786 bl_interleave_lp = dsi_compute_interleave_lp(bllp,
3787 enter_hs_mode_lat, exit_hs_mode_lat,
3788 lp_clk_div, dsi_fclk_hsdiv);
3791 DSSDBG("DSI HS interleaving(TXBYTECLKHS) HSA %d, HFP %d, HBP %d, BLLP %d\n",
3792 hsa_interleave_hs, hfp_interleave_hs, hbp_interleave_hs,
3795 DSSDBG("DSI LP interleaving(bytes) HSA %d, HFP %d, HBP %d, BLLP %d\n",
3796 hsa_interleave_lp, hfp_interleave_lp, hbp_interleave_lp,
3799 r = dsi_read_reg(dsidev, DSI_VM_TIMING4);
3800 r = FLD_MOD(r, hsa_interleave_hs, 23, 16);
3801 r = FLD_MOD(r, hfp_interleave_hs, 15, 8);
3802 r = FLD_MOD(r, hbp_interleave_hs, 7, 0);
3803 dsi_write_reg(dsidev, DSI_VM_TIMING4, r);
3805 r = dsi_read_reg(dsidev, DSI_VM_TIMING5);
3806 r = FLD_MOD(r, hsa_interleave_lp, 23, 16);
3807 r = FLD_MOD(r, hfp_interleave_lp, 15, 8);
3808 r = FLD_MOD(r, hbp_interleave_lp, 7, 0);
3809 dsi_write_reg(dsidev, DSI_VM_TIMING5, r);
3811 r = dsi_read_reg(dsidev, DSI_VM_TIMING6);
3812 r = FLD_MOD(r, bl_interleave_hs, 31, 15);
3813 r = FLD_MOD(r, bl_interleave_lp, 16, 0);
3814 dsi_write_reg(dsidev, DSI_VM_TIMING6, r);
3817 static int dsi_proto_config(struct platform_device *dsidev)
3819 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3823 dsi_config_tx_fifo(dsidev, DSI_FIFO_SIZE_32,
3828 dsi_config_rx_fifo(dsidev, DSI_FIFO_SIZE_32,
3833 /* XXX what values for the timeouts? */
3834 dsi_set_stop_state_counter(dsidev, 0x1000, false, false);
3835 dsi_set_ta_timeout(dsidev, 0x1fff, true, true);
3836 dsi_set_lp_rx_timeout(dsidev, 0x1fff, true, true);
3837 dsi_set_hs_tx_timeout(dsidev, 0x1fff, true, true);
3839 switch (dsi_get_pixel_size(dsi->pix_fmt)) {
3854 r = dsi_read_reg(dsidev, DSI_CTRL);
3855 r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */
3856 r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */
3857 r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */
3858 r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/
3859 r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
3860 r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */
3861 r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */
3862 r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */
3863 if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
3864 r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */
3865 /* DCS_CMD_CODE, 1=start, 0=continue */
3866 r = FLD_MOD(r, 0, 25, 25);
3869 dsi_write_reg(dsidev, DSI_CTRL, r);
3871 dsi_config_vp_num_line_buffers(dsidev);
3873 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3874 dsi_config_vp_sync_events(dsidev);
3875 dsi_config_blanking_modes(dsidev);
3876 dsi_config_cmd_mode_interleaving(dsidev);
3879 dsi_vc_initial_config(dsidev, 0);
3880 dsi_vc_initial_config(dsidev, 1);
3881 dsi_vc_initial_config(dsidev, 2);
3882 dsi_vc_initial_config(dsidev, 3);
3887 static void dsi_proto_timings(struct platform_device *dsidev)
3889 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3890 unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail;
3891 unsigned tclk_pre, tclk_post;
3892 unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;
3893 unsigned ths_trail, ths_exit;
3894 unsigned ddr_clk_pre, ddr_clk_post;
3895 unsigned enter_hs_mode_lat, exit_hs_mode_lat;
3897 int ndl = dsi->num_lanes_used - 1;
3900 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
3901 ths_prepare = FLD_GET(r, 31, 24);
3902 ths_prepare_ths_zero = FLD_GET(r, 23, 16);
3903 ths_zero = ths_prepare_ths_zero - ths_prepare;
3904 ths_trail = FLD_GET(r, 15, 8);
3905 ths_exit = FLD_GET(r, 7, 0);
3907 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
3908 tlpx = FLD_GET(r, 20, 16) * 2;
3909 tclk_trail = FLD_GET(r, 15, 8);
3910 tclk_zero = FLD_GET(r, 7, 0);
3912 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
3913 tclk_prepare = FLD_GET(r, 7, 0);
3917 /* min 60ns + 52*UI */
3918 tclk_post = ns2ddr(dsidev, 60) + 26;
3920 ths_eot = DIV_ROUND_UP(4, ndl);
3922 ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
3924 ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot;
3926 BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
3927 BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
3929 r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
3930 r = FLD_MOD(r, ddr_clk_pre, 15, 8);
3931 r = FLD_MOD(r, ddr_clk_post, 7, 0);
3932 dsi_write_reg(dsidev, DSI_CLK_TIMING, r);
3934 DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
3938 enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
3939 DIV_ROUND_UP(ths_prepare, 4) +
3940 DIV_ROUND_UP(ths_zero + 3, 4);
3942 exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
3944 r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
3945 FLD_VAL(exit_hs_mode_lat, 15, 0);
3946 dsi_write_reg(dsidev, DSI_VM_TIMING7, r);
3948 DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
3949 enter_hs_mode_lat, exit_hs_mode_lat);
3951 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3952 /* TODO: Implement a video mode check_timings function */
3953 int hsa = dsi->vm_timings.hsa;
3954 int hfp = dsi->vm_timings.hfp;
3955 int hbp = dsi->vm_timings.hbp;
3956 int vsa = dsi->vm_timings.vsa;
3957 int vfp = dsi->vm_timings.vfp;
3958 int vbp = dsi->vm_timings.vbp;
3959 int window_sync = dsi->vm_timings.window_sync;
3961 struct omap_video_timings *timings = &dsi->timings;
3962 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3963 int tl, t_he, width_bytes;
3965 hsync_end = dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE;
3967 ((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0;
3969 width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8);
3971 /* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */
3972 tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp +
3973 DIV_ROUND_UP(width_bytes + 6, ndl) + hbp;
3975 DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp,
3976 hfp, hsync_end ? hsa : 0, tl);
3977 DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp,
3978 vsa, timings->y_res);
3980 r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
3981 r = FLD_MOD(r, hbp, 11, 0); /* HBP */
3982 r = FLD_MOD(r, hfp, 23, 12); /* HFP */
3983 r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24); /* HSA */
3984 dsi_write_reg(dsidev, DSI_VM_TIMING1, r);
3986 r = dsi_read_reg(dsidev, DSI_VM_TIMING2);
3987 r = FLD_MOD(r, vbp, 7, 0); /* VBP */
3988 r = FLD_MOD(r, vfp, 15, 8); /* VFP */
3989 r = FLD_MOD(r, vsa, 23, 16); /* VSA */
3990 r = FLD_MOD(r, window_sync, 27, 24); /* WINDOW_SYNC */
3991 dsi_write_reg(dsidev, DSI_VM_TIMING2, r);
3993 r = dsi_read_reg(dsidev, DSI_VM_TIMING3);
3994 r = FLD_MOD(r, timings->y_res, 14, 0); /* VACT */
3995 r = FLD_MOD(r, tl, 31, 16); /* TL */
3996 dsi_write_reg(dsidev, DSI_VM_TIMING3, r);
4000 static int dsi_configure_pins(struct omap_dss_device *dssdev,
4001 const struct omap_dsi_pin_config *pin_cfg)
4003 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4004 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4007 struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
4011 static const enum dsi_lane_function functions[] = {
4019 num_pins = pin_cfg->num_pins;
4020 pins = pin_cfg->pins;
4022 if (num_pins < 4 || num_pins > dsi->num_lanes_supported * 2
4023 || num_pins % 2 != 0)
4026 for (i = 0; i < DSI_MAX_NR_LANES; ++i)
4027 lanes[i].function = DSI_LANE_UNUSED;
4031 for (i = 0; i < num_pins; i += 2) {
4038 if (dx < 0 || dx >= dsi->num_lanes_supported * 2)
4041 if (dy < 0 || dy >= dsi->num_lanes_supported * 2)
4056 lanes[lane].function = functions[i / 2];
4057 lanes[lane].polarity = pol;
4061 memcpy(dsi->lanes, lanes, sizeof(dsi->lanes));
4062 dsi->num_lanes_used = num_lanes;
4067 static int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel)
4069 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4070 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4071 struct omap_overlay_manager *mgr = dsi->output.manager;
4072 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
4073 struct omap_dss_device *out = &dsi->output;
4078 if (out == NULL || out->manager == NULL) {
4079 DSSERR("failed to enable display: no output/manager\n");
4083 r = dsi_display_init_dispc(dsidev, mgr);
4085 goto err_init_dispc;
4087 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
4088 switch (dsi->pix_fmt) {
4089 case OMAP_DSS_DSI_FMT_RGB888:
4090 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24;
4092 case OMAP_DSS_DSI_FMT_RGB666:
4093 data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
4095 case OMAP_DSS_DSI_FMT_RGB666_PACKED:
4096 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18;
4098 case OMAP_DSS_DSI_FMT_RGB565:
4099 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16;
4106 dsi_if_enable(dsidev, false);
4107 dsi_vc_enable(dsidev, channel, false);
4109 /* MODE, 1 = video mode */
4110 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 4, 4);
4112 word_count = DIV_ROUND_UP(dsi->timings.x_res * bpp, 8);
4114 dsi_vc_write_long_header(dsidev, channel, data_type,
4117 dsi_vc_enable(dsidev, channel, true);
4118 dsi_if_enable(dsidev, true);
4121 r = dss_mgr_enable(mgr);
4123 goto err_mgr_enable;
4128 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
4129 dsi_if_enable(dsidev, false);
4130 dsi_vc_enable(dsidev, channel, false);
4133 dsi_display_uninit_dispc(dsidev, mgr);
4138 static void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel)
4140 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4141 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4142 struct omap_overlay_manager *mgr = dsi->output.manager;
4144 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
4145 dsi_if_enable(dsidev, false);
4146 dsi_vc_enable(dsidev, channel, false);
4148 /* MODE, 0 = command mode */
4149 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 0, 4, 4);
4151 dsi_vc_enable(dsidev, channel, true);
4152 dsi_if_enable(dsidev, true);
4155 dss_mgr_disable(mgr);
4157 dsi_display_uninit_dispc(dsidev, mgr);
4160 static void dsi_update_screen_dispc(struct platform_device *dsidev)
4162 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4163 struct omap_overlay_manager *mgr = dsi->output.manager;
4168 unsigned packet_payload;
4169 unsigned packet_len;
4172 const unsigned channel = dsi->update_channel;
4173 const unsigned line_buf_size = dsi->line_buffer_size;
4174 u16 w = dsi->timings.x_res;
4175 u16 h = dsi->timings.y_res;
4177 DSSDBG("dsi_update_screen_dispc(%dx%d)\n", w, h);
4179 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_VP);
4181 bytespp = dsi_get_pixel_size(dsi->pix_fmt) / 8;
4182 bytespl = w * bytespp;
4183 bytespf = bytespl * h;
4185 /* NOTE: packet_payload has to be equal to N * bytespl, where N is
4186 * number of lines in a packet. See errata about VP_CLK_RATIO */
4188 if (bytespf < line_buf_size)
4189 packet_payload = bytespf;
4191 packet_payload = (line_buf_size) / bytespl * bytespl;
4193 packet_len = packet_payload + 1; /* 1 byte for DCS cmd */
4194 total_len = (bytespf / packet_payload) * packet_len;
4196 if (bytespf % packet_payload)
4197 total_len += (bytespf % packet_payload) + 1;
4199 l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
4200 dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
4202 dsi_vc_write_long_header(dsidev, channel, MIPI_DSI_DCS_LONG_WRITE,
4205 if (dsi->te_enabled)
4206 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
4208 l = FLD_MOD(l, 1, 31, 31); /* TE_START */
4209 dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
4211 /* We put SIDLEMODE to no-idle for the duration of the transfer,
4212 * because DSS interrupts are not capable of waking up the CPU and the
4213 * framedone interrupt could be delayed for quite a long time. I think
4214 * the same goes for any DSS interrupts, but for some reason I have not
4215 * seen the problem anywhere else than here.
4217 dispc_disable_sidle();
4219 dsi_perf_mark_start(dsidev);
4221 r = schedule_delayed_work(&dsi->framedone_timeout_work,
4222 msecs_to_jiffies(250));
4225 dss_mgr_set_timings(mgr, &dsi->timings);
4227 dss_mgr_start_update(mgr);
4229 if (dsi->te_enabled) {
4230 /* disable LP_RX_TO, so that we can receive TE. Time to wait
4231 * for TE is longer than the timer allows */
4232 REG_FLD_MOD(dsidev, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
4234 dsi_vc_send_bta(dsidev, channel);
4236 #ifdef DSI_CATCH_MISSING_TE
4237 mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250));
4242 #ifdef DSI_CATCH_MISSING_TE
4243 static void dsi_te_timeout(unsigned long arg)
4245 DSSERR("TE not received for 250ms!\n");
4249 static void dsi_handle_framedone(struct platform_device *dsidev, int error)
4251 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4253 /* SIDLEMODE back to smart-idle */
4254 dispc_enable_sidle();
4256 if (dsi->te_enabled) {
4257 /* enable LP_RX_TO again after the TE */
4258 REG_FLD_MOD(dsidev, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
4261 dsi->framedone_callback(error, dsi->framedone_data);
4264 dsi_perf_show(dsidev, "DISPC");
4267 static void dsi_framedone_timeout_work_callback(struct work_struct *work)
4269 struct dsi_data *dsi = container_of(work, struct dsi_data,
4270 framedone_timeout_work.work);
4271 /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after
4272 * 250ms which would conflict with this timeout work. What should be
4273 * done is first cancel the transfer on the HW, and then cancel the
4274 * possibly scheduled framedone work. However, cancelling the transfer
4275 * on the HW is buggy, and would probably require resetting the whole
4278 DSSERR("Framedone not received for 250ms!\n");
4280 dsi_handle_framedone(dsi->pdev, -ETIMEDOUT);
4283 static void dsi_framedone_irq_callback(void *data)
4285 struct platform_device *dsidev = (struct platform_device *) data;
4286 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4288 /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
4289 * turns itself off. However, DSI still has the pixels in its buffers,
4290 * and is sending the data.
4293 cancel_delayed_work(&dsi->framedone_timeout_work);
4295 dsi_handle_framedone(dsidev, 0);
4298 static int dsi_update(struct omap_dss_device *dssdev, int channel,
4299 void (*callback)(int, void *), void *data)
4301 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4302 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4305 dsi_perf_mark_setup(dsidev);
4307 dsi->update_channel = channel;
4309 dsi->framedone_callback = callback;
4310 dsi->framedone_data = data;
4312 dw = dsi->timings.x_res;
4313 dh = dsi->timings.y_res;
4315 #ifdef DSI_PERF_MEASURE
4316 dsi->update_bytes = dw * dh *
4317 dsi_get_pixel_size(dsi->pix_fmt) / 8;
4319 dsi_update_screen_dispc(dsidev);
4326 static int dsi_configure_dispc_clocks(struct platform_device *dsidev)
4328 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4329 struct dispc_clock_info dispc_cinfo;
4333 fck = dsi_get_pll_hsdiv_dispc_rate(dsidev);
4335 dispc_cinfo.lck_div = dsi->user_dispc_cinfo.lck_div;
4336 dispc_cinfo.pck_div = dsi->user_dispc_cinfo.pck_div;
4338 r = dispc_calc_clock_rates(fck, &dispc_cinfo);
4340 DSSERR("Failed to calc dispc clocks\n");
4344 dsi->mgr_config.clock_info = dispc_cinfo;
4349 static int dsi_display_init_dispc(struct platform_device *dsidev,
4350 struct omap_overlay_manager *mgr)
4352 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4355 dss_select_lcd_clk_source(mgr->id, dsi->module_id == 0 ?
4356 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC :
4357 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC);
4359 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) {
4360 r = dss_mgr_register_framedone_handler(mgr,
4361 dsi_framedone_irq_callback, dsidev);
4363 DSSERR("can't register FRAMEDONE handler\n");
4367 dsi->mgr_config.stallmode = true;
4368 dsi->mgr_config.fifohandcheck = true;
4370 dsi->mgr_config.stallmode = false;
4371 dsi->mgr_config.fifohandcheck = false;
4375 * override interlace, logic level and edge related parameters in
4376 * omap_video_timings with default values
4378 dsi->timings.interlace = false;
4379 dsi->timings.hsync_level = OMAPDSS_SIG_ACTIVE_HIGH;
4380 dsi->timings.vsync_level = OMAPDSS_SIG_ACTIVE_HIGH;
4381 dsi->timings.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
4382 dsi->timings.de_level = OMAPDSS_SIG_ACTIVE_HIGH;
4383 dsi->timings.sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES;
4385 dss_mgr_set_timings(mgr, &dsi->timings);
4387 r = dsi_configure_dispc_clocks(dsidev);
4391 dsi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
4392 dsi->mgr_config.video_port_width =
4393 dsi_get_pixel_size(dsi->pix_fmt);
4394 dsi->mgr_config.lcden_sig_polarity = 0;
4396 dss_mgr_set_lcd_config(mgr, &dsi->mgr_config);
4400 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE)
4401 dss_mgr_unregister_framedone_handler(mgr,
4402 dsi_framedone_irq_callback, dsidev);
4404 dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK);
4408 static void dsi_display_uninit_dispc(struct platform_device *dsidev,
4409 struct omap_overlay_manager *mgr)
4411 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4413 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE)
4414 dss_mgr_unregister_framedone_handler(mgr,
4415 dsi_framedone_irq_callback, dsidev);
4417 dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK);
4420 static int dsi_configure_dsi_clocks(struct platform_device *dsidev)
4422 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4423 struct dsi_clock_info cinfo;
4426 cinfo = dsi->user_dsi_cinfo;
4428 r = dsi_calc_clock_rates(dsidev, &cinfo);
4430 DSSERR("Failed to calc dsi clocks\n");
4434 r = dsi_pll_set_clock_div(dsidev, &cinfo);
4436 DSSERR("Failed to set dsi clocks\n");
4443 static int dsi_display_init_dsi(struct platform_device *dsidev)
4445 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4448 r = dsi_pll_init(dsidev, true, true);
4452 r = dsi_configure_dsi_clocks(dsidev);
4456 dss_select_dsi_clk_source(dsi->module_id, dsi->module_id == 0 ?
4457 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI :
4458 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI);
4462 r = dsi_cio_init(dsidev);
4466 _dsi_print_reset_status(dsidev);
4468 dsi_proto_timings(dsidev);
4469 dsi_set_lp_clk_divisor(dsidev);
4472 _dsi_print_reset_status(dsidev);
4474 r = dsi_proto_config(dsidev);
4478 /* enable interface */
4479 dsi_vc_enable(dsidev, 0, 1);
4480 dsi_vc_enable(dsidev, 1, 1);
4481 dsi_vc_enable(dsidev, 2, 1);
4482 dsi_vc_enable(dsidev, 3, 1);
4483 dsi_if_enable(dsidev, 1);
4484 dsi_force_tx_stop_mode_io(dsidev);
4488 dsi_cio_uninit(dsidev);
4490 dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK);
4492 dsi_pll_uninit(dsidev, true);
4497 static void dsi_display_uninit_dsi(struct platform_device *dsidev,
4498 bool disconnect_lanes, bool enter_ulps)
4500 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4502 if (enter_ulps && !dsi->ulps_enabled)
4503 dsi_enter_ulps(dsidev);
4505 /* disable interface */
4506 dsi_if_enable(dsidev, 0);
4507 dsi_vc_enable(dsidev, 0, 0);
4508 dsi_vc_enable(dsidev, 1, 0);
4509 dsi_vc_enable(dsidev, 2, 0);
4510 dsi_vc_enable(dsidev, 3, 0);
4512 dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK);
4513 dsi_cio_uninit(dsidev);
4514 dsi_pll_uninit(dsidev, disconnect_lanes);
4517 static int dsi_display_enable(struct omap_dss_device *dssdev)
4519 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4520 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4523 DSSDBG("dsi_display_enable\n");
4525 WARN_ON(!dsi_bus_is_locked(dsidev));
4527 mutex_lock(&dsi->lock);
4529 r = dsi_runtime_get(dsidev);
4533 dsi_enable_pll_clock(dsidev, 1);
4535 _dsi_initialize_irq(dsidev);
4537 r = dsi_display_init_dsi(dsidev);
4541 mutex_unlock(&dsi->lock);
4546 dsi_enable_pll_clock(dsidev, 0);
4547 dsi_runtime_put(dsidev);
4549 mutex_unlock(&dsi->lock);
4550 DSSDBG("dsi_display_enable FAILED\n");
4554 static void dsi_display_disable(struct omap_dss_device *dssdev,
4555 bool disconnect_lanes, bool enter_ulps)
4557 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4558 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4560 DSSDBG("dsi_display_disable\n");
4562 WARN_ON(!dsi_bus_is_locked(dsidev));
4564 mutex_lock(&dsi->lock);
4566 dsi_sync_vc(dsidev, 0);
4567 dsi_sync_vc(dsidev, 1);
4568 dsi_sync_vc(dsidev, 2);
4569 dsi_sync_vc(dsidev, 3);
4571 dsi_display_uninit_dsi(dsidev, disconnect_lanes, enter_ulps);
4573 dsi_runtime_put(dsidev);
4574 dsi_enable_pll_clock(dsidev, 0);
4576 mutex_unlock(&dsi->lock);
4579 static int dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
4581 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4582 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4584 dsi->te_enabled = enable;
4588 #ifdef PRINT_VERBOSE_VM_TIMINGS
4589 static void print_dsi_vm(const char *str,
4590 const struct omap_dss_dsi_videomode_timings *t)
4592 unsigned long byteclk = t->hsclk / 4;
4593 int bl, wc, pps, tot;
4595 wc = DIV_ROUND_UP(t->hact * t->bitspp, 8);
4596 pps = DIV_ROUND_UP(wc + 6, t->ndl); /* pixel packet size */
4597 bl = t->hss + t->hsa + t->hse + t->hbp + t->hfp;
4600 #define TO_DSI_T(x) ((u32)div64_u64((u64)x * 1000000000llu, byteclk))
4602 pr_debug("%s bck %lu, %u/%u/%u/%u/%u/%u = %u+%u = %u, "
4603 "%u/%u/%u/%u/%u/%u = %u + %u = %u\n",
4606 t->hss, t->hsa, t->hse, t->hbp, pps, t->hfp,
4622 static void print_dispc_vm(const char *str, const struct omap_video_timings *t)
4624 unsigned long pck = t->pixelclock;
4628 bl = t->hsw + t->hbp + t->hfp;
4631 #define TO_DISPC_T(x) ((u32)div64_u64((u64)x * 1000000000llu, pck))
4633 pr_debug("%s pck %lu, %u/%u/%u/%u = %u+%u = %u, "
4634 "%u/%u/%u/%u = %u + %u = %u\n",
4637 t->hsw, t->hbp, hact, t->hfp,
4649 /* note: this is not quite accurate */
4650 static void print_dsi_dispc_vm(const char *str,
4651 const struct omap_dss_dsi_videomode_timings *t)
4653 struct omap_video_timings vm = { 0 };
4654 unsigned long byteclk = t->hsclk / 4;
4657 int dsi_hact, dsi_htot;
4659 dsi_tput = (u64)byteclk * t->ndl * 8;
4660 pck = (u32)div64_u64(dsi_tput, t->bitspp);
4661 dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(t->hact * t->bitspp, 8) + 6, t->ndl);
4662 dsi_htot = t->hss + t->hsa + t->hse + t->hbp + dsi_hact + t->hfp;
4664 vm.pixelclock = pck;
4665 vm.hsw = div64_u64((u64)(t->hsa + t->hse) * pck, byteclk);
4666 vm.hbp = div64_u64((u64)t->hbp * pck, byteclk);
4667 vm.hfp = div64_u64((u64)t->hfp * pck, byteclk);
4670 print_dispc_vm(str, &vm);
4672 #endif /* PRINT_VERBOSE_VM_TIMINGS */
4674 static bool dsi_cm_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
4675 unsigned long pck, void *data)
4677 struct dsi_clk_calc_ctx *ctx = data;
4678 struct omap_video_timings *t = &ctx->dispc_vm;
4680 ctx->dispc_cinfo.lck_div = lckd;
4681 ctx->dispc_cinfo.pck_div = pckd;
4682 ctx->dispc_cinfo.lck = lck;
4683 ctx->dispc_cinfo.pck = pck;
4685 *t = *ctx->config->timings;
4686 t->pixelclock = pck;
4687 t->x_res = ctx->config->timings->x_res;
4688 t->y_res = ctx->config->timings->y_res;
4689 t->hsw = t->hfp = t->hbp = t->vsw = 1;
4690 t->vfp = t->vbp = 0;
4695 static bool dsi_cm_calc_hsdiv_cb(int regm_dispc, unsigned long dispc,
4698 struct dsi_clk_calc_ctx *ctx = data;
4700 ctx->dsi_cinfo.regm_dispc = regm_dispc;
4701 ctx->dsi_cinfo.dsi_pll_hsdiv_dispc_clk = dispc;
4703 return dispc_div_calc(dispc, ctx->req_pck_min, ctx->req_pck_max,
4704 dsi_cm_calc_dispc_cb, ctx);
4707 static bool dsi_cm_calc_pll_cb(int regn, int regm, unsigned long fint,
4708 unsigned long pll, void *data)
4710 struct dsi_clk_calc_ctx *ctx = data;
4712 ctx->dsi_cinfo.regn = regn;
4713 ctx->dsi_cinfo.regm = regm;
4714 ctx->dsi_cinfo.fint = fint;
4715 ctx->dsi_cinfo.clkin4ddr = pll;
4717 return dsi_hsdiv_calc(ctx->dsidev, pll, ctx->req_pck_min,
4718 dsi_cm_calc_hsdiv_cb, ctx);
4721 static bool dsi_cm_calc(struct dsi_data *dsi,
4722 const struct omap_dss_dsi_config *cfg,
4723 struct dsi_clk_calc_ctx *ctx)
4725 unsigned long clkin;
4727 unsigned long pll_min, pll_max;
4728 unsigned long pck, txbyteclk;
4730 clkin = clk_get_rate(dsi->sys_clk);
4731 bitspp = dsi_get_pixel_size(cfg->pixel_format);
4732 ndl = dsi->num_lanes_used - 1;
4735 * Here we should calculate minimum txbyteclk to be able to send the
4736 * frame in time, and also to handle TE. That's not very simple, though,
4737 * especially as we go to LP between each pixel packet due to HW
4738 * "feature". So let's just estimate very roughly and multiply by 1.5.
4740 pck = cfg->timings->pixelclock;
4742 txbyteclk = pck * bitspp / 8 / ndl;
4744 memset(ctx, 0, sizeof(*ctx));
4745 ctx->dsidev = dsi->pdev;
4747 ctx->req_pck_min = pck;
4748 ctx->req_pck_nom = pck;
4749 ctx->req_pck_max = pck * 3 / 2;
4750 ctx->dsi_cinfo.clkin = clkin;
4752 pll_min = max(cfg->hs_clk_min * 4, txbyteclk * 4 * 4);
4753 pll_max = cfg->hs_clk_max * 4;
4755 return dsi_pll_calc(dsi->pdev, clkin,
4757 dsi_cm_calc_pll_cb, ctx);
4760 static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx)
4762 struct dsi_data *dsi = dsi_get_dsidrv_data(ctx->dsidev);
4763 const struct omap_dss_dsi_config *cfg = ctx->config;
4764 int bitspp = dsi_get_pixel_size(cfg->pixel_format);
4765 int ndl = dsi->num_lanes_used - 1;
4766 unsigned long hsclk = ctx->dsi_cinfo.clkin4ddr / 4;
4767 unsigned long byteclk = hsclk / 4;
4769 unsigned long dispc_pck, req_pck_min, req_pck_nom, req_pck_max;
4771 int panel_htot, panel_hbl; /* pixels */
4772 int dispc_htot, dispc_hbl; /* pixels */
4773 int dsi_htot, dsi_hact, dsi_hbl, hss, hse; /* byteclks */
4775 const struct omap_video_timings *req_vm;
4776 struct omap_video_timings *dispc_vm;
4777 struct omap_dss_dsi_videomode_timings *dsi_vm;
4778 u64 dsi_tput, dispc_tput;
4780 dsi_tput = (u64)byteclk * ndl * 8;
4782 req_vm = cfg->timings;
4783 req_pck_min = ctx->req_pck_min;
4784 req_pck_max = ctx->req_pck_max;
4785 req_pck_nom = ctx->req_pck_nom;
4787 dispc_pck = ctx->dispc_cinfo.pck;
4788 dispc_tput = (u64)dispc_pck * bitspp;
4790 xres = req_vm->x_res;
4792 panel_hbl = req_vm->hfp + req_vm->hbp + req_vm->hsw;
4793 panel_htot = xres + panel_hbl;
4795 dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(xres * bitspp, 8) + 6, ndl);
4798 * When there are no line buffers, DISPC and DSI must have the
4799 * same tput. Otherwise DISPC tput needs to be higher than DSI's.
4801 if (dsi->line_buffer_size < xres * bitspp / 8) {
4802 if (dispc_tput != dsi_tput)
4805 if (dispc_tput < dsi_tput)
4809 /* DSI tput must be over the min requirement */
4810 if (dsi_tput < (u64)bitspp * req_pck_min)
4813 /* When non-burst mode, DSI tput must be below max requirement. */
4814 if (cfg->trans_mode != OMAP_DSS_DSI_BURST_MODE) {
4815 if (dsi_tput > (u64)bitspp * req_pck_max)
4819 hss = DIV_ROUND_UP(4, ndl);
4821 if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) {
4822 if (ndl == 3 && req_vm->hsw == 0)
4825 hse = DIV_ROUND_UP(4, ndl);
4830 /* DSI htot to match the panel's nominal pck */
4831 dsi_htot = div64_u64((u64)panel_htot * byteclk, req_pck_nom);
4833 /* fail if there would be no time for blanking */
4834 if (dsi_htot < hss + hse + dsi_hact)
4837 /* total DSI blanking needed to achieve panel's TL */
4838 dsi_hbl = dsi_htot - dsi_hact;
4840 /* DISPC htot to match the DSI TL */
4841 dispc_htot = div64_u64((u64)dsi_htot * dispc_pck, byteclk);
4843 /* verify that the DSI and DISPC TLs are the same */
4844 if ((u64)dsi_htot * dispc_pck != (u64)dispc_htot * byteclk)
4847 dispc_hbl = dispc_htot - xres;
4849 /* setup DSI videomode */
4851 dsi_vm = &ctx->dsi_vm;
4852 memset(dsi_vm, 0, sizeof(*dsi_vm));
4854 dsi_vm->hsclk = hsclk;
4857 dsi_vm->bitspp = bitspp;
4859 if (cfg->trans_mode != OMAP_DSS_DSI_PULSE_MODE) {
4861 } else if (ndl == 3 && req_vm->hsw == 0) {
4864 hsa = div64_u64((u64)req_vm->hsw * byteclk, req_pck_nom);
4865 hsa = max(hsa - hse, 1);
4868 hbp = div64_u64((u64)req_vm->hbp * byteclk, req_pck_nom);
4871 hfp = dsi_hbl - (hss + hsa + hse + hbp);
4874 /* we need to take cycles from hbp */
4877 hbp = max(hbp - t, 1);
4878 hfp = dsi_hbl - (hss + hsa + hse + hbp);
4880 if (hfp < 1 && hsa > 0) {
4881 /* we need to take cycles from hsa */
4883 hsa = max(hsa - t, 1);
4884 hfp = dsi_hbl - (hss + hsa + hse + hbp);
4895 dsi_vm->hact = xres;
4898 dsi_vm->vsa = req_vm->vsw;
4899 dsi_vm->vbp = req_vm->vbp;
4900 dsi_vm->vact = req_vm->y_res;
4901 dsi_vm->vfp = req_vm->vfp;
4903 dsi_vm->trans_mode = cfg->trans_mode;
4905 dsi_vm->blanking_mode = 0;
4906 dsi_vm->hsa_blanking_mode = 1;
4907 dsi_vm->hfp_blanking_mode = 1;
4908 dsi_vm->hbp_blanking_mode = 1;
4910 dsi_vm->ddr_clk_always_on = cfg->ddr_clk_always_on;
4911 dsi_vm->window_sync = 4;
4913 /* setup DISPC videomode */
4915 dispc_vm = &ctx->dispc_vm;
4916 *dispc_vm = *req_vm;
4917 dispc_vm->pixelclock = dispc_pck;
4919 if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) {
4920 hsa = div64_u64((u64)req_vm->hsw * dispc_pck,
4927 hbp = div64_u64((u64)req_vm->hbp * dispc_pck, req_pck_nom);
4930 hfp = dispc_hbl - hsa - hbp;
4933 /* we need to take cycles from hbp */
4936 hbp = max(hbp - t, 1);
4937 hfp = dispc_hbl - hsa - hbp;
4940 /* we need to take cycles from hsa */
4942 hsa = max(hsa - t, 1);
4943 hfp = dispc_hbl - hsa - hbp;
4950 dispc_vm->hfp = hfp;
4951 dispc_vm->hsw = hsa;
4952 dispc_vm->hbp = hbp;
4958 static bool dsi_vm_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
4959 unsigned long pck, void *data)
4961 struct dsi_clk_calc_ctx *ctx = data;
4963 ctx->dispc_cinfo.lck_div = lckd;
4964 ctx->dispc_cinfo.pck_div = pckd;
4965 ctx->dispc_cinfo.lck = lck;
4966 ctx->dispc_cinfo.pck = pck;
4968 if (dsi_vm_calc_blanking(ctx) == false)
4971 #ifdef PRINT_VERBOSE_VM_TIMINGS
4972 print_dispc_vm("dispc", &ctx->dispc_vm);
4973 print_dsi_vm("dsi ", &ctx->dsi_vm);
4974 print_dispc_vm("req ", ctx->config->timings);
4975 print_dsi_dispc_vm("act ", &ctx->dsi_vm);
4981 static bool dsi_vm_calc_hsdiv_cb(int regm_dispc, unsigned long dispc,
4984 struct dsi_clk_calc_ctx *ctx = data;
4985 unsigned long pck_max;
4987 ctx->dsi_cinfo.regm_dispc = regm_dispc;
4988 ctx->dsi_cinfo.dsi_pll_hsdiv_dispc_clk = dispc;
4991 * In burst mode we can let the dispc pck be arbitrarily high, but it
4992 * limits our scaling abilities. So for now, don't aim too high.
4995 if (ctx->config->trans_mode == OMAP_DSS_DSI_BURST_MODE)
4996 pck_max = ctx->req_pck_max + 10000000;
4998 pck_max = ctx->req_pck_max;
5000 return dispc_div_calc(dispc, ctx->req_pck_min, pck_max,
5001 dsi_vm_calc_dispc_cb, ctx);
5004 static bool dsi_vm_calc_pll_cb(int regn, int regm, unsigned long fint,
5005 unsigned long pll, void *data)
5007 struct dsi_clk_calc_ctx *ctx = data;
5009 ctx->dsi_cinfo.regn = regn;
5010 ctx->dsi_cinfo.regm = regm;
5011 ctx->dsi_cinfo.fint = fint;
5012 ctx->dsi_cinfo.clkin4ddr = pll;
5014 return dsi_hsdiv_calc(ctx->dsidev, pll, ctx->req_pck_min,
5015 dsi_vm_calc_hsdiv_cb, ctx);
5018 static bool dsi_vm_calc(struct dsi_data *dsi,
5019 const struct omap_dss_dsi_config *cfg,
5020 struct dsi_clk_calc_ctx *ctx)
5022 const struct omap_video_timings *t = cfg->timings;
5023 unsigned long clkin;
5024 unsigned long pll_min;
5025 unsigned long pll_max;
5026 int ndl = dsi->num_lanes_used - 1;
5027 int bitspp = dsi_get_pixel_size(cfg->pixel_format);
5028 unsigned long byteclk_min;
5030 clkin = clk_get_rate(dsi->sys_clk);
5032 memset(ctx, 0, sizeof(*ctx));
5033 ctx->dsidev = dsi->pdev;
5036 ctx->dsi_cinfo.clkin = clkin;
5038 /* these limits should come from the panel driver */
5039 ctx->req_pck_min = t->pixelclock - 1000;
5040 ctx->req_pck_nom = t->pixelclock;
5041 ctx->req_pck_max = t->pixelclock + 1000;
5043 byteclk_min = div64_u64((u64)ctx->req_pck_min * bitspp, ndl * 8);
5044 pll_min = max(cfg->hs_clk_min * 4, byteclk_min * 4 * 4);
5046 if (cfg->trans_mode == OMAP_DSS_DSI_BURST_MODE) {
5047 pll_max = cfg->hs_clk_max * 4;
5049 unsigned long byteclk_max;
5050 byteclk_max = div64_u64((u64)ctx->req_pck_max * bitspp,
5053 pll_max = byteclk_max * 4 * 4;
5056 return dsi_pll_calc(dsi->pdev, clkin,
5058 dsi_vm_calc_pll_cb, ctx);
5061 static int dsi_set_config(struct omap_dss_device *dssdev,
5062 const struct omap_dss_dsi_config *config)
5064 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
5065 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5066 struct dsi_clk_calc_ctx ctx;
5070 mutex_lock(&dsi->lock);
5072 dsi->pix_fmt = config->pixel_format;
5073 dsi->mode = config->mode;
5075 if (config->mode == OMAP_DSS_DSI_VIDEO_MODE)
5076 ok = dsi_vm_calc(dsi, config, &ctx);
5078 ok = dsi_cm_calc(dsi, config, &ctx);
5081 DSSERR("failed to find suitable DSI clock settings\n");
5086 dsi_pll_calc_dsi_fck(&ctx.dsi_cinfo);
5088 r = dsi_lp_clock_calc(&ctx.dsi_cinfo, config->lp_clk_min,
5089 config->lp_clk_max);
5091 DSSERR("failed to find suitable DSI LP clock settings\n");
5095 dsi->user_dsi_cinfo = ctx.dsi_cinfo;
5096 dsi->user_dispc_cinfo = ctx.dispc_cinfo;
5098 dsi->timings = ctx.dispc_vm;
5099 dsi->vm_timings = ctx.dsi_vm;
5101 mutex_unlock(&dsi->lock);
5105 mutex_unlock(&dsi->lock);
5111 * Return a hardcoded channel for the DSI output. This should work for
5112 * current use cases, but this can be later expanded to either resolve
5113 * the channel in some more dynamic manner, or get the channel as a user
5116 static enum omap_channel dsi_get_channel(int module_id)
5118 switch (omapdss_get_version()) {
5119 case OMAPDSS_VER_OMAP24xx:
5120 DSSWARN("DSI not supported\n");
5121 return OMAP_DSS_CHANNEL_LCD;
5123 case OMAPDSS_VER_OMAP34xx_ES1:
5124 case OMAPDSS_VER_OMAP34xx_ES3:
5125 case OMAPDSS_VER_OMAP3630:
5126 case OMAPDSS_VER_AM35xx:
5127 return OMAP_DSS_CHANNEL_LCD;
5129 case OMAPDSS_VER_OMAP4430_ES1:
5130 case OMAPDSS_VER_OMAP4430_ES2:
5131 case OMAPDSS_VER_OMAP4:
5132 switch (module_id) {
5134 return OMAP_DSS_CHANNEL_LCD;
5136 return OMAP_DSS_CHANNEL_LCD2;
5138 DSSWARN("unsupported module id\n");
5139 return OMAP_DSS_CHANNEL_LCD;
5142 case OMAPDSS_VER_OMAP5:
5143 switch (module_id) {
5145 return OMAP_DSS_CHANNEL_LCD;
5147 return OMAP_DSS_CHANNEL_LCD3;
5149 DSSWARN("unsupported module id\n");
5150 return OMAP_DSS_CHANNEL_LCD;
5154 DSSWARN("unsupported DSS version\n");
5155 return OMAP_DSS_CHANNEL_LCD;
5159 static int dsi_request_vc(struct omap_dss_device *dssdev, int *channel)
5161 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
5162 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5165 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
5166 if (!dsi->vc[i].dssdev) {
5167 dsi->vc[i].dssdev = dssdev;
5173 DSSERR("cannot get VC for display %s", dssdev->name);
5177 static int dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id)
5179 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
5180 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5182 if (vc_id < 0 || vc_id > 3) {
5183 DSSERR("VC ID out of range\n");
5187 if (channel < 0 || channel > 3) {
5188 DSSERR("Virtual Channel out of range\n");
5192 if (dsi->vc[channel].dssdev != dssdev) {
5193 DSSERR("Virtual Channel not allocated to display %s\n",
5198 dsi->vc[channel].vc_id = vc_id;
5203 static void dsi_release_vc(struct omap_dss_device *dssdev, int channel)
5205 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
5206 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5208 if ((channel >= 0 && channel <= 3) &&
5209 dsi->vc[channel].dssdev == dssdev) {
5210 dsi->vc[channel].dssdev = NULL;
5211 dsi->vc[channel].vc_id = 0;
5215 void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev)
5217 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 7, 1) != 1)
5218 DSSERR("%s (%s) not active\n",
5219 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
5220 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC));
5223 void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev)
5225 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 8, 1) != 1)
5226 DSSERR("%s (%s) not active\n",
5227 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
5228 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI));
5231 static void dsi_calc_clock_param_ranges(struct platform_device *dsidev)
5233 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5235 dsi->regn_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGN);
5236 dsi->regm_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM);
5237 dsi->regm_dispc_max =
5238 dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DISPC);
5239 dsi->regm_dsi_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DSI);
5240 dsi->fint_min = dss_feat_get_param_min(FEAT_PARAM_DSIPLL_FINT);
5241 dsi->fint_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_FINT);
5242 dsi->lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV);
5245 static int dsi_get_clocks(struct platform_device *dsidev)
5247 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5250 clk = devm_clk_get(&dsidev->dev, "fck");
5252 DSSERR("can't get fck\n");
5253 return PTR_ERR(clk);
5258 clk = devm_clk_get(&dsidev->dev, "sys_clk");
5260 DSSERR("can't get sys_clk\n");
5261 return PTR_ERR(clk);
5269 static int dsi_connect(struct omap_dss_device *dssdev,
5270 struct omap_dss_device *dst)
5272 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
5273 struct omap_overlay_manager *mgr;
5276 r = dsi_regulator_init(dsidev);
5280 mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel);
5284 r = dss_mgr_connect(mgr, dssdev);
5288 r = omapdss_output_set_device(dssdev, dst);
5290 DSSERR("failed to connect output to new device: %s\n",
5292 dss_mgr_disconnect(mgr, dssdev);
5299 static void dsi_disconnect(struct omap_dss_device *dssdev,
5300 struct omap_dss_device *dst)
5302 WARN_ON(dst != dssdev->dst);
5304 if (dst != dssdev->dst)
5307 omapdss_output_unset_device(dssdev);
5309 if (dssdev->manager)
5310 dss_mgr_disconnect(dssdev->manager, dssdev);
5313 static const struct omapdss_dsi_ops dsi_ops = {
5314 .connect = dsi_connect,
5315 .disconnect = dsi_disconnect,
5317 .bus_lock = dsi_bus_lock,
5318 .bus_unlock = dsi_bus_unlock,
5320 .enable = dsi_display_enable,
5321 .disable = dsi_display_disable,
5323 .enable_hs = dsi_vc_enable_hs,
5325 .configure_pins = dsi_configure_pins,
5326 .set_config = dsi_set_config,
5328 .enable_video_output = dsi_enable_video_output,
5329 .disable_video_output = dsi_disable_video_output,
5331 .update = dsi_update,
5333 .enable_te = dsi_enable_te,
5335 .request_vc = dsi_request_vc,
5336 .set_vc_id = dsi_set_vc_id,
5337 .release_vc = dsi_release_vc,
5339 .dcs_write = dsi_vc_dcs_write,
5340 .dcs_write_nosync = dsi_vc_dcs_write_nosync,
5341 .dcs_read = dsi_vc_dcs_read,
5343 .gen_write = dsi_vc_generic_write,
5344 .gen_write_nosync = dsi_vc_generic_write_nosync,
5345 .gen_read = dsi_vc_generic_read,
5347 .bta_sync = dsi_vc_send_bta_sync,
5349 .set_max_rx_packet_size = dsi_vc_set_max_rx_packet_size,
5352 static void dsi_init_output(struct platform_device *dsidev)
5354 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5355 struct omap_dss_device *out = &dsi->output;
5357 out->dev = &dsidev->dev;
5358 out->id = dsi->module_id == 0 ?
5359 OMAP_DSS_OUTPUT_DSI1 : OMAP_DSS_OUTPUT_DSI2;
5361 out->output_type = OMAP_DISPLAY_TYPE_DSI;
5362 out->name = dsi->module_id == 0 ? "dsi.0" : "dsi.1";
5363 out->dispc_channel = dsi_get_channel(dsi->module_id);
5364 out->ops.dsi = &dsi_ops;
5365 out->owner = THIS_MODULE;
5367 omapdss_register_output(out);
5370 static void dsi_uninit_output(struct platform_device *dsidev)
5372 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5373 struct omap_dss_device *out = &dsi->output;
5375 omapdss_unregister_output(out);
5378 static int dsi_probe_of(struct platform_device *pdev)
5380 struct device_node *node = pdev->dev.of_node;
5381 struct dsi_data *dsi = dsi_get_dsidrv_data(pdev);
5382 struct property *prop;
5386 struct device_node *ep;
5387 struct omap_dsi_pin_config pin_cfg;
5389 ep = omapdss_of_get_first_endpoint(node);
5393 prop = of_find_property(ep, "lanes", &len);
5395 dev_err(&pdev->dev, "failed to find lane data\n");
5400 num_pins = len / sizeof(u32);
5402 if (num_pins < 4 || num_pins % 2 != 0 ||
5403 num_pins > dsi->num_lanes_supported * 2) {
5404 dev_err(&pdev->dev, "bad number of lanes\n");
5409 r = of_property_read_u32_array(ep, "lanes", lane_arr, num_pins);
5411 dev_err(&pdev->dev, "failed to read lane data\n");
5415 pin_cfg.num_pins = num_pins;
5416 for (i = 0; i < num_pins; ++i)
5417 pin_cfg.pins[i] = (int)lane_arr[i];
5419 r = dsi_configure_pins(&dsi->output, &pin_cfg);
5421 dev_err(&pdev->dev, "failed to configure pins");
5434 /* DSI1 HW IP initialisation */
5435 static int omap_dsihw_probe(struct platform_device *dsidev)
5439 struct dsi_data *dsi;
5440 struct resource *dsi_mem;
5441 struct resource *res;
5442 struct resource temp_res;
5444 dsi = devm_kzalloc(&dsidev->dev, sizeof(*dsi), GFP_KERNEL);
5449 dev_set_drvdata(&dsidev->dev, dsi);
5451 spin_lock_init(&dsi->irq_lock);
5452 spin_lock_init(&dsi->errors_lock);
5455 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
5456 spin_lock_init(&dsi->irq_stats_lock);
5457 dsi->irq_stats.last_reset = jiffies;
5460 mutex_init(&dsi->lock);
5461 sema_init(&dsi->bus_lock, 1);
5463 INIT_DEFERRABLE_WORK(&dsi->framedone_timeout_work,
5464 dsi_framedone_timeout_work_callback);
5466 #ifdef DSI_CATCH_MISSING_TE
5467 init_timer(&dsi->te_timer);
5468 dsi->te_timer.function = dsi_te_timeout;
5469 dsi->te_timer.data = 0;
5472 res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "proto");
5474 res = platform_get_resource(dsidev, IORESOURCE_MEM, 0);
5476 DSSERR("can't get IORESOURCE_MEM DSI\n");
5480 temp_res.start = res->start;
5481 temp_res.end = temp_res.start + DSI_PROTO_SZ - 1;
5487 dsi->proto_base = devm_ioremap(&dsidev->dev, res->start,
5488 resource_size(res));
5489 if (!dsi->proto_base) {
5490 DSSERR("can't ioremap DSI protocol engine\n");
5494 res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "phy");
5496 res = platform_get_resource(dsidev, IORESOURCE_MEM, 0);
5498 DSSERR("can't get IORESOURCE_MEM DSI\n");
5502 temp_res.start = res->start + DSI_PHY_OFFSET;
5503 temp_res.end = temp_res.start + DSI_PHY_SZ - 1;
5507 dsi->phy_base = devm_ioremap(&dsidev->dev, res->start,
5508 resource_size(res));
5509 if (!dsi->proto_base) {
5510 DSSERR("can't ioremap DSI PHY\n");
5514 res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "pll");
5516 res = platform_get_resource(dsidev, IORESOURCE_MEM, 0);
5518 DSSERR("can't get IORESOURCE_MEM DSI\n");
5522 temp_res.start = res->start + DSI_PLL_OFFSET;
5523 temp_res.end = temp_res.start + DSI_PLL_SZ - 1;
5527 dsi->pll_base = devm_ioremap(&dsidev->dev, res->start,
5528 resource_size(res));
5529 if (!dsi->proto_base) {
5530 DSSERR("can't ioremap DSI PLL\n");
5534 dsi->irq = platform_get_irq(dsi->pdev, 0);
5536 DSSERR("platform_get_irq failed\n");
5540 r = devm_request_irq(&dsidev->dev, dsi->irq, omap_dsi_irq_handler,
5541 IRQF_SHARED, dev_name(&dsidev->dev), dsi->pdev);
5543 DSSERR("request_irq failed\n");
5547 if (dsidev->dev.of_node) {
5548 const struct of_device_id *match;
5549 const struct dsi_module_id_data *d;
5551 match = of_match_node(dsi_of_match, dsidev->dev.of_node);
5553 DSSERR("unsupported DSI module\n");
5559 while (d->address != 0 && d->address != dsi_mem->start)
5562 if (d->address == 0) {
5563 DSSERR("unsupported DSI module\n");
5567 dsi->module_id = d->id;
5569 dsi->module_id = dsidev->id;
5572 /* DSI VCs initialization */
5573 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
5574 dsi->vc[i].source = DSI_VC_SOURCE_L4;
5575 dsi->vc[i].dssdev = NULL;
5576 dsi->vc[i].vc_id = 0;
5579 dsi_calc_clock_param_ranges(dsidev);
5581 r = dsi_get_clocks(dsidev);
5585 pm_runtime_enable(&dsidev->dev);
5587 r = dsi_runtime_get(dsidev);
5589 goto err_runtime_get;
5591 rev = dsi_read_reg(dsidev, DSI_REVISION);
5592 dev_dbg(&dsidev->dev, "OMAP DSI rev %d.%d\n",
5593 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
5595 /* DSI on OMAP3 doesn't have register DSI_GNQ, set number
5596 * of data to 3 by default */
5597 if (dss_has_feature(FEAT_DSI_GNQ))
5599 dsi->num_lanes_supported = 1 + REG_GET(dsidev, DSI_GNQ, 11, 9);
5601 dsi->num_lanes_supported = 3;
5603 dsi->line_buffer_size = dsi_get_line_buf_size(dsidev);
5605 dsi_init_output(dsidev);
5607 if (dsidev->dev.of_node) {
5608 r = dsi_probe_of(dsidev);
5610 DSSERR("Invalid DSI DT data\n");
5614 r = of_platform_populate(dsidev->dev.of_node, NULL, NULL,
5617 DSSERR("Failed to populate DSI child devices: %d\n", r);
5620 dsi_runtime_put(dsidev);
5622 if (dsi->module_id == 0)
5623 dss_debugfs_create_file("dsi1_regs", dsi1_dump_regs);
5624 else if (dsi->module_id == 1)
5625 dss_debugfs_create_file("dsi2_regs", dsi2_dump_regs);
5627 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
5628 if (dsi->module_id == 0)
5629 dss_debugfs_create_file("dsi1_irqs", dsi1_dump_irqs);
5630 else if (dsi->module_id == 1)
5631 dss_debugfs_create_file("dsi2_irqs", dsi2_dump_irqs);
5637 dsi_uninit_output(dsidev);
5638 dsi_runtime_put(dsidev);
5641 pm_runtime_disable(&dsidev->dev);
5645 static int dsi_unregister_child(struct device *dev, void *data)
5647 struct platform_device *pdev = to_platform_device(dev);
5648 platform_device_unregister(pdev);
5652 static int __exit omap_dsihw_remove(struct platform_device *dsidev)
5654 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5656 device_for_each_child(&dsidev->dev, NULL, dsi_unregister_child);
5658 WARN_ON(dsi->scp_clk_refcount > 0);
5660 dsi_uninit_output(dsidev);
5662 pm_runtime_disable(&dsidev->dev);
5664 if (dsi->vdds_dsi_reg != NULL && dsi->vdds_dsi_enabled) {
5665 regulator_disable(dsi->vdds_dsi_reg);
5666 dsi->vdds_dsi_enabled = false;
5672 static int dsi_runtime_suspend(struct device *dev)
5674 dispc_runtime_put();
5679 static int dsi_runtime_resume(struct device *dev)
5683 r = dispc_runtime_get();
5690 static const struct dev_pm_ops dsi_pm_ops = {
5691 .runtime_suspend = dsi_runtime_suspend,
5692 .runtime_resume = dsi_runtime_resume,
5695 static const struct dsi_module_id_data dsi_of_data_omap3[] = {
5696 { .address = 0x4804fc00, .id = 0, },
5700 static const struct dsi_module_id_data dsi_of_data_omap4[] = {
5701 { .address = 0x58004000, .id = 0, },
5702 { .address = 0x58005000, .id = 1, },
5706 static const struct of_device_id dsi_of_match[] = {
5707 { .compatible = "ti,omap3-dsi", .data = dsi_of_data_omap3, },
5708 { .compatible = "ti,omap4-dsi", .data = dsi_of_data_omap4, },
5712 static struct platform_driver omap_dsihw_driver = {
5713 .probe = omap_dsihw_probe,
5714 .remove = __exit_p(omap_dsihw_remove),
5716 .name = "omapdss_dsi",
5717 .owner = THIS_MODULE,
5719 .of_match_table = dsi_of_match,
5723 int __init dsi_init_platform_driver(void)
5725 return platform_driver_register(&omap_dsihw_driver);
5728 void __exit dsi_uninit_platform_driver(void)
5730 platform_driver_unregister(&omap_dsihw_driver);