2 * linux/drivers/video/omap2/dss/dsi.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #define DSS_SUBSYS_NAME "DSI"
22 #include <linux/kernel.h>
24 #include <linux/clk.h>
25 #include <linux/device.h>
26 #include <linux/err.h>
27 #include <linux/interrupt.h>
28 #include <linux/delay.h>
29 #include <linux/mutex.h>
30 #include <linux/semaphore.h>
31 #include <linux/seq_file.h>
32 #include <linux/platform_device.h>
33 #include <linux/regulator/consumer.h>
34 #include <linux/wait.h>
35 #include <linux/workqueue.h>
37 #include <plat/display.h>
38 #include <plat/clock.h>
42 /*#define VERBOSE_IRQ*/
43 #define DSI_CATCH_MISSING_TE
45 struct dsi_reg { u16 idx; };
47 #define DSI_REG(idx) ((const struct dsi_reg) { idx })
49 #define DSI_SZ_REGS SZ_1K
50 /* DSI Protocol Engine */
52 #define DSI_REVISION DSI_REG(0x0000)
53 #define DSI_SYSCONFIG DSI_REG(0x0010)
54 #define DSI_SYSSTATUS DSI_REG(0x0014)
55 #define DSI_IRQSTATUS DSI_REG(0x0018)
56 #define DSI_IRQENABLE DSI_REG(0x001C)
57 #define DSI_CTRL DSI_REG(0x0040)
58 #define DSI_COMPLEXIO_CFG1 DSI_REG(0x0048)
59 #define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(0x004C)
60 #define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(0x0050)
61 #define DSI_CLK_CTRL DSI_REG(0x0054)
62 #define DSI_TIMING1 DSI_REG(0x0058)
63 #define DSI_TIMING2 DSI_REG(0x005C)
64 #define DSI_VM_TIMING1 DSI_REG(0x0060)
65 #define DSI_VM_TIMING2 DSI_REG(0x0064)
66 #define DSI_VM_TIMING3 DSI_REG(0x0068)
67 #define DSI_CLK_TIMING DSI_REG(0x006C)
68 #define DSI_TX_FIFO_VC_SIZE DSI_REG(0x0070)
69 #define DSI_RX_FIFO_VC_SIZE DSI_REG(0x0074)
70 #define DSI_COMPLEXIO_CFG2 DSI_REG(0x0078)
71 #define DSI_RX_FIFO_VC_FULLNESS DSI_REG(0x007C)
72 #define DSI_VM_TIMING4 DSI_REG(0x0080)
73 #define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(0x0084)
74 #define DSI_VM_TIMING5 DSI_REG(0x0088)
75 #define DSI_VM_TIMING6 DSI_REG(0x008C)
76 #define DSI_VM_TIMING7 DSI_REG(0x0090)
77 #define DSI_STOPCLK_TIMING DSI_REG(0x0094)
78 #define DSI_VC_CTRL(n) DSI_REG(0x0100 + (n * 0x20))
79 #define DSI_VC_TE(n) DSI_REG(0x0104 + (n * 0x20))
80 #define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(0x0108 + (n * 0x20))
81 #define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(0x010C + (n * 0x20))
82 #define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(0x0110 + (n * 0x20))
83 #define DSI_VC_IRQSTATUS(n) DSI_REG(0x0118 + (n * 0x20))
84 #define DSI_VC_IRQENABLE(n) DSI_REG(0x011C + (n * 0x20))
88 #define DSI_DSIPHY_CFG0 DSI_REG(0x200 + 0x0000)
89 #define DSI_DSIPHY_CFG1 DSI_REG(0x200 + 0x0004)
90 #define DSI_DSIPHY_CFG2 DSI_REG(0x200 + 0x0008)
91 #define DSI_DSIPHY_CFG5 DSI_REG(0x200 + 0x0014)
93 /* DSI_PLL_CTRL_SCP */
95 #define DSI_PLL_CONTROL DSI_REG(0x300 + 0x0000)
96 #define DSI_PLL_STATUS DSI_REG(0x300 + 0x0004)
97 #define DSI_PLL_GO DSI_REG(0x300 + 0x0008)
98 #define DSI_PLL_CONFIGURATION1 DSI_REG(0x300 + 0x000C)
99 #define DSI_PLL_CONFIGURATION2 DSI_REG(0x300 + 0x0010)
101 #define REG_GET(idx, start, end) \
102 FLD_GET(dsi_read_reg(idx), start, end)
104 #define REG_FLD_MOD(idx, val, start, end) \
105 dsi_write_reg(idx, FLD_MOD(dsi_read_reg(idx), val, start, end))
107 /* Global interrupts */
108 #define DSI_IRQ_VC0 (1 << 0)
109 #define DSI_IRQ_VC1 (1 << 1)
110 #define DSI_IRQ_VC2 (1 << 2)
111 #define DSI_IRQ_VC3 (1 << 3)
112 #define DSI_IRQ_WAKEUP (1 << 4)
113 #define DSI_IRQ_RESYNC (1 << 5)
114 #define DSI_IRQ_PLL_LOCK (1 << 7)
115 #define DSI_IRQ_PLL_UNLOCK (1 << 8)
116 #define DSI_IRQ_PLL_RECALL (1 << 9)
117 #define DSI_IRQ_COMPLEXIO_ERR (1 << 10)
118 #define DSI_IRQ_HS_TX_TIMEOUT (1 << 14)
119 #define DSI_IRQ_LP_RX_TIMEOUT (1 << 15)
120 #define DSI_IRQ_TE_TRIGGER (1 << 16)
121 #define DSI_IRQ_ACK_TRIGGER (1 << 17)
122 #define DSI_IRQ_SYNC_LOST (1 << 18)
123 #define DSI_IRQ_LDO_POWER_GOOD (1 << 19)
124 #define DSI_IRQ_TA_TIMEOUT (1 << 20)
125 #define DSI_IRQ_ERROR_MASK \
126 (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
128 #define DSI_IRQ_CHANNEL_MASK 0xf
130 /* Virtual channel interrupts */
131 #define DSI_VC_IRQ_CS (1 << 0)
132 #define DSI_VC_IRQ_ECC_CORR (1 << 1)
133 #define DSI_VC_IRQ_PACKET_SENT (1 << 2)
134 #define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3)
135 #define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4)
136 #define DSI_VC_IRQ_BTA (1 << 5)
137 #define DSI_VC_IRQ_ECC_NO_CORR (1 << 6)
138 #define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7)
139 #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
140 #define DSI_VC_IRQ_ERROR_MASK \
141 (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
142 DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
143 DSI_VC_IRQ_FIFO_TX_UDF)
145 /* ComplexIO interrupts */
146 #define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0)
147 #define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1)
148 #define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2)
149 #define DSI_CIO_IRQ_ERRESC1 (1 << 5)
150 #define DSI_CIO_IRQ_ERRESC2 (1 << 6)
151 #define DSI_CIO_IRQ_ERRESC3 (1 << 7)
152 #define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10)
153 #define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11)
154 #define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12)
155 #define DSI_CIO_IRQ_STATEULPS1 (1 << 15)
156 #define DSI_CIO_IRQ_STATEULPS2 (1 << 16)
157 #define DSI_CIO_IRQ_STATEULPS3 (1 << 17)
158 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20)
159 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21)
160 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22)
161 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23)
162 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24)
163 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25)
164 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30)
165 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31)
166 #define DSI_CIO_IRQ_ERROR_MASK \
167 (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
168 DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
169 DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRCONTROL1 | \
170 DSI_CIO_IRQ_ERRCONTROL2 | DSI_CIO_IRQ_ERRCONTROL3 | \
171 DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
172 DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
173 DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3)
175 #define DSI_DT_DCS_SHORT_WRITE_0 0x05
176 #define DSI_DT_DCS_SHORT_WRITE_1 0x15
177 #define DSI_DT_DCS_READ 0x06
178 #define DSI_DT_SET_MAX_RET_PKG_SIZE 0x37
179 #define DSI_DT_NULL_PACKET 0x09
180 #define DSI_DT_DCS_LONG_WRITE 0x39
182 #define DSI_DT_RX_ACK_WITH_ERR 0x02
183 #define DSI_DT_RX_DCS_LONG_READ 0x1c
184 #define DSI_DT_RX_SHORT_READ_1 0x21
185 #define DSI_DT_RX_SHORT_READ_2 0x22
187 #define FINT_MAX 2100000
188 #define FINT_MIN 750000
189 #define REGN_MAX (1 << 7)
190 #define REGM_MAX ((1 << 11) - 1)
191 #define REGM3_MAX (1 << 4)
192 #define REGM4_MAX (1 << 4)
193 #define LP_DIV_MAX ((1 << 13) - 1)
197 DSI_FIFO_SIZE_32 = 1,
198 DSI_FIFO_SIZE_64 = 2,
199 DSI_FIFO_SIZE_96 = 3,
200 DSI_FIFO_SIZE_128 = 4,
208 struct dsi_update_region {
210 struct omap_dss_device *device;
213 struct dsi_irq_stats {
214 unsigned long last_reset;
216 unsigned dsi_irqs[32];
217 unsigned vc_irqs[4][32];
218 unsigned cio_irqs[32];
223 struct platform_device *pdev;
227 struct dsi_clock_info current_cinfo;
229 struct regulator *vdds_dsi_reg;
232 enum dsi_vc_mode mode;
233 struct omap_dss_device *dssdev;
234 enum fifo_size fifo_size;
238 struct semaphore bus_lock;
242 struct completion bta_completion;
243 void (*bta_callback)(void);
246 struct dsi_update_region update_region;
250 struct workqueue_struct *workqueue;
252 void (*framedone_callback)(int, void *);
253 void *framedone_data;
255 struct delayed_work framedone_timeout_work;
257 #ifdef DSI_CATCH_MISSING_TE
258 struct timer_list te_timer;
261 unsigned long cache_req_pck;
262 unsigned long cache_clk_freq;
263 struct dsi_clock_info cache_cinfo;
266 spinlock_t errors_lock;
268 ktime_t perf_setup_time;
269 ktime_t perf_start_time;
274 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
275 spinlock_t irq_stats_lock;
276 struct dsi_irq_stats irq_stats;
281 static unsigned int dsi_perf;
282 module_param_named(dsi_perf, dsi_perf, bool, 0644);
285 static inline void dsi_write_reg(const struct dsi_reg idx, u32 val)
287 __raw_writel(val, dsi.base + idx.idx);
290 static inline u32 dsi_read_reg(const struct dsi_reg idx)
292 return __raw_readl(dsi.base + idx.idx);
296 void dsi_save_context(void)
300 void dsi_restore_context(void)
304 void dsi_bus_lock(void)
308 EXPORT_SYMBOL(dsi_bus_lock);
310 void dsi_bus_unlock(void)
314 EXPORT_SYMBOL(dsi_bus_unlock);
316 static bool dsi_bus_is_locked(void)
318 return dsi.bus_lock.count == 0;
321 static inline int wait_for_bit_change(const struct dsi_reg idx, int bitnum,
326 while (REG_GET(idx, bitnum, bitnum) != value) {
335 static void dsi_perf_mark_setup(void)
337 dsi.perf_setup_time = ktime_get();
340 static void dsi_perf_mark_start(void)
342 dsi.perf_start_time = ktime_get();
345 static void dsi_perf_show(const char *name)
347 ktime_t t, setup_time, trans_time;
349 u32 setup_us, trans_us, total_us;
356 setup_time = ktime_sub(dsi.perf_start_time, dsi.perf_setup_time);
357 setup_us = (u32)ktime_to_us(setup_time);
361 trans_time = ktime_sub(t, dsi.perf_start_time);
362 trans_us = (u32)ktime_to_us(trans_time);
366 total_us = setup_us + trans_us;
368 total_bytes = dsi.update_region.w *
369 dsi.update_region.h *
370 dsi.update_region.device->ctrl.pixel_size / 8;
372 printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), "
373 "%u bytes, %u kbytes/sec\n",
378 1000*1000 / total_us,
380 total_bytes * 1000 / total_us);
383 #define dsi_perf_mark_setup()
384 #define dsi_perf_mark_start()
385 #define dsi_perf_show(x)
388 static void print_irq_status(u32 status)
391 if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0)
394 printk(KERN_DEBUG "DSI IRQ: 0x%x: ", status);
397 if (status & DSI_IRQ_##x) \
423 static void print_irq_status_vc(int channel, u32 status)
426 if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
429 printk(KERN_DEBUG "DSI VC(%d) IRQ 0x%x: ", channel, status);
432 if (status & DSI_VC_IRQ_##x) \
449 static void print_irq_status_cio(u32 status)
451 printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status);
454 if (status & DSI_CIO_IRQ_##x) \
468 PIS(ERRCONTENTIONLP0_1);
469 PIS(ERRCONTENTIONLP1_1);
470 PIS(ERRCONTENTIONLP0_2);
471 PIS(ERRCONTENTIONLP1_2);
472 PIS(ERRCONTENTIONLP0_3);
473 PIS(ERRCONTENTIONLP1_3);
474 PIS(ULPSACTIVENOT_ALL0);
475 PIS(ULPSACTIVENOT_ALL1);
481 static int debug_irq;
483 /* called from dss */
484 static irqreturn_t omap_dsi_irq_handler(int irq, void *arg)
486 u32 irqstatus, vcstatus, ciostatus;
489 irqstatus = dsi_read_reg(DSI_IRQSTATUS);
491 /* IRQ is not for us */
495 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
496 spin_lock(&dsi.irq_stats_lock);
497 dsi.irq_stats.irq_count++;
498 dss_collect_irq_stats(irqstatus, dsi.irq_stats.dsi_irqs);
501 if (irqstatus & DSI_IRQ_ERROR_MASK) {
502 DSSERR("DSI error, irqstatus %x\n", irqstatus);
503 print_irq_status(irqstatus);
504 spin_lock(&dsi.errors_lock);
505 dsi.errors |= irqstatus & DSI_IRQ_ERROR_MASK;
506 spin_unlock(&dsi.errors_lock);
507 } else if (debug_irq) {
508 print_irq_status(irqstatus);
511 #ifdef DSI_CATCH_MISSING_TE
512 if (irqstatus & DSI_IRQ_TE_TRIGGER)
513 del_timer(&dsi.te_timer);
516 for (i = 0; i < 4; ++i) {
517 if ((irqstatus & (1<<i)) == 0)
520 vcstatus = dsi_read_reg(DSI_VC_IRQSTATUS(i));
522 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
523 dss_collect_irq_stats(vcstatus, dsi.irq_stats.vc_irqs[i]);
526 if (vcstatus & DSI_VC_IRQ_BTA) {
527 complete(&dsi.bta_completion);
529 if (dsi.bta_callback)
533 if (vcstatus & DSI_VC_IRQ_ERROR_MASK) {
534 DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
536 print_irq_status_vc(i, vcstatus);
537 } else if (debug_irq) {
538 print_irq_status_vc(i, vcstatus);
541 dsi_write_reg(DSI_VC_IRQSTATUS(i), vcstatus);
542 /* flush posted write */
543 dsi_read_reg(DSI_VC_IRQSTATUS(i));
546 if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
547 ciostatus = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
549 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
550 dss_collect_irq_stats(ciostatus, dsi.irq_stats.cio_irqs);
553 dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
554 /* flush posted write */
555 dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
557 if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) {
558 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
559 print_irq_status_cio(ciostatus);
560 } else if (debug_irq) {
561 print_irq_status_cio(ciostatus);
565 dsi_write_reg(DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
566 /* flush posted write */
567 dsi_read_reg(DSI_IRQSTATUS);
569 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
570 spin_unlock(&dsi.irq_stats_lock);
575 static void _dsi_initialize_irq(void)
580 /* disable all interrupts */
581 dsi_write_reg(DSI_IRQENABLE, 0);
582 for (i = 0; i < 4; ++i)
583 dsi_write_reg(DSI_VC_IRQENABLE(i), 0);
584 dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE, 0);
586 /* clear interrupt status */
587 l = dsi_read_reg(DSI_IRQSTATUS);
588 dsi_write_reg(DSI_IRQSTATUS, l & ~DSI_IRQ_CHANNEL_MASK);
590 for (i = 0; i < 4; ++i) {
591 l = dsi_read_reg(DSI_VC_IRQSTATUS(i));
592 dsi_write_reg(DSI_VC_IRQSTATUS(i), l);
595 l = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
596 dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, l);
598 /* enable error irqs */
599 l = DSI_IRQ_ERROR_MASK;
600 #ifdef DSI_CATCH_MISSING_TE
601 l |= DSI_IRQ_TE_TRIGGER;
603 dsi_write_reg(DSI_IRQENABLE, l);
605 l = DSI_VC_IRQ_ERROR_MASK;
606 for (i = 0; i < 4; ++i)
607 dsi_write_reg(DSI_VC_IRQENABLE(i), l);
609 l = DSI_CIO_IRQ_ERROR_MASK;
610 dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE, l);
613 static u32 dsi_get_errors(void)
617 spin_lock_irqsave(&dsi.errors_lock, flags);
620 spin_unlock_irqrestore(&dsi.errors_lock, flags);
624 static void dsi_vc_enable_bta_irq(int channel)
628 dsi_write_reg(DSI_VC_IRQSTATUS(channel), DSI_VC_IRQ_BTA);
630 l = dsi_read_reg(DSI_VC_IRQENABLE(channel));
632 dsi_write_reg(DSI_VC_IRQENABLE(channel), l);
635 static void dsi_vc_disable_bta_irq(int channel)
639 l = dsi_read_reg(DSI_VC_IRQENABLE(channel));
640 l &= ~DSI_VC_IRQ_BTA;
641 dsi_write_reg(DSI_VC_IRQENABLE(channel), l);
644 /* DSI func clock. this could also be DSI2_PLL_FCLK */
645 static inline void enable_clocks(bool enable)
648 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
650 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
653 /* source clock for DSI PLL. this could also be PCLKFREE */
654 static inline void dsi_enable_pll_clock(bool enable)
657 dss_clk_enable(DSS_CLK_SYSCK);
659 dss_clk_disable(DSS_CLK_SYSCK);
661 if (enable && dsi.pll_locked) {
662 if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1)
663 DSSERR("cannot lock PLL when enabling clocks\n");
668 static void _dsi_print_reset_status(void)
675 /* A dummy read using the SCP interface to any DSIPHY register is
676 * required after DSIPHY reset to complete the reset of the DSI complex
678 l = dsi_read_reg(DSI_DSIPHY_CFG5);
680 printk(KERN_DEBUG "DSI resets: ");
682 l = dsi_read_reg(DSI_PLL_STATUS);
683 printk("PLL (%d) ", FLD_GET(l, 0, 0));
685 l = dsi_read_reg(DSI_COMPLEXIO_CFG1);
686 printk("CIO (%d) ", FLD_GET(l, 29, 29));
688 l = dsi_read_reg(DSI_DSIPHY_CFG5);
689 printk("PHY (%x, %d, %d, %d)\n",
696 #define _dsi_print_reset_status()
699 static inline int dsi_if_enable(bool enable)
701 DSSDBG("dsi_if_enable(%d)\n", enable);
703 enable = enable ? 1 : 0;
704 REG_FLD_MOD(DSI_CTRL, enable, 0, 0); /* IF_EN */
706 if (wait_for_bit_change(DSI_CTRL, 0, enable) != enable) {
707 DSSERR("Failed to set dsi_if_enable to %d\n", enable);
714 unsigned long dsi_get_dsi1_pll_rate(void)
716 return dsi.current_cinfo.dsi1_pll_fclk;
719 static unsigned long dsi_get_dsi2_pll_rate(void)
721 return dsi.current_cinfo.dsi2_pll_fclk;
724 static unsigned long dsi_get_txbyteclkhs(void)
726 return dsi.current_cinfo.clkin4ddr / 16;
729 static unsigned long dsi_fclk_rate(void)
733 if (dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK) {
734 /* DSI FCLK source is DSS1_ALWON_FCK, which is dss1_fck */
735 r = dss_clk_get_rate(DSS_CLK_FCK);
737 /* DSI FCLK source is DSI2_PLL_FCLK */
738 r = dsi_get_dsi2_pll_rate();
744 static int dsi_set_lp_clk_divisor(struct omap_dss_device *dssdev)
746 unsigned long dsi_fclk;
748 unsigned long lp_clk;
750 lp_clk_div = dssdev->phy.dsi.div.lp_clk_div;
752 if (lp_clk_div == 0 || lp_clk_div > LP_DIV_MAX)
755 dsi_fclk = dsi_fclk_rate();
757 lp_clk = dsi_fclk / 2 / lp_clk_div;
759 DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
760 dsi.current_cinfo.lp_clk = lp_clk;
761 dsi.current_cinfo.lp_clk_div = lp_clk_div;
763 REG_FLD_MOD(DSI_CLK_CTRL, lp_clk_div, 12, 0); /* LP_CLK_DIVISOR */
765 REG_FLD_MOD(DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0,
766 21, 21); /* LP_RX_SYNCHRO_ENABLE */
772 enum dsi_pll_power_state {
773 DSI_PLL_POWER_OFF = 0x0,
774 DSI_PLL_POWER_ON_HSCLK = 0x1,
775 DSI_PLL_POWER_ON_ALL = 0x2,
776 DSI_PLL_POWER_ON_DIV = 0x3,
779 static int dsi_pll_power(enum dsi_pll_power_state state)
783 REG_FLD_MOD(DSI_CLK_CTRL, state, 31, 30); /* PLL_PWR_CMD */
786 while (FLD_GET(dsi_read_reg(DSI_CLK_CTRL), 29, 28) != state) {
788 DSSERR("Failed to set DSI PLL power mode to %d\n",
798 /* calculate clock rates using dividers in cinfo */
799 static int dsi_calc_clock_rates(struct omap_dss_device *dssdev,
800 struct dsi_clock_info *cinfo)
802 if (cinfo->regn == 0 || cinfo->regn > REGN_MAX)
805 if (cinfo->regm == 0 || cinfo->regm > REGM_MAX)
808 if (cinfo->regm3 > REGM3_MAX)
811 if (cinfo->regm4 > REGM4_MAX)
814 if (cinfo->use_dss2_fck) {
815 cinfo->clkin = dss_clk_get_rate(DSS_CLK_SYSCK);
816 /* XXX it is unclear if highfreq should be used
817 * with DSS2_FCK source also */
820 cinfo->clkin = dispc_pclk_rate(dssdev->manager->id);
822 if (cinfo->clkin < 32000000)
828 cinfo->fint = cinfo->clkin / (cinfo->regn * (cinfo->highfreq ? 2 : 1));
830 if (cinfo->fint > FINT_MAX || cinfo->fint < FINT_MIN)
833 cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint;
835 if (cinfo->clkin4ddr > 1800 * 1000 * 1000)
838 if (cinfo->regm3 > 0)
839 cinfo->dsi1_pll_fclk = cinfo->clkin4ddr / cinfo->regm3;
841 cinfo->dsi1_pll_fclk = 0;
843 if (cinfo->regm4 > 0)
844 cinfo->dsi2_pll_fclk = cinfo->clkin4ddr / cinfo->regm4;
846 cinfo->dsi2_pll_fclk = 0;
851 int dsi_pll_calc_clock_div_pck(bool is_tft, unsigned long req_pck,
852 struct dsi_clock_info *dsi_cinfo,
853 struct dispc_clock_info *dispc_cinfo)
855 struct dsi_clock_info cur, best;
856 struct dispc_clock_info best_dispc;
859 unsigned long dss_clk_fck2;
861 dss_clk_fck2 = dss_clk_get_rate(DSS_CLK_SYSCK);
863 if (req_pck == dsi.cache_req_pck &&
864 dsi.cache_cinfo.clkin == dss_clk_fck2) {
865 DSSDBG("DSI clock info found from cache\n");
866 *dsi_cinfo = dsi.cache_cinfo;
867 dispc_find_clk_divs(is_tft, req_pck, dsi_cinfo->dsi1_pll_fclk,
872 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
874 if (min_fck_per_pck &&
875 req_pck * min_fck_per_pck > DISPC_MAX_FCK) {
876 DSSERR("Requested pixel clock not possible with the current "
877 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
878 "the constraint off.\n");
882 DSSDBG("dsi_pll_calc\n");
885 memset(&best, 0, sizeof(best));
886 memset(&best_dispc, 0, sizeof(best_dispc));
888 memset(&cur, 0, sizeof(cur));
889 cur.clkin = dss_clk_fck2;
890 cur.use_dss2_fck = 1;
893 /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */
894 /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */
895 /* To reduce PLL lock time, keep Fint high (around 2 MHz) */
896 for (cur.regn = 1; cur.regn < REGN_MAX; ++cur.regn) {
897 if (cur.highfreq == 0)
898 cur.fint = cur.clkin / cur.regn;
900 cur.fint = cur.clkin / (2 * cur.regn);
902 if (cur.fint > FINT_MAX || cur.fint < FINT_MIN)
905 /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */
906 for (cur.regm = 1; cur.regm < REGM_MAX; ++cur.regm) {
909 a = 2 * cur.regm * (cur.clkin/1000);
910 b = cur.regn * (cur.highfreq + 1);
911 cur.clkin4ddr = a / b * 1000;
913 if (cur.clkin4ddr > 1800 * 1000 * 1000)
916 /* DSI1_PLL_FCLK(MHz) = DSIPHY(MHz) / regm3 < 173MHz */
917 for (cur.regm3 = 1; cur.regm3 < REGM3_MAX;
919 struct dispc_clock_info cur_dispc;
920 cur.dsi1_pll_fclk = cur.clkin4ddr / cur.regm3;
922 /* this will narrow down the search a bit,
923 * but still give pixclocks below what was
925 if (cur.dsi1_pll_fclk < req_pck)
928 if (cur.dsi1_pll_fclk > DISPC_MAX_FCK)
931 if (min_fck_per_pck &&
933 req_pck * min_fck_per_pck)
938 dispc_find_clk_divs(is_tft, req_pck,
942 if (abs(cur_dispc.pck - req_pck) <
943 abs(best_dispc.pck - req_pck)) {
945 best_dispc = cur_dispc;
947 if (cur_dispc.pck == req_pck)
955 if (min_fck_per_pck) {
956 DSSERR("Could not find suitable clock settings.\n"
957 "Turning FCK/PCK constraint off and"
963 DSSERR("Could not find suitable clock settings.\n");
968 /* DSI2_PLL_FCLK (regm4) is not used */
970 best.dsi2_pll_fclk = 0;
975 *dispc_cinfo = best_dispc;
977 dsi.cache_req_pck = req_pck;
978 dsi.cache_clk_freq = 0;
979 dsi.cache_cinfo = best;
984 int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo)
992 dsi.current_cinfo.fint = cinfo->fint;
993 dsi.current_cinfo.clkin4ddr = cinfo->clkin4ddr;
994 dsi.current_cinfo.dsi1_pll_fclk = cinfo->dsi1_pll_fclk;
995 dsi.current_cinfo.dsi2_pll_fclk = cinfo->dsi2_pll_fclk;
997 dsi.current_cinfo.regn = cinfo->regn;
998 dsi.current_cinfo.regm = cinfo->regm;
999 dsi.current_cinfo.regm3 = cinfo->regm3;
1000 dsi.current_cinfo.regm4 = cinfo->regm4;
1002 DSSDBG("DSI Fint %ld\n", cinfo->fint);
1004 DSSDBG("clkin (%s) rate %ld, highfreq %d\n",
1005 cinfo->use_dss2_fck ? "dss2_fck" : "pclkfree",
1009 /* DSIPHY == CLKIN4DDR */
1010 DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu / %d = %lu\n",
1014 cinfo->highfreq + 1,
1017 DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
1018 cinfo->clkin4ddr / 1000 / 1000 / 2);
1020 DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4);
1022 DSSDBG("regm3 = %d, dsi1_pll_fclk = %lu\n",
1023 cinfo->regm3, cinfo->dsi1_pll_fclk);
1024 DSSDBG("regm4 = %d, dsi2_pll_fclk = %lu\n",
1025 cinfo->regm4, cinfo->dsi2_pll_fclk);
1027 REG_FLD_MOD(DSI_PLL_CONTROL, 0, 0, 0); /* DSI_PLL_AUTOMODE = manual */
1029 l = dsi_read_reg(DSI_PLL_CONFIGURATION1);
1030 l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */
1031 l = FLD_MOD(l, cinfo->regn - 1, 7, 1); /* DSI_PLL_REGN */
1032 l = FLD_MOD(l, cinfo->regm, 18, 8); /* DSI_PLL_REGM */
1033 l = FLD_MOD(l, cinfo->regm3 > 0 ? cinfo->regm3 - 1 : 0,
1034 22, 19); /* DSI_CLOCK_DIV */
1035 l = FLD_MOD(l, cinfo->regm4 > 0 ? cinfo->regm4 - 1 : 0,
1036 26, 23); /* DSIPROTO_CLOCK_DIV */
1037 dsi_write_reg(DSI_PLL_CONFIGURATION1, l);
1039 BUG_ON(cinfo->fint < 750000 || cinfo->fint > 2100000);
1040 if (cinfo->fint < 1000000)
1042 else if (cinfo->fint < 1250000)
1044 else if (cinfo->fint < 1500000)
1046 else if (cinfo->fint < 1750000)
1051 l = dsi_read_reg(DSI_PLL_CONFIGURATION2);
1052 l = FLD_MOD(l, f, 4, 1); /* DSI_PLL_FREQSEL */
1053 l = FLD_MOD(l, cinfo->use_dss2_fck ? 0 : 1,
1054 11, 11); /* DSI_PLL_CLKSEL */
1055 l = FLD_MOD(l, cinfo->highfreq,
1056 12, 12); /* DSI_PLL_HIGHFREQ */
1057 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1058 l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */
1059 l = FLD_MOD(l, 1, 20, 20); /* DSI_HSDIVBYPASS */
1060 dsi_write_reg(DSI_PLL_CONFIGURATION2, l);
1062 REG_FLD_MOD(DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */
1064 if (wait_for_bit_change(DSI_PLL_GO, 0, 0) != 0) {
1065 DSSERR("dsi pll go bit not going down.\n");
1070 if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1) {
1071 DSSERR("cannot lock PLL\n");
1078 l = dsi_read_reg(DSI_PLL_CONFIGURATION2);
1079 l = FLD_MOD(l, 0, 0, 0); /* DSI_PLL_IDLE */
1080 l = FLD_MOD(l, 0, 5, 5); /* DSI_PLL_PLLLPMODE */
1081 l = FLD_MOD(l, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */
1082 l = FLD_MOD(l, 0, 7, 7); /* DSI_PLL_TIGHTPHASELOCK */
1083 l = FLD_MOD(l, 0, 8, 8); /* DSI_PLL_DRIFTGUARDEN */
1084 l = FLD_MOD(l, 0, 10, 9); /* DSI_PLL_LOCKSEL */
1085 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1086 l = FLD_MOD(l, 1, 14, 14); /* DSIPHY_CLKINEN */
1087 l = FLD_MOD(l, 0, 15, 15); /* DSI_BYPASSEN */
1088 l = FLD_MOD(l, 1, 16, 16); /* DSS_CLOCK_EN */
1089 l = FLD_MOD(l, 0, 17, 17); /* DSS_CLOCK_PWDN */
1090 l = FLD_MOD(l, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */
1091 l = FLD_MOD(l, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */
1092 l = FLD_MOD(l, 0, 20, 20); /* DSI_HSDIVBYPASS */
1093 dsi_write_reg(DSI_PLL_CONFIGURATION2, l);
1095 DSSDBG("PLL config done\n");
1100 int dsi_pll_init(struct omap_dss_device *dssdev, bool enable_hsclk,
1104 enum dsi_pll_power_state pwstate;
1106 DSSDBG("PLL init\n");
1109 dsi_enable_pll_clock(1);
1111 r = regulator_enable(dsi.vdds_dsi_reg);
1115 /* XXX PLL does not come out of reset without this... */
1116 dispc_pck_free_enable(1);
1118 if (wait_for_bit_change(DSI_PLL_STATUS, 0, 1) != 1) {
1119 DSSERR("PLL not coming out of reset.\n");
1121 dispc_pck_free_enable(0);
1125 /* XXX ... but if left on, we get problems when planes do not
1126 * fill the whole display. No idea about this */
1127 dispc_pck_free_enable(0);
1129 if (enable_hsclk && enable_hsdiv)
1130 pwstate = DSI_PLL_POWER_ON_ALL;
1131 else if (enable_hsclk)
1132 pwstate = DSI_PLL_POWER_ON_HSCLK;
1133 else if (enable_hsdiv)
1134 pwstate = DSI_PLL_POWER_ON_DIV;
1136 pwstate = DSI_PLL_POWER_OFF;
1138 r = dsi_pll_power(pwstate);
1143 DSSDBG("PLL init done\n");
1147 regulator_disable(dsi.vdds_dsi_reg);
1150 dsi_enable_pll_clock(0);
1154 void dsi_pll_uninit(void)
1157 dsi_enable_pll_clock(0);
1160 dsi_pll_power(DSI_PLL_POWER_OFF);
1161 regulator_disable(dsi.vdds_dsi_reg);
1162 DSSDBG("PLL uninit done\n");
1165 void dsi_dump_clocks(struct seq_file *s)
1168 struct dsi_clock_info *cinfo = &dsi.current_cinfo;
1172 clksel = REG_GET(DSI_PLL_CONFIGURATION2, 11, 11);
1174 seq_printf(s, "- DSI PLL -\n");
1176 seq_printf(s, "dsi pll source = %s\n",
1178 "dss2_alwon_fclk" : "pclkfree");
1180 seq_printf(s, "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn);
1182 seq_printf(s, "CLKIN4DDR\t%-16luregm %u\n",
1183 cinfo->clkin4ddr, cinfo->regm);
1185 seq_printf(s, "dsi1_pll_fck\t%-16luregm3 %u\t(%s)\n",
1186 cinfo->dsi1_pll_fclk,
1188 dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ?
1191 seq_printf(s, "dsi2_pll_fck\t%-16luregm4 %u\t(%s)\n",
1192 cinfo->dsi2_pll_fclk,
1194 dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ?
1197 seq_printf(s, "- DSI -\n");
1199 seq_printf(s, "dsi fclk source = %s\n",
1200 dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ?
1201 "dss1_alwon_fclk" : "dsi2_pll_fclk");
1203 seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate());
1205 seq_printf(s, "DDR_CLK\t\t%lu\n",
1206 cinfo->clkin4ddr / 4);
1208 seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs());
1210 seq_printf(s, "LP_CLK\t\t%lu\n", cinfo->lp_clk);
1212 seq_printf(s, "VP_CLK\t\t%lu\n"
1214 dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD),
1215 dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD));
1220 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
1221 void dsi_dump_irqs(struct seq_file *s)
1223 unsigned long flags;
1224 struct dsi_irq_stats stats;
1226 spin_lock_irqsave(&dsi.irq_stats_lock, flags);
1228 stats = dsi.irq_stats;
1229 memset(&dsi.irq_stats, 0, sizeof(dsi.irq_stats));
1230 dsi.irq_stats.last_reset = jiffies;
1232 spin_unlock_irqrestore(&dsi.irq_stats_lock, flags);
1234 seq_printf(s, "period %u ms\n",
1235 jiffies_to_msecs(jiffies - stats.last_reset));
1237 seq_printf(s, "irqs %d\n", stats.irq_count);
1239 seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);
1241 seq_printf(s, "-- DSI interrupts --\n");
1257 PIS(LDO_POWER_GOOD);
1262 seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
1263 stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
1264 stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
1265 stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
1266 stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
1268 seq_printf(s, "-- VC interrupts --\n");
1277 PIS(PP_BUSY_CHANGE);
1281 seq_printf(s, "%-20s %10d\n", #x, \
1282 stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
1284 seq_printf(s, "-- CIO interrupts --\n");
1297 PIS(ERRCONTENTIONLP0_1);
1298 PIS(ERRCONTENTIONLP1_1);
1299 PIS(ERRCONTENTIONLP0_2);
1300 PIS(ERRCONTENTIONLP1_2);
1301 PIS(ERRCONTENTIONLP0_3);
1302 PIS(ERRCONTENTIONLP1_3);
1303 PIS(ULPSACTIVENOT_ALL0);
1304 PIS(ULPSACTIVENOT_ALL1);
1309 void dsi_dump_regs(struct seq_file *s)
1311 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(r))
1313 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
1315 DUMPREG(DSI_REVISION);
1316 DUMPREG(DSI_SYSCONFIG);
1317 DUMPREG(DSI_SYSSTATUS);
1318 DUMPREG(DSI_IRQSTATUS);
1319 DUMPREG(DSI_IRQENABLE);
1321 DUMPREG(DSI_COMPLEXIO_CFG1);
1322 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
1323 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
1324 DUMPREG(DSI_CLK_CTRL);
1325 DUMPREG(DSI_TIMING1);
1326 DUMPREG(DSI_TIMING2);
1327 DUMPREG(DSI_VM_TIMING1);
1328 DUMPREG(DSI_VM_TIMING2);
1329 DUMPREG(DSI_VM_TIMING3);
1330 DUMPREG(DSI_CLK_TIMING);
1331 DUMPREG(DSI_TX_FIFO_VC_SIZE);
1332 DUMPREG(DSI_RX_FIFO_VC_SIZE);
1333 DUMPREG(DSI_COMPLEXIO_CFG2);
1334 DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
1335 DUMPREG(DSI_VM_TIMING4);
1336 DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
1337 DUMPREG(DSI_VM_TIMING5);
1338 DUMPREG(DSI_VM_TIMING6);
1339 DUMPREG(DSI_VM_TIMING7);
1340 DUMPREG(DSI_STOPCLK_TIMING);
1342 DUMPREG(DSI_VC_CTRL(0));
1343 DUMPREG(DSI_VC_TE(0));
1344 DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
1345 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
1346 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
1347 DUMPREG(DSI_VC_IRQSTATUS(0));
1348 DUMPREG(DSI_VC_IRQENABLE(0));
1350 DUMPREG(DSI_VC_CTRL(1));
1351 DUMPREG(DSI_VC_TE(1));
1352 DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
1353 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
1354 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
1355 DUMPREG(DSI_VC_IRQSTATUS(1));
1356 DUMPREG(DSI_VC_IRQENABLE(1));
1358 DUMPREG(DSI_VC_CTRL(2));
1359 DUMPREG(DSI_VC_TE(2));
1360 DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
1361 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
1362 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
1363 DUMPREG(DSI_VC_IRQSTATUS(2));
1364 DUMPREG(DSI_VC_IRQENABLE(2));
1366 DUMPREG(DSI_VC_CTRL(3));
1367 DUMPREG(DSI_VC_TE(3));
1368 DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
1369 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
1370 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
1371 DUMPREG(DSI_VC_IRQSTATUS(3));
1372 DUMPREG(DSI_VC_IRQENABLE(3));
1374 DUMPREG(DSI_DSIPHY_CFG0);
1375 DUMPREG(DSI_DSIPHY_CFG1);
1376 DUMPREG(DSI_DSIPHY_CFG2);
1377 DUMPREG(DSI_DSIPHY_CFG5);
1379 DUMPREG(DSI_PLL_CONTROL);
1380 DUMPREG(DSI_PLL_STATUS);
1381 DUMPREG(DSI_PLL_GO);
1382 DUMPREG(DSI_PLL_CONFIGURATION1);
1383 DUMPREG(DSI_PLL_CONFIGURATION2);
1385 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
1389 enum dsi_complexio_power_state {
1390 DSI_COMPLEXIO_POWER_OFF = 0x0,
1391 DSI_COMPLEXIO_POWER_ON = 0x1,
1392 DSI_COMPLEXIO_POWER_ULPS = 0x2,
1395 static int dsi_complexio_power(enum dsi_complexio_power_state state)
1400 REG_FLD_MOD(DSI_COMPLEXIO_CFG1, state, 28, 27);
1403 while (FLD_GET(dsi_read_reg(DSI_COMPLEXIO_CFG1), 26, 25) != state) {
1405 DSSERR("failed to set complexio power state to "
1415 static void dsi_complexio_config(struct omap_dss_device *dssdev)
1419 int clk_lane = dssdev->phy.dsi.clk_lane;
1420 int data1_lane = dssdev->phy.dsi.data1_lane;
1421 int data2_lane = dssdev->phy.dsi.data2_lane;
1422 int clk_pol = dssdev->phy.dsi.clk_pol;
1423 int data1_pol = dssdev->phy.dsi.data1_pol;
1424 int data2_pol = dssdev->phy.dsi.data2_pol;
1426 r = dsi_read_reg(DSI_COMPLEXIO_CFG1);
1427 r = FLD_MOD(r, clk_lane, 2, 0);
1428 r = FLD_MOD(r, clk_pol, 3, 3);
1429 r = FLD_MOD(r, data1_lane, 6, 4);
1430 r = FLD_MOD(r, data1_pol, 7, 7);
1431 r = FLD_MOD(r, data2_lane, 10, 8);
1432 r = FLD_MOD(r, data2_pol, 11, 11);
1433 dsi_write_reg(DSI_COMPLEXIO_CFG1, r);
1435 /* The configuration of the DSI complex I/O (number of data lanes,
1436 position, differential order) should not be changed while
1437 DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. In order for
1438 the hardware to take into account a new configuration of the complex
1439 I/O (done in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to
1440 follow this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1,
1441 then reset the DSS.DSI_CTRL[0] IF_EN to 0, then set
1442 DSS.DSI_CLK_CTRL[20] LP_CLK_ENABLE to 1 and finally set again the
1443 DSS.DSI_CTRL[0] IF_EN bit to 1. If the sequence is not followed, the
1444 DSI complex I/O configuration is unknown. */
1447 REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
1448 REG_FLD_MOD(DSI_CTRL, 0, 0, 0);
1449 REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20);
1450 REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
1454 static inline unsigned ns2ddr(unsigned ns)
1456 /* convert time in ns to ddr ticks, rounding up */
1457 unsigned long ddr_clk = dsi.current_cinfo.clkin4ddr / 4;
1458 return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
1461 static inline unsigned ddr2ns(unsigned ddr)
1463 unsigned long ddr_clk = dsi.current_cinfo.clkin4ddr / 4;
1464 return ddr * 1000 * 1000 / (ddr_clk / 1000);
1467 static void dsi_complexio_timings(void)
1470 u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
1471 u32 tlpx_half, tclk_trail, tclk_zero;
1474 /* calculate timings */
1476 /* 1 * DDR_CLK = 2 * UI */
1478 /* min 40ns + 4*UI max 85ns + 6*UI */
1479 ths_prepare = ns2ddr(70) + 2;
1481 /* min 145ns + 10*UI */
1482 ths_prepare_ths_zero = ns2ddr(175) + 2;
1484 /* min max(8*UI, 60ns+4*UI) */
1485 ths_trail = ns2ddr(60) + 5;
1488 ths_exit = ns2ddr(145);
1491 tlpx_half = ns2ddr(25);
1494 tclk_trail = ns2ddr(60) + 2;
1496 /* min 38ns, max 95ns */
1497 tclk_prepare = ns2ddr(65);
1499 /* min tclk-prepare + tclk-zero = 300ns */
1500 tclk_zero = ns2ddr(260);
1502 DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
1503 ths_prepare, ddr2ns(ths_prepare),
1504 ths_prepare_ths_zero, ddr2ns(ths_prepare_ths_zero));
1505 DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
1506 ths_trail, ddr2ns(ths_trail),
1507 ths_exit, ddr2ns(ths_exit));
1509 DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
1510 "tclk_zero %u (%uns)\n",
1511 tlpx_half, ddr2ns(tlpx_half),
1512 tclk_trail, ddr2ns(tclk_trail),
1513 tclk_zero, ddr2ns(tclk_zero));
1514 DSSDBG("tclk_prepare %u (%uns)\n",
1515 tclk_prepare, ddr2ns(tclk_prepare));
1517 /* program timings */
1519 r = dsi_read_reg(DSI_DSIPHY_CFG0);
1520 r = FLD_MOD(r, ths_prepare, 31, 24);
1521 r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
1522 r = FLD_MOD(r, ths_trail, 15, 8);
1523 r = FLD_MOD(r, ths_exit, 7, 0);
1524 dsi_write_reg(DSI_DSIPHY_CFG0, r);
1526 r = dsi_read_reg(DSI_DSIPHY_CFG1);
1527 r = FLD_MOD(r, tlpx_half, 22, 16);
1528 r = FLD_MOD(r, tclk_trail, 15, 8);
1529 r = FLD_MOD(r, tclk_zero, 7, 0);
1530 dsi_write_reg(DSI_DSIPHY_CFG1, r);
1532 r = dsi_read_reg(DSI_DSIPHY_CFG2);
1533 r = FLD_MOD(r, tclk_prepare, 7, 0);
1534 dsi_write_reg(DSI_DSIPHY_CFG2, r);
1538 static int dsi_complexio_init(struct omap_dss_device *dssdev)
1542 DSSDBG("dsi_complexio_init\n");
1544 /* CIO_CLK_ICG, enable L3 clk to CIO */
1545 REG_FLD_MOD(DSI_CLK_CTRL, 1, 14, 14);
1547 /* A dummy read using the SCP interface to any DSIPHY register is
1548 * required after DSIPHY reset to complete the reset of the DSI complex
1550 dsi_read_reg(DSI_DSIPHY_CFG5);
1552 if (wait_for_bit_change(DSI_DSIPHY_CFG5, 30, 1) != 1) {
1553 DSSERR("ComplexIO PHY not coming out of reset.\n");
1558 dsi_complexio_config(dssdev);
1560 r = dsi_complexio_power(DSI_COMPLEXIO_POWER_ON);
1565 if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
1566 DSSERR("ComplexIO not coming out of reset.\n");
1571 if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 21, 1) != 1) {
1572 DSSERR("ComplexIO LDO power down.\n");
1577 dsi_complexio_timings();
1580 The configuration of the DSI complex I/O (number of data lanes,
1581 position, differential order) should not be changed while
1582 DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. For the
1583 hardware to recognize a new configuration of the complex I/O (done
1584 in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to follow
1585 this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1, next
1586 reset the DSS.DSI_CTRL[0] IF_EN to 0, then set DSS.DSI_CLK_CTRL[20]
1587 LP_CLK_ENABLE to 1, and finally, set again the DSS.DSI_CTRL[0] IF_EN
1588 bit to 1. If the sequence is not followed, the DSi complex I/O
1589 configuration is undetermined.
1593 REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
1597 DSSDBG("CIO init done\n");
1602 static void dsi_complexio_uninit(void)
1604 dsi_complexio_power(DSI_COMPLEXIO_POWER_OFF);
1607 static int _dsi_wait_reset(void)
1611 while (REG_GET(DSI_SYSSTATUS, 0, 0) == 0) {
1613 DSSERR("soft reset failed\n");
1622 static int _dsi_reset(void)
1625 REG_FLD_MOD(DSI_SYSCONFIG, 1, 1, 1);
1626 return _dsi_wait_reset();
1629 static void dsi_config_tx_fifo(enum fifo_size size1, enum fifo_size size2,
1630 enum fifo_size size3, enum fifo_size size4)
1636 dsi.vc[0].fifo_size = size1;
1637 dsi.vc[1].fifo_size = size2;
1638 dsi.vc[2].fifo_size = size3;
1639 dsi.vc[3].fifo_size = size4;
1641 for (i = 0; i < 4; i++) {
1643 int size = dsi.vc[i].fifo_size;
1645 if (add + size > 4) {
1646 DSSERR("Illegal FIFO configuration\n");
1650 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
1652 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
1656 dsi_write_reg(DSI_TX_FIFO_VC_SIZE, r);
1659 static void dsi_config_rx_fifo(enum fifo_size size1, enum fifo_size size2,
1660 enum fifo_size size3, enum fifo_size size4)
1666 dsi.vc[0].fifo_size = size1;
1667 dsi.vc[1].fifo_size = size2;
1668 dsi.vc[2].fifo_size = size3;
1669 dsi.vc[3].fifo_size = size4;
1671 for (i = 0; i < 4; i++) {
1673 int size = dsi.vc[i].fifo_size;
1675 if (add + size > 4) {
1676 DSSERR("Illegal FIFO configuration\n");
1680 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
1682 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
1686 dsi_write_reg(DSI_RX_FIFO_VC_SIZE, r);
1689 static int dsi_force_tx_stop_mode_io(void)
1693 r = dsi_read_reg(DSI_TIMING1);
1694 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
1695 dsi_write_reg(DSI_TIMING1, r);
1697 if (wait_for_bit_change(DSI_TIMING1, 15, 0) != 0) {
1698 DSSERR("TX_STOP bit not going down\n");
1705 static int dsi_vc_enable(int channel, bool enable)
1707 DSSDBG("dsi_vc_enable channel %d, enable %d\n",
1710 enable = enable ? 1 : 0;
1712 REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 0, 0);
1714 if (wait_for_bit_change(DSI_VC_CTRL(channel), 0, enable) != enable) {
1715 DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
1722 static void dsi_vc_initial_config(int channel)
1726 DSSDBGF("%d", channel);
1728 r = dsi_read_reg(DSI_VC_CTRL(channel));
1730 if (FLD_GET(r, 15, 15)) /* VC_BUSY */
1731 DSSERR("VC(%d) busy when trying to configure it!\n",
1734 r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
1735 r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */
1736 r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
1737 r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
1738 r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
1739 r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
1740 r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
1742 r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
1743 r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
1745 dsi_write_reg(DSI_VC_CTRL(channel), r);
1747 dsi.vc[channel].mode = DSI_VC_MODE_L4;
1750 static int dsi_vc_config_l4(int channel)
1752 if (dsi.vc[channel].mode == DSI_VC_MODE_L4)
1755 DSSDBGF("%d", channel);
1757 dsi_vc_enable(channel, 0);
1760 if (wait_for_bit_change(DSI_VC_CTRL(channel), 15, 0) != 0) {
1761 DSSERR("vc(%d) busy when trying to config for L4\n", channel);
1765 REG_FLD_MOD(DSI_VC_CTRL(channel), 0, 1, 1); /* SOURCE, 0 = L4 */
1767 dsi_vc_enable(channel, 1);
1769 dsi.vc[channel].mode = DSI_VC_MODE_L4;
1774 static int dsi_vc_config_vp(int channel)
1776 if (dsi.vc[channel].mode == DSI_VC_MODE_VP)
1779 DSSDBGF("%d", channel);
1781 dsi_vc_enable(channel, 0);
1784 if (wait_for_bit_change(DSI_VC_CTRL(channel), 15, 0) != 0) {
1785 DSSERR("vc(%d) busy when trying to config for VP\n", channel);
1789 REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 1, 1); /* SOURCE, 1 = video port */
1791 dsi_vc_enable(channel, 1);
1793 dsi.vc[channel].mode = DSI_VC_MODE_VP;
1799 void omapdss_dsi_vc_enable_hs(int channel, bool enable)
1801 DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
1803 WARN_ON(!dsi_bus_is_locked());
1805 dsi_vc_enable(channel, 0);
1808 REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 9, 9);
1810 dsi_vc_enable(channel, 1);
1813 dsi_force_tx_stop_mode_io();
1815 EXPORT_SYMBOL(omapdss_dsi_vc_enable_hs);
1817 static void dsi_vc_flush_long_data(int channel)
1819 while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
1821 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
1822 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
1826 (val >> 24) & 0xff);
1830 static void dsi_show_rx_ack_with_err(u16 err)
1832 DSSERR("\tACK with ERROR (%#x):\n", err);
1834 DSSERR("\t\tSoT Error\n");
1836 DSSERR("\t\tSoT Sync Error\n");
1838 DSSERR("\t\tEoT Sync Error\n");
1840 DSSERR("\t\tEscape Mode Entry Command Error\n");
1842 DSSERR("\t\tLP Transmit Sync Error\n");
1844 DSSERR("\t\tHS Receive Timeout Error\n");
1846 DSSERR("\t\tFalse Control Error\n");
1848 DSSERR("\t\t(reserved7)\n");
1850 DSSERR("\t\tECC Error, single-bit (corrected)\n");
1852 DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
1853 if (err & (1 << 10))
1854 DSSERR("\t\tChecksum Error\n");
1855 if (err & (1 << 11))
1856 DSSERR("\t\tData type not recognized\n");
1857 if (err & (1 << 12))
1858 DSSERR("\t\tInvalid VC ID\n");
1859 if (err & (1 << 13))
1860 DSSERR("\t\tInvalid Transmission Length\n");
1861 if (err & (1 << 14))
1862 DSSERR("\t\t(reserved14)\n");
1863 if (err & (1 << 15))
1864 DSSERR("\t\tDSI Protocol Violation\n");
1867 static u16 dsi_vc_flush_receive_data(int channel)
1869 /* RX_FIFO_NOT_EMPTY */
1870 while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
1873 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
1874 DSSERR("\trawval %#08x\n", val);
1875 dt = FLD_GET(val, 5, 0);
1876 if (dt == DSI_DT_RX_ACK_WITH_ERR) {
1877 u16 err = FLD_GET(val, 23, 8);
1878 dsi_show_rx_ack_with_err(err);
1879 } else if (dt == DSI_DT_RX_SHORT_READ_1) {
1880 DSSERR("\tDCS short response, 1 byte: %#x\n",
1881 FLD_GET(val, 23, 8));
1882 } else if (dt == DSI_DT_RX_SHORT_READ_2) {
1883 DSSERR("\tDCS short response, 2 byte: %#x\n",
1884 FLD_GET(val, 23, 8));
1885 } else if (dt == DSI_DT_RX_DCS_LONG_READ) {
1886 DSSERR("\tDCS long response, len %d\n",
1887 FLD_GET(val, 23, 8));
1888 dsi_vc_flush_long_data(channel);
1890 DSSERR("\tunknown datatype 0x%02x\n", dt);
1896 static int dsi_vc_send_bta(int channel)
1898 if (dsi.debug_write || dsi.debug_read)
1899 DSSDBG("dsi_vc_send_bta %d\n", channel);
1901 WARN_ON(!dsi_bus_is_locked());
1903 if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { /* RX_FIFO_NOT_EMPTY */
1904 DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
1905 dsi_vc_flush_receive_data(channel);
1908 REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
1913 int dsi_vc_send_bta_sync(int channel)
1918 INIT_COMPLETION(dsi.bta_completion);
1920 dsi_vc_enable_bta_irq(channel);
1922 r = dsi_vc_send_bta(channel);
1926 if (wait_for_completion_timeout(&dsi.bta_completion,
1927 msecs_to_jiffies(500)) == 0) {
1928 DSSERR("Failed to receive BTA\n");
1933 err = dsi_get_errors();
1935 DSSERR("Error while sending BTA: %x\n", err);
1940 dsi_vc_disable_bta_irq(channel);
1944 EXPORT_SYMBOL(dsi_vc_send_bta_sync);
1946 static inline void dsi_vc_write_long_header(int channel, u8 data_type,
1952 WARN_ON(!dsi_bus_is_locked());
1954 data_id = data_type | channel << 6;
1956 val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
1957 FLD_VAL(ecc, 31, 24);
1959 dsi_write_reg(DSI_VC_LONG_PACKET_HEADER(channel), val);
1962 static inline void dsi_vc_write_long_payload(int channel,
1963 u8 b1, u8 b2, u8 b3, u8 b4)
1967 val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0;
1969 /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
1970 b1, b2, b3, b4, val); */
1972 dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
1975 static int dsi_vc_send_long(int channel, u8 data_type, u8 *data, u16 len,
1984 if (dsi.debug_write)
1985 DSSDBG("dsi_vc_send_long, %d bytes\n", len);
1988 if (dsi.vc[channel].fifo_size * 32 * 4 < len + 4) {
1989 DSSERR("unable to send long packet: packet too long.\n");
1993 dsi_vc_config_l4(channel);
1995 dsi_vc_write_long_header(channel, data_type, len, ecc);
1998 for (i = 0; i < len >> 2; i++) {
1999 if (dsi.debug_write)
2000 DSSDBG("\tsending full packet %d\n", i);
2007 dsi_vc_write_long_payload(channel, b1, b2, b3, b4);
2012 b1 = 0; b2 = 0; b3 = 0;
2014 if (dsi.debug_write)
2015 DSSDBG("\tsending remainder bytes %d\n", i);
2032 dsi_vc_write_long_payload(channel, b1, b2, b3, 0);
2038 static int dsi_vc_send_short(int channel, u8 data_type, u16 data, u8 ecc)
2043 WARN_ON(!dsi_bus_is_locked());
2045 if (dsi.debug_write)
2046 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
2048 data_type, data & 0xff, (data >> 8) & 0xff);
2050 dsi_vc_config_l4(channel);
2052 if (FLD_GET(dsi_read_reg(DSI_VC_CTRL(channel)), 16, 16)) {
2053 DSSERR("ERROR FIFO FULL, aborting transfer\n");
2057 data_id = data_type | channel << 6;
2059 r = (data_id << 0) | (data << 8) | (ecc << 24);
2061 dsi_write_reg(DSI_VC_SHORT_PACKET_HEADER(channel), r);
2066 int dsi_vc_send_null(int channel)
2068 u8 nullpkg[] = {0, 0, 0, 0};
2069 return dsi_vc_send_long(channel, DSI_DT_NULL_PACKET, nullpkg, 4, 0);
2071 EXPORT_SYMBOL(dsi_vc_send_null);
2073 int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len)
2080 r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_0,
2082 } else if (len == 2) {
2083 r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_1,
2084 data[0] | (data[1] << 8), 0);
2086 /* 0x39 = DCS Long Write */
2087 r = dsi_vc_send_long(channel, DSI_DT_DCS_LONG_WRITE,
2093 EXPORT_SYMBOL(dsi_vc_dcs_write_nosync);
2095 int dsi_vc_dcs_write(int channel, u8 *data, int len)
2099 r = dsi_vc_dcs_write_nosync(channel, data, len);
2103 r = dsi_vc_send_bta_sync(channel);
2107 if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { /* RX_FIFO_NOT_EMPTY */
2108 DSSERR("rx fifo not empty after write, dumping data:\n");
2109 dsi_vc_flush_receive_data(channel);
2116 DSSERR("dsi_vc_dcs_write(ch %d, cmd 0x%02x, len %d) failed\n",
2117 channel, data[0], len);
2120 EXPORT_SYMBOL(dsi_vc_dcs_write);
2122 int dsi_vc_dcs_write_0(int channel, u8 dcs_cmd)
2124 return dsi_vc_dcs_write(channel, &dcs_cmd, 1);
2126 EXPORT_SYMBOL(dsi_vc_dcs_write_0);
2128 int dsi_vc_dcs_write_1(int channel, u8 dcs_cmd, u8 param)
2133 return dsi_vc_dcs_write(channel, buf, 2);
2135 EXPORT_SYMBOL(dsi_vc_dcs_write_1);
2137 int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen)
2144 DSSDBG("dsi_vc_dcs_read(ch%d, dcs_cmd %x)\n", channel, dcs_cmd);
2146 r = dsi_vc_send_short(channel, DSI_DT_DCS_READ, dcs_cmd, 0);
2150 r = dsi_vc_send_bta_sync(channel);
2154 /* RX_FIFO_NOT_EMPTY */
2155 if (REG_GET(DSI_VC_CTRL(channel), 20, 20) == 0) {
2156 DSSERR("RX fifo empty when trying to read.\n");
2161 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
2163 DSSDBG("\theader: %08x\n", val);
2164 dt = FLD_GET(val, 5, 0);
2165 if (dt == DSI_DT_RX_ACK_WITH_ERR) {
2166 u16 err = FLD_GET(val, 23, 8);
2167 dsi_show_rx_ack_with_err(err);
2171 } else if (dt == DSI_DT_RX_SHORT_READ_1) {
2172 u8 data = FLD_GET(val, 15, 8);
2174 DSSDBG("\tDCS short response, 1 byte: %02x\n", data);
2184 } else if (dt == DSI_DT_RX_SHORT_READ_2) {
2185 u16 data = FLD_GET(val, 23, 8);
2187 DSSDBG("\tDCS short response, 2 byte: %04x\n", data);
2194 buf[0] = data & 0xff;
2195 buf[1] = (data >> 8) & 0xff;
2198 } else if (dt == DSI_DT_RX_DCS_LONG_READ) {
2200 int len = FLD_GET(val, 23, 8);
2202 DSSDBG("\tDCS long response, len %d\n", len);
2209 /* two byte checksum ends the packet, not included in len */
2210 for (w = 0; w < len + 2;) {
2212 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
2214 DSSDBG("\t\t%02x %02x %02x %02x\n",
2218 (val >> 24) & 0xff);
2220 for (b = 0; b < 4; ++b) {
2222 buf[w] = (val >> (b * 8)) & 0xff;
2223 /* we discard the 2 byte checksum */
2230 DSSERR("\tunknown datatype 0x%02x\n", dt);
2237 DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n",
2242 EXPORT_SYMBOL(dsi_vc_dcs_read);
2244 int dsi_vc_dcs_read_1(int channel, u8 dcs_cmd, u8 *data)
2248 r = dsi_vc_dcs_read(channel, dcs_cmd, data, 1);
2258 EXPORT_SYMBOL(dsi_vc_dcs_read_1);
2260 int dsi_vc_dcs_read_2(int channel, u8 dcs_cmd, u8 *data1, u8 *data2)
2265 r = dsi_vc_dcs_read(channel, dcs_cmd, buf, 2);
2278 EXPORT_SYMBOL(dsi_vc_dcs_read_2);
2280 int dsi_vc_set_max_rx_packet_size(int channel, u16 len)
2282 return dsi_vc_send_short(channel, DSI_DT_SET_MAX_RET_PKG_SIZE,
2285 EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size);
2287 static void dsi_set_lp_rx_timeout(unsigned ticks, bool x4, bool x16)
2290 unsigned long total_ticks;
2293 BUG_ON(ticks > 0x1fff);
2295 /* ticks in DSI_FCK */
2296 fck = dsi_fclk_rate();
2298 r = dsi_read_reg(DSI_TIMING2);
2299 r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */
2300 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */
2301 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */
2302 r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */
2303 dsi_write_reg(DSI_TIMING2, r);
2305 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
2307 DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n",
2309 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
2310 (total_ticks * 1000) / (fck / 1000 / 1000));
2313 static void dsi_set_ta_timeout(unsigned ticks, bool x8, bool x16)
2316 unsigned long total_ticks;
2319 BUG_ON(ticks > 0x1fff);
2321 /* ticks in DSI_FCK */
2322 fck = dsi_fclk_rate();
2324 r = dsi_read_reg(DSI_TIMING1);
2325 r = FLD_MOD(r, 1, 31, 31); /* TA_TO */
2326 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */
2327 r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */
2328 r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */
2329 dsi_write_reg(DSI_TIMING1, r);
2331 total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1);
2333 DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n",
2335 ticks, x8 ? " x8" : "", x16 ? " x16" : "",
2336 (total_ticks * 1000) / (fck / 1000 / 1000));
2339 static void dsi_set_stop_state_counter(unsigned ticks, bool x4, bool x16)
2342 unsigned long total_ticks;
2345 BUG_ON(ticks > 0x1fff);
2347 /* ticks in DSI_FCK */
2348 fck = dsi_fclk_rate();
2350 r = dsi_read_reg(DSI_TIMING1);
2351 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2352 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */
2353 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */
2354 r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */
2355 dsi_write_reg(DSI_TIMING1, r);
2357 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
2359 DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n",
2361 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
2362 (total_ticks * 1000) / (fck / 1000 / 1000));
2365 static void dsi_set_hs_tx_timeout(unsigned ticks, bool x4, bool x16)
2368 unsigned long total_ticks;
2371 BUG_ON(ticks > 0x1fff);
2373 /* ticks in TxByteClkHS */
2374 fck = dsi_get_txbyteclkhs();
2376 r = dsi_read_reg(DSI_TIMING2);
2377 r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */
2378 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */
2379 r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */
2380 r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */
2381 dsi_write_reg(DSI_TIMING2, r);
2383 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
2385 DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n",
2387 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
2388 (total_ticks * 1000) / (fck / 1000 / 1000));
2390 static int dsi_proto_config(struct omap_dss_device *dssdev)
2395 dsi_config_tx_fifo(DSI_FIFO_SIZE_32,
2400 dsi_config_rx_fifo(DSI_FIFO_SIZE_32,
2405 /* XXX what values for the timeouts? */
2406 dsi_set_stop_state_counter(0x1000, false, false);
2407 dsi_set_ta_timeout(0x1fff, true, true);
2408 dsi_set_lp_rx_timeout(0x1fff, true, true);
2409 dsi_set_hs_tx_timeout(0x1fff, true, true);
2411 switch (dssdev->ctrl.pixel_size) {
2425 r = dsi_read_reg(DSI_CTRL);
2426 r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */
2427 r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */
2428 r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */
2429 r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/
2430 r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
2431 r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */
2432 r = FLD_MOD(r, 2, 13, 12); /* LINE_BUFFER, 2 lines */
2433 r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */
2434 r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */
2435 r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */
2436 r = FLD_MOD(r, 0, 25, 25); /* DCS_CMD_CODE, 1=start, 0=continue */
2438 dsi_write_reg(DSI_CTRL, r);
2440 dsi_vc_initial_config(0);
2441 dsi_vc_initial_config(1);
2442 dsi_vc_initial_config(2);
2443 dsi_vc_initial_config(3);
2448 static void dsi_proto_timings(struct omap_dss_device *dssdev)
2450 unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail;
2451 unsigned tclk_pre, tclk_post;
2452 unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;
2453 unsigned ths_trail, ths_exit;
2454 unsigned ddr_clk_pre, ddr_clk_post;
2455 unsigned enter_hs_mode_lat, exit_hs_mode_lat;
2459 r = dsi_read_reg(DSI_DSIPHY_CFG0);
2460 ths_prepare = FLD_GET(r, 31, 24);
2461 ths_prepare_ths_zero = FLD_GET(r, 23, 16);
2462 ths_zero = ths_prepare_ths_zero - ths_prepare;
2463 ths_trail = FLD_GET(r, 15, 8);
2464 ths_exit = FLD_GET(r, 7, 0);
2466 r = dsi_read_reg(DSI_DSIPHY_CFG1);
2467 tlpx = FLD_GET(r, 22, 16) * 2;
2468 tclk_trail = FLD_GET(r, 15, 8);
2469 tclk_zero = FLD_GET(r, 7, 0);
2471 r = dsi_read_reg(DSI_DSIPHY_CFG2);
2472 tclk_prepare = FLD_GET(r, 7, 0);
2476 /* min 60ns + 52*UI */
2477 tclk_post = ns2ddr(60) + 26;
2479 /* ths_eot is 2 for 2 datalanes and 4 for 1 datalane */
2480 if (dssdev->phy.dsi.data1_lane != 0 &&
2481 dssdev->phy.dsi.data2_lane != 0)
2486 ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
2488 ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot;
2490 BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
2491 BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
2493 r = dsi_read_reg(DSI_CLK_TIMING);
2494 r = FLD_MOD(r, ddr_clk_pre, 15, 8);
2495 r = FLD_MOD(r, ddr_clk_post, 7, 0);
2496 dsi_write_reg(DSI_CLK_TIMING, r);
2498 DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
2502 enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
2503 DIV_ROUND_UP(ths_prepare, 4) +
2504 DIV_ROUND_UP(ths_zero + 3, 4);
2506 exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
2508 r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
2509 FLD_VAL(exit_hs_mode_lat, 15, 0);
2510 dsi_write_reg(DSI_VM_TIMING7, r);
2512 DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
2513 enter_hs_mode_lat, exit_hs_mode_lat);
2517 #define DSI_DECL_VARS \
2518 int __dsi_cb = 0; u32 __dsi_cv = 0;
2520 #define DSI_FLUSH(ch) \
2521 if (__dsi_cb > 0) { \
2522 /*DSSDBG("sending long packet %#010x\n", __dsi_cv);*/ \
2523 dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(ch), __dsi_cv); \
2524 __dsi_cb = __dsi_cv = 0; \
2527 #define DSI_PUSH(ch, data) \
2529 __dsi_cv |= (data) << (__dsi_cb * 8); \
2530 /*DSSDBG("cv = %#010x, cb = %d\n", __dsi_cv, __dsi_cb);*/ \
2531 if (++__dsi_cb > 3) \
2535 static int dsi_update_screen_l4(struct omap_dss_device *dssdev,
2536 int x, int y, int w, int h)
2538 /* Note: supports only 24bit colors in 32bit container */
2540 int fifo_stalls = 0;
2541 int max_dsi_packet_size;
2542 int max_data_per_packet;
2543 int max_pixels_per_packet;
2545 int bytespp = dssdev->ctrl.pixel_size / 8;
2551 struct omap_overlay *ovl;
2555 DSSDBG("dsi_update_screen_l4 (%d,%d %dx%d)\n",
2558 ovl = dssdev->manager->overlays[0];
2560 if (ovl->info.color_mode != OMAP_DSS_COLOR_RGB24U)
2563 if (dssdev->ctrl.pixel_size != 24)
2566 scr_width = ovl->info.screen_width;
2567 data = ovl->info.vaddr;
2569 start_offset = scr_width * y + x;
2570 horiz_inc = scr_width - w;
2573 /* We need header(4) + DCSCMD(1) + pixels(numpix*bytespp) bytes
2576 /* When using CPU, max long packet size is TX buffer size */
2577 max_dsi_packet_size = dsi.vc[0].fifo_size * 32 * 4;
2579 /* we seem to get better perf if we divide the tx fifo to half,
2580 and while the other half is being sent, we fill the other half
2581 max_dsi_packet_size /= 2; */
2583 max_data_per_packet = max_dsi_packet_size - 4 - 1;
2585 max_pixels_per_packet = max_data_per_packet / bytespp;
2587 DSSDBG("max_pixels_per_packet %d\n", max_pixels_per_packet);
2589 pixels_left = w * h;
2591 DSSDBG("total pixels %d\n", pixels_left);
2593 data += start_offset;
2595 while (pixels_left > 0) {
2596 /* 0x2c = write_memory_start */
2597 /* 0x3c = write_memory_continue */
2598 u8 dcs_cmd = first ? 0x2c : 0x3c;
2604 /* using fifo not empty */
2605 /* TX_FIFO_NOT_EMPTY */
2606 while (FLD_GET(dsi_read_reg(DSI_VC_CTRL(0)), 5, 5)) {
2608 if (fifo_stalls > 0xfffff) {
2609 DSSERR("fifo stalls overflow, pixels left %d\n",
2617 /* using fifo emptiness */
2618 while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 <
2619 max_dsi_packet_size) {
2621 if (fifo_stalls > 0xfffff) {
2622 DSSERR("fifo stalls overflow, pixels left %d\n",
2629 while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 == 0) {
2631 if (fifo_stalls > 0xfffff) {
2632 DSSERR("fifo stalls overflow, pixels left %d\n",
2639 pixels = min(max_pixels_per_packet, pixels_left);
2641 pixels_left -= pixels;
2643 dsi_vc_write_long_header(0, DSI_DT_DCS_LONG_WRITE,
2644 1 + pixels * bytespp, 0);
2646 DSI_PUSH(0, dcs_cmd);
2648 while (pixels-- > 0) {
2649 u32 pix = __raw_readl(data++);
2651 DSI_PUSH(0, (pix >> 16) & 0xff);
2652 DSI_PUSH(0, (pix >> 8) & 0xff);
2653 DSI_PUSH(0, (pix >> 0) & 0xff);
2656 if (current_x == x+w) {
2668 static void dsi_update_screen_dispc(struct omap_dss_device *dssdev,
2669 u16 x, u16 y, u16 w, u16 h)
2675 unsigned packet_payload;
2676 unsigned packet_len;
2679 const unsigned channel = dsi.update_channel;
2680 /* line buffer is 1024 x 24bits */
2681 /* XXX: for some reason using full buffer size causes considerable TX
2682 * slowdown with update sizes that fill the whole buffer */
2683 const unsigned line_buf_size = 1023 * 3;
2685 DSSDBG("dsi_update_screen_dispc(%d,%d %dx%d)\n",
2688 dsi_vc_config_vp(channel);
2690 bytespp = dssdev->ctrl.pixel_size / 8;
2691 bytespl = w * bytespp;
2692 bytespf = bytespl * h;
2694 /* NOTE: packet_payload has to be equal to N * bytespl, where N is
2695 * number of lines in a packet. See errata about VP_CLK_RATIO */
2697 if (bytespf < line_buf_size)
2698 packet_payload = bytespf;
2700 packet_payload = (line_buf_size) / bytespl * bytespl;
2702 packet_len = packet_payload + 1; /* 1 byte for DCS cmd */
2703 total_len = (bytespf / packet_payload) * packet_len;
2705 if (bytespf % packet_payload)
2706 total_len += (bytespf % packet_payload) + 1;
2708 l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
2709 dsi_write_reg(DSI_VC_TE(channel), l);
2711 dsi_vc_write_long_header(channel, DSI_DT_DCS_LONG_WRITE, packet_len, 0);
2714 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
2716 l = FLD_MOD(l, 1, 31, 31); /* TE_START */
2717 dsi_write_reg(DSI_VC_TE(channel), l);
2719 /* We put SIDLEMODE to no-idle for the duration of the transfer,
2720 * because DSS interrupts are not capable of waking up the CPU and the
2721 * framedone interrupt could be delayed for quite a long time. I think
2722 * the same goes for any DSS interrupts, but for some reason I have not
2723 * seen the problem anywhere else than here.
2725 dispc_disable_sidle();
2727 dsi_perf_mark_start();
2729 r = queue_delayed_work(dsi.workqueue, &dsi.framedone_timeout_work,
2730 msecs_to_jiffies(250));
2733 dss_start_update(dssdev);
2735 if (dsi.te_enabled) {
2736 /* disable LP_RX_TO, so that we can receive TE. Time to wait
2737 * for TE is longer than the timer allows */
2738 REG_FLD_MOD(DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
2740 dsi_vc_send_bta(channel);
2742 #ifdef DSI_CATCH_MISSING_TE
2743 mod_timer(&dsi.te_timer, jiffies + msecs_to_jiffies(250));
2748 #ifdef DSI_CATCH_MISSING_TE
2749 static void dsi_te_timeout(unsigned long arg)
2751 DSSERR("TE not received for 250ms!\n");
2755 static void dsi_handle_framedone(int error)
2757 const int channel = dsi.update_channel;
2759 cancel_delayed_work(&dsi.framedone_timeout_work);
2761 dsi_vc_disable_bta_irq(channel);
2763 /* SIDLEMODE back to smart-idle */
2764 dispc_enable_sidle();
2766 dsi.bta_callback = NULL;
2768 if (dsi.te_enabled) {
2769 /* enable LP_RX_TO again after the TE */
2770 REG_FLD_MOD(DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
2773 /* RX_FIFO_NOT_EMPTY */
2774 if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
2775 DSSERR("Received error during frame transfer:\n");
2776 dsi_vc_flush_receive_data(channel);
2781 dsi.framedone_callback(error, dsi.framedone_data);
2784 dsi_perf_show("DISPC");
2787 static void dsi_framedone_timeout_work_callback(struct work_struct *work)
2789 /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after
2790 * 250ms which would conflict with this timeout work. What should be
2791 * done is first cancel the transfer on the HW, and then cancel the
2792 * possibly scheduled framedone work. However, cancelling the transfer
2793 * on the HW is buggy, and would probably require resetting the whole
2796 DSSERR("Framedone not received for 250ms!\n");
2798 dsi_handle_framedone(-ETIMEDOUT);
2801 static void dsi_framedone_bta_callback(void)
2803 dsi_handle_framedone(0);
2805 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
2806 dispc_fake_vsync_irq();
2810 static void dsi_framedone_irq_callback(void *data, u32 mask)
2812 const int channel = dsi.update_channel;
2815 /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
2816 * turns itself off. However, DSI still has the pixels in its buffers,
2817 * and is sending the data.
2820 if (dsi.te_enabled) {
2821 /* enable LP_RX_TO again after the TE */
2822 REG_FLD_MOD(DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
2825 /* Send BTA after the frame. We need this for the TE to work, as TE
2826 * trigger is only sent for BTAs without preceding packet. Thus we need
2827 * to BTA after the pixel packets so that next BTA will cause TE
2830 * This is not needed when TE is not in use, but we do it anyway to
2831 * make sure that the transfer has been completed. It would be more
2832 * optimal, but more complex, to wait only just before starting next
2835 * Also, as there's no interrupt telling when the transfer has been
2836 * done and the channel could be reconfigured, the only way is to
2837 * busyloop until TE_SIZE is zero. With BTA we can do this
2841 dsi.bta_callback = dsi_framedone_bta_callback;
2845 dsi_vc_enable_bta_irq(channel);
2847 r = dsi_vc_send_bta(channel);
2849 DSSERR("BTA after framedone failed\n");
2850 dsi_handle_framedone(-EIO);
2854 int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
2855 u16 *x, u16 *y, u16 *w, u16 *h,
2856 bool enlarge_update_area)
2860 dssdev->driver->get_resolution(dssdev, &dw, &dh);
2862 if (*x > dw || *y > dh)
2874 if (*w == 0 || *h == 0)
2877 dsi_perf_mark_setup();
2879 if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
2880 dss_setup_partial_planes(dssdev, x, y, w, h,
2881 enlarge_update_area);
2882 dispc_set_lcd_size(dssdev->manager->id, *w, *h);
2887 EXPORT_SYMBOL(omap_dsi_prepare_update);
2889 int omap_dsi_update(struct omap_dss_device *dssdev,
2891 u16 x, u16 y, u16 w, u16 h,
2892 void (*callback)(int, void *), void *data)
2894 dsi.update_channel = channel;
2896 /* OMAP DSS cannot send updates of odd widths.
2897 * omap_dsi_prepare_update() makes the widths even, but add a BUG_ON
2898 * here to make sure we catch erroneous updates. Otherwise we'll only
2899 * see rather obscure HW error happening, as DSS halts. */
2902 if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
2903 dsi.framedone_callback = callback;
2904 dsi.framedone_data = data;
2906 dsi.update_region.x = x;
2907 dsi.update_region.y = y;
2908 dsi.update_region.w = w;
2909 dsi.update_region.h = h;
2910 dsi.update_region.device = dssdev;
2912 dsi_update_screen_dispc(dssdev, x, y, w, h);
2916 r = dsi_update_screen_l4(dssdev, x, y, w, h);
2920 dsi_perf_show("L4");
2926 EXPORT_SYMBOL(omap_dsi_update);
2930 static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
2934 r = omap_dispc_register_isr(dsi_framedone_irq_callback, NULL,
2935 DISPC_IRQ_FRAMEDONE);
2937 DSSERR("can't get FRAMEDONE irq\n");
2941 dispc_set_lcd_display_type(dssdev->manager->id,
2942 OMAP_DSS_LCD_DISPLAY_TFT);
2944 dispc_set_parallel_interface_mode(dssdev->manager->id,
2945 OMAP_DSS_PARALLELMODE_DSI);
2946 dispc_enable_fifohandcheck(dssdev->manager->id, 1);
2948 dispc_set_tft_data_lines(dssdev->manager->id, dssdev->ctrl.pixel_size);
2951 struct omap_video_timings timings = {
2960 dispc_set_lcd_timings(dssdev->manager->id, &timings);
2966 static void dsi_display_uninit_dispc(struct omap_dss_device *dssdev)
2968 omap_dispc_unregister_isr(dsi_framedone_irq_callback, NULL,
2969 DISPC_IRQ_FRAMEDONE);
2972 static int dsi_configure_dsi_clocks(struct omap_dss_device *dssdev)
2974 struct dsi_clock_info cinfo;
2977 /* we always use DSS2_FCK as input clock */
2978 cinfo.use_dss2_fck = true;
2979 cinfo.regn = dssdev->phy.dsi.div.regn;
2980 cinfo.regm = dssdev->phy.dsi.div.regm;
2981 cinfo.regm3 = dssdev->phy.dsi.div.regm3;
2982 cinfo.regm4 = dssdev->phy.dsi.div.regm4;
2983 r = dsi_calc_clock_rates(dssdev, &cinfo);
2985 DSSERR("Failed to calc dsi clocks\n");
2989 r = dsi_pll_set_clock_div(&cinfo);
2991 DSSERR("Failed to set dsi clocks\n");
2998 static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev)
3000 struct dispc_clock_info dispc_cinfo;
3002 unsigned long long fck;
3004 fck = dsi_get_dsi1_pll_rate();
3006 dispc_cinfo.lck_div = dssdev->phy.dsi.div.lck_div;
3007 dispc_cinfo.pck_div = dssdev->phy.dsi.div.pck_div;
3009 r = dispc_calc_clock_rates(fck, &dispc_cinfo);
3011 DSSERR("Failed to calc dispc clocks\n");
3015 r = dispc_set_clock_div(dssdev->manager->id, &dispc_cinfo);
3017 DSSERR("Failed to set dispc clocks\n");
3024 static int dsi_display_init_dsi(struct omap_dss_device *dssdev)
3028 _dsi_print_reset_status();
3030 r = dsi_pll_init(dssdev, true, true);
3034 r = dsi_configure_dsi_clocks(dssdev);
3038 dss_select_dispc_clk_source(DSS_SRC_DSI1_PLL_FCLK);
3039 dss_select_dsi_clk_source(DSS_SRC_DSI2_PLL_FCLK);
3043 r = dsi_configure_dispc_clocks(dssdev);
3047 r = dsi_complexio_init(dssdev);
3051 _dsi_print_reset_status();
3053 dsi_proto_timings(dssdev);
3054 dsi_set_lp_clk_divisor(dssdev);
3057 _dsi_print_reset_status();
3059 r = dsi_proto_config(dssdev);
3063 /* enable interface */
3064 dsi_vc_enable(0, 1);
3065 dsi_vc_enable(1, 1);
3066 dsi_vc_enable(2, 1);
3067 dsi_vc_enable(3, 1);
3069 dsi_force_tx_stop_mode_io();
3073 dsi_complexio_uninit();
3075 dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
3076 dss_select_dsi_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
3083 static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev)
3085 /* disable interface */
3087 dsi_vc_enable(0, 0);
3088 dsi_vc_enable(1, 0);
3089 dsi_vc_enable(2, 0);
3090 dsi_vc_enable(3, 0);
3092 dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
3093 dss_select_dsi_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
3094 dsi_complexio_uninit();
3098 static int dsi_core_init(void)
3101 REG_FLD_MOD(DSI_SYSCONFIG, 1, 0, 0);
3104 REG_FLD_MOD(DSI_SYSCONFIG, 1, 2, 2);
3106 /* SIDLEMODE smart-idle */
3107 REG_FLD_MOD(DSI_SYSCONFIG, 2, 4, 3);
3109 _dsi_initialize_irq();
3114 int omapdss_dsi_display_enable(struct omap_dss_device *dssdev)
3118 DSSDBG("dsi_display_enable\n");
3120 WARN_ON(!dsi_bus_is_locked());
3122 mutex_lock(&dsi.lock);
3124 r = omap_dss_start_device(dssdev);
3126 DSSERR("failed to start device\n");
3131 dsi_enable_pll_clock(1);
3139 r = dsi_display_init_dispc(dssdev);
3143 r = dsi_display_init_dsi(dssdev);
3147 mutex_unlock(&dsi.lock);
3152 dsi_display_uninit_dispc(dssdev);
3155 dsi_enable_pll_clock(0);
3156 omap_dss_stop_device(dssdev);
3158 mutex_unlock(&dsi.lock);
3159 DSSDBG("dsi_display_enable FAILED\n");
3162 EXPORT_SYMBOL(omapdss_dsi_display_enable);
3164 void omapdss_dsi_display_disable(struct omap_dss_device *dssdev)
3166 DSSDBG("dsi_display_disable\n");
3168 WARN_ON(!dsi_bus_is_locked());
3170 mutex_lock(&dsi.lock);
3172 dsi_display_uninit_dispc(dssdev);
3174 dsi_display_uninit_dsi(dssdev);
3177 dsi_enable_pll_clock(0);
3179 omap_dss_stop_device(dssdev);
3181 mutex_unlock(&dsi.lock);
3183 EXPORT_SYMBOL(omapdss_dsi_display_disable);
3185 int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
3187 dsi.te_enabled = enable;
3190 EXPORT_SYMBOL(omapdss_dsi_enable_te);
3192 void dsi_get_overlay_fifo_thresholds(enum omap_plane plane,
3193 u32 fifo_size, enum omap_burst_size *burst_size,
3194 u32 *fifo_low, u32 *fifo_high)
3196 unsigned burst_size_bytes;
3198 *burst_size = OMAP_DSS_BURST_16x32;
3199 burst_size_bytes = 16 * 32 / 8;
3201 *fifo_high = fifo_size - burst_size_bytes;
3202 *fifo_low = fifo_size - burst_size_bytes * 2;
3205 int dsi_init_display(struct omap_dss_device *dssdev)
3207 DSSDBG("DSI init\n");
3209 /* XXX these should be figured out dynamically */
3210 dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE |
3211 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM;
3213 dsi.vc[0].dssdev = dssdev;
3214 dsi.vc[1].dssdev = dssdev;
3216 if (dsi.vdds_dsi_reg == NULL) {
3217 struct regulator *vdds_dsi;
3219 vdds_dsi = regulator_get(&dsi.pdev->dev, "vdds_dsi");
3221 if (IS_ERR(vdds_dsi)) {
3222 DSSERR("can't get VDDS_DSI regulator\n");
3223 return PTR_ERR(vdds_dsi);
3226 dsi.vdds_dsi_reg = vdds_dsi;
3232 void dsi_wait_dsi1_pll_active(void)
3234 if (wait_for_bit_change(DSI_PLL_STATUS, 7, 1) != 1)
3235 DSSERR("DSI1 PLL clock not active\n");
3238 void dsi_wait_dsi2_pll_active(void)
3240 if (wait_for_bit_change(DSI_PLL_STATUS, 8, 1) != 1)
3241 DSSERR("DSI2 PLL clock not active\n");
3244 static int dsi_init(struct platform_device *pdev)
3248 struct resource *dsi_mem;
3250 spin_lock_init(&dsi.errors_lock);
3253 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3254 spin_lock_init(&dsi.irq_stats_lock);
3255 dsi.irq_stats.last_reset = jiffies;
3258 init_completion(&dsi.bta_completion);
3260 mutex_init(&dsi.lock);
3261 sema_init(&dsi.bus_lock, 1);
3263 dsi.workqueue = create_singlethread_workqueue("dsi");
3264 if (dsi.workqueue == NULL)
3267 INIT_DELAYED_WORK_DEFERRABLE(&dsi.framedone_timeout_work,
3268 dsi_framedone_timeout_work_callback);
3270 #ifdef DSI_CATCH_MISSING_TE
3271 init_timer(&dsi.te_timer);
3272 dsi.te_timer.function = dsi_te_timeout;
3273 dsi.te_timer.data = 0;
3275 dsi_mem = platform_get_resource(dsi.pdev, IORESOURCE_MEM, 0);
3277 DSSERR("can't get IORESOURCE_MEM DSI\n");
3281 dsi.base = ioremap(dsi_mem->start, resource_size(dsi_mem));
3283 DSSERR("can't ioremap DSI\n");
3287 dsi.irq = platform_get_irq(dsi.pdev, 0);
3289 DSSERR("platform_get_irq failed\n");
3294 r = request_irq(dsi.irq, omap_dsi_irq_handler, IRQF_SHARED,
3295 "OMAP DSI1", dsi.pdev);
3297 DSSERR("request_irq failed\n");
3303 rev = dsi_read_reg(DSI_REVISION);
3304 dev_dbg(&pdev->dev, "OMAP DSI rev %d.%d\n",
3305 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3313 destroy_workqueue(dsi.workqueue);
3317 static void dsi_exit(void)
3319 if (dsi.vdds_dsi_reg != NULL) {
3320 regulator_put(dsi.vdds_dsi_reg);
3321 dsi.vdds_dsi_reg = NULL;
3324 free_irq(dsi.irq, dsi.pdev);
3327 destroy_workqueue(dsi.workqueue);
3329 DSSDBG("omap_dsi_exit\n");
3332 /* DSI1 HW IP initialisation */
3333 static int omap_dsi1hw_probe(struct platform_device *pdev)
3339 DSSERR("Failed to initialize DSI\n");
3346 static int omap_dsi1hw_remove(struct platform_device *pdev)
3352 static struct platform_driver omap_dsi1hw_driver = {
3353 .probe = omap_dsi1hw_probe,
3354 .remove = omap_dsi1hw_remove,
3356 .name = "omapdss_dsi1",
3357 .owner = THIS_MODULE,
3361 int dsi_init_platform_driver(void)
3363 return platform_driver_register(&omap_dsi1hw_driver);
3366 void dsi_uninit_platform_driver(void)
3368 return platform_driver_unregister(&omap_dsi1hw_driver);