2 * linux/drivers/video/omap2/dss/dsi.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #define DSS_SUBSYS_NAME "DSI"
22 #include <linux/kernel.h>
24 #include <linux/clk.h>
25 #include <linux/device.h>
26 #include <linux/err.h>
27 #include <linux/interrupt.h>
28 #include <linux/delay.h>
29 #include <linux/mutex.h>
30 #include <linux/semaphore.h>
31 #include <linux/seq_file.h>
32 #include <linux/platform_device.h>
33 #include <linux/regulator/consumer.h>
34 #include <linux/wait.h>
35 #include <linux/workqueue.h>
37 #include <plat/display.h>
38 #include <plat/clock.h>
41 #include "dss_features.h"
43 /*#define VERBOSE_IRQ*/
44 #define DSI_CATCH_MISSING_TE
46 struct dsi_reg { u16 idx; };
48 #define DSI_REG(idx) ((const struct dsi_reg) { idx })
50 #define DSI_SZ_REGS SZ_1K
51 /* DSI Protocol Engine */
53 #define DSI_REVISION DSI_REG(0x0000)
54 #define DSI_SYSCONFIG DSI_REG(0x0010)
55 #define DSI_SYSSTATUS DSI_REG(0x0014)
56 #define DSI_IRQSTATUS DSI_REG(0x0018)
57 #define DSI_IRQENABLE DSI_REG(0x001C)
58 #define DSI_CTRL DSI_REG(0x0040)
59 #define DSI_COMPLEXIO_CFG1 DSI_REG(0x0048)
60 #define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(0x004C)
61 #define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(0x0050)
62 #define DSI_CLK_CTRL DSI_REG(0x0054)
63 #define DSI_TIMING1 DSI_REG(0x0058)
64 #define DSI_TIMING2 DSI_REG(0x005C)
65 #define DSI_VM_TIMING1 DSI_REG(0x0060)
66 #define DSI_VM_TIMING2 DSI_REG(0x0064)
67 #define DSI_VM_TIMING3 DSI_REG(0x0068)
68 #define DSI_CLK_TIMING DSI_REG(0x006C)
69 #define DSI_TX_FIFO_VC_SIZE DSI_REG(0x0070)
70 #define DSI_RX_FIFO_VC_SIZE DSI_REG(0x0074)
71 #define DSI_COMPLEXIO_CFG2 DSI_REG(0x0078)
72 #define DSI_RX_FIFO_VC_FULLNESS DSI_REG(0x007C)
73 #define DSI_VM_TIMING4 DSI_REG(0x0080)
74 #define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(0x0084)
75 #define DSI_VM_TIMING5 DSI_REG(0x0088)
76 #define DSI_VM_TIMING6 DSI_REG(0x008C)
77 #define DSI_VM_TIMING7 DSI_REG(0x0090)
78 #define DSI_STOPCLK_TIMING DSI_REG(0x0094)
79 #define DSI_VC_CTRL(n) DSI_REG(0x0100 + (n * 0x20))
80 #define DSI_VC_TE(n) DSI_REG(0x0104 + (n * 0x20))
81 #define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(0x0108 + (n * 0x20))
82 #define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(0x010C + (n * 0x20))
83 #define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(0x0110 + (n * 0x20))
84 #define DSI_VC_IRQSTATUS(n) DSI_REG(0x0118 + (n * 0x20))
85 #define DSI_VC_IRQENABLE(n) DSI_REG(0x011C + (n * 0x20))
89 #define DSI_DSIPHY_CFG0 DSI_REG(0x200 + 0x0000)
90 #define DSI_DSIPHY_CFG1 DSI_REG(0x200 + 0x0004)
91 #define DSI_DSIPHY_CFG2 DSI_REG(0x200 + 0x0008)
92 #define DSI_DSIPHY_CFG5 DSI_REG(0x200 + 0x0014)
94 /* DSI_PLL_CTRL_SCP */
96 #define DSI_PLL_CONTROL DSI_REG(0x300 + 0x0000)
97 #define DSI_PLL_STATUS DSI_REG(0x300 + 0x0004)
98 #define DSI_PLL_GO DSI_REG(0x300 + 0x0008)
99 #define DSI_PLL_CONFIGURATION1 DSI_REG(0x300 + 0x000C)
100 #define DSI_PLL_CONFIGURATION2 DSI_REG(0x300 + 0x0010)
102 #define REG_GET(idx, start, end) \
103 FLD_GET(dsi_read_reg(idx), start, end)
105 #define REG_FLD_MOD(idx, val, start, end) \
106 dsi_write_reg(idx, FLD_MOD(dsi_read_reg(idx), val, start, end))
108 /* Global interrupts */
109 #define DSI_IRQ_VC0 (1 << 0)
110 #define DSI_IRQ_VC1 (1 << 1)
111 #define DSI_IRQ_VC2 (1 << 2)
112 #define DSI_IRQ_VC3 (1 << 3)
113 #define DSI_IRQ_WAKEUP (1 << 4)
114 #define DSI_IRQ_RESYNC (1 << 5)
115 #define DSI_IRQ_PLL_LOCK (1 << 7)
116 #define DSI_IRQ_PLL_UNLOCK (1 << 8)
117 #define DSI_IRQ_PLL_RECALL (1 << 9)
118 #define DSI_IRQ_COMPLEXIO_ERR (1 << 10)
119 #define DSI_IRQ_HS_TX_TIMEOUT (1 << 14)
120 #define DSI_IRQ_LP_RX_TIMEOUT (1 << 15)
121 #define DSI_IRQ_TE_TRIGGER (1 << 16)
122 #define DSI_IRQ_ACK_TRIGGER (1 << 17)
123 #define DSI_IRQ_SYNC_LOST (1 << 18)
124 #define DSI_IRQ_LDO_POWER_GOOD (1 << 19)
125 #define DSI_IRQ_TA_TIMEOUT (1 << 20)
126 #define DSI_IRQ_ERROR_MASK \
127 (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
129 #define DSI_IRQ_CHANNEL_MASK 0xf
131 /* Virtual channel interrupts */
132 #define DSI_VC_IRQ_CS (1 << 0)
133 #define DSI_VC_IRQ_ECC_CORR (1 << 1)
134 #define DSI_VC_IRQ_PACKET_SENT (1 << 2)
135 #define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3)
136 #define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4)
137 #define DSI_VC_IRQ_BTA (1 << 5)
138 #define DSI_VC_IRQ_ECC_NO_CORR (1 << 6)
139 #define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7)
140 #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
141 #define DSI_VC_IRQ_ERROR_MASK \
142 (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
143 DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
144 DSI_VC_IRQ_FIFO_TX_UDF)
146 /* ComplexIO interrupts */
147 #define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0)
148 #define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1)
149 #define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2)
150 #define DSI_CIO_IRQ_ERRESC1 (1 << 5)
151 #define DSI_CIO_IRQ_ERRESC2 (1 << 6)
152 #define DSI_CIO_IRQ_ERRESC3 (1 << 7)
153 #define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10)
154 #define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11)
155 #define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12)
156 #define DSI_CIO_IRQ_STATEULPS1 (1 << 15)
157 #define DSI_CIO_IRQ_STATEULPS2 (1 << 16)
158 #define DSI_CIO_IRQ_STATEULPS3 (1 << 17)
159 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20)
160 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21)
161 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22)
162 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23)
163 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24)
164 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25)
165 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30)
166 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31)
167 #define DSI_CIO_IRQ_ERROR_MASK \
168 (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
169 DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
170 DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRCONTROL1 | \
171 DSI_CIO_IRQ_ERRCONTROL2 | DSI_CIO_IRQ_ERRCONTROL3 | \
172 DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
173 DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
174 DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3)
176 #define DSI_DT_DCS_SHORT_WRITE_0 0x05
177 #define DSI_DT_DCS_SHORT_WRITE_1 0x15
178 #define DSI_DT_DCS_READ 0x06
179 #define DSI_DT_SET_MAX_RET_PKG_SIZE 0x37
180 #define DSI_DT_NULL_PACKET 0x09
181 #define DSI_DT_DCS_LONG_WRITE 0x39
183 #define DSI_DT_RX_ACK_WITH_ERR 0x02
184 #define DSI_DT_RX_DCS_LONG_READ 0x1c
185 #define DSI_DT_RX_SHORT_READ_1 0x21
186 #define DSI_DT_RX_SHORT_READ_2 0x22
188 typedef void (*omap_dsi_isr_t) (void *arg, u32 mask);
190 #define DSI_MAX_NR_ISRS 2
192 struct dsi_isr_data {
200 DSI_FIFO_SIZE_32 = 1,
201 DSI_FIFO_SIZE_64 = 2,
202 DSI_FIFO_SIZE_96 = 3,
203 DSI_FIFO_SIZE_128 = 4,
211 struct dsi_update_region {
213 struct omap_dss_device *device;
216 struct dsi_irq_stats {
217 unsigned long last_reset;
219 unsigned dsi_irqs[32];
220 unsigned vc_irqs[4][32];
221 unsigned cio_irqs[32];
224 struct dsi_isr_tables {
225 struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS];
226 struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS];
227 struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS];
232 struct platform_device *pdev;
236 struct dsi_clock_info current_cinfo;
238 struct regulator *vdds_dsi_reg;
241 enum dsi_vc_mode mode;
242 struct omap_dss_device *dssdev;
243 enum fifo_size fifo_size;
248 struct semaphore bus_lock;
253 struct dsi_isr_tables isr_tables;
254 /* space for a copy used by the interrupt handler */
255 struct dsi_isr_tables isr_tables_copy;
258 struct dsi_update_region update_region;
262 struct workqueue_struct *workqueue;
264 void (*framedone_callback)(int, void *);
265 void *framedone_data;
267 struct delayed_work framedone_timeout_work;
269 #ifdef DSI_CATCH_MISSING_TE
270 struct timer_list te_timer;
273 unsigned long cache_req_pck;
274 unsigned long cache_clk_freq;
275 struct dsi_clock_info cache_cinfo;
278 spinlock_t errors_lock;
280 ktime_t perf_setup_time;
281 ktime_t perf_start_time;
286 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
287 spinlock_t irq_stats_lock;
288 struct dsi_irq_stats irq_stats;
290 /* DSI PLL Parameter Ranges */
291 unsigned long regm_max, regn_max;
292 unsigned long regm_dispc_max, regm_dsi_max;
293 unsigned long fint_min, fint_max;
294 unsigned long lpdiv_max;
298 static unsigned int dsi_perf;
299 module_param_named(dsi_perf, dsi_perf, bool, 0644);
302 static inline void dsi_write_reg(const struct dsi_reg idx, u32 val)
304 __raw_writel(val, dsi.base + idx.idx);
307 static inline u32 dsi_read_reg(const struct dsi_reg idx)
309 return __raw_readl(dsi.base + idx.idx);
313 void dsi_save_context(void)
317 void dsi_restore_context(void)
321 void dsi_bus_lock(void)
325 EXPORT_SYMBOL(dsi_bus_lock);
327 void dsi_bus_unlock(void)
331 EXPORT_SYMBOL(dsi_bus_unlock);
333 static bool dsi_bus_is_locked(void)
335 return dsi.bus_lock.count == 0;
338 static void dsi_completion_handler(void *data, u32 mask)
340 complete((struct completion *)data);
343 static inline int wait_for_bit_change(const struct dsi_reg idx, int bitnum,
348 while (REG_GET(idx, bitnum, bitnum) != value) {
357 static void dsi_perf_mark_setup(void)
359 dsi.perf_setup_time = ktime_get();
362 static void dsi_perf_mark_start(void)
364 dsi.perf_start_time = ktime_get();
367 static void dsi_perf_show(const char *name)
369 ktime_t t, setup_time, trans_time;
371 u32 setup_us, trans_us, total_us;
378 setup_time = ktime_sub(dsi.perf_start_time, dsi.perf_setup_time);
379 setup_us = (u32)ktime_to_us(setup_time);
383 trans_time = ktime_sub(t, dsi.perf_start_time);
384 trans_us = (u32)ktime_to_us(trans_time);
388 total_us = setup_us + trans_us;
390 total_bytes = dsi.update_region.w *
391 dsi.update_region.h *
392 dsi.update_region.device->ctrl.pixel_size / 8;
394 printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), "
395 "%u bytes, %u kbytes/sec\n",
400 1000*1000 / total_us,
402 total_bytes * 1000 / total_us);
405 #define dsi_perf_mark_setup()
406 #define dsi_perf_mark_start()
407 #define dsi_perf_show(x)
410 static void print_irq_status(u32 status)
416 if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0)
419 printk(KERN_DEBUG "DSI IRQ: 0x%x: ", status);
422 if (status & DSI_IRQ_##x) \
448 static void print_irq_status_vc(int channel, u32 status)
454 if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
457 printk(KERN_DEBUG "DSI VC(%d) IRQ 0x%x: ", channel, status);
460 if (status & DSI_VC_IRQ_##x) \
477 static void print_irq_status_cio(u32 status)
482 printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status);
485 if (status & DSI_CIO_IRQ_##x) \
499 PIS(ERRCONTENTIONLP0_1);
500 PIS(ERRCONTENTIONLP1_1);
501 PIS(ERRCONTENTIONLP0_2);
502 PIS(ERRCONTENTIONLP1_2);
503 PIS(ERRCONTENTIONLP0_3);
504 PIS(ERRCONTENTIONLP1_3);
505 PIS(ULPSACTIVENOT_ALL0);
506 PIS(ULPSACTIVENOT_ALL1);
512 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
513 static void dsi_collect_irq_stats(u32 irqstatus, u32 *vcstatus, u32 ciostatus)
517 spin_lock(&dsi.irq_stats_lock);
519 dsi.irq_stats.irq_count++;
520 dss_collect_irq_stats(irqstatus, dsi.irq_stats.dsi_irqs);
522 for (i = 0; i < 4; ++i)
523 dss_collect_irq_stats(vcstatus[i], dsi.irq_stats.vc_irqs[i]);
525 dss_collect_irq_stats(ciostatus, dsi.irq_stats.cio_irqs);
527 spin_unlock(&dsi.irq_stats_lock);
530 #define dsi_collect_irq_stats(irqstatus, vcstatus, ciostatus)
533 static int debug_irq;
535 static void dsi_handle_irq_errors(u32 irqstatus, u32 *vcstatus, u32 ciostatus)
539 if (irqstatus & DSI_IRQ_ERROR_MASK) {
540 DSSERR("DSI error, irqstatus %x\n", irqstatus);
541 print_irq_status(irqstatus);
542 spin_lock(&dsi.errors_lock);
543 dsi.errors |= irqstatus & DSI_IRQ_ERROR_MASK;
544 spin_unlock(&dsi.errors_lock);
545 } else if (debug_irq) {
546 print_irq_status(irqstatus);
549 for (i = 0; i < 4; ++i) {
550 if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) {
551 DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
553 print_irq_status_vc(i, vcstatus[i]);
554 } else if (debug_irq) {
555 print_irq_status_vc(i, vcstatus[i]);
559 if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) {
560 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
561 print_irq_status_cio(ciostatus);
562 } else if (debug_irq) {
563 print_irq_status_cio(ciostatus);
567 static void dsi_call_isrs(struct dsi_isr_data *isr_array,
568 unsigned isr_array_size, u32 irqstatus)
570 struct dsi_isr_data *isr_data;
573 for (i = 0; i < isr_array_size; i++) {
574 isr_data = &isr_array[i];
575 if (isr_data->isr && isr_data->mask & irqstatus)
576 isr_data->isr(isr_data->arg, irqstatus);
580 static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables,
581 u32 irqstatus, u32 *vcstatus, u32 ciostatus)
585 dsi_call_isrs(isr_tables->isr_table,
586 ARRAY_SIZE(isr_tables->isr_table),
589 for (i = 0; i < 4; ++i) {
590 if (vcstatus[i] == 0)
592 dsi_call_isrs(isr_tables->isr_table_vc[i],
593 ARRAY_SIZE(isr_tables->isr_table_vc[i]),
598 dsi_call_isrs(isr_tables->isr_table_cio,
599 ARRAY_SIZE(isr_tables->isr_table_cio),
603 static irqreturn_t omap_dsi_irq_handler(int irq, void *arg)
605 u32 irqstatus, vcstatus[4], ciostatus;
608 spin_lock(&dsi.irq_lock);
610 irqstatus = dsi_read_reg(DSI_IRQSTATUS);
612 /* IRQ is not for us */
614 spin_unlock(&dsi.irq_lock);
618 dsi_write_reg(DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
619 /* flush posted write */
620 dsi_read_reg(DSI_IRQSTATUS);
622 for (i = 0; i < 4; ++i) {
623 if ((irqstatus & (1 << i)) == 0) {
628 vcstatus[i] = dsi_read_reg(DSI_VC_IRQSTATUS(i));
630 dsi_write_reg(DSI_VC_IRQSTATUS(i), vcstatus[i]);
631 /* flush posted write */
632 dsi_read_reg(DSI_VC_IRQSTATUS(i));
635 if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
636 ciostatus = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
638 dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
639 /* flush posted write */
640 dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
645 #ifdef DSI_CATCH_MISSING_TE
646 if (irqstatus & DSI_IRQ_TE_TRIGGER)
647 del_timer(&dsi.te_timer);
650 /* make a copy and unlock, so that isrs can unregister
652 memcpy(&dsi.isr_tables_copy, &dsi.isr_tables, sizeof(dsi.isr_tables));
654 spin_unlock(&dsi.irq_lock);
656 dsi_handle_isrs(&dsi.isr_tables_copy, irqstatus, vcstatus, ciostatus);
658 dsi_handle_irq_errors(irqstatus, vcstatus, ciostatus);
660 dsi_collect_irq_stats(irqstatus, vcstatus, ciostatus);
665 /* dsi.irq_lock has to be locked by the caller */
666 static void _omap_dsi_configure_irqs(struct dsi_isr_data *isr_array,
667 unsigned isr_array_size, u32 default_mask,
668 const struct dsi_reg enable_reg,
669 const struct dsi_reg status_reg)
671 struct dsi_isr_data *isr_data;
678 for (i = 0; i < isr_array_size; i++) {
679 isr_data = &isr_array[i];
681 if (isr_data->isr == NULL)
684 mask |= isr_data->mask;
687 old_mask = dsi_read_reg(enable_reg);
688 /* clear the irqstatus for newly enabled irqs */
689 dsi_write_reg(status_reg, (mask ^ old_mask) & mask);
690 dsi_write_reg(enable_reg, mask);
692 /* flush posted writes */
693 dsi_read_reg(enable_reg);
694 dsi_read_reg(status_reg);
697 /* dsi.irq_lock has to be locked by the caller */
698 static void _omap_dsi_set_irqs(void)
700 u32 mask = DSI_IRQ_ERROR_MASK;
701 #ifdef DSI_CATCH_MISSING_TE
702 mask |= DSI_IRQ_TE_TRIGGER;
704 _omap_dsi_configure_irqs(dsi.isr_tables.isr_table,
705 ARRAY_SIZE(dsi.isr_tables.isr_table), mask,
706 DSI_IRQENABLE, DSI_IRQSTATUS);
709 /* dsi.irq_lock has to be locked by the caller */
710 static void _omap_dsi_set_irqs_vc(int vc)
712 _omap_dsi_configure_irqs(dsi.isr_tables.isr_table_vc[vc],
713 ARRAY_SIZE(dsi.isr_tables.isr_table_vc[vc]),
714 DSI_VC_IRQ_ERROR_MASK,
715 DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc));
718 /* dsi.irq_lock has to be locked by the caller */
719 static void _omap_dsi_set_irqs_cio(void)
721 _omap_dsi_configure_irqs(dsi.isr_tables.isr_table_cio,
722 ARRAY_SIZE(dsi.isr_tables.isr_table_cio),
723 DSI_CIO_IRQ_ERROR_MASK,
724 DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS);
727 static void _dsi_initialize_irq(void)
732 spin_lock_irqsave(&dsi.irq_lock, flags);
734 memset(&dsi.isr_tables, 0, sizeof(dsi.isr_tables));
736 _omap_dsi_set_irqs();
737 for (vc = 0; vc < 4; ++vc)
738 _omap_dsi_set_irqs_vc(vc);
739 _omap_dsi_set_irqs_cio();
741 spin_unlock_irqrestore(&dsi.irq_lock, flags);
744 static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
745 struct dsi_isr_data *isr_array, unsigned isr_array_size)
747 struct dsi_isr_data *isr_data;
753 /* check for duplicate entry and find a free slot */
755 for (i = 0; i < isr_array_size; i++) {
756 isr_data = &isr_array[i];
758 if (isr_data->isr == isr && isr_data->arg == arg &&
759 isr_data->mask == mask) {
763 if (isr_data->isr == NULL && free_idx == -1)
770 isr_data = &isr_array[free_idx];
773 isr_data->mask = mask;
778 static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
779 struct dsi_isr_data *isr_array, unsigned isr_array_size)
781 struct dsi_isr_data *isr_data;
784 for (i = 0; i < isr_array_size; i++) {
785 isr_data = &isr_array[i];
786 if (isr_data->isr != isr || isr_data->arg != arg ||
787 isr_data->mask != mask)
790 isr_data->isr = NULL;
791 isr_data->arg = NULL;
800 static int dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask)
805 spin_lock_irqsave(&dsi.irq_lock, flags);
807 r = _dsi_register_isr(isr, arg, mask, dsi.isr_tables.isr_table,
808 ARRAY_SIZE(dsi.isr_tables.isr_table));
811 _omap_dsi_set_irqs();
813 spin_unlock_irqrestore(&dsi.irq_lock, flags);
818 static int dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask)
823 spin_lock_irqsave(&dsi.irq_lock, flags);
825 r = _dsi_unregister_isr(isr, arg, mask, dsi.isr_tables.isr_table,
826 ARRAY_SIZE(dsi.isr_tables.isr_table));
829 _omap_dsi_set_irqs();
831 spin_unlock_irqrestore(&dsi.irq_lock, flags);
836 static int dsi_register_isr_vc(int channel, omap_dsi_isr_t isr, void *arg,
842 spin_lock_irqsave(&dsi.irq_lock, flags);
844 r = _dsi_register_isr(isr, arg, mask,
845 dsi.isr_tables.isr_table_vc[channel],
846 ARRAY_SIZE(dsi.isr_tables.isr_table_vc[channel]));
849 _omap_dsi_set_irqs_vc(channel);
851 spin_unlock_irqrestore(&dsi.irq_lock, flags);
856 static int dsi_unregister_isr_vc(int channel, omap_dsi_isr_t isr, void *arg,
862 spin_lock_irqsave(&dsi.irq_lock, flags);
864 r = _dsi_unregister_isr(isr, arg, mask,
865 dsi.isr_tables.isr_table_vc[channel],
866 ARRAY_SIZE(dsi.isr_tables.isr_table_vc[channel]));
869 _omap_dsi_set_irqs_vc(channel);
871 spin_unlock_irqrestore(&dsi.irq_lock, flags);
876 static int dsi_register_isr_cio(omap_dsi_isr_t isr, void *arg, u32 mask)
881 spin_lock_irqsave(&dsi.irq_lock, flags);
883 r = _dsi_register_isr(isr, arg, mask, dsi.isr_tables.isr_table_cio,
884 ARRAY_SIZE(dsi.isr_tables.isr_table_cio));
887 _omap_dsi_set_irqs_cio();
889 spin_unlock_irqrestore(&dsi.irq_lock, flags);
894 static int dsi_unregister_isr_cio(omap_dsi_isr_t isr, void *arg, u32 mask)
899 spin_lock_irqsave(&dsi.irq_lock, flags);
901 r = _dsi_unregister_isr(isr, arg, mask, dsi.isr_tables.isr_table_cio,
902 ARRAY_SIZE(dsi.isr_tables.isr_table_cio));
905 _omap_dsi_set_irqs_cio();
907 spin_unlock_irqrestore(&dsi.irq_lock, flags);
912 static u32 dsi_get_errors(void)
916 spin_lock_irqsave(&dsi.errors_lock, flags);
919 spin_unlock_irqrestore(&dsi.errors_lock, flags);
923 /* DSI func clock. this could also be dsi_pll_hsdiv_dsi_clk */
924 static inline void enable_clocks(bool enable)
927 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
929 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
932 /* source clock for DSI PLL. this could also be PCLKFREE */
933 static inline void dsi_enable_pll_clock(bool enable)
936 dss_clk_enable(DSS_CLK_SYSCK);
938 dss_clk_disable(DSS_CLK_SYSCK);
940 if (enable && dsi.pll_locked) {
941 if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1)
942 DSSERR("cannot lock PLL when enabling clocks\n");
947 static void _dsi_print_reset_status(void)
954 /* A dummy read using the SCP interface to any DSIPHY register is
955 * required after DSIPHY reset to complete the reset of the DSI complex
957 l = dsi_read_reg(DSI_DSIPHY_CFG5);
959 printk(KERN_DEBUG "DSI resets: ");
961 l = dsi_read_reg(DSI_PLL_STATUS);
962 printk("PLL (%d) ", FLD_GET(l, 0, 0));
964 l = dsi_read_reg(DSI_COMPLEXIO_CFG1);
965 printk("CIO (%d) ", FLD_GET(l, 29, 29));
967 l = dsi_read_reg(DSI_DSIPHY_CFG5);
968 printk("PHY (%x, %d, %d, %d)\n",
975 #define _dsi_print_reset_status()
978 static inline int dsi_if_enable(bool enable)
980 DSSDBG("dsi_if_enable(%d)\n", enable);
982 enable = enable ? 1 : 0;
983 REG_FLD_MOD(DSI_CTRL, enable, 0, 0); /* IF_EN */
985 if (wait_for_bit_change(DSI_CTRL, 0, enable) != enable) {
986 DSSERR("Failed to set dsi_if_enable to %d\n", enable);
993 unsigned long dsi_get_pll_hsdiv_dispc_rate(void)
995 return dsi.current_cinfo.dsi_pll_hsdiv_dispc_clk;
998 static unsigned long dsi_get_pll_hsdiv_dsi_rate(void)
1000 return dsi.current_cinfo.dsi_pll_hsdiv_dsi_clk;
1003 static unsigned long dsi_get_txbyteclkhs(void)
1005 return dsi.current_cinfo.clkin4ddr / 16;
1008 static unsigned long dsi_fclk_rate(void)
1012 if (dss_get_dsi_clk_source() == DSS_CLK_SRC_FCK) {
1013 /* DSI FCLK source is DSS_CLK_FCK */
1014 r = dss_clk_get_rate(DSS_CLK_FCK);
1016 /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */
1017 r = dsi_get_pll_hsdiv_dsi_rate();
1023 static int dsi_set_lp_clk_divisor(struct omap_dss_device *dssdev)
1025 unsigned long dsi_fclk;
1026 unsigned lp_clk_div;
1027 unsigned long lp_clk;
1029 lp_clk_div = dssdev->phy.dsi.div.lp_clk_div;
1031 if (lp_clk_div == 0 || lp_clk_div > dsi.lpdiv_max)
1034 dsi_fclk = dsi_fclk_rate();
1036 lp_clk = dsi_fclk / 2 / lp_clk_div;
1038 DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
1039 dsi.current_cinfo.lp_clk = lp_clk;
1040 dsi.current_cinfo.lp_clk_div = lp_clk_div;
1042 REG_FLD_MOD(DSI_CLK_CTRL, lp_clk_div, 12, 0); /* LP_CLK_DIVISOR */
1044 REG_FLD_MOD(DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0,
1045 21, 21); /* LP_RX_SYNCHRO_ENABLE */
1051 enum dsi_pll_power_state {
1052 DSI_PLL_POWER_OFF = 0x0,
1053 DSI_PLL_POWER_ON_HSCLK = 0x1,
1054 DSI_PLL_POWER_ON_ALL = 0x2,
1055 DSI_PLL_POWER_ON_DIV = 0x3,
1058 static int dsi_pll_power(enum dsi_pll_power_state state)
1062 REG_FLD_MOD(DSI_CLK_CTRL, state, 31, 30); /* PLL_PWR_CMD */
1064 /* PLL_PWR_STATUS */
1065 while (FLD_GET(dsi_read_reg(DSI_CLK_CTRL), 29, 28) != state) {
1067 DSSERR("Failed to set DSI PLL power mode to %d\n",
1077 /* calculate clock rates using dividers in cinfo */
1078 static int dsi_calc_clock_rates(struct omap_dss_device *dssdev,
1079 struct dsi_clock_info *cinfo)
1081 if (cinfo->regn == 0 || cinfo->regn > dsi.regn_max)
1084 if (cinfo->regm == 0 || cinfo->regm > dsi.regm_max)
1087 if (cinfo->regm_dispc > dsi.regm_dispc_max)
1090 if (cinfo->regm_dsi > dsi.regm_dsi_max)
1093 if (cinfo->use_sys_clk) {
1094 cinfo->clkin = dss_clk_get_rate(DSS_CLK_SYSCK);
1095 /* XXX it is unclear if highfreq should be used
1096 * with DSS_SYS_CLK source also */
1097 cinfo->highfreq = 0;
1099 cinfo->clkin = dispc_pclk_rate(dssdev->manager->id);
1101 if (cinfo->clkin < 32000000)
1102 cinfo->highfreq = 0;
1104 cinfo->highfreq = 1;
1107 cinfo->fint = cinfo->clkin / (cinfo->regn * (cinfo->highfreq ? 2 : 1));
1109 if (cinfo->fint > dsi.fint_max || cinfo->fint < dsi.fint_min)
1112 cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint;
1114 if (cinfo->clkin4ddr > 1800 * 1000 * 1000)
1117 if (cinfo->regm_dispc > 0)
1118 cinfo->dsi_pll_hsdiv_dispc_clk =
1119 cinfo->clkin4ddr / cinfo->regm_dispc;
1121 cinfo->dsi_pll_hsdiv_dispc_clk = 0;
1123 if (cinfo->regm_dsi > 0)
1124 cinfo->dsi_pll_hsdiv_dsi_clk =
1125 cinfo->clkin4ddr / cinfo->regm_dsi;
1127 cinfo->dsi_pll_hsdiv_dsi_clk = 0;
1132 int dsi_pll_calc_clock_div_pck(bool is_tft, unsigned long req_pck,
1133 struct dsi_clock_info *dsi_cinfo,
1134 struct dispc_clock_info *dispc_cinfo)
1136 struct dsi_clock_info cur, best;
1137 struct dispc_clock_info best_dispc;
1138 int min_fck_per_pck;
1140 unsigned long dss_sys_clk, max_dss_fck;
1142 dss_sys_clk = dss_clk_get_rate(DSS_CLK_SYSCK);
1144 max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
1146 if (req_pck == dsi.cache_req_pck &&
1147 dsi.cache_cinfo.clkin == dss_sys_clk) {
1148 DSSDBG("DSI clock info found from cache\n");
1149 *dsi_cinfo = dsi.cache_cinfo;
1150 dispc_find_clk_divs(is_tft, req_pck,
1151 dsi_cinfo->dsi_pll_hsdiv_dispc_clk, dispc_cinfo);
1155 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
1157 if (min_fck_per_pck &&
1158 req_pck * min_fck_per_pck > max_dss_fck) {
1159 DSSERR("Requested pixel clock not possible with the current "
1160 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
1161 "the constraint off.\n");
1162 min_fck_per_pck = 0;
1165 DSSDBG("dsi_pll_calc\n");
1168 memset(&best, 0, sizeof(best));
1169 memset(&best_dispc, 0, sizeof(best_dispc));
1171 memset(&cur, 0, sizeof(cur));
1172 cur.clkin = dss_sys_clk;
1173 cur.use_sys_clk = 1;
1176 /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */
1177 /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */
1178 /* To reduce PLL lock time, keep Fint high (around 2 MHz) */
1179 for (cur.regn = 1; cur.regn < dsi.regn_max; ++cur.regn) {
1180 if (cur.highfreq == 0)
1181 cur.fint = cur.clkin / cur.regn;
1183 cur.fint = cur.clkin / (2 * cur.regn);
1185 if (cur.fint > dsi.fint_max || cur.fint < dsi.fint_min)
1188 /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */
1189 for (cur.regm = 1; cur.regm < dsi.regm_max; ++cur.regm) {
1192 a = 2 * cur.regm * (cur.clkin/1000);
1193 b = cur.regn * (cur.highfreq + 1);
1194 cur.clkin4ddr = a / b * 1000;
1196 if (cur.clkin4ddr > 1800 * 1000 * 1000)
1199 /* dsi_pll_hsdiv_dispc_clk(MHz) =
1200 * DSIPHY(MHz) / regm_dispc < 173MHz/186Mhz */
1201 for (cur.regm_dispc = 1; cur.regm_dispc < dsi.regm_dispc_max;
1203 struct dispc_clock_info cur_dispc;
1204 cur.dsi_pll_hsdiv_dispc_clk =
1205 cur.clkin4ddr / cur.regm_dispc;
1207 /* this will narrow down the search a bit,
1208 * but still give pixclocks below what was
1210 if (cur.dsi_pll_hsdiv_dispc_clk < req_pck)
1213 if (cur.dsi_pll_hsdiv_dispc_clk > max_dss_fck)
1216 if (min_fck_per_pck &&
1217 cur.dsi_pll_hsdiv_dispc_clk <
1218 req_pck * min_fck_per_pck)
1223 dispc_find_clk_divs(is_tft, req_pck,
1224 cur.dsi_pll_hsdiv_dispc_clk,
1227 if (abs(cur_dispc.pck - req_pck) <
1228 abs(best_dispc.pck - req_pck)) {
1230 best_dispc = cur_dispc;
1232 if (cur_dispc.pck == req_pck)
1240 if (min_fck_per_pck) {
1241 DSSERR("Could not find suitable clock settings.\n"
1242 "Turning FCK/PCK constraint off and"
1244 min_fck_per_pck = 0;
1248 DSSERR("Could not find suitable clock settings.\n");
1253 /* dsi_pll_hsdiv_dsi_clk (regm_dsi) is not used */
1255 best.dsi_pll_hsdiv_dsi_clk = 0;
1260 *dispc_cinfo = best_dispc;
1262 dsi.cache_req_pck = req_pck;
1263 dsi.cache_clk_freq = 0;
1264 dsi.cache_cinfo = best;
1269 int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo)
1274 u8 regn_start, regn_end, regm_start, regm_end;
1275 u8 regm_dispc_start, regm_dispc_end, regm_dsi_start, regm_dsi_end;
1279 dsi.current_cinfo.fint = cinfo->fint;
1280 dsi.current_cinfo.clkin4ddr = cinfo->clkin4ddr;
1281 dsi.current_cinfo.dsi_pll_hsdiv_dispc_clk =
1282 cinfo->dsi_pll_hsdiv_dispc_clk;
1283 dsi.current_cinfo.dsi_pll_hsdiv_dsi_clk =
1284 cinfo->dsi_pll_hsdiv_dsi_clk;
1286 dsi.current_cinfo.regn = cinfo->regn;
1287 dsi.current_cinfo.regm = cinfo->regm;
1288 dsi.current_cinfo.regm_dispc = cinfo->regm_dispc;
1289 dsi.current_cinfo.regm_dsi = cinfo->regm_dsi;
1291 DSSDBG("DSI Fint %ld\n", cinfo->fint);
1293 DSSDBG("clkin (%s) rate %ld, highfreq %d\n",
1294 cinfo->use_sys_clk ? "dss_sys_clk" : "pclkfree",
1298 /* DSIPHY == CLKIN4DDR */
1299 DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu / %d = %lu\n",
1303 cinfo->highfreq + 1,
1306 DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
1307 cinfo->clkin4ddr / 1000 / 1000 / 2);
1309 DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4);
1311 DSSDBG("regm_dispc = %d, %s (%s) = %lu\n", cinfo->regm_dispc,
1312 dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1313 dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1314 cinfo->dsi_pll_hsdiv_dispc_clk);
1315 DSSDBG("regm_dsi = %d, %s (%s) = %lu\n", cinfo->regm_dsi,
1316 dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1317 dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1318 cinfo->dsi_pll_hsdiv_dsi_clk);
1320 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGN, ®n_start, ®n_end);
1321 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM, ®m_start, ®m_end);
1322 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DISPC, ®m_dispc_start,
1324 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DSI, ®m_dsi_start,
1327 REG_FLD_MOD(DSI_PLL_CONTROL, 0, 0, 0); /* DSI_PLL_AUTOMODE = manual */
1329 l = dsi_read_reg(DSI_PLL_CONFIGURATION1);
1330 l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */
1332 l = FLD_MOD(l, cinfo->regn - 1, regn_start, regn_end);
1334 l = FLD_MOD(l, cinfo->regm, regm_start, regm_end);
1336 l = FLD_MOD(l, cinfo->regm_dispc > 0 ? cinfo->regm_dispc - 1 : 0,
1337 regm_dispc_start, regm_dispc_end);
1338 /* DSIPROTO_CLOCK_DIV */
1339 l = FLD_MOD(l, cinfo->regm_dsi > 0 ? cinfo->regm_dsi - 1 : 0,
1340 regm_dsi_start, regm_dsi_end);
1341 dsi_write_reg(DSI_PLL_CONFIGURATION1, l);
1343 BUG_ON(cinfo->fint < dsi.fint_min || cinfo->fint > dsi.fint_max);
1344 if (cinfo->fint < 1000000)
1346 else if (cinfo->fint < 1250000)
1348 else if (cinfo->fint < 1500000)
1350 else if (cinfo->fint < 1750000)
1355 l = dsi_read_reg(DSI_PLL_CONFIGURATION2);
1356 l = FLD_MOD(l, f, 4, 1); /* DSI_PLL_FREQSEL */
1357 l = FLD_MOD(l, cinfo->use_sys_clk ? 0 : 1,
1358 11, 11); /* DSI_PLL_CLKSEL */
1359 l = FLD_MOD(l, cinfo->highfreq,
1360 12, 12); /* DSI_PLL_HIGHFREQ */
1361 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1362 l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */
1363 l = FLD_MOD(l, 1, 20, 20); /* DSI_HSDIVBYPASS */
1364 dsi_write_reg(DSI_PLL_CONFIGURATION2, l);
1366 REG_FLD_MOD(DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */
1368 if (wait_for_bit_change(DSI_PLL_GO, 0, 0) != 0) {
1369 DSSERR("dsi pll go bit not going down.\n");
1374 if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1) {
1375 DSSERR("cannot lock PLL\n");
1382 l = dsi_read_reg(DSI_PLL_CONFIGURATION2);
1383 l = FLD_MOD(l, 0, 0, 0); /* DSI_PLL_IDLE */
1384 l = FLD_MOD(l, 0, 5, 5); /* DSI_PLL_PLLLPMODE */
1385 l = FLD_MOD(l, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */
1386 l = FLD_MOD(l, 0, 7, 7); /* DSI_PLL_TIGHTPHASELOCK */
1387 l = FLD_MOD(l, 0, 8, 8); /* DSI_PLL_DRIFTGUARDEN */
1388 l = FLD_MOD(l, 0, 10, 9); /* DSI_PLL_LOCKSEL */
1389 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1390 l = FLD_MOD(l, 1, 14, 14); /* DSIPHY_CLKINEN */
1391 l = FLD_MOD(l, 0, 15, 15); /* DSI_BYPASSEN */
1392 l = FLD_MOD(l, 1, 16, 16); /* DSS_CLOCK_EN */
1393 l = FLD_MOD(l, 0, 17, 17); /* DSS_CLOCK_PWDN */
1394 l = FLD_MOD(l, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */
1395 l = FLD_MOD(l, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */
1396 l = FLD_MOD(l, 0, 20, 20); /* DSI_HSDIVBYPASS */
1397 dsi_write_reg(DSI_PLL_CONFIGURATION2, l);
1399 DSSDBG("PLL config done\n");
1404 int dsi_pll_init(struct omap_dss_device *dssdev, bool enable_hsclk,
1408 enum dsi_pll_power_state pwstate;
1410 DSSDBG("PLL init\n");
1412 #ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
1414 * HACK: this is just a quick hack to get the USE_DSI_PLL
1415 * option working. USE_DSI_PLL is itself a big hack, and
1416 * should be removed.
1418 if (dsi.vdds_dsi_reg == NULL) {
1419 struct regulator *vdds_dsi;
1421 vdds_dsi = regulator_get(&dsi.pdev->dev, "vdds_dsi");
1423 if (IS_ERR(vdds_dsi)) {
1424 DSSERR("can't get VDDS_DSI regulator\n");
1425 return PTR_ERR(vdds_dsi);
1428 dsi.vdds_dsi_reg = vdds_dsi;
1433 dsi_enable_pll_clock(1);
1435 r = regulator_enable(dsi.vdds_dsi_reg);
1439 /* XXX PLL does not come out of reset without this... */
1440 dispc_pck_free_enable(1);
1442 if (wait_for_bit_change(DSI_PLL_STATUS, 0, 1) != 1) {
1443 DSSERR("PLL not coming out of reset.\n");
1445 dispc_pck_free_enable(0);
1449 /* XXX ... but if left on, we get problems when planes do not
1450 * fill the whole display. No idea about this */
1451 dispc_pck_free_enable(0);
1453 if (enable_hsclk && enable_hsdiv)
1454 pwstate = DSI_PLL_POWER_ON_ALL;
1455 else if (enable_hsclk)
1456 pwstate = DSI_PLL_POWER_ON_HSCLK;
1457 else if (enable_hsdiv)
1458 pwstate = DSI_PLL_POWER_ON_DIV;
1460 pwstate = DSI_PLL_POWER_OFF;
1462 r = dsi_pll_power(pwstate);
1467 DSSDBG("PLL init done\n");
1471 regulator_disable(dsi.vdds_dsi_reg);
1474 dsi_enable_pll_clock(0);
1478 void dsi_pll_uninit(void)
1481 dsi_enable_pll_clock(0);
1484 dsi_pll_power(DSI_PLL_POWER_OFF);
1485 regulator_disable(dsi.vdds_dsi_reg);
1486 DSSDBG("PLL uninit done\n");
1489 void dsi_dump_clocks(struct seq_file *s)
1492 struct dsi_clock_info *cinfo = &dsi.current_cinfo;
1493 enum dss_clk_source dispc_clk_src, dsi_clk_src;
1495 dispc_clk_src = dss_get_dispc_clk_source();
1496 dsi_clk_src = dss_get_dsi_clk_source();
1500 clksel = REG_GET(DSI_PLL_CONFIGURATION2, 11, 11);
1502 seq_printf(s, "- DSI PLL -\n");
1504 seq_printf(s, "dsi pll source = %s\n",
1506 "dss_sys_clk" : "pclkfree");
1508 seq_printf(s, "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn);
1510 seq_printf(s, "CLKIN4DDR\t%-16luregm %u\n",
1511 cinfo->clkin4ddr, cinfo->regm);
1513 seq_printf(s, "%s (%s)\t%-16luregm_dispc %u\t(%s)\n",
1514 dss_get_generic_clk_source_name(dispc_clk_src),
1515 dss_feat_get_clk_source_name(dispc_clk_src),
1516 cinfo->dsi_pll_hsdiv_dispc_clk,
1518 dispc_clk_src == DSS_CLK_SRC_FCK ?
1521 seq_printf(s, "%s (%s)\t%-16luregm_dsi %u\t(%s)\n",
1522 dss_get_generic_clk_source_name(dsi_clk_src),
1523 dss_feat_get_clk_source_name(dsi_clk_src),
1524 cinfo->dsi_pll_hsdiv_dsi_clk,
1526 dsi_clk_src == DSS_CLK_SRC_FCK ?
1529 seq_printf(s, "- DSI -\n");
1531 seq_printf(s, "dsi fclk source = %s (%s)\n",
1532 dss_get_generic_clk_source_name(dsi_clk_src),
1533 dss_feat_get_clk_source_name(dsi_clk_src));
1535 seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate());
1537 seq_printf(s, "DDR_CLK\t\t%lu\n",
1538 cinfo->clkin4ddr / 4);
1540 seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs());
1542 seq_printf(s, "LP_CLK\t\t%lu\n", cinfo->lp_clk);
1544 seq_printf(s, "VP_CLK\t\t%lu\n"
1546 dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD),
1547 dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD));
1552 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
1553 void dsi_dump_irqs(struct seq_file *s)
1555 unsigned long flags;
1556 struct dsi_irq_stats stats;
1558 spin_lock_irqsave(&dsi.irq_stats_lock, flags);
1560 stats = dsi.irq_stats;
1561 memset(&dsi.irq_stats, 0, sizeof(dsi.irq_stats));
1562 dsi.irq_stats.last_reset = jiffies;
1564 spin_unlock_irqrestore(&dsi.irq_stats_lock, flags);
1566 seq_printf(s, "period %u ms\n",
1567 jiffies_to_msecs(jiffies - stats.last_reset));
1569 seq_printf(s, "irqs %d\n", stats.irq_count);
1571 seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);
1573 seq_printf(s, "-- DSI interrupts --\n");
1589 PIS(LDO_POWER_GOOD);
1594 seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
1595 stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
1596 stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
1597 stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
1598 stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
1600 seq_printf(s, "-- VC interrupts --\n");
1609 PIS(PP_BUSY_CHANGE);
1613 seq_printf(s, "%-20s %10d\n", #x, \
1614 stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
1616 seq_printf(s, "-- CIO interrupts --\n");
1629 PIS(ERRCONTENTIONLP0_1);
1630 PIS(ERRCONTENTIONLP1_1);
1631 PIS(ERRCONTENTIONLP0_2);
1632 PIS(ERRCONTENTIONLP1_2);
1633 PIS(ERRCONTENTIONLP0_3);
1634 PIS(ERRCONTENTIONLP1_3);
1635 PIS(ULPSACTIVENOT_ALL0);
1636 PIS(ULPSACTIVENOT_ALL1);
1641 void dsi_dump_regs(struct seq_file *s)
1643 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(r))
1645 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
1647 DUMPREG(DSI_REVISION);
1648 DUMPREG(DSI_SYSCONFIG);
1649 DUMPREG(DSI_SYSSTATUS);
1650 DUMPREG(DSI_IRQSTATUS);
1651 DUMPREG(DSI_IRQENABLE);
1653 DUMPREG(DSI_COMPLEXIO_CFG1);
1654 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
1655 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
1656 DUMPREG(DSI_CLK_CTRL);
1657 DUMPREG(DSI_TIMING1);
1658 DUMPREG(DSI_TIMING2);
1659 DUMPREG(DSI_VM_TIMING1);
1660 DUMPREG(DSI_VM_TIMING2);
1661 DUMPREG(DSI_VM_TIMING3);
1662 DUMPREG(DSI_CLK_TIMING);
1663 DUMPREG(DSI_TX_FIFO_VC_SIZE);
1664 DUMPREG(DSI_RX_FIFO_VC_SIZE);
1665 DUMPREG(DSI_COMPLEXIO_CFG2);
1666 DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
1667 DUMPREG(DSI_VM_TIMING4);
1668 DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
1669 DUMPREG(DSI_VM_TIMING5);
1670 DUMPREG(DSI_VM_TIMING6);
1671 DUMPREG(DSI_VM_TIMING7);
1672 DUMPREG(DSI_STOPCLK_TIMING);
1674 DUMPREG(DSI_VC_CTRL(0));
1675 DUMPREG(DSI_VC_TE(0));
1676 DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
1677 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
1678 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
1679 DUMPREG(DSI_VC_IRQSTATUS(0));
1680 DUMPREG(DSI_VC_IRQENABLE(0));
1682 DUMPREG(DSI_VC_CTRL(1));
1683 DUMPREG(DSI_VC_TE(1));
1684 DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
1685 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
1686 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
1687 DUMPREG(DSI_VC_IRQSTATUS(1));
1688 DUMPREG(DSI_VC_IRQENABLE(1));
1690 DUMPREG(DSI_VC_CTRL(2));
1691 DUMPREG(DSI_VC_TE(2));
1692 DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
1693 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
1694 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
1695 DUMPREG(DSI_VC_IRQSTATUS(2));
1696 DUMPREG(DSI_VC_IRQENABLE(2));
1698 DUMPREG(DSI_VC_CTRL(3));
1699 DUMPREG(DSI_VC_TE(3));
1700 DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
1701 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
1702 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
1703 DUMPREG(DSI_VC_IRQSTATUS(3));
1704 DUMPREG(DSI_VC_IRQENABLE(3));
1706 DUMPREG(DSI_DSIPHY_CFG0);
1707 DUMPREG(DSI_DSIPHY_CFG1);
1708 DUMPREG(DSI_DSIPHY_CFG2);
1709 DUMPREG(DSI_DSIPHY_CFG5);
1711 DUMPREG(DSI_PLL_CONTROL);
1712 DUMPREG(DSI_PLL_STATUS);
1713 DUMPREG(DSI_PLL_GO);
1714 DUMPREG(DSI_PLL_CONFIGURATION1);
1715 DUMPREG(DSI_PLL_CONFIGURATION2);
1717 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
1721 enum dsi_complexio_power_state {
1722 DSI_COMPLEXIO_POWER_OFF = 0x0,
1723 DSI_COMPLEXIO_POWER_ON = 0x1,
1724 DSI_COMPLEXIO_POWER_ULPS = 0x2,
1727 static int dsi_complexio_power(enum dsi_complexio_power_state state)
1732 REG_FLD_MOD(DSI_COMPLEXIO_CFG1, state, 28, 27);
1735 while (FLD_GET(dsi_read_reg(DSI_COMPLEXIO_CFG1), 26, 25) != state) {
1737 DSSERR("failed to set complexio power state to "
1747 static void dsi_complexio_config(struct omap_dss_device *dssdev)
1751 int clk_lane = dssdev->phy.dsi.clk_lane;
1752 int data1_lane = dssdev->phy.dsi.data1_lane;
1753 int data2_lane = dssdev->phy.dsi.data2_lane;
1754 int clk_pol = dssdev->phy.dsi.clk_pol;
1755 int data1_pol = dssdev->phy.dsi.data1_pol;
1756 int data2_pol = dssdev->phy.dsi.data2_pol;
1758 r = dsi_read_reg(DSI_COMPLEXIO_CFG1);
1759 r = FLD_MOD(r, clk_lane, 2, 0);
1760 r = FLD_MOD(r, clk_pol, 3, 3);
1761 r = FLD_MOD(r, data1_lane, 6, 4);
1762 r = FLD_MOD(r, data1_pol, 7, 7);
1763 r = FLD_MOD(r, data2_lane, 10, 8);
1764 r = FLD_MOD(r, data2_pol, 11, 11);
1765 dsi_write_reg(DSI_COMPLEXIO_CFG1, r);
1767 /* The configuration of the DSI complex I/O (number of data lanes,
1768 position, differential order) should not be changed while
1769 DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. In order for
1770 the hardware to take into account a new configuration of the complex
1771 I/O (done in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to
1772 follow this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1,
1773 then reset the DSS.DSI_CTRL[0] IF_EN to 0, then set
1774 DSS.DSI_CLK_CTRL[20] LP_CLK_ENABLE to 1 and finally set again the
1775 DSS.DSI_CTRL[0] IF_EN bit to 1. If the sequence is not followed, the
1776 DSI complex I/O configuration is unknown. */
1779 REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
1780 REG_FLD_MOD(DSI_CTRL, 0, 0, 0);
1781 REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20);
1782 REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
1786 static inline unsigned ns2ddr(unsigned ns)
1788 /* convert time in ns to ddr ticks, rounding up */
1789 unsigned long ddr_clk = dsi.current_cinfo.clkin4ddr / 4;
1790 return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
1793 static inline unsigned ddr2ns(unsigned ddr)
1795 unsigned long ddr_clk = dsi.current_cinfo.clkin4ddr / 4;
1796 return ddr * 1000 * 1000 / (ddr_clk / 1000);
1799 static void dsi_complexio_timings(void)
1802 u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
1803 u32 tlpx_half, tclk_trail, tclk_zero;
1806 /* calculate timings */
1808 /* 1 * DDR_CLK = 2 * UI */
1810 /* min 40ns + 4*UI max 85ns + 6*UI */
1811 ths_prepare = ns2ddr(70) + 2;
1813 /* min 145ns + 10*UI */
1814 ths_prepare_ths_zero = ns2ddr(175) + 2;
1816 /* min max(8*UI, 60ns+4*UI) */
1817 ths_trail = ns2ddr(60) + 5;
1820 ths_exit = ns2ddr(145);
1823 tlpx_half = ns2ddr(25);
1826 tclk_trail = ns2ddr(60) + 2;
1828 /* min 38ns, max 95ns */
1829 tclk_prepare = ns2ddr(65);
1831 /* min tclk-prepare + tclk-zero = 300ns */
1832 tclk_zero = ns2ddr(260);
1834 DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
1835 ths_prepare, ddr2ns(ths_prepare),
1836 ths_prepare_ths_zero, ddr2ns(ths_prepare_ths_zero));
1837 DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
1838 ths_trail, ddr2ns(ths_trail),
1839 ths_exit, ddr2ns(ths_exit));
1841 DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
1842 "tclk_zero %u (%uns)\n",
1843 tlpx_half, ddr2ns(tlpx_half),
1844 tclk_trail, ddr2ns(tclk_trail),
1845 tclk_zero, ddr2ns(tclk_zero));
1846 DSSDBG("tclk_prepare %u (%uns)\n",
1847 tclk_prepare, ddr2ns(tclk_prepare));
1849 /* program timings */
1851 r = dsi_read_reg(DSI_DSIPHY_CFG0);
1852 r = FLD_MOD(r, ths_prepare, 31, 24);
1853 r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
1854 r = FLD_MOD(r, ths_trail, 15, 8);
1855 r = FLD_MOD(r, ths_exit, 7, 0);
1856 dsi_write_reg(DSI_DSIPHY_CFG0, r);
1858 r = dsi_read_reg(DSI_DSIPHY_CFG1);
1859 r = FLD_MOD(r, tlpx_half, 22, 16);
1860 r = FLD_MOD(r, tclk_trail, 15, 8);
1861 r = FLD_MOD(r, tclk_zero, 7, 0);
1862 dsi_write_reg(DSI_DSIPHY_CFG1, r);
1864 r = dsi_read_reg(DSI_DSIPHY_CFG2);
1865 r = FLD_MOD(r, tclk_prepare, 7, 0);
1866 dsi_write_reg(DSI_DSIPHY_CFG2, r);
1870 static int dsi_complexio_init(struct omap_dss_device *dssdev)
1874 DSSDBG("dsi_complexio_init\n");
1876 /* CIO_CLK_ICG, enable L3 clk to CIO */
1877 REG_FLD_MOD(DSI_CLK_CTRL, 1, 14, 14);
1879 /* A dummy read using the SCP interface to any DSIPHY register is
1880 * required after DSIPHY reset to complete the reset of the DSI complex
1882 dsi_read_reg(DSI_DSIPHY_CFG5);
1884 if (wait_for_bit_change(DSI_DSIPHY_CFG5, 30, 1) != 1) {
1885 DSSERR("ComplexIO PHY not coming out of reset.\n");
1890 dsi_complexio_config(dssdev);
1892 r = dsi_complexio_power(DSI_COMPLEXIO_POWER_ON);
1897 if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
1898 DSSERR("ComplexIO not coming out of reset.\n");
1903 if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 21, 1) != 1) {
1904 DSSERR("ComplexIO LDO power down.\n");
1909 dsi_complexio_timings();
1912 The configuration of the DSI complex I/O (number of data lanes,
1913 position, differential order) should not be changed while
1914 DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. For the
1915 hardware to recognize a new configuration of the complex I/O (done
1916 in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to follow
1917 this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1, next
1918 reset the DSS.DSI_CTRL[0] IF_EN to 0, then set DSS.DSI_CLK_CTRL[20]
1919 LP_CLK_ENABLE to 1, and finally, set again the DSS.DSI_CTRL[0] IF_EN
1920 bit to 1. If the sequence is not followed, the DSi complex I/O
1921 configuration is undetermined.
1925 REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
1929 DSSDBG("CIO init done\n");
1934 static void dsi_complexio_uninit(void)
1936 dsi_complexio_power(DSI_COMPLEXIO_POWER_OFF);
1939 static int _dsi_wait_reset(void)
1943 while (REG_GET(DSI_SYSSTATUS, 0, 0) == 0) {
1945 DSSERR("soft reset failed\n");
1954 static int _dsi_reset(void)
1957 REG_FLD_MOD(DSI_SYSCONFIG, 1, 1, 1);
1958 return _dsi_wait_reset();
1961 static void dsi_config_tx_fifo(enum fifo_size size1, enum fifo_size size2,
1962 enum fifo_size size3, enum fifo_size size4)
1968 dsi.vc[0].fifo_size = size1;
1969 dsi.vc[1].fifo_size = size2;
1970 dsi.vc[2].fifo_size = size3;
1971 dsi.vc[3].fifo_size = size4;
1973 for (i = 0; i < 4; i++) {
1975 int size = dsi.vc[i].fifo_size;
1977 if (add + size > 4) {
1978 DSSERR("Illegal FIFO configuration\n");
1982 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
1984 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
1988 dsi_write_reg(DSI_TX_FIFO_VC_SIZE, r);
1991 static void dsi_config_rx_fifo(enum fifo_size size1, enum fifo_size size2,
1992 enum fifo_size size3, enum fifo_size size4)
1998 dsi.vc[0].fifo_size = size1;
1999 dsi.vc[1].fifo_size = size2;
2000 dsi.vc[2].fifo_size = size3;
2001 dsi.vc[3].fifo_size = size4;
2003 for (i = 0; i < 4; i++) {
2005 int size = dsi.vc[i].fifo_size;
2007 if (add + size > 4) {
2008 DSSERR("Illegal FIFO configuration\n");
2012 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2014 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
2018 dsi_write_reg(DSI_RX_FIFO_VC_SIZE, r);
2021 static int dsi_force_tx_stop_mode_io(void)
2025 r = dsi_read_reg(DSI_TIMING1);
2026 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2027 dsi_write_reg(DSI_TIMING1, r);
2029 if (wait_for_bit_change(DSI_TIMING1, 15, 0) != 0) {
2030 DSSERR("TX_STOP bit not going down\n");
2037 static int dsi_vc_enable(int channel, bool enable)
2039 DSSDBG("dsi_vc_enable channel %d, enable %d\n",
2042 enable = enable ? 1 : 0;
2044 REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 0, 0);
2046 if (wait_for_bit_change(DSI_VC_CTRL(channel), 0, enable) != enable) {
2047 DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
2054 static void dsi_vc_initial_config(int channel)
2058 DSSDBGF("%d", channel);
2060 r = dsi_read_reg(DSI_VC_CTRL(channel));
2062 if (FLD_GET(r, 15, 15)) /* VC_BUSY */
2063 DSSERR("VC(%d) busy when trying to configure it!\n",
2066 r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
2067 r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */
2068 r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
2069 r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
2070 r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
2071 r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
2072 r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
2074 r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
2075 r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
2077 dsi_write_reg(DSI_VC_CTRL(channel), r);
2080 static int dsi_vc_config_l4(int channel)
2082 if (dsi.vc[channel].mode == DSI_VC_MODE_L4)
2085 DSSDBGF("%d", channel);
2087 dsi_vc_enable(channel, 0);
2090 if (wait_for_bit_change(DSI_VC_CTRL(channel), 15, 0) != 0) {
2091 DSSERR("vc(%d) busy when trying to config for L4\n", channel);
2095 REG_FLD_MOD(DSI_VC_CTRL(channel), 0, 1, 1); /* SOURCE, 0 = L4 */
2097 dsi_vc_enable(channel, 1);
2099 dsi.vc[channel].mode = DSI_VC_MODE_L4;
2104 static int dsi_vc_config_vp(int channel)
2106 if (dsi.vc[channel].mode == DSI_VC_MODE_VP)
2109 DSSDBGF("%d", channel);
2111 dsi_vc_enable(channel, 0);
2114 if (wait_for_bit_change(DSI_VC_CTRL(channel), 15, 0) != 0) {
2115 DSSERR("vc(%d) busy when trying to config for VP\n", channel);
2119 REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 1, 1); /* SOURCE, 1 = video port */
2121 dsi_vc_enable(channel, 1);
2123 dsi.vc[channel].mode = DSI_VC_MODE_VP;
2129 void omapdss_dsi_vc_enable_hs(int channel, bool enable)
2131 DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
2133 WARN_ON(!dsi_bus_is_locked());
2135 dsi_vc_enable(channel, 0);
2138 REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 9, 9);
2140 dsi_vc_enable(channel, 1);
2143 dsi_force_tx_stop_mode_io();
2145 EXPORT_SYMBOL(omapdss_dsi_vc_enable_hs);
2147 static void dsi_vc_flush_long_data(int channel)
2149 while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
2151 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
2152 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
2156 (val >> 24) & 0xff);
2160 static void dsi_show_rx_ack_with_err(u16 err)
2162 DSSERR("\tACK with ERROR (%#x):\n", err);
2164 DSSERR("\t\tSoT Error\n");
2166 DSSERR("\t\tSoT Sync Error\n");
2168 DSSERR("\t\tEoT Sync Error\n");
2170 DSSERR("\t\tEscape Mode Entry Command Error\n");
2172 DSSERR("\t\tLP Transmit Sync Error\n");
2174 DSSERR("\t\tHS Receive Timeout Error\n");
2176 DSSERR("\t\tFalse Control Error\n");
2178 DSSERR("\t\t(reserved7)\n");
2180 DSSERR("\t\tECC Error, single-bit (corrected)\n");
2182 DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
2183 if (err & (1 << 10))
2184 DSSERR("\t\tChecksum Error\n");
2185 if (err & (1 << 11))
2186 DSSERR("\t\tData type not recognized\n");
2187 if (err & (1 << 12))
2188 DSSERR("\t\tInvalid VC ID\n");
2189 if (err & (1 << 13))
2190 DSSERR("\t\tInvalid Transmission Length\n");
2191 if (err & (1 << 14))
2192 DSSERR("\t\t(reserved14)\n");
2193 if (err & (1 << 15))
2194 DSSERR("\t\tDSI Protocol Violation\n");
2197 static u16 dsi_vc_flush_receive_data(int channel)
2199 /* RX_FIFO_NOT_EMPTY */
2200 while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
2203 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
2204 DSSERR("\trawval %#08x\n", val);
2205 dt = FLD_GET(val, 5, 0);
2206 if (dt == DSI_DT_RX_ACK_WITH_ERR) {
2207 u16 err = FLD_GET(val, 23, 8);
2208 dsi_show_rx_ack_with_err(err);
2209 } else if (dt == DSI_DT_RX_SHORT_READ_1) {
2210 DSSERR("\tDCS short response, 1 byte: %#x\n",
2211 FLD_GET(val, 23, 8));
2212 } else if (dt == DSI_DT_RX_SHORT_READ_2) {
2213 DSSERR("\tDCS short response, 2 byte: %#x\n",
2214 FLD_GET(val, 23, 8));
2215 } else if (dt == DSI_DT_RX_DCS_LONG_READ) {
2216 DSSERR("\tDCS long response, len %d\n",
2217 FLD_GET(val, 23, 8));
2218 dsi_vc_flush_long_data(channel);
2220 DSSERR("\tunknown datatype 0x%02x\n", dt);
2226 static int dsi_vc_send_bta(int channel)
2228 if (dsi.debug_write || dsi.debug_read)
2229 DSSDBG("dsi_vc_send_bta %d\n", channel);
2231 WARN_ON(!dsi_bus_is_locked());
2233 if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { /* RX_FIFO_NOT_EMPTY */
2234 DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
2235 dsi_vc_flush_receive_data(channel);
2238 REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
2243 int dsi_vc_send_bta_sync(int channel)
2245 DECLARE_COMPLETION_ONSTACK(completion);
2249 r = dsi_register_isr_vc(channel, dsi_completion_handler,
2250 &completion, DSI_VC_IRQ_BTA);
2254 r = dsi_register_isr(dsi_completion_handler, &completion,
2255 DSI_IRQ_ERROR_MASK);
2259 r = dsi_vc_send_bta(channel);
2263 if (wait_for_completion_timeout(&completion,
2264 msecs_to_jiffies(500)) == 0) {
2265 DSSERR("Failed to receive BTA\n");
2270 err = dsi_get_errors();
2272 DSSERR("Error while sending BTA: %x\n", err);
2277 dsi_unregister_isr(dsi_completion_handler, &completion,
2278 DSI_IRQ_ERROR_MASK);
2280 dsi_unregister_isr_vc(channel, dsi_completion_handler,
2281 &completion, DSI_VC_IRQ_BTA);
2285 EXPORT_SYMBOL(dsi_vc_send_bta_sync);
2287 static inline void dsi_vc_write_long_header(int channel, u8 data_type,
2293 WARN_ON(!dsi_bus_is_locked());
2295 data_id = data_type | dsi.vc[channel].vc_id << 6;
2297 val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
2298 FLD_VAL(ecc, 31, 24);
2300 dsi_write_reg(DSI_VC_LONG_PACKET_HEADER(channel), val);
2303 static inline void dsi_vc_write_long_payload(int channel,
2304 u8 b1, u8 b2, u8 b3, u8 b4)
2308 val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0;
2310 /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
2311 b1, b2, b3, b4, val); */
2313 dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
2316 static int dsi_vc_send_long(int channel, u8 data_type, u8 *data, u16 len,
2325 if (dsi.debug_write)
2326 DSSDBG("dsi_vc_send_long, %d bytes\n", len);
2329 if (dsi.vc[channel].fifo_size * 32 * 4 < len + 4) {
2330 DSSERR("unable to send long packet: packet too long.\n");
2334 dsi_vc_config_l4(channel);
2336 dsi_vc_write_long_header(channel, data_type, len, ecc);
2339 for (i = 0; i < len >> 2; i++) {
2340 if (dsi.debug_write)
2341 DSSDBG("\tsending full packet %d\n", i);
2348 dsi_vc_write_long_payload(channel, b1, b2, b3, b4);
2353 b1 = 0; b2 = 0; b3 = 0;
2355 if (dsi.debug_write)
2356 DSSDBG("\tsending remainder bytes %d\n", i);
2373 dsi_vc_write_long_payload(channel, b1, b2, b3, 0);
2379 static int dsi_vc_send_short(int channel, u8 data_type, u16 data, u8 ecc)
2384 WARN_ON(!dsi_bus_is_locked());
2386 if (dsi.debug_write)
2387 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
2389 data_type, data & 0xff, (data >> 8) & 0xff);
2391 dsi_vc_config_l4(channel);
2393 if (FLD_GET(dsi_read_reg(DSI_VC_CTRL(channel)), 16, 16)) {
2394 DSSERR("ERROR FIFO FULL, aborting transfer\n");
2398 data_id = data_type | dsi.vc[channel].vc_id << 6;
2400 r = (data_id << 0) | (data << 8) | (ecc << 24);
2402 dsi_write_reg(DSI_VC_SHORT_PACKET_HEADER(channel), r);
2407 int dsi_vc_send_null(int channel)
2409 u8 nullpkg[] = {0, 0, 0, 0};
2410 return dsi_vc_send_long(channel, DSI_DT_NULL_PACKET, nullpkg, 4, 0);
2412 EXPORT_SYMBOL(dsi_vc_send_null);
2414 int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len)
2421 r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_0,
2423 } else if (len == 2) {
2424 r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_1,
2425 data[0] | (data[1] << 8), 0);
2427 /* 0x39 = DCS Long Write */
2428 r = dsi_vc_send_long(channel, DSI_DT_DCS_LONG_WRITE,
2434 EXPORT_SYMBOL(dsi_vc_dcs_write_nosync);
2436 int dsi_vc_dcs_write(int channel, u8 *data, int len)
2440 r = dsi_vc_dcs_write_nosync(channel, data, len);
2444 r = dsi_vc_send_bta_sync(channel);
2448 if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { /* RX_FIFO_NOT_EMPTY */
2449 DSSERR("rx fifo not empty after write, dumping data:\n");
2450 dsi_vc_flush_receive_data(channel);
2457 DSSERR("dsi_vc_dcs_write(ch %d, cmd 0x%02x, len %d) failed\n",
2458 channel, data[0], len);
2461 EXPORT_SYMBOL(dsi_vc_dcs_write);
2463 int dsi_vc_dcs_write_0(int channel, u8 dcs_cmd)
2465 return dsi_vc_dcs_write(channel, &dcs_cmd, 1);
2467 EXPORT_SYMBOL(dsi_vc_dcs_write_0);
2469 int dsi_vc_dcs_write_1(int channel, u8 dcs_cmd, u8 param)
2474 return dsi_vc_dcs_write(channel, buf, 2);
2476 EXPORT_SYMBOL(dsi_vc_dcs_write_1);
2478 int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen)
2485 DSSDBG("dsi_vc_dcs_read(ch%d, dcs_cmd %x)\n", channel, dcs_cmd);
2487 r = dsi_vc_send_short(channel, DSI_DT_DCS_READ, dcs_cmd, 0);
2491 r = dsi_vc_send_bta_sync(channel);
2495 /* RX_FIFO_NOT_EMPTY */
2496 if (REG_GET(DSI_VC_CTRL(channel), 20, 20) == 0) {
2497 DSSERR("RX fifo empty when trying to read.\n");
2502 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
2504 DSSDBG("\theader: %08x\n", val);
2505 dt = FLD_GET(val, 5, 0);
2506 if (dt == DSI_DT_RX_ACK_WITH_ERR) {
2507 u16 err = FLD_GET(val, 23, 8);
2508 dsi_show_rx_ack_with_err(err);
2512 } else if (dt == DSI_DT_RX_SHORT_READ_1) {
2513 u8 data = FLD_GET(val, 15, 8);
2515 DSSDBG("\tDCS short response, 1 byte: %02x\n", data);
2525 } else if (dt == DSI_DT_RX_SHORT_READ_2) {
2526 u16 data = FLD_GET(val, 23, 8);
2528 DSSDBG("\tDCS short response, 2 byte: %04x\n", data);
2535 buf[0] = data & 0xff;
2536 buf[1] = (data >> 8) & 0xff;
2539 } else if (dt == DSI_DT_RX_DCS_LONG_READ) {
2541 int len = FLD_GET(val, 23, 8);
2543 DSSDBG("\tDCS long response, len %d\n", len);
2550 /* two byte checksum ends the packet, not included in len */
2551 for (w = 0; w < len + 2;) {
2553 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
2555 DSSDBG("\t\t%02x %02x %02x %02x\n",
2559 (val >> 24) & 0xff);
2561 for (b = 0; b < 4; ++b) {
2563 buf[w] = (val >> (b * 8)) & 0xff;
2564 /* we discard the 2 byte checksum */
2571 DSSERR("\tunknown datatype 0x%02x\n", dt);
2578 DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n",
2583 EXPORT_SYMBOL(dsi_vc_dcs_read);
2585 int dsi_vc_dcs_read_1(int channel, u8 dcs_cmd, u8 *data)
2589 r = dsi_vc_dcs_read(channel, dcs_cmd, data, 1);
2599 EXPORT_SYMBOL(dsi_vc_dcs_read_1);
2601 int dsi_vc_dcs_read_2(int channel, u8 dcs_cmd, u8 *data1, u8 *data2)
2606 r = dsi_vc_dcs_read(channel, dcs_cmd, buf, 2);
2619 EXPORT_SYMBOL(dsi_vc_dcs_read_2);
2621 int dsi_vc_set_max_rx_packet_size(int channel, u16 len)
2623 return dsi_vc_send_short(channel, DSI_DT_SET_MAX_RET_PKG_SIZE,
2626 EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size);
2628 static void dsi_set_lp_rx_timeout(unsigned ticks, bool x4, bool x16)
2631 unsigned long total_ticks;
2634 BUG_ON(ticks > 0x1fff);
2636 /* ticks in DSI_FCK */
2637 fck = dsi_fclk_rate();
2639 r = dsi_read_reg(DSI_TIMING2);
2640 r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */
2641 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */
2642 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */
2643 r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */
2644 dsi_write_reg(DSI_TIMING2, r);
2646 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
2648 DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n",
2650 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
2651 (total_ticks * 1000) / (fck / 1000 / 1000));
2654 static void dsi_set_ta_timeout(unsigned ticks, bool x8, bool x16)
2657 unsigned long total_ticks;
2660 BUG_ON(ticks > 0x1fff);
2662 /* ticks in DSI_FCK */
2663 fck = dsi_fclk_rate();
2665 r = dsi_read_reg(DSI_TIMING1);
2666 r = FLD_MOD(r, 1, 31, 31); /* TA_TO */
2667 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */
2668 r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */
2669 r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */
2670 dsi_write_reg(DSI_TIMING1, r);
2672 total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1);
2674 DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n",
2676 ticks, x8 ? " x8" : "", x16 ? " x16" : "",
2677 (total_ticks * 1000) / (fck / 1000 / 1000));
2680 static void dsi_set_stop_state_counter(unsigned ticks, bool x4, bool x16)
2683 unsigned long total_ticks;
2686 BUG_ON(ticks > 0x1fff);
2688 /* ticks in DSI_FCK */
2689 fck = dsi_fclk_rate();
2691 r = dsi_read_reg(DSI_TIMING1);
2692 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2693 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */
2694 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */
2695 r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */
2696 dsi_write_reg(DSI_TIMING1, r);
2698 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
2700 DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n",
2702 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
2703 (total_ticks * 1000) / (fck / 1000 / 1000));
2706 static void dsi_set_hs_tx_timeout(unsigned ticks, bool x4, bool x16)
2709 unsigned long total_ticks;
2712 BUG_ON(ticks > 0x1fff);
2714 /* ticks in TxByteClkHS */
2715 fck = dsi_get_txbyteclkhs();
2717 r = dsi_read_reg(DSI_TIMING2);
2718 r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */
2719 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */
2720 r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */
2721 r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */
2722 dsi_write_reg(DSI_TIMING2, r);
2724 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
2726 DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n",
2728 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
2729 (total_ticks * 1000) / (fck / 1000 / 1000));
2731 static int dsi_proto_config(struct omap_dss_device *dssdev)
2736 dsi_config_tx_fifo(DSI_FIFO_SIZE_32,
2741 dsi_config_rx_fifo(DSI_FIFO_SIZE_32,
2746 /* XXX what values for the timeouts? */
2747 dsi_set_stop_state_counter(0x1000, false, false);
2748 dsi_set_ta_timeout(0x1fff, true, true);
2749 dsi_set_lp_rx_timeout(0x1fff, true, true);
2750 dsi_set_hs_tx_timeout(0x1fff, true, true);
2752 switch (dssdev->ctrl.pixel_size) {
2766 r = dsi_read_reg(DSI_CTRL);
2767 r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */
2768 r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */
2769 r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */
2770 r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/
2771 r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
2772 r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */
2773 r = FLD_MOD(r, 2, 13, 12); /* LINE_BUFFER, 2 lines */
2774 r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */
2775 r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */
2776 r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */
2777 r = FLD_MOD(r, 0, 25, 25); /* DCS_CMD_CODE, 1=start, 0=continue */
2779 dsi_write_reg(DSI_CTRL, r);
2781 dsi_vc_initial_config(0);
2782 dsi_vc_initial_config(1);
2783 dsi_vc_initial_config(2);
2784 dsi_vc_initial_config(3);
2789 static void dsi_proto_timings(struct omap_dss_device *dssdev)
2791 unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail;
2792 unsigned tclk_pre, tclk_post;
2793 unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;
2794 unsigned ths_trail, ths_exit;
2795 unsigned ddr_clk_pre, ddr_clk_post;
2796 unsigned enter_hs_mode_lat, exit_hs_mode_lat;
2800 r = dsi_read_reg(DSI_DSIPHY_CFG0);
2801 ths_prepare = FLD_GET(r, 31, 24);
2802 ths_prepare_ths_zero = FLD_GET(r, 23, 16);
2803 ths_zero = ths_prepare_ths_zero - ths_prepare;
2804 ths_trail = FLD_GET(r, 15, 8);
2805 ths_exit = FLD_GET(r, 7, 0);
2807 r = dsi_read_reg(DSI_DSIPHY_CFG1);
2808 tlpx = FLD_GET(r, 22, 16) * 2;
2809 tclk_trail = FLD_GET(r, 15, 8);
2810 tclk_zero = FLD_GET(r, 7, 0);
2812 r = dsi_read_reg(DSI_DSIPHY_CFG2);
2813 tclk_prepare = FLD_GET(r, 7, 0);
2817 /* min 60ns + 52*UI */
2818 tclk_post = ns2ddr(60) + 26;
2820 /* ths_eot is 2 for 2 datalanes and 4 for 1 datalane */
2821 if (dssdev->phy.dsi.data1_lane != 0 &&
2822 dssdev->phy.dsi.data2_lane != 0)
2827 ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
2829 ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot;
2831 BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
2832 BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
2834 r = dsi_read_reg(DSI_CLK_TIMING);
2835 r = FLD_MOD(r, ddr_clk_pre, 15, 8);
2836 r = FLD_MOD(r, ddr_clk_post, 7, 0);
2837 dsi_write_reg(DSI_CLK_TIMING, r);
2839 DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
2843 enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
2844 DIV_ROUND_UP(ths_prepare, 4) +
2845 DIV_ROUND_UP(ths_zero + 3, 4);
2847 exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
2849 r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
2850 FLD_VAL(exit_hs_mode_lat, 15, 0);
2851 dsi_write_reg(DSI_VM_TIMING7, r);
2853 DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
2854 enter_hs_mode_lat, exit_hs_mode_lat);
2858 #define DSI_DECL_VARS \
2859 int __dsi_cb = 0; u32 __dsi_cv = 0;
2861 #define DSI_FLUSH(ch) \
2862 if (__dsi_cb > 0) { \
2863 /*DSSDBG("sending long packet %#010x\n", __dsi_cv);*/ \
2864 dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(ch), __dsi_cv); \
2865 __dsi_cb = __dsi_cv = 0; \
2868 #define DSI_PUSH(ch, data) \
2870 __dsi_cv |= (data) << (__dsi_cb * 8); \
2871 /*DSSDBG("cv = %#010x, cb = %d\n", __dsi_cv, __dsi_cb);*/ \
2872 if (++__dsi_cb > 3) \
2876 static int dsi_update_screen_l4(struct omap_dss_device *dssdev,
2877 int x, int y, int w, int h)
2879 /* Note: supports only 24bit colors in 32bit container */
2881 int fifo_stalls = 0;
2882 int max_dsi_packet_size;
2883 int max_data_per_packet;
2884 int max_pixels_per_packet;
2886 int bytespp = dssdev->ctrl.pixel_size / 8;
2892 struct omap_overlay *ovl;
2896 DSSDBG("dsi_update_screen_l4 (%d,%d %dx%d)\n",
2899 ovl = dssdev->manager->overlays[0];
2901 if (ovl->info.color_mode != OMAP_DSS_COLOR_RGB24U)
2904 if (dssdev->ctrl.pixel_size != 24)
2907 scr_width = ovl->info.screen_width;
2908 data = ovl->info.vaddr;
2910 start_offset = scr_width * y + x;
2911 horiz_inc = scr_width - w;
2914 /* We need header(4) + DCSCMD(1) + pixels(numpix*bytespp) bytes
2917 /* When using CPU, max long packet size is TX buffer size */
2918 max_dsi_packet_size = dsi.vc[0].fifo_size * 32 * 4;
2920 /* we seem to get better perf if we divide the tx fifo to half,
2921 and while the other half is being sent, we fill the other half
2922 max_dsi_packet_size /= 2; */
2924 max_data_per_packet = max_dsi_packet_size - 4 - 1;
2926 max_pixels_per_packet = max_data_per_packet / bytespp;
2928 DSSDBG("max_pixels_per_packet %d\n", max_pixels_per_packet);
2930 pixels_left = w * h;
2932 DSSDBG("total pixels %d\n", pixels_left);
2934 data += start_offset;
2936 while (pixels_left > 0) {
2937 /* 0x2c = write_memory_start */
2938 /* 0x3c = write_memory_continue */
2939 u8 dcs_cmd = first ? 0x2c : 0x3c;
2945 /* using fifo not empty */
2946 /* TX_FIFO_NOT_EMPTY */
2947 while (FLD_GET(dsi_read_reg(DSI_VC_CTRL(0)), 5, 5)) {
2949 if (fifo_stalls > 0xfffff) {
2950 DSSERR("fifo stalls overflow, pixels left %d\n",
2958 /* using fifo emptiness */
2959 while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 <
2960 max_dsi_packet_size) {
2962 if (fifo_stalls > 0xfffff) {
2963 DSSERR("fifo stalls overflow, pixels left %d\n",
2970 while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 == 0) {
2972 if (fifo_stalls > 0xfffff) {
2973 DSSERR("fifo stalls overflow, pixels left %d\n",
2980 pixels = min(max_pixels_per_packet, pixels_left);
2982 pixels_left -= pixels;
2984 dsi_vc_write_long_header(0, DSI_DT_DCS_LONG_WRITE,
2985 1 + pixels * bytespp, 0);
2987 DSI_PUSH(0, dcs_cmd);
2989 while (pixels-- > 0) {
2990 u32 pix = __raw_readl(data++);
2992 DSI_PUSH(0, (pix >> 16) & 0xff);
2993 DSI_PUSH(0, (pix >> 8) & 0xff);
2994 DSI_PUSH(0, (pix >> 0) & 0xff);
2997 if (current_x == x+w) {
3009 static void dsi_update_screen_dispc(struct omap_dss_device *dssdev,
3010 u16 x, u16 y, u16 w, u16 h)
3016 unsigned packet_payload;
3017 unsigned packet_len;
3020 const unsigned channel = dsi.update_channel;
3021 /* line buffer is 1024 x 24bits */
3022 /* XXX: for some reason using full buffer size causes considerable TX
3023 * slowdown with update sizes that fill the whole buffer */
3024 const unsigned line_buf_size = 1023 * 3;
3026 DSSDBG("dsi_update_screen_dispc(%d,%d %dx%d)\n",
3029 dsi_vc_config_vp(channel);
3031 bytespp = dssdev->ctrl.pixel_size / 8;
3032 bytespl = w * bytespp;
3033 bytespf = bytespl * h;
3035 /* NOTE: packet_payload has to be equal to N * bytespl, where N is
3036 * number of lines in a packet. See errata about VP_CLK_RATIO */
3038 if (bytespf < line_buf_size)
3039 packet_payload = bytespf;
3041 packet_payload = (line_buf_size) / bytespl * bytespl;
3043 packet_len = packet_payload + 1; /* 1 byte for DCS cmd */
3044 total_len = (bytespf / packet_payload) * packet_len;
3046 if (bytespf % packet_payload)
3047 total_len += (bytespf % packet_payload) + 1;
3049 l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
3050 dsi_write_reg(DSI_VC_TE(channel), l);
3052 dsi_vc_write_long_header(channel, DSI_DT_DCS_LONG_WRITE, packet_len, 0);
3055 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
3057 l = FLD_MOD(l, 1, 31, 31); /* TE_START */
3058 dsi_write_reg(DSI_VC_TE(channel), l);
3060 /* We put SIDLEMODE to no-idle for the duration of the transfer,
3061 * because DSS interrupts are not capable of waking up the CPU and the
3062 * framedone interrupt could be delayed for quite a long time. I think
3063 * the same goes for any DSS interrupts, but for some reason I have not
3064 * seen the problem anywhere else than here.
3066 dispc_disable_sidle();
3068 dsi_perf_mark_start();
3070 r = queue_delayed_work(dsi.workqueue, &dsi.framedone_timeout_work,
3071 msecs_to_jiffies(250));
3074 dss_start_update(dssdev);
3076 if (dsi.te_enabled) {
3077 /* disable LP_RX_TO, so that we can receive TE. Time to wait
3078 * for TE is longer than the timer allows */
3079 REG_FLD_MOD(DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
3081 dsi_vc_send_bta(channel);
3083 #ifdef DSI_CATCH_MISSING_TE
3084 mod_timer(&dsi.te_timer, jiffies + msecs_to_jiffies(250));
3089 #ifdef DSI_CATCH_MISSING_TE
3090 static void dsi_te_timeout(unsigned long arg)
3092 DSSERR("TE not received for 250ms!\n");
3096 static void dsi_framedone_bta_callback(void *data, u32 mask);
3098 static void dsi_handle_framedone(int error)
3100 const int channel = dsi.update_channel;
3102 dsi_unregister_isr_vc(channel, dsi_framedone_bta_callback,
3103 NULL, DSI_VC_IRQ_BTA);
3105 cancel_delayed_work(&dsi.framedone_timeout_work);
3107 /* SIDLEMODE back to smart-idle */
3108 dispc_enable_sidle();
3110 if (dsi.te_enabled) {
3111 /* enable LP_RX_TO again after the TE */
3112 REG_FLD_MOD(DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
3115 /* RX_FIFO_NOT_EMPTY */
3116 if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
3117 DSSERR("Received error during frame transfer:\n");
3118 dsi_vc_flush_receive_data(channel);
3123 dsi.framedone_callback(error, dsi.framedone_data);
3126 dsi_perf_show("DISPC");
3129 static void dsi_framedone_timeout_work_callback(struct work_struct *work)
3131 /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after
3132 * 250ms which would conflict with this timeout work. What should be
3133 * done is first cancel the transfer on the HW, and then cancel the
3134 * possibly scheduled framedone work. However, cancelling the transfer
3135 * on the HW is buggy, and would probably require resetting the whole
3138 DSSERR("Framedone not received for 250ms!\n");
3140 dsi_handle_framedone(-ETIMEDOUT);
3143 static void dsi_framedone_bta_callback(void *data, u32 mask)
3145 dsi_handle_framedone(0);
3147 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
3148 dispc_fake_vsync_irq();
3152 static void dsi_framedone_irq_callback(void *data, u32 mask)
3154 const int channel = dsi.update_channel;
3157 /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
3158 * turns itself off. However, DSI still has the pixels in its buffers,
3159 * and is sending the data.
3162 if (dsi.te_enabled) {
3163 /* enable LP_RX_TO again after the TE */
3164 REG_FLD_MOD(DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
3167 /* Send BTA after the frame. We need this for the TE to work, as TE
3168 * trigger is only sent for BTAs without preceding packet. Thus we need
3169 * to BTA after the pixel packets so that next BTA will cause TE
3172 * This is not needed when TE is not in use, but we do it anyway to
3173 * make sure that the transfer has been completed. It would be more
3174 * optimal, but more complex, to wait only just before starting next
3177 * Also, as there's no interrupt telling when the transfer has been
3178 * done and the channel could be reconfigured, the only way is to
3179 * busyloop until TE_SIZE is zero. With BTA we can do this
3183 r = dsi_register_isr_vc(channel, dsi_framedone_bta_callback,
3184 NULL, DSI_VC_IRQ_BTA);
3186 DSSERR("Failed to register BTA ISR\n");
3187 dsi_handle_framedone(-EIO);
3191 r = dsi_vc_send_bta(channel);
3193 DSSERR("BTA after framedone failed\n");
3194 dsi_unregister_isr_vc(channel, dsi_framedone_bta_callback,
3195 NULL, DSI_VC_IRQ_BTA);
3196 dsi_handle_framedone(-EIO);
3200 int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
3201 u16 *x, u16 *y, u16 *w, u16 *h,
3202 bool enlarge_update_area)
3206 dssdev->driver->get_resolution(dssdev, &dw, &dh);
3208 if (*x > dw || *y > dh)
3220 if (*w == 0 || *h == 0)
3223 dsi_perf_mark_setup();
3225 if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
3226 dss_setup_partial_planes(dssdev, x, y, w, h,
3227 enlarge_update_area);
3228 dispc_set_lcd_size(dssdev->manager->id, *w, *h);
3233 EXPORT_SYMBOL(omap_dsi_prepare_update);
3235 int omap_dsi_update(struct omap_dss_device *dssdev,
3237 u16 x, u16 y, u16 w, u16 h,
3238 void (*callback)(int, void *), void *data)
3240 dsi.update_channel = channel;
3242 /* OMAP DSS cannot send updates of odd widths.
3243 * omap_dsi_prepare_update() makes the widths even, but add a BUG_ON
3244 * here to make sure we catch erroneous updates. Otherwise we'll only
3245 * see rather obscure HW error happening, as DSS halts. */
3248 if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
3249 dsi.framedone_callback = callback;
3250 dsi.framedone_data = data;
3252 dsi.update_region.x = x;
3253 dsi.update_region.y = y;
3254 dsi.update_region.w = w;
3255 dsi.update_region.h = h;
3256 dsi.update_region.device = dssdev;
3258 dsi_update_screen_dispc(dssdev, x, y, w, h);
3262 r = dsi_update_screen_l4(dssdev, x, y, w, h);
3266 dsi_perf_show("L4");
3272 EXPORT_SYMBOL(omap_dsi_update);
3276 static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
3280 r = omap_dispc_register_isr(dsi_framedone_irq_callback, NULL,
3281 DISPC_IRQ_FRAMEDONE);
3283 DSSERR("can't get FRAMEDONE irq\n");
3287 dispc_set_lcd_display_type(dssdev->manager->id,
3288 OMAP_DSS_LCD_DISPLAY_TFT);
3290 dispc_set_parallel_interface_mode(dssdev->manager->id,
3291 OMAP_DSS_PARALLELMODE_DSI);
3292 dispc_enable_fifohandcheck(dssdev->manager->id, 1);
3294 dispc_set_tft_data_lines(dssdev->manager->id, dssdev->ctrl.pixel_size);
3297 struct omap_video_timings timings = {
3306 dispc_set_lcd_timings(dssdev->manager->id, &timings);
3312 static void dsi_display_uninit_dispc(struct omap_dss_device *dssdev)
3314 omap_dispc_unregister_isr(dsi_framedone_irq_callback, NULL,
3315 DISPC_IRQ_FRAMEDONE);
3318 static int dsi_configure_dsi_clocks(struct omap_dss_device *dssdev)
3320 struct dsi_clock_info cinfo;
3323 /* we always use DSS_CLK_SYSCK as input clock */
3324 cinfo.use_sys_clk = true;
3325 cinfo.regn = dssdev->phy.dsi.div.regn;
3326 cinfo.regm = dssdev->phy.dsi.div.regm;
3327 cinfo.regm_dispc = dssdev->phy.dsi.div.regm_dispc;
3328 cinfo.regm_dsi = dssdev->phy.dsi.div.regm_dsi;
3329 r = dsi_calc_clock_rates(dssdev, &cinfo);
3331 DSSERR("Failed to calc dsi clocks\n");
3335 r = dsi_pll_set_clock_div(&cinfo);
3337 DSSERR("Failed to set dsi clocks\n");
3344 static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev)
3346 struct dispc_clock_info dispc_cinfo;
3348 unsigned long long fck;
3350 fck = dsi_get_pll_hsdiv_dispc_rate();
3352 dispc_cinfo.lck_div = dssdev->phy.dsi.div.lck_div;
3353 dispc_cinfo.pck_div = dssdev->phy.dsi.div.pck_div;
3355 r = dispc_calc_clock_rates(fck, &dispc_cinfo);
3357 DSSERR("Failed to calc dispc clocks\n");
3361 r = dispc_set_clock_div(dssdev->manager->id, &dispc_cinfo);
3363 DSSERR("Failed to set dispc clocks\n");
3370 static int dsi_display_init_dsi(struct omap_dss_device *dssdev)
3374 _dsi_print_reset_status();
3376 r = dsi_pll_init(dssdev, true, true);
3380 r = dsi_configure_dsi_clocks(dssdev);
3384 dss_select_dispc_clk_source(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC);
3385 dss_select_dsi_clk_source(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI);
3389 r = dsi_configure_dispc_clocks(dssdev);
3393 r = dsi_complexio_init(dssdev);
3397 _dsi_print_reset_status();
3399 dsi_proto_timings(dssdev);
3400 dsi_set_lp_clk_divisor(dssdev);
3403 _dsi_print_reset_status();
3405 r = dsi_proto_config(dssdev);
3409 /* enable interface */
3410 dsi_vc_enable(0, 1);
3411 dsi_vc_enable(1, 1);
3412 dsi_vc_enable(2, 1);
3413 dsi_vc_enable(3, 1);
3415 dsi_force_tx_stop_mode_io();
3419 dsi_complexio_uninit();
3421 dss_select_dispc_clk_source(DSS_CLK_SRC_FCK);
3422 dss_select_dsi_clk_source(DSS_CLK_SRC_FCK);
3429 static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev)
3431 /* disable interface */
3433 dsi_vc_enable(0, 0);
3434 dsi_vc_enable(1, 0);
3435 dsi_vc_enable(2, 0);
3436 dsi_vc_enable(3, 0);
3438 dss_select_dispc_clk_source(DSS_CLK_SRC_FCK);
3439 dss_select_dsi_clk_source(DSS_CLK_SRC_FCK);
3440 dsi_complexio_uninit();
3444 static int dsi_core_init(void)
3447 REG_FLD_MOD(DSI_SYSCONFIG, 1, 0, 0);
3450 REG_FLD_MOD(DSI_SYSCONFIG, 1, 2, 2);
3452 /* SIDLEMODE smart-idle */
3453 REG_FLD_MOD(DSI_SYSCONFIG, 2, 4, 3);
3455 _dsi_initialize_irq();
3460 int omapdss_dsi_display_enable(struct omap_dss_device *dssdev)
3464 DSSDBG("dsi_display_enable\n");
3466 WARN_ON(!dsi_bus_is_locked());
3468 mutex_lock(&dsi.lock);
3470 r = omap_dss_start_device(dssdev);
3472 DSSERR("failed to start device\n");
3477 dsi_enable_pll_clock(1);
3485 r = dsi_display_init_dispc(dssdev);
3489 r = dsi_display_init_dsi(dssdev);
3493 mutex_unlock(&dsi.lock);
3498 dsi_display_uninit_dispc(dssdev);
3501 dsi_enable_pll_clock(0);
3502 omap_dss_stop_device(dssdev);
3504 mutex_unlock(&dsi.lock);
3505 DSSDBG("dsi_display_enable FAILED\n");
3508 EXPORT_SYMBOL(omapdss_dsi_display_enable);
3510 void omapdss_dsi_display_disable(struct omap_dss_device *dssdev)
3512 DSSDBG("dsi_display_disable\n");
3514 WARN_ON(!dsi_bus_is_locked());
3516 mutex_lock(&dsi.lock);
3518 dsi_display_uninit_dispc(dssdev);
3520 dsi_display_uninit_dsi(dssdev);
3523 dsi_enable_pll_clock(0);
3525 omap_dss_stop_device(dssdev);
3527 mutex_unlock(&dsi.lock);
3529 EXPORT_SYMBOL(omapdss_dsi_display_disable);
3531 int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
3533 dsi.te_enabled = enable;
3536 EXPORT_SYMBOL(omapdss_dsi_enable_te);
3538 void dsi_get_overlay_fifo_thresholds(enum omap_plane plane,
3539 u32 fifo_size, enum omap_burst_size *burst_size,
3540 u32 *fifo_low, u32 *fifo_high)
3542 unsigned burst_size_bytes;
3544 *burst_size = OMAP_DSS_BURST_16x32;
3545 burst_size_bytes = 16 * 32 / 8;
3547 *fifo_high = fifo_size - burst_size_bytes;
3548 *fifo_low = fifo_size - burst_size_bytes * 2;
3551 int dsi_init_display(struct omap_dss_device *dssdev)
3553 DSSDBG("DSI init\n");
3555 /* XXX these should be figured out dynamically */
3556 dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE |
3557 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM;
3559 if (dsi.vdds_dsi_reg == NULL) {
3560 struct regulator *vdds_dsi;
3562 vdds_dsi = regulator_get(&dsi.pdev->dev, "vdds_dsi");
3564 if (IS_ERR(vdds_dsi)) {
3565 DSSERR("can't get VDDS_DSI regulator\n");
3566 return PTR_ERR(vdds_dsi);
3569 dsi.vdds_dsi_reg = vdds_dsi;
3575 int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel)
3579 for (i = 0; i < ARRAY_SIZE(dsi.vc); i++) {
3580 if (!dsi.vc[i].dssdev) {
3581 dsi.vc[i].dssdev = dssdev;
3587 DSSERR("cannot get VC for display %s", dssdev->name);
3590 EXPORT_SYMBOL(omap_dsi_request_vc);
3592 int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id)
3594 if (vc_id < 0 || vc_id > 3) {
3595 DSSERR("VC ID out of range\n");
3599 if (channel < 0 || channel > 3) {
3600 DSSERR("Virtual Channel out of range\n");
3604 if (dsi.vc[channel].dssdev != dssdev) {
3605 DSSERR("Virtual Channel not allocated to display %s\n",
3610 dsi.vc[channel].vc_id = vc_id;
3614 EXPORT_SYMBOL(omap_dsi_set_vc_id);
3616 void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel)
3618 if ((channel >= 0 && channel <= 3) &&
3619 dsi.vc[channel].dssdev == dssdev) {
3620 dsi.vc[channel].dssdev = NULL;
3621 dsi.vc[channel].vc_id = 0;
3624 EXPORT_SYMBOL(omap_dsi_release_vc);
3626 void dsi_wait_pll_hsdiv_dispc_active(void)
3628 if (wait_for_bit_change(DSI_PLL_STATUS, 7, 1) != 1)
3629 DSSERR("%s (%s) not active\n",
3630 dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
3631 dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC));
3634 void dsi_wait_pll_hsdiv_dsi_active(void)
3636 if (wait_for_bit_change(DSI_PLL_STATUS, 8, 1) != 1)
3637 DSSERR("%s (%s) not active\n",
3638 dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
3639 dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI));
3642 static void dsi_calc_clock_param_ranges(void)
3644 dsi.regn_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGN);
3645 dsi.regm_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM);
3646 dsi.regm_dispc_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DISPC);
3647 dsi.regm_dsi_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DSI);
3648 dsi.fint_min = dss_feat_get_param_min(FEAT_PARAM_DSIPLL_FINT);
3649 dsi.fint_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_FINT);
3650 dsi.lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV);
3653 static int dsi_init(struct platform_device *pdev)
3657 struct resource *dsi_mem;
3659 spin_lock_init(&dsi.irq_lock);
3660 spin_lock_init(&dsi.errors_lock);
3663 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3664 spin_lock_init(&dsi.irq_stats_lock);
3665 dsi.irq_stats.last_reset = jiffies;
3668 mutex_init(&dsi.lock);
3669 sema_init(&dsi.bus_lock, 1);
3671 dsi.workqueue = create_singlethread_workqueue("dsi");
3672 if (dsi.workqueue == NULL)
3675 INIT_DELAYED_WORK_DEFERRABLE(&dsi.framedone_timeout_work,
3676 dsi_framedone_timeout_work_callback);
3678 #ifdef DSI_CATCH_MISSING_TE
3679 init_timer(&dsi.te_timer);
3680 dsi.te_timer.function = dsi_te_timeout;
3681 dsi.te_timer.data = 0;
3683 dsi_mem = platform_get_resource(dsi.pdev, IORESOURCE_MEM, 0);
3685 DSSERR("can't get IORESOURCE_MEM DSI\n");
3689 dsi.base = ioremap(dsi_mem->start, resource_size(dsi_mem));
3691 DSSERR("can't ioremap DSI\n");
3695 dsi.irq = platform_get_irq(dsi.pdev, 0);
3697 DSSERR("platform_get_irq failed\n");
3702 r = request_irq(dsi.irq, omap_dsi_irq_handler, IRQF_SHARED,
3703 "OMAP DSI1", dsi.pdev);
3705 DSSERR("request_irq failed\n");
3709 /* DSI VCs initialization */
3710 for (i = 0; i < ARRAY_SIZE(dsi.vc); i++) {
3711 dsi.vc[i].mode = DSI_VC_MODE_L4;
3712 dsi.vc[i].dssdev = NULL;
3713 dsi.vc[i].vc_id = 0;
3716 dsi_calc_clock_param_ranges();
3720 rev = dsi_read_reg(DSI_REVISION);
3721 dev_dbg(&pdev->dev, "OMAP DSI rev %d.%d\n",
3722 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3730 destroy_workqueue(dsi.workqueue);
3734 static void dsi_exit(void)
3736 if (dsi.vdds_dsi_reg != NULL) {
3737 regulator_put(dsi.vdds_dsi_reg);
3738 dsi.vdds_dsi_reg = NULL;
3741 free_irq(dsi.irq, dsi.pdev);
3744 destroy_workqueue(dsi.workqueue);
3746 DSSDBG("omap_dsi_exit\n");
3749 /* DSI1 HW IP initialisation */
3750 static int omap_dsi1hw_probe(struct platform_device *pdev)
3756 DSSERR("Failed to initialize DSI\n");
3763 static int omap_dsi1hw_remove(struct platform_device *pdev)
3769 static struct platform_driver omap_dsi1hw_driver = {
3770 .probe = omap_dsi1hw_probe,
3771 .remove = omap_dsi1hw_remove,
3773 .name = "omapdss_dsi1",
3774 .owner = THIS_MODULE,
3778 int dsi_init_platform_driver(void)
3780 return platform_driver_register(&omap_dsi1hw_driver);
3783 void dsi_uninit_platform_driver(void)
3785 return platform_driver_unregister(&omap_dsi1hw_driver);