2 * linux/drivers/video/omap2/dss/dss.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * Some code and ideas taken from drivers/video/omap/ driver
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
23 #define DSS_SUBSYS_NAME "DSS"
25 #include <linux/kernel.h>
27 #include <linux/err.h>
28 #include <linux/delay.h>
29 #include <linux/seq_file.h>
30 #include <linux/clk.h>
31 #include <linux/platform_device.h>
32 #include <linux/pm_runtime.h>
34 #include <video/omapdss.h>
35 #include <plat/clock.h>
37 #include "dss_features.h"
39 #define DSS_SZ_REGS SZ_512
45 #define DSS_REG(idx) ((const struct dss_reg) { idx })
47 #define DSS_REVISION DSS_REG(0x0000)
48 #define DSS_SYSCONFIG DSS_REG(0x0010)
49 #define DSS_SYSSTATUS DSS_REG(0x0014)
50 #define DSS_CONTROL DSS_REG(0x0040)
51 #define DSS_SDI_CONTROL DSS_REG(0x0044)
52 #define DSS_PLL_CONTROL DSS_REG(0x0048)
53 #define DSS_SDI_STATUS DSS_REG(0x005C)
55 #define REG_GET(idx, start, end) \
56 FLD_GET(dss_read_reg(idx), start, end)
58 #define REG_FLD_MOD(idx, val, start, end) \
59 dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end))
62 struct platform_device *pdev;
65 struct clk *dpll4_m4_ck;
68 unsigned long cache_req_pck;
69 unsigned long cache_prate;
70 struct dss_clock_info cache_dss_cinfo;
71 struct dispc_clock_info cache_dispc_cinfo;
73 enum omap_dss_clk_source dsi_clk_source[MAX_NUM_DSI];
74 enum omap_dss_clk_source dispc_clk_source;
75 enum omap_dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS];
78 u32 ctx[DSS_SZ_REGS / sizeof(u32)];
81 static const char * const dss_generic_clk_source_names[] = {
82 [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "DSI_PLL_HSDIV_DISPC",
83 [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "DSI_PLL_HSDIV_DSI",
84 [OMAP_DSS_CLK_SRC_FCK] = "DSS_FCK",
87 static inline void dss_write_reg(const struct dss_reg idx, u32 val)
89 __raw_writel(val, dss.base + idx.idx);
92 static inline u32 dss_read_reg(const struct dss_reg idx)
94 return __raw_readl(dss.base + idx.idx);
98 dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg)
100 dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)])
102 static void dss_save_context(void)
104 DSSDBG("dss_save_context\n");
108 if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
109 OMAP_DISPLAY_TYPE_SDI) {
114 dss.ctx_valid = true;
116 DSSDBG("context saved\n");
119 static void dss_restore_context(void)
121 DSSDBG("dss_restore_context\n");
128 if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
129 OMAP_DISPLAY_TYPE_SDI) {
134 DSSDBG("context restored\n");
140 void dss_sdi_init(u8 datapairs)
144 BUG_ON(datapairs > 3 || datapairs < 1);
146 l = dss_read_reg(DSS_SDI_CONTROL);
147 l = FLD_MOD(l, 0xf, 19, 15); /* SDI_PDIV */
148 l = FLD_MOD(l, datapairs-1, 3, 2); /* SDI_PRSEL */
149 l = FLD_MOD(l, 2, 1, 0); /* SDI_BWSEL */
150 dss_write_reg(DSS_SDI_CONTROL, l);
152 l = dss_read_reg(DSS_PLL_CONTROL);
153 l = FLD_MOD(l, 0x7, 25, 22); /* SDI_PLL_FREQSEL */
154 l = FLD_MOD(l, 0xb, 16, 11); /* SDI_PLL_REGN */
155 l = FLD_MOD(l, 0xb4, 10, 1); /* SDI_PLL_REGM */
156 dss_write_reg(DSS_PLL_CONTROL, l);
159 int dss_sdi_enable(void)
161 unsigned long timeout;
163 dispc_pck_free_enable(1);
166 REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */
167 udelay(1); /* wait 2x PCLK */
170 REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */
172 /* Waiting for PLL lock request to complete */
173 timeout = jiffies + msecs_to_jiffies(500);
174 while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6)) {
175 if (time_after_eq(jiffies, timeout)) {
176 DSSERR("PLL lock request timed out\n");
181 /* Clearing PLL_GO bit */
182 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28);
184 /* Waiting for PLL to lock */
185 timeout = jiffies + msecs_to_jiffies(500);
186 while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5))) {
187 if (time_after_eq(jiffies, timeout)) {
188 DSSERR("PLL lock timed out\n");
193 dispc_lcd_enable_signal(1);
195 /* Waiting for SDI reset to complete */
196 timeout = jiffies + msecs_to_jiffies(500);
197 while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 2))) {
198 if (time_after_eq(jiffies, timeout)) {
199 DSSERR("SDI reset timed out\n");
207 dispc_lcd_enable_signal(0);
210 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
212 dispc_pck_free_enable(0);
217 void dss_sdi_disable(void)
219 dispc_lcd_enable_signal(0);
221 dispc_pck_free_enable(0);
224 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
227 const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src)
229 return dss_generic_clk_source_names[clk_src];
233 void dss_dump_clocks(struct seq_file *s)
235 unsigned long dpll4_ck_rate;
236 unsigned long dpll4_m4_ck_rate;
237 const char *fclk_name, *fclk_real_name;
238 unsigned long fclk_rate;
240 if (dss_runtime_get())
243 seq_printf(s, "- DSS -\n");
245 fclk_name = dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_FCK);
246 fclk_real_name = dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_FCK);
247 fclk_rate = clk_get_rate(dss.dss_clk);
249 if (dss.dpll4_m4_ck) {
250 dpll4_ck_rate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
251 dpll4_m4_ck_rate = clk_get_rate(dss.dpll4_m4_ck);
253 seq_printf(s, "dpll4_ck %lu\n", dpll4_ck_rate);
255 if (cpu_is_omap3630() || cpu_is_omap44xx())
256 seq_printf(s, "%s (%s) = %lu / %lu = %lu\n",
257 fclk_name, fclk_real_name,
259 dpll4_ck_rate / dpll4_m4_ck_rate,
262 seq_printf(s, "%s (%s) = %lu / %lu * 2 = %lu\n",
263 fclk_name, fclk_real_name,
265 dpll4_ck_rate / dpll4_m4_ck_rate,
268 seq_printf(s, "%s (%s) = %lu\n",
269 fclk_name, fclk_real_name,
276 void dss_dump_regs(struct seq_file *s)
278 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r))
280 if (dss_runtime_get())
283 DUMPREG(DSS_REVISION);
284 DUMPREG(DSS_SYSCONFIG);
285 DUMPREG(DSS_SYSSTATUS);
286 DUMPREG(DSS_CONTROL);
288 if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
289 OMAP_DISPLAY_TYPE_SDI) {
290 DUMPREG(DSS_SDI_CONTROL);
291 DUMPREG(DSS_PLL_CONTROL);
292 DUMPREG(DSS_SDI_STATUS);
299 void dss_select_dispc_clk_source(enum omap_dss_clk_source clk_src)
301 struct platform_device *dsidev;
306 case OMAP_DSS_CLK_SRC_FCK:
309 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
311 dsidev = dsi_get_dsidev_from_id(0);
312 dsi_wait_pll_hsdiv_dispc_active(dsidev);
314 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
316 dsidev = dsi_get_dsidev_from_id(1);
317 dsi_wait_pll_hsdiv_dispc_active(dsidev);
323 dss_feat_get_reg_field(FEAT_REG_DISPC_CLK_SWITCH, &start, &end);
325 REG_FLD_MOD(DSS_CONTROL, b, start, end); /* DISPC_CLK_SWITCH */
327 dss.dispc_clk_source = clk_src;
330 void dss_select_dsi_clk_source(int dsi_module,
331 enum omap_dss_clk_source clk_src)
333 struct platform_device *dsidev;
337 case OMAP_DSS_CLK_SRC_FCK:
340 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI:
341 BUG_ON(dsi_module != 0);
343 dsidev = dsi_get_dsidev_from_id(0);
344 dsi_wait_pll_hsdiv_dsi_active(dsidev);
346 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI:
347 BUG_ON(dsi_module != 1);
349 dsidev = dsi_get_dsidev_from_id(1);
350 dsi_wait_pll_hsdiv_dsi_active(dsidev);
356 REG_FLD_MOD(DSS_CONTROL, b, 1, 1); /* DSI_CLK_SWITCH */
358 dss.dsi_clk_source[dsi_module] = clk_src;
361 void dss_select_lcd_clk_source(enum omap_channel channel,
362 enum omap_dss_clk_source clk_src)
364 struct platform_device *dsidev;
367 if (!dss_has_feature(FEAT_LCD_CLK_SRC))
371 case OMAP_DSS_CLK_SRC_FCK:
374 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
375 BUG_ON(channel != OMAP_DSS_CHANNEL_LCD);
377 dsidev = dsi_get_dsidev_from_id(0);
378 dsi_wait_pll_hsdiv_dispc_active(dsidev);
380 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
381 BUG_ON(channel != OMAP_DSS_CHANNEL_LCD2);
383 dsidev = dsi_get_dsidev_from_id(1);
384 dsi_wait_pll_hsdiv_dispc_active(dsidev);
390 pos = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 12;
391 REG_FLD_MOD(DSS_CONTROL, b, pos, pos); /* LCDx_CLK_SWITCH */
393 ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 1;
394 dss.lcd_clk_source[ix] = clk_src;
397 enum omap_dss_clk_source dss_get_dispc_clk_source(void)
399 return dss.dispc_clk_source;
402 enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module)
404 return dss.dsi_clk_source[dsi_module];
407 enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel)
409 if (dss_has_feature(FEAT_LCD_CLK_SRC)) {
410 int ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 1;
411 return dss.lcd_clk_source[ix];
413 /* LCD_CLK source is the same as DISPC_FCLK source for
415 return dss.dispc_clk_source;
419 /* calculate clock rates using dividers in cinfo */
420 int dss_calc_clock_rates(struct dss_clock_info *cinfo)
422 if (dss.dpll4_m4_ck) {
424 u16 fck_div_max = 16;
426 if (cpu_is_omap3630() || cpu_is_omap44xx())
429 if (cinfo->fck_div > fck_div_max || cinfo->fck_div == 0)
432 prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
434 cinfo->fck = prate / cinfo->fck_div;
436 if (cinfo->fck_div != 0)
438 cinfo->fck = clk_get_rate(dss.dss_clk);
444 int dss_set_clock_div(struct dss_clock_info *cinfo)
446 if (dss.dpll4_m4_ck) {
450 prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
451 DSSDBG("dpll4_m4 = %ld\n", prate);
453 r = clk_set_rate(dss.dpll4_m4_ck, prate / cinfo->fck_div);
457 if (cinfo->fck_div != 0)
461 DSSDBG("fck = %ld (%d)\n", cinfo->fck, cinfo->fck_div);
466 int dss_get_clock_div(struct dss_clock_info *cinfo)
468 cinfo->fck = clk_get_rate(dss.dss_clk);
470 if (dss.dpll4_m4_ck) {
473 prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
475 if (cpu_is_omap3630() || cpu_is_omap44xx())
476 cinfo->fck_div = prate / (cinfo->fck);
478 cinfo->fck_div = prate / (cinfo->fck / 2);
486 unsigned long dss_get_dpll4_rate(void)
489 return clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
494 int dss_calc_clock_div(bool is_tft, unsigned long req_pck,
495 struct dss_clock_info *dss_cinfo,
496 struct dispc_clock_info *dispc_cinfo)
499 struct dss_clock_info best_dss;
500 struct dispc_clock_info best_dispc;
502 unsigned long fck, max_dss_fck;
504 u16 fck_div, fck_div_max = 16;
509 prate = dss_get_dpll4_rate();
511 max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
513 fck = clk_get_rate(dss.dss_clk);
514 if (req_pck == dss.cache_req_pck &&
515 ((cpu_is_omap34xx() && prate == dss.cache_prate) ||
516 dss.cache_dss_cinfo.fck == fck)) {
517 DSSDBG("dispc clock info found from cache.\n");
518 *dss_cinfo = dss.cache_dss_cinfo;
519 *dispc_cinfo = dss.cache_dispc_cinfo;
523 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
525 if (min_fck_per_pck &&
526 req_pck * min_fck_per_pck > max_dss_fck) {
527 DSSERR("Requested pixel clock not possible with the current "
528 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
529 "the constraint off.\n");
534 memset(&best_dss, 0, sizeof(best_dss));
535 memset(&best_dispc, 0, sizeof(best_dispc));
537 if (dss.dpll4_m4_ck == NULL) {
538 struct dispc_clock_info cur_dispc;
539 /* XXX can we change the clock on omap2? */
540 fck = clk_get_rate(dss.dss_clk);
543 dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc);
547 best_dss.fck_div = fck_div;
549 best_dispc = cur_dispc;
553 if (cpu_is_omap3630() || cpu_is_omap44xx())
556 for (fck_div = fck_div_max; fck_div > 0; --fck_div) {
557 struct dispc_clock_info cur_dispc;
559 if (fck_div_max == 32)
560 fck = prate / fck_div;
562 fck = prate / fck_div * 2;
564 if (fck > max_dss_fck)
567 if (min_fck_per_pck &&
568 fck < req_pck * min_fck_per_pck)
573 dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc);
575 if (abs(cur_dispc.pck - req_pck) <
576 abs(best_dispc.pck - req_pck)) {
579 best_dss.fck_div = fck_div;
581 best_dispc = cur_dispc;
583 if (cur_dispc.pck == req_pck)
591 if (min_fck_per_pck) {
592 DSSERR("Could not find suitable clock settings.\n"
593 "Turning FCK/PCK constraint off and"
599 DSSERR("Could not find suitable clock settings.\n");
605 *dss_cinfo = best_dss;
607 *dispc_cinfo = best_dispc;
609 dss.cache_req_pck = req_pck;
610 dss.cache_prate = prate;
611 dss.cache_dss_cinfo = best_dss;
612 dss.cache_dispc_cinfo = best_dispc;
617 void dss_set_venc_output(enum omap_dss_venc_type type)
621 if (type == OMAP_DSS_VENC_TYPE_COMPOSITE)
623 else if (type == OMAP_DSS_VENC_TYPE_SVIDEO)
628 /* venc out selection. 0 = comp, 1 = svideo */
629 REG_FLD_MOD(DSS_CONTROL, l, 6, 6);
632 void dss_set_dac_pwrdn_bgz(bool enable)
634 REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */
637 void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select hdmi)
639 REG_FLD_MOD(DSS_CONTROL, hdmi, 15, 15); /* VENC_HDMI_SWITCH */
642 enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void)
644 enum omap_display_type displays;
646 displays = dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_DIGIT);
647 if ((displays & OMAP_DISPLAY_TYPE_HDMI) == 0)
648 return DSS_VENC_TV_CLK;
650 return REG_GET(DSS_CONTROL, 15, 15);
653 static int dss_get_clocks(void)
658 clk = clk_get(&dss.pdev->dev, "fck");
660 DSSERR("can't get clock fck\n");
667 if (cpu_is_omap34xx()) {
668 clk = clk_get(NULL, "dpll4_m4_ck");
670 DSSERR("Failed to get dpll4_m4_ck\n");
674 } else if (cpu_is_omap44xx()) {
675 clk = clk_get(NULL, "dpll_per_m5x2_ck");
677 DSSERR("Failed to get dpll_per_m5x2_ck\n");
681 } else { /* omap24xx */
685 dss.dpll4_m4_ck = clk;
691 clk_put(dss.dss_clk);
693 clk_put(dss.dpll4_m4_ck);
698 static void dss_put_clocks(void)
701 clk_put(dss.dpll4_m4_ck);
702 clk_put(dss.dss_clk);
705 int dss_runtime_get(void)
709 DSSDBG("dss_runtime_get\n");
711 r = pm_runtime_get_sync(&dss.pdev->dev);
713 return r < 0 ? r : 0;
716 void dss_runtime_put(void)
720 DSSDBG("dss_runtime_put\n");
722 r = pm_runtime_put(&dss.pdev->dev);
727 #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
728 void dss_debug_dump_clocks(struct seq_file *s)
731 dispc_dump_clocks(s);
732 #ifdef CONFIG_OMAP2_DSS_DSI
738 /* DSS HW IP initialisation */
739 static int omap_dsshw_probe(struct platform_device *pdev)
741 struct resource *dss_mem;
747 dss_mem = platform_get_resource(dss.pdev, IORESOURCE_MEM, 0);
749 DSSERR("can't get IORESOURCE_MEM DSS\n");
753 dss.base = ioremap(dss_mem->start, resource_size(dss_mem));
755 DSSERR("can't ioremap DSS\n");
760 r = dss_get_clocks();
764 pm_runtime_enable(&pdev->dev);
766 r = dss_runtime_get();
768 goto err_runtime_get;
771 REG_FLD_MOD(DSS_CONTROL, 0, 0, 0);
773 #ifdef CONFIG_OMAP2_DSS_VENC
774 REG_FLD_MOD(DSS_CONTROL, 1, 4, 4); /* venc dac demen */
775 REG_FLD_MOD(DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */
776 REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */
778 dss.dsi_clk_source[0] = OMAP_DSS_CLK_SRC_FCK;
779 dss.dsi_clk_source[1] = OMAP_DSS_CLK_SRC_FCK;
780 dss.dispc_clk_source = OMAP_DSS_CLK_SRC_FCK;
781 dss.lcd_clk_source[0] = OMAP_DSS_CLK_SRC_FCK;
782 dss.lcd_clk_source[1] = OMAP_DSS_CLK_SRC_FCK;
786 DSSERR("Failed to initialize DPI\n");
792 DSSERR("Failed to initialize SDI\n");
796 rev = dss_read_reg(DSS_REVISION);
797 printk(KERN_INFO "OMAP DSS rev %d.%d\n",
798 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
808 pm_runtime_disable(&pdev->dev);
816 static int omap_dsshw_remove(struct platform_device *pdev)
823 pm_runtime_disable(&pdev->dev);
830 static int dss_runtime_suspend(struct device *dev)
836 static int dss_runtime_resume(struct device *dev)
838 dss_restore_context();
842 static const struct dev_pm_ops dss_pm_ops = {
843 .runtime_suspend = dss_runtime_suspend,
844 .runtime_resume = dss_runtime_resume,
847 static struct platform_driver omap_dsshw_driver = {
848 .probe = omap_dsshw_probe,
849 .remove = omap_dsshw_remove,
851 .name = "omapdss_dss",
852 .owner = THIS_MODULE,
857 int dss_init_platform_driver(void)
859 return platform_driver_register(&omap_dsshw_driver);
862 void dss_uninit_platform_driver(void)
864 return platform_driver_unregister(&omap_dsshw_driver);