2 * linux/drivers/video/omap2/dss/dss.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * Some code and ideas taken from drivers/video/omap/ driver
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
23 #define DSS_SUBSYS_NAME "DSS"
25 #include <linux/kernel.h>
27 #include <linux/export.h>
28 #include <linux/err.h>
29 #include <linux/delay.h>
30 #include <linux/seq_file.h>
31 #include <linux/clk.h>
32 #include <linux/platform_device.h>
33 #include <linux/pm_runtime.h>
35 #include <video/omapdss.h>
38 #include <plat/clock.h>
41 #include "dss_features.h"
43 #define DSS_SZ_REGS SZ_512
49 #define DSS_REG(idx) ((const struct dss_reg) { idx })
51 #define DSS_REVISION DSS_REG(0x0000)
52 #define DSS_SYSCONFIG DSS_REG(0x0010)
53 #define DSS_SYSSTATUS DSS_REG(0x0014)
54 #define DSS_CONTROL DSS_REG(0x0040)
55 #define DSS_SDI_CONTROL DSS_REG(0x0044)
56 #define DSS_PLL_CONTROL DSS_REG(0x0048)
57 #define DSS_SDI_STATUS DSS_REG(0x005C)
59 #define REG_GET(idx, start, end) \
60 FLD_GET(dss_read_reg(idx), start, end)
62 #define REG_FLD_MOD(idx, val, start, end) \
63 dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end))
65 static int dss_runtime_get(void);
66 static void dss_runtime_put(void);
69 struct platform_device *pdev;
72 struct clk *dpll4_m4_ck;
75 unsigned long cache_req_pck;
76 unsigned long cache_prate;
77 struct dss_clock_info cache_dss_cinfo;
78 struct dispc_clock_info cache_dispc_cinfo;
80 enum omap_dss_clk_source dsi_clk_source[MAX_NUM_DSI];
81 enum omap_dss_clk_source dispc_clk_source;
82 enum omap_dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS];
85 u32 ctx[DSS_SZ_REGS / sizeof(u32)];
88 static const char * const dss_generic_clk_source_names[] = {
89 [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "DSI_PLL_HSDIV_DISPC",
90 [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "DSI_PLL_HSDIV_DSI",
91 [OMAP_DSS_CLK_SRC_FCK] = "DSS_FCK",
94 static inline void dss_write_reg(const struct dss_reg idx, u32 val)
96 __raw_writel(val, dss.base + idx.idx);
99 static inline u32 dss_read_reg(const struct dss_reg idx)
101 return __raw_readl(dss.base + idx.idx);
105 dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg)
107 dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)])
109 static void dss_save_context(void)
111 DSSDBG("dss_save_context\n");
115 if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
116 OMAP_DISPLAY_TYPE_SDI) {
121 dss.ctx_valid = true;
123 DSSDBG("context saved\n");
126 static void dss_restore_context(void)
128 DSSDBG("dss_restore_context\n");
135 if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
136 OMAP_DISPLAY_TYPE_SDI) {
141 DSSDBG("context restored\n");
147 void dss_sdi_init(u8 datapairs)
151 BUG_ON(datapairs > 3 || datapairs < 1);
153 l = dss_read_reg(DSS_SDI_CONTROL);
154 l = FLD_MOD(l, 0xf, 19, 15); /* SDI_PDIV */
155 l = FLD_MOD(l, datapairs-1, 3, 2); /* SDI_PRSEL */
156 l = FLD_MOD(l, 2, 1, 0); /* SDI_BWSEL */
157 dss_write_reg(DSS_SDI_CONTROL, l);
159 l = dss_read_reg(DSS_PLL_CONTROL);
160 l = FLD_MOD(l, 0x7, 25, 22); /* SDI_PLL_FREQSEL */
161 l = FLD_MOD(l, 0xb, 16, 11); /* SDI_PLL_REGN */
162 l = FLD_MOD(l, 0xb4, 10, 1); /* SDI_PLL_REGM */
163 dss_write_reg(DSS_PLL_CONTROL, l);
166 int dss_sdi_enable(void)
168 unsigned long timeout;
170 dispc_pck_free_enable(1);
173 REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */
174 udelay(1); /* wait 2x PCLK */
177 REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */
179 /* Waiting for PLL lock request to complete */
180 timeout = jiffies + msecs_to_jiffies(500);
181 while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6)) {
182 if (time_after_eq(jiffies, timeout)) {
183 DSSERR("PLL lock request timed out\n");
188 /* Clearing PLL_GO bit */
189 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28);
191 /* Waiting for PLL to lock */
192 timeout = jiffies + msecs_to_jiffies(500);
193 while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5))) {
194 if (time_after_eq(jiffies, timeout)) {
195 DSSERR("PLL lock timed out\n");
200 dispc_lcd_enable_signal(1);
202 /* Waiting for SDI reset to complete */
203 timeout = jiffies + msecs_to_jiffies(500);
204 while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 2))) {
205 if (time_after_eq(jiffies, timeout)) {
206 DSSERR("SDI reset timed out\n");
214 dispc_lcd_enable_signal(0);
217 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
219 dispc_pck_free_enable(0);
224 void dss_sdi_disable(void)
226 dispc_lcd_enable_signal(0);
228 dispc_pck_free_enable(0);
231 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
234 const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src)
236 return dss_generic_clk_source_names[clk_src];
240 void dss_dump_clocks(struct seq_file *s)
242 unsigned long dpll4_ck_rate;
243 unsigned long dpll4_m4_ck_rate;
244 const char *fclk_name, *fclk_real_name;
245 unsigned long fclk_rate;
247 if (dss_runtime_get())
250 seq_printf(s, "- DSS -\n");
252 fclk_name = dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_FCK);
253 fclk_real_name = dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_FCK);
254 fclk_rate = clk_get_rate(dss.dss_clk);
256 if (dss.dpll4_m4_ck) {
257 dpll4_ck_rate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
258 dpll4_m4_ck_rate = clk_get_rate(dss.dpll4_m4_ck);
260 seq_printf(s, "dpll4_ck %lu\n", dpll4_ck_rate);
262 if (cpu_is_omap3630() || cpu_is_omap44xx())
263 seq_printf(s, "%s (%s) = %lu / %lu = %lu\n",
264 fclk_name, fclk_real_name,
266 dpll4_ck_rate / dpll4_m4_ck_rate,
269 seq_printf(s, "%s (%s) = %lu / %lu * 2 = %lu\n",
270 fclk_name, fclk_real_name,
272 dpll4_ck_rate / dpll4_m4_ck_rate,
275 seq_printf(s, "%s (%s) = %lu\n",
276 fclk_name, fclk_real_name,
283 static void dss_dump_regs(struct seq_file *s)
285 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r))
287 if (dss_runtime_get())
290 DUMPREG(DSS_REVISION);
291 DUMPREG(DSS_SYSCONFIG);
292 DUMPREG(DSS_SYSSTATUS);
293 DUMPREG(DSS_CONTROL);
295 if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
296 OMAP_DISPLAY_TYPE_SDI) {
297 DUMPREG(DSS_SDI_CONTROL);
298 DUMPREG(DSS_PLL_CONTROL);
299 DUMPREG(DSS_SDI_STATUS);
306 void dss_select_dispc_clk_source(enum omap_dss_clk_source clk_src)
308 struct platform_device *dsidev;
313 case OMAP_DSS_CLK_SRC_FCK:
316 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
318 dsidev = dsi_get_dsidev_from_id(0);
319 dsi_wait_pll_hsdiv_dispc_active(dsidev);
321 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
323 dsidev = dsi_get_dsidev_from_id(1);
324 dsi_wait_pll_hsdiv_dispc_active(dsidev);
331 dss_feat_get_reg_field(FEAT_REG_DISPC_CLK_SWITCH, &start, &end);
333 REG_FLD_MOD(DSS_CONTROL, b, start, end); /* DISPC_CLK_SWITCH */
335 dss.dispc_clk_source = clk_src;
338 void dss_select_dsi_clk_source(int dsi_module,
339 enum omap_dss_clk_source clk_src)
341 struct platform_device *dsidev;
345 case OMAP_DSS_CLK_SRC_FCK:
348 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI:
349 BUG_ON(dsi_module != 0);
351 dsidev = dsi_get_dsidev_from_id(0);
352 dsi_wait_pll_hsdiv_dsi_active(dsidev);
354 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI:
355 BUG_ON(dsi_module != 1);
357 dsidev = dsi_get_dsidev_from_id(1);
358 dsi_wait_pll_hsdiv_dsi_active(dsidev);
365 pos = dsi_module == 0 ? 1 : 10;
366 REG_FLD_MOD(DSS_CONTROL, b, pos, pos); /* DSIx_CLK_SWITCH */
368 dss.dsi_clk_source[dsi_module] = clk_src;
371 void dss_select_lcd_clk_source(enum omap_channel channel,
372 enum omap_dss_clk_source clk_src)
374 struct platform_device *dsidev;
377 if (!dss_has_feature(FEAT_LCD_CLK_SRC))
381 case OMAP_DSS_CLK_SRC_FCK:
384 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
385 BUG_ON(channel != OMAP_DSS_CHANNEL_LCD);
387 dsidev = dsi_get_dsidev_from_id(0);
388 dsi_wait_pll_hsdiv_dispc_active(dsidev);
390 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
391 BUG_ON(channel != OMAP_DSS_CHANNEL_LCD2);
393 dsidev = dsi_get_dsidev_from_id(1);
394 dsi_wait_pll_hsdiv_dispc_active(dsidev);
401 pos = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 12;
402 REG_FLD_MOD(DSS_CONTROL, b, pos, pos); /* LCDx_CLK_SWITCH */
404 ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 1;
405 dss.lcd_clk_source[ix] = clk_src;
408 enum omap_dss_clk_source dss_get_dispc_clk_source(void)
410 return dss.dispc_clk_source;
413 enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module)
415 return dss.dsi_clk_source[dsi_module];
418 enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel)
420 if (dss_has_feature(FEAT_LCD_CLK_SRC)) {
421 int ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 1;
422 return dss.lcd_clk_source[ix];
424 /* LCD_CLK source is the same as DISPC_FCLK source for
426 return dss.dispc_clk_source;
430 /* calculate clock rates using dividers in cinfo */
431 int dss_calc_clock_rates(struct dss_clock_info *cinfo)
433 if (dss.dpll4_m4_ck) {
435 u16 fck_div_max = 16;
437 if (cpu_is_omap3630() || cpu_is_omap44xx())
440 if (cinfo->fck_div > fck_div_max || cinfo->fck_div == 0)
443 prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
445 cinfo->fck = prate / cinfo->fck_div;
447 if (cinfo->fck_div != 0)
449 cinfo->fck = clk_get_rate(dss.dss_clk);
455 int dss_set_clock_div(struct dss_clock_info *cinfo)
457 if (dss.dpll4_m4_ck) {
461 prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
462 DSSDBG("dpll4_m4 = %ld\n", prate);
464 r = clk_set_rate(dss.dpll4_m4_ck, prate / cinfo->fck_div);
468 if (cinfo->fck_div != 0)
472 DSSDBG("fck = %ld (%d)\n", cinfo->fck, cinfo->fck_div);
477 int dss_get_clock_div(struct dss_clock_info *cinfo)
479 cinfo->fck = clk_get_rate(dss.dss_clk);
481 if (dss.dpll4_m4_ck) {
484 prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
486 if (cpu_is_omap3630() || cpu_is_omap44xx())
487 cinfo->fck_div = prate / (cinfo->fck);
489 cinfo->fck_div = prate / (cinfo->fck / 2);
497 unsigned long dss_get_dpll4_rate(void)
500 return clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
505 int dss_calc_clock_div(bool is_tft, unsigned long req_pck,
506 struct dss_clock_info *dss_cinfo,
507 struct dispc_clock_info *dispc_cinfo)
510 struct dss_clock_info best_dss;
511 struct dispc_clock_info best_dispc;
513 unsigned long fck, max_dss_fck;
515 u16 fck_div, fck_div_max = 16;
520 prate = dss_get_dpll4_rate();
522 max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
524 fck = clk_get_rate(dss.dss_clk);
525 if (req_pck == dss.cache_req_pck &&
526 ((cpu_is_omap34xx() && prate == dss.cache_prate) ||
527 dss.cache_dss_cinfo.fck == fck)) {
528 DSSDBG("dispc clock info found from cache.\n");
529 *dss_cinfo = dss.cache_dss_cinfo;
530 *dispc_cinfo = dss.cache_dispc_cinfo;
534 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
536 if (min_fck_per_pck &&
537 req_pck * min_fck_per_pck > max_dss_fck) {
538 DSSERR("Requested pixel clock not possible with the current "
539 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
540 "the constraint off.\n");
545 memset(&best_dss, 0, sizeof(best_dss));
546 memset(&best_dispc, 0, sizeof(best_dispc));
548 if (dss.dpll4_m4_ck == NULL) {
549 struct dispc_clock_info cur_dispc;
550 /* XXX can we change the clock on omap2? */
551 fck = clk_get_rate(dss.dss_clk);
554 dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc);
558 best_dss.fck_div = fck_div;
560 best_dispc = cur_dispc;
564 if (cpu_is_omap3630() || cpu_is_omap44xx())
567 for (fck_div = fck_div_max; fck_div > 0; --fck_div) {
568 struct dispc_clock_info cur_dispc;
570 if (fck_div_max == 32)
571 fck = prate / fck_div;
573 fck = prate / fck_div * 2;
575 if (fck > max_dss_fck)
578 if (min_fck_per_pck &&
579 fck < req_pck * min_fck_per_pck)
584 dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc);
586 if (abs(cur_dispc.pck - req_pck) <
587 abs(best_dispc.pck - req_pck)) {
590 best_dss.fck_div = fck_div;
592 best_dispc = cur_dispc;
594 if (cur_dispc.pck == req_pck)
602 if (min_fck_per_pck) {
603 DSSERR("Could not find suitable clock settings.\n"
604 "Turning FCK/PCK constraint off and"
610 DSSERR("Could not find suitable clock settings.\n");
616 *dss_cinfo = best_dss;
618 *dispc_cinfo = best_dispc;
620 dss.cache_req_pck = req_pck;
621 dss.cache_prate = prate;
622 dss.cache_dss_cinfo = best_dss;
623 dss.cache_dispc_cinfo = best_dispc;
628 void dss_set_venc_output(enum omap_dss_venc_type type)
632 if (type == OMAP_DSS_VENC_TYPE_COMPOSITE)
634 else if (type == OMAP_DSS_VENC_TYPE_SVIDEO)
639 /* venc out selection. 0 = comp, 1 = svideo */
640 REG_FLD_MOD(DSS_CONTROL, l, 6, 6);
643 void dss_set_dac_pwrdn_bgz(bool enable)
645 REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */
648 void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select hdmi)
650 REG_FLD_MOD(DSS_CONTROL, hdmi, 15, 15); /* VENC_HDMI_SWITCH */
653 enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void)
655 enum omap_display_type displays;
657 displays = dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_DIGIT);
658 if ((displays & OMAP_DISPLAY_TYPE_HDMI) == 0)
659 return DSS_VENC_TV_CLK;
661 return REG_GET(DSS_CONTROL, 15, 15);
664 static int dss_get_clocks(void)
669 clk = clk_get(&dss.pdev->dev, "fck");
671 DSSERR("can't get clock fck\n");
678 if (cpu_is_omap34xx()) {
679 clk = clk_get(NULL, "dpll4_m4_ck");
681 DSSERR("Failed to get dpll4_m4_ck\n");
685 } else if (cpu_is_omap44xx()) {
686 clk = clk_get(NULL, "dpll_per_m5x2_ck");
688 DSSERR("Failed to get dpll_per_m5x2_ck\n");
692 } else { /* omap24xx */
696 dss.dpll4_m4_ck = clk;
702 clk_put(dss.dss_clk);
704 clk_put(dss.dpll4_m4_ck);
709 static void dss_put_clocks(void)
712 clk_put(dss.dpll4_m4_ck);
713 clk_put(dss.dss_clk);
716 static int dss_runtime_get(void)
720 DSSDBG("dss_runtime_get\n");
722 r = pm_runtime_get_sync(&dss.pdev->dev);
724 return r < 0 ? r : 0;
727 static void dss_runtime_put(void)
731 DSSDBG("dss_runtime_put\n");
733 r = pm_runtime_put_sync(&dss.pdev->dev);
738 #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
739 void dss_debug_dump_clocks(struct seq_file *s)
742 dispc_dump_clocks(s);
743 #ifdef CONFIG_OMAP2_DSS_DSI
749 /* DSS HW IP initialisation */
750 static int __init omap_dsshw_probe(struct platform_device *pdev)
752 struct resource *dss_mem;
758 dss_mem = platform_get_resource(dss.pdev, IORESOURCE_MEM, 0);
760 DSSERR("can't get IORESOURCE_MEM DSS\n");
764 dss.base = devm_ioremap(&pdev->dev, dss_mem->start,
765 resource_size(dss_mem));
767 DSSERR("can't ioremap DSS\n");
771 r = dss_get_clocks();
775 pm_runtime_enable(&pdev->dev);
777 r = dss_runtime_get();
779 goto err_runtime_get;
782 REG_FLD_MOD(DSS_CONTROL, 0, 0, 0);
784 #ifdef CONFIG_OMAP2_DSS_VENC
785 REG_FLD_MOD(DSS_CONTROL, 1, 4, 4); /* venc dac demen */
786 REG_FLD_MOD(DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */
787 REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */
789 dss.dsi_clk_source[0] = OMAP_DSS_CLK_SRC_FCK;
790 dss.dsi_clk_source[1] = OMAP_DSS_CLK_SRC_FCK;
791 dss.dispc_clk_source = OMAP_DSS_CLK_SRC_FCK;
792 dss.lcd_clk_source[0] = OMAP_DSS_CLK_SRC_FCK;
793 dss.lcd_clk_source[1] = OMAP_DSS_CLK_SRC_FCK;
795 rev = dss_read_reg(DSS_REVISION);
796 printk(KERN_INFO "OMAP DSS rev %d.%d\n",
797 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
801 dss_debugfs_create_file("dss", dss_dump_regs);
806 pm_runtime_disable(&pdev->dev);
811 static int __exit omap_dsshw_remove(struct platform_device *pdev)
813 pm_runtime_disable(&pdev->dev);
820 static int dss_runtime_suspend(struct device *dev)
823 dss_set_min_bus_tput(dev, 0);
827 static int dss_runtime_resume(struct device *dev)
831 * Set an arbitrarily high tput request to ensure OPP100.
832 * What we should really do is to make a request to stay in OPP100,
833 * without any tput requirements, but that is not currently possible
837 r = dss_set_min_bus_tput(dev, 1000000000);
841 dss_restore_context();
845 static const struct dev_pm_ops dss_pm_ops = {
846 .runtime_suspend = dss_runtime_suspend,
847 .runtime_resume = dss_runtime_resume,
850 static struct platform_driver omap_dsshw_driver = {
851 .remove = __exit_p(omap_dsshw_remove),
853 .name = "omapdss_dss",
854 .owner = THIS_MODULE,
859 int __init dss_init_platform_driver(void)
861 return platform_driver_probe(&omap_dsshw_driver, omap_dsshw_probe);
864 void dss_uninit_platform_driver(void)
866 platform_driver_unregister(&omap_dsshw_driver);