drivers/video/omap2/dss/dss.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dss.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #define DSS_SUBSYS_NAME "DSS"
  24
  25 #include <linux/kernel.h>
  26 #include <linux/io.h>
  27 #include <linux/err.h>
  28 #include <linux/delay.h>
  29 #include <linux/seq_file.h>
  30 #include <linux/clk.h>
  31 #include <linux/platform_device.h>
  32
  33 #include <video/omapdss.h>
  34 #include <plat/clock.h>
  35 #include "dss.h"
  36 #include "dss_features.h"
  37
  38 #define DSS_SZ_REGS                     SZ_512
  39
  40 struct dss_reg {
  41         u16 idx;
  42 };
  43
  44 #define DSS_REG(idx)                    ((const struct dss_reg) { idx })
  45
  46 #define DSS_REVISION                    DSS_REG(0x0000)
  47 #define DSS_SYSCONFIG                   DSS_REG(0x0010)
  48 #define DSS_SYSSTATUS                   DSS_REG(0x0014)
  49 #define DSS_CONTROL                     DSS_REG(0x0040)
  50 #define DSS_SDI_CONTROL                 DSS_REG(0x0044)
  51 #define DSS_PLL_CONTROL                 DSS_REG(0x0048)
  52 #define DSS_SDI_STATUS                  DSS_REG(0x005C)
  53
  54 #define REG_GET(idx, start, end) \
  55         FLD_GET(dss_read_reg(idx), start, end)
  56
  57 #define REG_FLD_MOD(idx, val, start, end) \
  58         dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end))
  59
  60 static struct {
  61         struct platform_device *pdev;
  62         void __iomem    *base;
  63         int             ctx_loss_cnt;
  64
  65         struct clk      *dpll4_m4_ck;
  66         struct clk      *dss_ick;
  67         struct clk      *dss_fck;
  68         struct clk      *dss_sys_clk;
  69         struct clk      *dss_tv_fck;
  70         struct clk      *dss_video_fck;
  71         unsigned        num_clks_enabled;
  72
  73         unsigned long   cache_req_pck;
  74         unsigned long   cache_prate;
  75         struct dss_clock_info cache_dss_cinfo;
  76         struct dispc_clock_info cache_dispc_cinfo;
  77
  78         enum omap_dss_clk_source dsi_clk_source[MAX_NUM_DSI];
  79         enum omap_dss_clk_source dispc_clk_source;
  80         enum omap_dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS];
  81
  82         u32             ctx[DSS_SZ_REGS / sizeof(u32)];
  83 } dss;
  84
  85 static const char * const dss_generic_clk_source_names[] = {
  86         [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC]  = "DSI_PLL_HSDIV_DISPC",
  87         [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI]    = "DSI_PLL_HSDIV_DSI",
  88         [OMAP_DSS_CLK_SRC_FCK]                  = "DSS_FCK",
  89 };
  90
  91 static void dss_clk_enable_all_no_ctx(void);
  92 static void dss_clk_disable_all_no_ctx(void);
  93 static void dss_clk_enable_no_ctx(enum dss_clock clks);
  94 static void dss_clk_disable_no_ctx(enum dss_clock clks);
  95
  96 static int _omap_dss_wait_reset(void);
  97
  98 static inline void dss_write_reg(const struct dss_reg idx, u32 val)
  99 {
 100         __raw_writel(val, dss.base + idx.idx);
 101 }
 102
 103 static inline u32 dss_read_reg(const struct dss_reg idx)
 104 {
 105         return __raw_readl(dss.base + idx.idx);
 106 }
 107
 108 #define SR(reg) \
 109         dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg)
 110 #define RR(reg) \
 111         dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)])
 112
 113 void dss_save_context(void)
 114 {
 115         if (cpu_is_omap24xx())
 116                 return;
 117
 118         SR(SYSCONFIG);
 119         SR(CONTROL);
 120
 121         if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
 122                         OMAP_DISPLAY_TYPE_SDI) {
 123                 SR(SDI_CONTROL);
 124                 SR(PLL_CONTROL);
 125         }
 126 }
 127
 128 void dss_restore_context(void)
 129 {
 130         if (_omap_dss_wait_reset())
 131                 DSSERR("DSS not coming out of reset after sleep\n");
 132
 133         RR(SYSCONFIG);
 134         RR(CONTROL);
 135
 136         if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
 137                         OMAP_DISPLAY_TYPE_SDI) {
 138                 RR(SDI_CONTROL);
 139                 RR(PLL_CONTROL);
 140         }
 141 }
 142
 143 #undef SR
 144 #undef RR
 145
 146 void dss_sdi_init(u8 datapairs)
 147 {
 148         u32 l;
 149
 150         BUG_ON(datapairs > 3 || datapairs < 1);
 151
 152         l = dss_read_reg(DSS_SDI_CONTROL);
 153         l = FLD_MOD(l, 0xf, 19, 15);            /* SDI_PDIV */
 154         l = FLD_MOD(l, datapairs-1, 3, 2);      /* SDI_PRSEL */
 155         l = FLD_MOD(l, 2, 1, 0);                /* SDI_BWSEL */
 156         dss_write_reg(DSS_SDI_CONTROL, l);
 157
 158         l = dss_read_reg(DSS_PLL_CONTROL);
 159         l = FLD_MOD(l, 0x7, 25, 22);    /* SDI_PLL_FREQSEL */
 160         l = FLD_MOD(l, 0xb, 16, 11);    /* SDI_PLL_REGN */
 161         l = FLD_MOD(l, 0xb4, 10, 1);    /* SDI_PLL_REGM */
 162         dss_write_reg(DSS_PLL_CONTROL, l);
 163 }
 164
 165 int dss_sdi_enable(void)
 166 {
 167         unsigned long timeout;
 168
 169         dispc_pck_free_enable(1);
 170
 171         /* Reset SDI PLL */
 172         REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */
 173         udelay(1);      /* wait 2x PCLK */
 174
 175         /* Lock SDI PLL */
 176         REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */
 177
 178         /* Waiting for PLL lock request to complete */
 179         timeout = jiffies + msecs_to_jiffies(500);
 180         while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6)) {
 181                 if (time_after_eq(jiffies, timeout)) {
 182                         DSSERR("PLL lock request timed out\n");
 183                         goto err1;
 184                 }
 185         }
 186
 187         /* Clearing PLL_GO bit */
 188         REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28);
 189
 190         /* Waiting for PLL to lock */
 191         timeout = jiffies + msecs_to_jiffies(500);
 192         while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5))) {
 193                 if (time_after_eq(jiffies, timeout)) {
 194                         DSSERR("PLL lock timed out\n");
 195                         goto err1;
 196                 }
 197         }
 198
 199         dispc_lcd_enable_signal(1);
 200
 201         /* Waiting for SDI reset to complete */
 202         timeout = jiffies + msecs_to_jiffies(500);
 203         while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 2))) {
 204                 if (time_after_eq(jiffies, timeout)) {
 205                         DSSERR("SDI reset timed out\n");
 206                         goto err2;
 207                 }
 208         }
 209
 210         return 0;
 211
 212  err2:
 213         dispc_lcd_enable_signal(0);
 214  err1:
 215         /* Reset SDI PLL */
 216         REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
 217
 218         dispc_pck_free_enable(0);
 219
 220         return -ETIMEDOUT;
 221 }
 222
 223 void dss_sdi_disable(void)
 224 {
 225         dispc_lcd_enable_signal(0);
 226
 227         dispc_pck_free_enable(0);
 228
 229         /* Reset SDI PLL */
 230         REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
 231 }
 232
 233 const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src)
 234 {
 235         return dss_generic_clk_source_names[clk_src];
 236 }
 237
 238 void dss_dump_clocks(struct seq_file *s)
 239 {
 240         unsigned long dpll4_ck_rate;
 241         unsigned long dpll4_m4_ck_rate;
 242         const char *fclk_name, *fclk_real_name;
 243         unsigned long fclk_rate;
 244
 245         dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
 246
 247         seq_printf(s, "- DSS -\n");
 248
 249         fclk_name = dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_FCK);
 250         fclk_real_name = dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_FCK);
 251         fclk_rate = dss_clk_get_rate(DSS_CLK_FCK);
 252
 253         if (dss.dpll4_m4_ck) {
 254                 dpll4_ck_rate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
 255                 dpll4_m4_ck_rate = clk_get_rate(dss.dpll4_m4_ck);
 256
 257                 seq_printf(s, "dpll4_ck %lu\n", dpll4_ck_rate);
 258
 259                 if (cpu_is_omap3630() || cpu_is_omap44xx())
 260                         seq_printf(s, "%s (%s) = %lu / %lu  = %lu\n",
 261                                         fclk_name, fclk_real_name,
 262                                         dpll4_ck_rate,
 263                                         dpll4_ck_rate / dpll4_m4_ck_rate,
 264                                         fclk_rate);
 265                 else
 266                         seq_printf(s, "%s (%s) = %lu / %lu * 2 = %lu\n",
 267                                         fclk_name, fclk_real_name,
 268                                         dpll4_ck_rate,
 269                                         dpll4_ck_rate / dpll4_m4_ck_rate,
 270                                         fclk_rate);
 271         } else {
 272                 seq_printf(s, "%s (%s) = %lu\n",
 273                                 fclk_name, fclk_real_name,
 274                                 fclk_rate);
 275         }
 276
 277         dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
 278 }
 279
 280 void dss_dump_regs(struct seq_file *s)
 281 {
 282 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r))
 283
 284         dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
 285
 286         DUMPREG(DSS_REVISION);
 287         DUMPREG(DSS_SYSCONFIG);
 288         DUMPREG(DSS_SYSSTATUS);
 289         DUMPREG(DSS_CONTROL);
 290
 291         if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
 292                         OMAP_DISPLAY_TYPE_SDI) {
 293                 DUMPREG(DSS_SDI_CONTROL);
 294                 DUMPREG(DSS_PLL_CONTROL);
 295                 DUMPREG(DSS_SDI_STATUS);
 296         }
 297
 298         dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
 299 #undef DUMPREG
 300 }
 301
 302 void dss_select_dispc_clk_source(enum omap_dss_clk_source clk_src)
 303 {
 304         struct platform_device *dsidev;
 305         int b;
 306         u8 start, end;
 307
 308         switch (clk_src) {
 309         case OMAP_DSS_CLK_SRC_FCK:
 310                 b = 0;
 311                 break;
 312         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
 313                 b = 1;
 314                 dsidev = dsi_get_dsidev_from_id(0);
 315                 dsi_wait_pll_hsdiv_dispc_active(dsidev);
 316                 break;
 317         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
 318                 b = 2;
 319                 dsidev = dsi_get_dsidev_from_id(1);
 320                 dsi_wait_pll_hsdiv_dispc_active(dsidev);
 321                 break;
 322         default:
 323                 BUG();
 324         }
 325
 326         dss_feat_get_reg_field(FEAT_REG_DISPC_CLK_SWITCH, &start, &end);
 327
 328         REG_FLD_MOD(DSS_CONTROL, b, start, end);        /* DISPC_CLK_SWITCH */
 329
 330         dss.dispc_clk_source = clk_src;
 331 }
 332
 333 void dss_select_dsi_clk_source(int dsi_module,
 334                 enum omap_dss_clk_source clk_src)
 335 {
 336         struct platform_device *dsidev;
 337         int b;
 338
 339         switch (clk_src) {
 340         case OMAP_DSS_CLK_SRC_FCK:
 341                 b = 0;
 342                 break;
 343         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI:
 344                 BUG_ON(dsi_module != 0);
 345                 b = 1;
 346                 dsidev = dsi_get_dsidev_from_id(0);
 347                 dsi_wait_pll_hsdiv_dsi_active(dsidev);
 348                 break;
 349         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI:
 350                 BUG_ON(dsi_module != 1);
 351                 b = 1;
 352                 dsidev = dsi_get_dsidev_from_id(1);
 353                 dsi_wait_pll_hsdiv_dsi_active(dsidev);
 354                 break;
 355         default:
 356                 BUG();
 357         }
 358
 359         REG_FLD_MOD(DSS_CONTROL, b, 1, 1);      /* DSI_CLK_SWITCH */
 360
 361         dss.dsi_clk_source[dsi_module] = clk_src;
 362 }
 363
 364 void dss_select_lcd_clk_source(enum omap_channel channel,
 365                 enum omap_dss_clk_source clk_src)
 366 {
 367         struct platform_device *dsidev;
 368         int b, ix, pos;
 369
 370         if (!dss_has_feature(FEAT_LCD_CLK_SRC))
 371                 return;
 372
 373         switch (clk_src) {
 374         case OMAP_DSS_CLK_SRC_FCK:
 375                 b = 0;
 376                 break;
 377         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
 378                 BUG_ON(channel != OMAP_DSS_CHANNEL_LCD);
 379                 b = 1;
 380                 dsidev = dsi_get_dsidev_from_id(0);
 381                 dsi_wait_pll_hsdiv_dispc_active(dsidev);
 382                 break;
 383         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
 384                 BUG_ON(channel != OMAP_DSS_CHANNEL_LCD2);
 385                 b = 1;
 386                 dsidev = dsi_get_dsidev_from_id(1);
 387                 dsi_wait_pll_hsdiv_dispc_active(dsidev);
 388                 break;
 389         default:
 390                 BUG();
 391         }
 392
 393         pos = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 12;
 394         REG_FLD_MOD(DSS_CONTROL, b, pos, pos);  /* LCDx_CLK_SWITCH */
 395
 396         ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 1;
 397         dss.lcd_clk_source[ix] = clk_src;
 398 }
 399
 400 enum omap_dss_clk_source dss_get_dispc_clk_source(void)
 401 {
 402         return dss.dispc_clk_source;
 403 }
 404
 405 enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module)
 406 {
 407         return dss.dsi_clk_source[dsi_module];
 408 }
 409
 410 enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel)
 411 {
 412         if (dss_has_feature(FEAT_LCD_CLK_SRC)) {
 413                 int ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 1;
 414                 return dss.lcd_clk_source[ix];
 415         } else {
 416                 /* LCD_CLK source is the same as DISPC_FCLK source for
 417                  * OMAP2 and OMAP3 */
 418                 return dss.dispc_clk_source;
 419         }
 420 }
 421
 422 /* calculate clock rates using dividers in cinfo */
 423 int dss_calc_clock_rates(struct dss_clock_info *cinfo)
 424 {
 425         if (dss.dpll4_m4_ck) {
 426                 unsigned long prate;
 427                 u16 fck_div_max = 16;
 428
 429                 if (cpu_is_omap3630() || cpu_is_omap44xx())
 430                         fck_div_max = 32;
 431
 432                 if (cinfo->fck_div > fck_div_max || cinfo->fck_div == 0)
 433                         return -EINVAL;
 434
 435                 prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
 436
 437                 cinfo->fck = prate / cinfo->fck_div;
 438         } else {
 439                 if (cinfo->fck_div != 0)
 440                         return -EINVAL;
 441                 cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK);
 442         }
 443
 444         return 0;
 445 }
 446
 447 int dss_set_clock_div(struct dss_clock_info *cinfo)
 448 {
 449         if (dss.dpll4_m4_ck) {
 450                 unsigned long prate;
 451                 int r;
 452
 453                 prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
 454                 DSSDBG("dpll4_m4 = %ld\n", prate);
 455
 456                 r = clk_set_rate(dss.dpll4_m4_ck, prate / cinfo->fck_div);
 457                 if (r)
 458                         return r;
 459         } else {
 460                 if (cinfo->fck_div != 0)
 461                         return -EINVAL;
 462         }
 463
 464         DSSDBG("fck = %ld (%d)\n", cinfo->fck, cinfo->fck_div);
 465
 466         return 0;
 467 }
 468
 469 int dss_get_clock_div(struct dss_clock_info *cinfo)
 470 {
 471         cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK);
 472
 473         if (dss.dpll4_m4_ck) {
 474                 unsigned long prate;
 475
 476                 prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
 477
 478                 if (cpu_is_omap3630() || cpu_is_omap44xx())
 479                         cinfo->fck_div = prate / (cinfo->fck);
 480                 else
 481                         cinfo->fck_div = prate / (cinfo->fck / 2);
 482         } else {
 483                 cinfo->fck_div = 0;
 484         }
 485
 486         return 0;
 487 }
 488
 489 unsigned long dss_get_dpll4_rate(void)
 490 {
 491         if (dss.dpll4_m4_ck)
 492                 return clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
 493         else
 494                 return 0;
 495 }
 496
 497 int dss_calc_clock_div(bool is_tft, unsigned long req_pck,
 498                 struct dss_clock_info *dss_cinfo,
 499                 struct dispc_clock_info *dispc_cinfo)
 500 {
 501         unsigned long prate;
 502         struct dss_clock_info best_dss;
 503         struct dispc_clock_info best_dispc;
 504
 505         unsigned long fck, max_dss_fck;
 506
 507         u16 fck_div, fck_div_max = 16;
 508
 509         int match = 0;
 510         int min_fck_per_pck;
 511
 512         prate = dss_get_dpll4_rate();
 513
 514         max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
 515
 516         fck = dss_clk_get_rate(DSS_CLK_FCK);
 517         if (req_pck == dss.cache_req_pck &&
 518                         ((cpu_is_omap34xx() && prate == dss.cache_prate) ||
 519                          dss.cache_dss_cinfo.fck == fck)) {
 520                 DSSDBG("dispc clock info found from cache.\n");
 521                 *dss_cinfo = dss.cache_dss_cinfo;
 522                 *dispc_cinfo = dss.cache_dispc_cinfo;
 523                 return 0;
 524         }
 525
 526         min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
 527
 528         if (min_fck_per_pck &&
 529                 req_pck * min_fck_per_pck > max_dss_fck) {
 530                 DSSERR("Requested pixel clock not possible with the current "
 531                                 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
 532                                 "the constraint off.\n");
 533                 min_fck_per_pck = 0;
 534         }
 535
 536 retry:
 537         memset(&best_dss, 0, sizeof(best_dss));
 538         memset(&best_dispc, 0, sizeof(best_dispc));
 539
 540         if (dss.dpll4_m4_ck == NULL) {
 541                 struct dispc_clock_info cur_dispc;
 542                 /* XXX can we change the clock on omap2? */
 543                 fck = dss_clk_get_rate(DSS_CLK_FCK);
 544                 fck_div = 1;
 545
 546                 dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc);
 547                 match = 1;
 548
 549                 best_dss.fck = fck;
 550                 best_dss.fck_div = fck_div;
 551
 552                 best_dispc = cur_dispc;
 553
 554                 goto found;
 555         } else {
 556                 if (cpu_is_omap3630() || cpu_is_omap44xx())
 557                         fck_div_max = 32;
 558
 559                 for (fck_div = fck_div_max; fck_div > 0; --fck_div) {
 560                         struct dispc_clock_info cur_dispc;
 561
 562                         if (fck_div_max == 32)
 563                                 fck = prate / fck_div;
 564                         else
 565                                 fck = prate / fck_div * 2;
 566
 567                         if (fck > max_dss_fck)
 568                                 continue;
 569
 570                         if (min_fck_per_pck &&
 571                                         fck < req_pck * min_fck_per_pck)
 572                                 continue;
 573
 574                         match = 1;
 575
 576                         dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc);
 577
 578                         if (abs(cur_dispc.pck - req_pck) <
 579                                         abs(best_dispc.pck - req_pck)) {
 580
 581                                 best_dss.fck = fck;
 582                                 best_dss.fck_div = fck_div;
 583
 584                                 best_dispc = cur_dispc;
 585
 586                                 if (cur_dispc.pck == req_pck)
 587                                         goto found;
 588                         }
 589                 }
 590         }
 591
 592 found:
 593         if (!match) {
 594                 if (min_fck_per_pck) {
 595                         DSSERR("Could not find suitable clock settings.\n"
 596                                         "Turning FCK/PCK constraint off and"
 597                                         "trying again.\n");
 598                         min_fck_per_pck = 0;
 599                         goto retry;
 600                 }
 601
 602                 DSSERR("Could not find suitable clock settings.\n");
 603
 604                 return -EINVAL;
 605         }
 606
 607         if (dss_cinfo)
 608                 *dss_cinfo = best_dss;
 609         if (dispc_cinfo)
 610                 *dispc_cinfo = best_dispc;
 611
 612         dss.cache_req_pck = req_pck;
 613         dss.cache_prate = prate;
 614         dss.cache_dss_cinfo = best_dss;
 615         dss.cache_dispc_cinfo = best_dispc;
 616
 617         return 0;
 618 }
 619
 620 static int _omap_dss_wait_reset(void)
 621 {
 622         int t = 0;
 623
 624         while (REG_GET(DSS_SYSSTATUS, 0, 0) == 0) {
 625                 if (++t > 1000) {
 626                         DSSERR("soft reset failed\n");
 627                         return -ENODEV;
 628                 }
 629                 udelay(1);
 630         }
 631
 632         return 0;
 633 }
 634
 635 static int _omap_dss_reset(void)
 636 {
 637         /* Soft reset */
 638         REG_FLD_MOD(DSS_SYSCONFIG, 1, 1, 1);
 639         return _omap_dss_wait_reset();
 640 }
 641
 642 void dss_set_venc_output(enum omap_dss_venc_type type)
 643 {
 644         int l = 0;
 645
 646         if (type == OMAP_DSS_VENC_TYPE_COMPOSITE)
 647                 l = 0;
 648         else if (type == OMAP_DSS_VENC_TYPE_SVIDEO)
 649                 l = 1;
 650         else
 651                 BUG();
 652
 653         /* venc out selection. 0 = comp, 1 = svideo */
 654         REG_FLD_MOD(DSS_CONTROL, l, 6, 6);
 655 }
 656
 657 void dss_set_dac_pwrdn_bgz(bool enable)
 658 {
 659         REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */
 660 }
 661
 662 void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select hdmi)
 663 {
 664         REG_FLD_MOD(DSS_CONTROL, hdmi, 15, 15); /* VENC_HDMI_SWITCH */
 665 }
 666
 667 /* CONTEXT */
 668 static void dss_init_ctx_loss_count(void)
 669 {
 670         struct device *dev = &dss.pdev->dev;
 671         struct omap_display_platform_data *pdata = dev->platform_data;
 672         struct omap_dss_board_info *board_data = pdata->board_data;
 673         int cnt = 0;
 674
 675         /*
 676          * get_context_loss_count returns negative on error. We'll ignore the
 677          * error and store the error to ctx_loss_cnt, which will cause
 678          * dss_need_ctx_restore() call to return true.
 679          */
 680
 681         if (board_data->get_context_loss_count)
 682                 cnt = board_data->get_context_loss_count(dev);
 683
 684         WARN_ON(cnt < 0);
 685
 686         dss.ctx_loss_cnt = cnt;
 687
 688         DSSDBG("initial ctx_loss_cnt %u\n", cnt);
 689 }
 690
 691 static bool dss_need_ctx_restore(void)
 692 {
 693         struct device *dev = &dss.pdev->dev;
 694         struct omap_display_platform_data *pdata = dev->platform_data;
 695         struct omap_dss_board_info *board_data = pdata->board_data;
 696         int cnt;
 697
 698         /*
 699          * If get_context_loss_count is not available, assume that we need
 700          * context restore always.
 701          */
 702         if (!board_data->get_context_loss_count)
 703                 return true;
 704
 705         cnt = board_data->get_context_loss_count(dev);
 706         if (cnt < 0) {
 707                 dev_err(dev, "getting context loss count failed, will force "
 708                                 "context restore\n");
 709                 dss.ctx_loss_cnt = cnt;
 710                 return true;
 711         }
 712
 713         if (cnt == dss.ctx_loss_cnt)
 714                 return false;
 715
 716         DSSDBG("ctx_loss_cnt %d -> %d\n", dss.ctx_loss_cnt, cnt);
 717         dss.ctx_loss_cnt = cnt;
 718
 719         return true;
 720 }
 721
 722 static void save_all_ctx(void)
 723 {
 724         DSSDBG("save context\n");
 725
 726         dss_clk_enable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK);
 727
 728         dss_save_context();
 729         dispc_save_context();
 730 #ifdef CONFIG_OMAP2_DSS_DSI
 731         dsi_save_context();
 732 #endif
 733
 734         dss_clk_disable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK);
 735 }
 736
 737 static void restore_all_ctx(void)
 738 {
 739         DSSDBG("restore context\n");
 740
 741         dss_clk_enable_all_no_ctx();
 742
 743         dss_restore_context();
 744         dispc_restore_context();
 745 #ifdef CONFIG_OMAP2_DSS_DSI
 746         dsi_restore_context();
 747 #endif
 748
 749         dss_clk_disable_all_no_ctx();
 750 }
 751
 752 static int dss_get_clock(struct clk **clock, const char *clk_name)
 753 {
 754         struct clk *clk;
 755
 756         clk = clk_get(&dss.pdev->dev, clk_name);
 757
 758         if (IS_ERR(clk)) {
 759                 DSSERR("can't get clock %s", clk_name);
 760                 return PTR_ERR(clk);
 761         }
 762
 763         *clock = clk;
 764
 765         DSSDBG("clk %s, rate %ld\n", clk_name, clk_get_rate(clk));
 766
 767         return 0;
 768 }
 769
 770 static int dss_get_clocks(void)
 771 {
 772         int r;
 773         struct clk *dpll4_m4_ck;
 774         struct omap_display_platform_data *pdata = dss.pdev->dev.platform_data;
 775
 776         dss.dss_ick = NULL;
 777         dss.dss_fck = NULL;
 778         dss.dss_sys_clk = NULL;
 779         dss.dss_tv_fck = NULL;
 780         dss.dss_video_fck = NULL;
 781
 782         r = dss_get_clock(&dss.dss_ick, "ick");
 783         if (r)
 784                 goto err;
 785
 786         r = dss_get_clock(&dss.dss_fck, "fck");
 787         if (r)
 788                 goto err;
 789
 790         if (!pdata->opt_clock_available) {
 791                 r = -ENODEV;
 792                 goto err;
 793         }
 794
 795         if (pdata->opt_clock_available("sys_clk")) {
 796                 r = dss_get_clock(&dss.dss_sys_clk, "sys_clk");
 797                 if (r)
 798                         goto err;
 799         }
 800
 801         if (pdata->opt_clock_available("tv_clk")) {
 802                 r = dss_get_clock(&dss.dss_tv_fck, "tv_clk");
 803                 if (r)
 804                         goto err;
 805         }
 806
 807         if (pdata->opt_clock_available("video_clk")) {
 808                 r = dss_get_clock(&dss.dss_video_fck, "video_clk");
 809                 if (r)
 810                         goto err;
 811         }
 812
 813         if (cpu_is_omap34xx()) {
 814                 dpll4_m4_ck = clk_get(NULL, "dpll4_m4_ck");
 815                 if (IS_ERR(dpll4_m4_ck)) {
 816                         DSSERR("Failed to get dpll4_m4_ck\n");
 817                         r = PTR_ERR(dpll4_m4_ck);
 818                         goto err;
 819                 }
 820         } else if (cpu_is_omap44xx()) {
 821                 dpll4_m4_ck = clk_get(NULL, "dpll_per_m5x2_ck");
 822                 if (IS_ERR(dpll4_m4_ck)) {
 823                         DSSERR("Failed to get dpll_per_m5x2_ck\n");
 824                         r = PTR_ERR(dpll4_m4_ck);
 825                         goto err;
 826                 }
 827         } else { /* omap24xx */
 828                 dpll4_m4_ck = NULL;
 829         }
 830
 831         dss.dpll4_m4_ck = dpll4_m4_ck;
 832
 833
 834         return 0;
 835
 836 err:
 837         if (dss.dss_ick)
 838                 clk_put(dss.dss_ick);
 839         if (dss.dss_fck)
 840                 clk_put(dss.dss_fck);
 841         if (dss.dss_sys_clk)
 842                 clk_put(dss.dss_sys_clk);
 843         if (dss.dss_tv_fck)
 844                 clk_put(dss.dss_tv_fck);
 845         if (dss.dss_video_fck)
 846                 clk_put(dss.dss_video_fck);
 847         if (dss.dpll4_m4_ck)
 848                 clk_put(dss.dpll4_m4_ck);
 849
 850         return r;
 851 }
 852
 853 static void dss_put_clocks(void)
 854 {
 855         if (dss.dpll4_m4_ck)
 856                 clk_put(dss.dpll4_m4_ck);
 857         if (dss.dss_video_fck)
 858                 clk_put(dss.dss_video_fck);
 859         if (dss.dss_tv_fck)
 860                 clk_put(dss.dss_tv_fck);
 861         if (dss.dss_sys_clk)
 862                 clk_put(dss.dss_sys_clk);
 863         clk_put(dss.dss_fck);
 864         clk_put(dss.dss_ick);
 865 }
 866
 867 unsigned long dss_clk_get_rate(enum dss_clock clk)
 868 {
 869         switch (clk) {
 870         case DSS_CLK_ICK:
 871                 return clk_get_rate(dss.dss_ick);
 872         case DSS_CLK_FCK:
 873                 return clk_get_rate(dss.dss_fck);
 874         case DSS_CLK_SYSCK:
 875                 return clk_get_rate(dss.dss_sys_clk);
 876         case DSS_CLK_TVFCK:
 877                 return clk_get_rate(dss.dss_tv_fck);
 878         case DSS_CLK_VIDFCK:
 879                 return clk_get_rate(dss.dss_video_fck);
 880         }
 881
 882         BUG();
 883         return 0;
 884 }
 885
 886 static unsigned count_clk_bits(enum dss_clock clks)
 887 {
 888         unsigned num_clks = 0;
 889
 890         if (clks & DSS_CLK_ICK)
 891                 ++num_clks;
 892         if (clks & DSS_CLK_FCK)
 893                 ++num_clks;
 894         if (clks & DSS_CLK_SYSCK)
 895                 ++num_clks;
 896         if (clks & DSS_CLK_TVFCK)
 897                 ++num_clks;
 898         if (clks & DSS_CLK_VIDFCK)
 899                 ++num_clks;
 900
 901         return num_clks;
 902 }
 903
 904 static void dss_clk_enable_no_ctx(enum dss_clock clks)
 905 {
 906         unsigned num_clks = count_clk_bits(clks);
 907
 908         if (clks & DSS_CLK_ICK)
 909                 clk_enable(dss.dss_ick);
 910         if (clks & DSS_CLK_FCK)
 911                 clk_enable(dss.dss_fck);
 912         if ((clks & DSS_CLK_SYSCK) && dss.dss_sys_clk)
 913                 clk_enable(dss.dss_sys_clk);
 914         if ((clks & DSS_CLK_TVFCK) && dss.dss_tv_fck)
 915                 clk_enable(dss.dss_tv_fck);
 916         if ((clks & DSS_CLK_VIDFCK) && dss.dss_video_fck)
 917                 clk_enable(dss.dss_video_fck);
 918
 919         dss.num_clks_enabled += num_clks;
 920 }
 921
 922 void dss_clk_enable(enum dss_clock clks)
 923 {
 924         bool check_ctx = dss.num_clks_enabled == 0;
 925
 926         dss_clk_enable_no_ctx(clks);
 927
 928         /*
 929          * HACK: On omap4 the registers may not be accessible right after
 930          * enabling the clocks. At some point this will be handled by
 931          * pm_runtime, but for the time begin this should make things work.
 932          */
 933         if (cpu_is_omap44xx() && check_ctx)
 934                 udelay(10);
 935
 936         if (check_ctx && cpu_is_omap34xx() && dss_need_ctx_restore())
 937                 restore_all_ctx();
 938 }
 939
 940 static void dss_clk_disable_no_ctx(enum dss_clock clks)
 941 {
 942         unsigned num_clks = count_clk_bits(clks);
 943
 944         if (clks & DSS_CLK_ICK)
 945                 clk_disable(dss.dss_ick);
 946         if (clks & DSS_CLK_FCK)
 947                 clk_disable(dss.dss_fck);
 948         if ((clks & DSS_CLK_SYSCK) && dss.dss_sys_clk)
 949                 clk_disable(dss.dss_sys_clk);
 950         if ((clks & DSS_CLK_TVFCK) && dss.dss_tv_fck)
 951                 clk_disable(dss.dss_tv_fck);
 952         if ((clks & DSS_CLK_VIDFCK) && dss.dss_video_fck)
 953                 clk_disable(dss.dss_video_fck);
 954
 955         dss.num_clks_enabled -= num_clks;
 956 }
 957
 958 void dss_clk_disable(enum dss_clock clks)
 959 {
 960         if (cpu_is_omap34xx()) {
 961                 unsigned num_clks = count_clk_bits(clks);
 962
 963                 BUG_ON(dss.num_clks_enabled < num_clks);
 964
 965                 if (dss.num_clks_enabled == num_clks)
 966                         save_all_ctx();
 967         }
 968
 969         dss_clk_disable_no_ctx(clks);
 970 }
 971
 972 static void dss_clk_enable_all_no_ctx(void)
 973 {
 974         enum dss_clock clks;
 975
 976         clks = DSS_CLK_ICK | DSS_CLK_FCK | DSS_CLK_SYSCK | DSS_CLK_TVFCK;
 977         if (cpu_is_omap34xx())
 978                 clks |= DSS_CLK_VIDFCK;
 979         dss_clk_enable_no_ctx(clks);
 980 }
 981
 982 static void dss_clk_disable_all_no_ctx(void)
 983 {
 984         enum dss_clock clks;
 985
 986         clks = DSS_CLK_ICK | DSS_CLK_FCK | DSS_CLK_SYSCK | DSS_CLK_TVFCK;
 987         if (cpu_is_omap34xx())
 988                 clks |= DSS_CLK_VIDFCK;
 989         dss_clk_disable_no_ctx(clks);
 990 }
 991
 992 /* DEBUGFS */
 993 #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
 994 void dss_debug_dump_clocks(struct seq_file *s)
 995 {
 996         dss_dump_clocks(s);
 997         dispc_dump_clocks(s);
 998 #ifdef CONFIG_OMAP2_DSS_DSI
 999         dsi_dump_clocks(s);
1000 #endif
1001 }
1002 #endif
1003
1004
1005 /* DSS HW IP initialisation */
1006 static int omap_dsshw_probe(struct platform_device *pdev)
1007 {
1008         struct resource *dss_mem;
1009         u32 rev;
1010         int r;
1011
1012         dss.pdev = pdev;
1013
1014         dss_mem = platform_get_resource(dss.pdev, IORESOURCE_MEM, 0);
1015         if (!dss_mem) {
1016                 DSSERR("can't get IORESOURCE_MEM DSS\n");
1017                 r = -EINVAL;
1018                 goto err_ioremap;
1019         }
1020         dss.base = ioremap(dss_mem->start, resource_size(dss_mem));
1021         if (!dss.base) {
1022                 DSSERR("can't ioremap DSS\n");
1023                 r = -ENOMEM;
1024                 goto err_ioremap;
1025         }
1026
1027         r = dss_get_clocks();
1028         if (r)
1029                 goto err_clocks;
1030
1031         dss_clk_enable_all_no_ctx();
1032
1033         dss_init_ctx_loss_count();
1034
1035         /* disable LCD and DIGIT output. This seems to fix the synclost
1036          * problem that we get, if the bootloader starts the DSS and
1037          * the kernel resets it */
1038         omap_writel(omap_readl(0x48050440) & ~0x3, 0x48050440);
1039
1040 #ifdef CONFIG_OMAP2_DSS_SLEEP_BEFORE_RESET
1041         /* We need to wait here a bit, otherwise we sometimes start to
1042          * get synclost errors, and after that only power cycle will
1043          * restore DSS functionality. I have no idea why this happens.
1044          * And we have to wait _before_ resetting the DSS, but after
1045          * enabling clocks.
1046          *
1047          * This bug was at least present on OMAP3430. It's unknown
1048          * if it happens on OMAP2 or OMAP3630.
1049          */
1050         msleep(50);
1051 #endif
1052
1053         _omap_dss_reset();
1054
1055         /* autoidle */
1056         REG_FLD_MOD(DSS_SYSCONFIG, 1, 0, 0);
1057
1058         /* Select DPLL */
1059         REG_FLD_MOD(DSS_CONTROL, 0, 0, 0);
1060
1061 #ifdef CONFIG_OMAP2_DSS_VENC
1062         REG_FLD_MOD(DSS_CONTROL, 1, 4, 4);      /* venc dac demen */
1063         REG_FLD_MOD(DSS_CONTROL, 1, 3, 3);      /* venc clock 4x enable */
1064         REG_FLD_MOD(DSS_CONTROL, 0, 2, 2);      /* venc clock mode = normal */
1065 #endif
1066         dss.dsi_clk_source[0] = OMAP_DSS_CLK_SRC_FCK;
1067         dss.dsi_clk_source[1] = OMAP_DSS_CLK_SRC_FCK;
1068         dss.dispc_clk_source = OMAP_DSS_CLK_SRC_FCK;
1069         dss.lcd_clk_source[0] = OMAP_DSS_CLK_SRC_FCK;
1070         dss.lcd_clk_source[1] = OMAP_DSS_CLK_SRC_FCK;
1071
1072         r = dpi_init();
1073         if (r) {
1074                 DSSERR("Failed to initialize DPI\n");
1075                 goto err_dpi;
1076         }
1077
1078         r = sdi_init();
1079         if (r) {
1080                 DSSERR("Failed to initialize SDI\n");
1081                 goto err_sdi;
1082         }
1083
1084         dss_save_context();
1085
1086         rev = dss_read_reg(DSS_REVISION);
1087         printk(KERN_INFO "OMAP DSS rev %d.%d\n",
1088                         FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
1089
1090         dss_clk_disable_all_no_ctx();
1091
1092         return 0;
1093 err_sdi:
1094         dpi_exit();
1095 err_dpi:
1096         dss_clk_disable_all_no_ctx();
1097         dss_put_clocks();
1098 err_clocks:
1099         iounmap(dss.base);
1100 err_ioremap:
1101         return r;
1102 }
1103
1104 static int omap_dsshw_remove(struct platform_device *pdev)
1105 {
1106         dpi_exit();
1107         sdi_exit();
1108
1109         iounmap(dss.base);
1110
1111         /*
1112          * As part of hwmod changes, DSS is not the only controller of dss
1113          * clocks; hwmod framework itself will also enable clocks during hwmod
1114          * init for dss, and autoidle is set in h/w for DSS. Hence, there's no
1115          * need to disable clocks if their usecounts > 1.
1116          */
1117         WARN_ON(dss.num_clks_enabled > 0);
1118
1119         dss_put_clocks();
1120
1121         return 0;
1122 }
1123
1124 static struct platform_driver omap_dsshw_driver = {
1125         .probe          = omap_dsshw_probe,
1126         .remove         = omap_dsshw_remove,
1127         .driver         = {
1128                 .name   = "omapdss_dss",
1129                 .owner  = THIS_MODULE,
1130         },
1131 };
1132
1133 int dss_init_platform_driver(void)
1134 {
1135         return platform_driver_register(&omap_dsshw_driver);
1136 }
1137
1138 void dss_uninit_platform_driver(void)
1139 {
1140         return platform_driver_unregister(&omap_dsshw_driver);
1141 }