drivers/video/omap2/dss/dss.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dss.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #define DSS_SUBSYS_NAME "DSS"
  24
  25 #include <linux/kernel.h>
  26 #include <linux/io.h>
  27 #include <linux/err.h>
  28 #include <linux/delay.h>
  29 #include <linux/seq_file.h>
  30 #include <linux/clk.h>
  31
  32 #include <plat/display.h>
  33 #include <plat/clock.h>
  34 #include "dss.h"
  35 #include "dss_features.h"
  36
  37 #define DSS_SZ_REGS                     SZ_512
  38
  39 struct dss_reg {
  40         u16 idx;
  41 };
  42
  43 #define DSS_REG(idx)                    ((const struct dss_reg) { idx })
  44
  45 #define DSS_REVISION                    DSS_REG(0x0000)
  46 #define DSS_SYSCONFIG                   DSS_REG(0x0010)
  47 #define DSS_SYSSTATUS                   DSS_REG(0x0014)
  48 #define DSS_IRQSTATUS                   DSS_REG(0x0018)
  49 #define DSS_CONTROL                     DSS_REG(0x0040)
  50 #define DSS_SDI_CONTROL                 DSS_REG(0x0044)
  51 #define DSS_PLL_CONTROL                 DSS_REG(0x0048)
  52 #define DSS_SDI_STATUS                  DSS_REG(0x005C)
  53
  54 #define REG_GET(idx, start, end) \
  55         FLD_GET(dss_read_reg(idx), start, end)
  56
  57 #define REG_FLD_MOD(idx, val, start, end) \
  58         dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end))
  59
  60 static struct {
  61         struct platform_device *pdev;
  62         void __iomem    *base;
  63         int             ctx_id;
  64
  65         struct clk      *dpll4_m4_ck;
  66         struct clk      *dss_ick;
  67         struct clk      *dss_fck;
  68         struct clk      *dss_sys_clk;
  69         struct clk      *dss_tv_fck;
  70         struct clk      *dss_video_fck;
  71         unsigned        num_clks_enabled;
  72
  73         unsigned long   cache_req_pck;
  74         unsigned long   cache_prate;
  75         struct dss_clock_info cache_dss_cinfo;
  76         struct dispc_clock_info cache_dispc_cinfo;
  77
  78         enum dss_clk_source dsi_clk_source;
  79         enum dss_clk_source dispc_clk_source;
  80         enum dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS];
  81
  82         u32             ctx[DSS_SZ_REGS / sizeof(u32)];
  83 } dss;
  84
  85 static const char * const dss_generic_clk_source_names[] = {
  86         [DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC]       = "DSI_PLL_HSDIV_DISPC",
  87         [DSS_CLK_SRC_DSI_PLL_HSDIV_DSI]         = "DSI_PLL_HSDIV_DSI",
  88         [DSS_CLK_SRC_FCK]                       = "DSS_FCK",
  89 };
  90
  91 static void dss_clk_enable_all_no_ctx(void);
  92 static void dss_clk_disable_all_no_ctx(void);
  93 static void dss_clk_enable_no_ctx(enum dss_clock clks);
  94 static void dss_clk_disable_no_ctx(enum dss_clock clks);
  95
  96 static int _omap_dss_wait_reset(void);
  97
  98 static inline void dss_write_reg(const struct dss_reg idx, u32 val)
  99 {
 100         __raw_writel(val, dss.base + idx.idx);
 101 }
 102
 103 static inline u32 dss_read_reg(const struct dss_reg idx)
 104 {
 105         return __raw_readl(dss.base + idx.idx);
 106 }
 107
 108 #define SR(reg) \
 109         dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg)
 110 #define RR(reg) \
 111         dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)])
 112
 113 void dss_save_context(void)
 114 {
 115         if (cpu_is_omap24xx())
 116                 return;
 117
 118         SR(SYSCONFIG);
 119         SR(CONTROL);
 120
 121         if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
 122                         OMAP_DISPLAY_TYPE_SDI) {
 123                 SR(SDI_CONTROL);
 124                 SR(PLL_CONTROL);
 125         }
 126 }
 127
 128 void dss_restore_context(void)
 129 {
 130         if (_omap_dss_wait_reset())
 131                 DSSERR("DSS not coming out of reset after sleep\n");
 132
 133         RR(SYSCONFIG);
 134         RR(CONTROL);
 135
 136         if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
 137                         OMAP_DISPLAY_TYPE_SDI) {
 138                 RR(SDI_CONTROL);
 139                 RR(PLL_CONTROL);
 140         }
 141 }
 142
 143 #undef SR
 144 #undef RR
 145
 146 void dss_sdi_init(u8 datapairs)
 147 {
 148         u32 l;
 149
 150         BUG_ON(datapairs > 3 || datapairs < 1);
 151
 152         l = dss_read_reg(DSS_SDI_CONTROL);
 153         l = FLD_MOD(l, 0xf, 19, 15);            /* SDI_PDIV */
 154         l = FLD_MOD(l, datapairs-1, 3, 2);      /* SDI_PRSEL */
 155         l = FLD_MOD(l, 2, 1, 0);                /* SDI_BWSEL */
 156         dss_write_reg(DSS_SDI_CONTROL, l);
 157
 158         l = dss_read_reg(DSS_PLL_CONTROL);
 159         l = FLD_MOD(l, 0x7, 25, 22);    /* SDI_PLL_FREQSEL */
 160         l = FLD_MOD(l, 0xb, 16, 11);    /* SDI_PLL_REGN */
 161         l = FLD_MOD(l, 0xb4, 10, 1);    /* SDI_PLL_REGM */
 162         dss_write_reg(DSS_PLL_CONTROL, l);
 163 }
 164
 165 int dss_sdi_enable(void)
 166 {
 167         unsigned long timeout;
 168
 169         dispc_pck_free_enable(1);
 170
 171         /* Reset SDI PLL */
 172         REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */
 173         udelay(1);      /* wait 2x PCLK */
 174
 175         /* Lock SDI PLL */
 176         REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */
 177
 178         /* Waiting for PLL lock request to complete */
 179         timeout = jiffies + msecs_to_jiffies(500);
 180         while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6)) {
 181                 if (time_after_eq(jiffies, timeout)) {
 182                         DSSERR("PLL lock request timed out\n");
 183                         goto err1;
 184                 }
 185         }
 186
 187         /* Clearing PLL_GO bit */
 188         REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28);
 189
 190         /* Waiting for PLL to lock */
 191         timeout = jiffies + msecs_to_jiffies(500);
 192         while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5))) {
 193                 if (time_after_eq(jiffies, timeout)) {
 194                         DSSERR("PLL lock timed out\n");
 195                         goto err1;
 196                 }
 197         }
 198
 199         dispc_lcd_enable_signal(1);
 200
 201         /* Waiting for SDI reset to complete */
 202         timeout = jiffies + msecs_to_jiffies(500);
 203         while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 2))) {
 204                 if (time_after_eq(jiffies, timeout)) {
 205                         DSSERR("SDI reset timed out\n");
 206                         goto err2;
 207                 }
 208         }
 209
 210         return 0;
 211
 212  err2:
 213         dispc_lcd_enable_signal(0);
 214  err1:
 215         /* Reset SDI PLL */
 216         REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
 217
 218         dispc_pck_free_enable(0);
 219
 220         return -ETIMEDOUT;
 221 }
 222
 223 void dss_sdi_disable(void)
 224 {
 225         dispc_lcd_enable_signal(0);
 226
 227         dispc_pck_free_enable(0);
 228
 229         /* Reset SDI PLL */
 230         REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
 231 }
 232
 233 const char *dss_get_generic_clk_source_name(enum dss_clk_source clk_src)
 234 {
 235         return dss_generic_clk_source_names[clk_src];
 236 }
 237
 238 void dss_dump_clocks(struct seq_file *s)
 239 {
 240         unsigned long dpll4_ck_rate;
 241         unsigned long dpll4_m4_ck_rate;
 242         const char *fclk_name, *fclk_real_name;
 243         unsigned long fclk_rate;
 244
 245         dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
 246
 247         seq_printf(s, "- DSS -\n");
 248
 249         fclk_name = dss_get_generic_clk_source_name(DSS_CLK_SRC_FCK);
 250         fclk_real_name = dss_feat_get_clk_source_name(DSS_CLK_SRC_FCK);
 251         fclk_rate = dss_clk_get_rate(DSS_CLK_FCK);
 252
 253         if (dss.dpll4_m4_ck) {
 254                 dpll4_ck_rate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
 255                 dpll4_m4_ck_rate = clk_get_rate(dss.dpll4_m4_ck);
 256
 257                 seq_printf(s, "dpll4_ck %lu\n", dpll4_ck_rate);
 258
 259                 if (cpu_is_omap3630() || cpu_is_omap44xx())
 260                         seq_printf(s, "%s (%s) = %lu / %lu  = %lu\n",
 261                                         fclk_name, fclk_real_name,
 262                                         dpll4_ck_rate,
 263                                         dpll4_ck_rate / dpll4_m4_ck_rate,
 264                                         fclk_rate);
 265                 else
 266                         seq_printf(s, "%s (%s) = %lu / %lu * 2 = %lu\n",
 267                                         fclk_name, fclk_real_name,
 268                                         dpll4_ck_rate,
 269                                         dpll4_ck_rate / dpll4_m4_ck_rate,
 270                                         fclk_rate);
 271         } else {
 272                 seq_printf(s, "%s (%s) = %lu\n",
 273                                 fclk_name, fclk_real_name,
 274                                 fclk_rate);
 275         }
 276
 277         dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
 278 }
 279
 280 void dss_dump_regs(struct seq_file *s)
 281 {
 282 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r))
 283
 284         dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
 285
 286         DUMPREG(DSS_REVISION);
 287         DUMPREG(DSS_SYSCONFIG);
 288         DUMPREG(DSS_SYSSTATUS);
 289         DUMPREG(DSS_IRQSTATUS);
 290         DUMPREG(DSS_CONTROL);
 291
 292         if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
 293                         OMAP_DISPLAY_TYPE_SDI) {
 294                 DUMPREG(DSS_SDI_CONTROL);
 295                 DUMPREG(DSS_PLL_CONTROL);
 296                 DUMPREG(DSS_SDI_STATUS);
 297         }
 298
 299         dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
 300 #undef DUMPREG
 301 }
 302
 303 void dss_select_dispc_clk_source(enum dss_clk_source clk_src)
 304 {
 305         int b;
 306         u8 start, end;
 307
 308         switch (clk_src) {
 309         case DSS_CLK_SRC_FCK:
 310                 b = 0;
 311                 break;
 312         case DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
 313                 b = 1;
 314                 dsi_wait_pll_hsdiv_dispc_active();
 315                 break;
 316         default:
 317                 BUG();
 318         }
 319
 320         dss_feat_get_reg_field(FEAT_REG_DISPC_CLK_SWITCH, &start, &end);
 321
 322         REG_FLD_MOD(DSS_CONTROL, b, start, end);        /* DISPC_CLK_SWITCH */
 323
 324         dss.dispc_clk_source = clk_src;
 325 }
 326
 327 void dss_select_dsi_clk_source(enum dss_clk_source clk_src)
 328 {
 329         int b;
 330
 331         switch (clk_src) {
 332         case DSS_CLK_SRC_FCK:
 333                 b = 0;
 334                 break;
 335         case DSS_CLK_SRC_DSI_PLL_HSDIV_DSI:
 336                 b = 1;
 337                 dsi_wait_pll_hsdiv_dsi_active();
 338                 break;
 339         default:
 340                 BUG();
 341         }
 342
 343         REG_FLD_MOD(DSS_CONTROL, b, 1, 1);      /* DSI_CLK_SWITCH */
 344
 345         dss.dsi_clk_source = clk_src;
 346 }
 347
 348 void dss_select_lcd_clk_source(enum omap_channel channel,
 349                 enum dss_clk_source clk_src)
 350 {
 351         int b, ix, pos;
 352
 353         if (!dss_has_feature(FEAT_LCD_CLK_SRC))
 354                 return;
 355
 356         switch (clk_src) {
 357         case DSS_CLK_SRC_FCK:
 358                 b = 0;
 359                 break;
 360         case DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
 361                 BUG_ON(channel != OMAP_DSS_CHANNEL_LCD);
 362                 b = 1;
 363                 dsi_wait_pll_hsdiv_dispc_active();
 364                 break;
 365         default:
 366                 BUG();
 367         }
 368
 369         pos = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 12;
 370         REG_FLD_MOD(DSS_CONTROL, b, pos, pos);  /* LCDx_CLK_SWITCH */
 371
 372         ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 1;
 373         dss.lcd_clk_source[ix] = clk_src;
 374 }
 375
 376 enum dss_clk_source dss_get_dispc_clk_source(void)
 377 {
 378         return dss.dispc_clk_source;
 379 }
 380
 381 enum dss_clk_source dss_get_dsi_clk_source(void)
 382 {
 383         return dss.dsi_clk_source;
 384 }
 385
 386 enum dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel)
 387 {
 388         int ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 1;
 389         return dss.lcd_clk_source[ix];
 390 }
 391
 392 /* calculate clock rates using dividers in cinfo */
 393 int dss_calc_clock_rates(struct dss_clock_info *cinfo)
 394 {
 395         if (dss.dpll4_m4_ck) {
 396                 unsigned long prate;
 397                 u16 fck_div_max = 16;
 398
 399                 if (cpu_is_omap3630() || cpu_is_omap44xx())
 400                         fck_div_max = 32;
 401
 402                 if (cinfo->fck_div > fck_div_max || cinfo->fck_div == 0)
 403                         return -EINVAL;
 404
 405                 prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
 406
 407                 cinfo->fck = prate / cinfo->fck_div;
 408         } else {
 409                 if (cinfo->fck_div != 0)
 410                         return -EINVAL;
 411                 cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK);
 412         }
 413
 414         return 0;
 415 }
 416
 417 int dss_set_clock_div(struct dss_clock_info *cinfo)
 418 {
 419         if (dss.dpll4_m4_ck) {
 420                 unsigned long prate;
 421                 int r;
 422
 423                 prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
 424                 DSSDBG("dpll4_m4 = %ld\n", prate);
 425
 426                 r = clk_set_rate(dss.dpll4_m4_ck, prate / cinfo->fck_div);
 427                 if (r)
 428                         return r;
 429         } else {
 430                 if (cinfo->fck_div != 0)
 431                         return -EINVAL;
 432         }
 433
 434         DSSDBG("fck = %ld (%d)\n", cinfo->fck, cinfo->fck_div);
 435
 436         return 0;
 437 }
 438
 439 int dss_get_clock_div(struct dss_clock_info *cinfo)
 440 {
 441         cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK);
 442
 443         if (dss.dpll4_m4_ck) {
 444                 unsigned long prate;
 445
 446                 prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
 447
 448                 if (cpu_is_omap3630() || cpu_is_omap44xx())
 449                         cinfo->fck_div = prate / (cinfo->fck);
 450                 else
 451                         cinfo->fck_div = prate / (cinfo->fck / 2);
 452         } else {
 453                 cinfo->fck_div = 0;
 454         }
 455
 456         return 0;
 457 }
 458
 459 unsigned long dss_get_dpll4_rate(void)
 460 {
 461         if (dss.dpll4_m4_ck)
 462                 return clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
 463         else
 464                 return 0;
 465 }
 466
 467 int dss_calc_clock_div(bool is_tft, unsigned long req_pck,
 468                 struct dss_clock_info *dss_cinfo,
 469                 struct dispc_clock_info *dispc_cinfo)
 470 {
 471         unsigned long prate;
 472         struct dss_clock_info best_dss;
 473         struct dispc_clock_info best_dispc;
 474
 475         unsigned long fck, max_dss_fck;
 476
 477         u16 fck_div, fck_div_max = 16;
 478
 479         int match = 0;
 480         int min_fck_per_pck;
 481
 482         prate = dss_get_dpll4_rate();
 483
 484         max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
 485
 486         fck = dss_clk_get_rate(DSS_CLK_FCK);
 487         if (req_pck == dss.cache_req_pck &&
 488                         ((cpu_is_omap34xx() && prate == dss.cache_prate) ||
 489                          dss.cache_dss_cinfo.fck == fck)) {
 490                 DSSDBG("dispc clock info found from cache.\n");
 491                 *dss_cinfo = dss.cache_dss_cinfo;
 492                 *dispc_cinfo = dss.cache_dispc_cinfo;
 493                 return 0;
 494         }
 495
 496         min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
 497
 498         if (min_fck_per_pck &&
 499                 req_pck * min_fck_per_pck > max_dss_fck) {
 500                 DSSERR("Requested pixel clock not possible with the current "
 501                                 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
 502                                 "the constraint off.\n");
 503                 min_fck_per_pck = 0;
 504         }
 505
 506 retry:
 507         memset(&best_dss, 0, sizeof(best_dss));
 508         memset(&best_dispc, 0, sizeof(best_dispc));
 509
 510         if (dss.dpll4_m4_ck == NULL) {
 511                 struct dispc_clock_info cur_dispc;
 512                 /* XXX can we change the clock on omap2? */
 513                 fck = dss_clk_get_rate(DSS_CLK_FCK);
 514                 fck_div = 1;
 515
 516                 dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc);
 517                 match = 1;
 518
 519                 best_dss.fck = fck;
 520                 best_dss.fck_div = fck_div;
 521
 522                 best_dispc = cur_dispc;
 523
 524                 goto found;
 525         } else {
 526                 if (cpu_is_omap3630() || cpu_is_omap44xx())
 527                         fck_div_max = 32;
 528
 529                 for (fck_div = fck_div_max; fck_div > 0; --fck_div) {
 530                         struct dispc_clock_info cur_dispc;
 531
 532                         if (fck_div_max == 32)
 533                                 fck = prate / fck_div;
 534                         else
 535                                 fck = prate / fck_div * 2;
 536
 537                         if (fck > max_dss_fck)
 538                                 continue;
 539
 540                         if (min_fck_per_pck &&
 541                                         fck < req_pck * min_fck_per_pck)
 542                                 continue;
 543
 544                         match = 1;
 545
 546                         dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc);
 547
 548                         if (abs(cur_dispc.pck - req_pck) <
 549                                         abs(best_dispc.pck - req_pck)) {
 550
 551                                 best_dss.fck = fck;
 552                                 best_dss.fck_div = fck_div;
 553
 554                                 best_dispc = cur_dispc;
 555
 556                                 if (cur_dispc.pck == req_pck)
 557                                         goto found;
 558                         }
 559                 }
 560         }
 561
 562 found:
 563         if (!match) {
 564                 if (min_fck_per_pck) {
 565                         DSSERR("Could not find suitable clock settings.\n"
 566                                         "Turning FCK/PCK constraint off and"
 567                                         "trying again.\n");
 568                         min_fck_per_pck = 0;
 569                         goto retry;
 570                 }
 571
 572                 DSSERR("Could not find suitable clock settings.\n");
 573
 574                 return -EINVAL;
 575         }
 576
 577         if (dss_cinfo)
 578                 *dss_cinfo = best_dss;
 579         if (dispc_cinfo)
 580                 *dispc_cinfo = best_dispc;
 581
 582         dss.cache_req_pck = req_pck;
 583         dss.cache_prate = prate;
 584         dss.cache_dss_cinfo = best_dss;
 585         dss.cache_dispc_cinfo = best_dispc;
 586
 587         return 0;
 588 }
 589
 590 static int _omap_dss_wait_reset(void)
 591 {
 592         int t = 0;
 593
 594         while (REG_GET(DSS_SYSSTATUS, 0, 0) == 0) {
 595                 if (++t > 1000) {
 596                         DSSERR("soft reset failed\n");
 597                         return -ENODEV;
 598                 }
 599                 udelay(1);
 600         }
 601
 602         return 0;
 603 }
 604
 605 static int _omap_dss_reset(void)
 606 {
 607         /* Soft reset */
 608         REG_FLD_MOD(DSS_SYSCONFIG, 1, 1, 1);
 609         return _omap_dss_wait_reset();
 610 }
 611
 612 void dss_set_venc_output(enum omap_dss_venc_type type)
 613 {
 614         int l = 0;
 615
 616         if (type == OMAP_DSS_VENC_TYPE_COMPOSITE)
 617                 l = 0;
 618         else if (type == OMAP_DSS_VENC_TYPE_SVIDEO)
 619                 l = 1;
 620         else
 621                 BUG();
 622
 623         /* venc out selection. 0 = comp, 1 = svideo */
 624         REG_FLD_MOD(DSS_CONTROL, l, 6, 6);
 625 }
 626
 627 void dss_set_dac_pwrdn_bgz(bool enable)
 628 {
 629         REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */
 630 }
 631
 632 void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select hdmi)
 633 {
 634         REG_FLD_MOD(DSS_CONTROL, hdmi, 15, 15); /* VENC_HDMI_SWITCH */
 635 }
 636
 637 static int dss_init(void)
 638 {
 639         int r;
 640         u32 rev;
 641         struct resource *dss_mem;
 642         struct clk *dpll4_m4_ck;
 643
 644         dss_mem = platform_get_resource(dss.pdev, IORESOURCE_MEM, 0);
 645         if (!dss_mem) {
 646                 DSSERR("can't get IORESOURCE_MEM DSS\n");
 647                 r = -EINVAL;
 648                 goto fail0;
 649         }
 650         dss.base = ioremap(dss_mem->start, resource_size(dss_mem));
 651         if (!dss.base) {
 652                 DSSERR("can't ioremap DSS\n");
 653                 r = -ENOMEM;
 654                 goto fail0;
 655         }
 656
 657         /* disable LCD and DIGIT output. This seems to fix the synclost
 658          * problem that we get, if the bootloader starts the DSS and
 659          * the kernel resets it */
 660         omap_writel(omap_readl(0x48050440) & ~0x3, 0x48050440);
 661
 662         /* We need to wait here a bit, otherwise we sometimes start to
 663          * get synclost errors, and after that only power cycle will
 664          * restore DSS functionality. I have no idea why this happens.
 665          * And we have to wait _before_ resetting the DSS, but after
 666          * enabling clocks.
 667          */
 668         msleep(50);
 669
 670         _omap_dss_reset();
 671
 672         /* autoidle */
 673         REG_FLD_MOD(DSS_SYSCONFIG, 1, 0, 0);
 674
 675         /* Select DPLL */
 676         REG_FLD_MOD(DSS_CONTROL, 0, 0, 0);
 677
 678 #ifdef CONFIG_OMAP2_DSS_VENC
 679         REG_FLD_MOD(DSS_CONTROL, 1, 4, 4);      /* venc dac demen */
 680         REG_FLD_MOD(DSS_CONTROL, 1, 3, 3);      /* venc clock 4x enable */
 681         REG_FLD_MOD(DSS_CONTROL, 0, 2, 2);      /* venc clock mode = normal */
 682 #endif
 683         if (cpu_is_omap34xx()) {
 684                 dpll4_m4_ck = clk_get(NULL, "dpll4_m4_ck");
 685                 if (IS_ERR(dpll4_m4_ck)) {
 686                         DSSERR("Failed to get dpll4_m4_ck\n");
 687                         r = PTR_ERR(dpll4_m4_ck);
 688                         goto fail1;
 689                 }
 690         } else if (cpu_is_omap44xx()) {
 691                 dpll4_m4_ck = clk_get(NULL, "dpll_per_m5x2_ck");
 692                 if (IS_ERR(dpll4_m4_ck)) {
 693                         DSSERR("Failed to get dpll4_m4_ck\n");
 694                         r = PTR_ERR(dpll4_m4_ck);
 695                         goto fail1;
 696                 }
 697         } else { /* omap24xx */
 698                 dpll4_m4_ck = NULL;
 699         }
 700
 701         dss.dpll4_m4_ck = dpll4_m4_ck;
 702
 703         dss.dsi_clk_source = DSS_CLK_SRC_FCK;
 704         dss.dispc_clk_source = DSS_CLK_SRC_FCK;
 705         dss.lcd_clk_source[0] = DSS_CLK_SRC_FCK;
 706         dss.lcd_clk_source[1] = DSS_CLK_SRC_FCK;
 707
 708         dss_save_context();
 709
 710         rev = dss_read_reg(DSS_REVISION);
 711         printk(KERN_INFO "OMAP DSS rev %d.%d\n",
 712                         FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
 713
 714         return 0;
 715
 716 fail1:
 717         iounmap(dss.base);
 718 fail0:
 719         return r;
 720 }
 721
 722 static void dss_exit(void)
 723 {
 724         if (dss.dpll4_m4_ck)
 725                 clk_put(dss.dpll4_m4_ck);
 726
 727         iounmap(dss.base);
 728 }
 729
 730 /* CONTEXT */
 731 static int dss_get_ctx_id(void)
 732 {
 733         struct omap_display_platform_data *pdata = dss.pdev->dev.platform_data;
 734         int r;
 735
 736         if (!pdata->board_data->get_last_off_on_transaction_id)
 737                 return 0;
 738         r = pdata->board_data->get_last_off_on_transaction_id(&dss.pdev->dev);
 739         if (r < 0) {
 740                 dev_err(&dss.pdev->dev, "getting transaction ID failed, "
 741                                 "will force context restore\n");
 742                 r = -1;
 743         }
 744         return r;
 745 }
 746
 747 int dss_need_ctx_restore(void)
 748 {
 749         int id = dss_get_ctx_id();
 750
 751         if (id < 0 || id != dss.ctx_id) {
 752                 DSSDBG("ctx id %d -> id %d\n",
 753                                 dss.ctx_id, id);
 754                 dss.ctx_id = id;
 755                 return 1;
 756         } else {
 757                 return 0;
 758         }
 759 }
 760
 761 static void save_all_ctx(void)
 762 {
 763         DSSDBG("save context\n");
 764
 765         dss_clk_enable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK);
 766
 767         dss_save_context();
 768         dispc_save_context();
 769 #ifdef CONFIG_OMAP2_DSS_DSI
 770         dsi_save_context();
 771 #endif
 772
 773         dss_clk_disable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK);
 774 }
 775
 776 static void restore_all_ctx(void)
 777 {
 778         DSSDBG("restore context\n");
 779
 780         dss_clk_enable_all_no_ctx();
 781
 782         dss_restore_context();
 783         dispc_restore_context();
 784 #ifdef CONFIG_OMAP2_DSS_DSI
 785         dsi_restore_context();
 786 #endif
 787
 788         dss_clk_disable_all_no_ctx();
 789 }
 790
 791 static int dss_get_clock(struct clk **clock, const char *clk_name)
 792 {
 793         struct clk *clk;
 794
 795         clk = clk_get(&dss.pdev->dev, clk_name);
 796
 797         if (IS_ERR(clk)) {
 798                 DSSERR("can't get clock %s", clk_name);
 799                 return PTR_ERR(clk);
 800         }
 801
 802         *clock = clk;
 803
 804         DSSDBG("clk %s, rate %ld\n", clk_name, clk_get_rate(clk));
 805
 806         return 0;
 807 }
 808
 809 static int dss_get_clocks(void)
 810 {
 811         int r;
 812         struct omap_display_platform_data *pdata = dss.pdev->dev.platform_data;
 813
 814         dss.dss_ick = NULL;
 815         dss.dss_fck = NULL;
 816         dss.dss_sys_clk = NULL;
 817         dss.dss_tv_fck = NULL;
 818         dss.dss_video_fck = NULL;
 819
 820         r = dss_get_clock(&dss.dss_ick, "ick");
 821         if (r)
 822                 goto err;
 823
 824         r = dss_get_clock(&dss.dss_fck, "fck");
 825         if (r)
 826                 goto err;
 827
 828         if (!pdata->opt_clock_available) {
 829                 r = -ENODEV;
 830                 goto err;
 831         }
 832
 833         if (pdata->opt_clock_available("sys_clk")) {
 834                 r = dss_get_clock(&dss.dss_sys_clk, "sys_clk");
 835                 if (r)
 836                         goto err;
 837         }
 838
 839         if (pdata->opt_clock_available("tv_clk")) {
 840                 r = dss_get_clock(&dss.dss_tv_fck, "tv_clk");
 841                 if (r)
 842                         goto err;
 843         }
 844
 845         if (pdata->opt_clock_available("video_clk")) {
 846                 r = dss_get_clock(&dss.dss_video_fck, "video_clk");
 847                 if (r)
 848                         goto err;
 849         }
 850
 851         return 0;
 852
 853 err:
 854         if (dss.dss_ick)
 855                 clk_put(dss.dss_ick);
 856         if (dss.dss_fck)
 857                 clk_put(dss.dss_fck);
 858         if (dss.dss_sys_clk)
 859                 clk_put(dss.dss_sys_clk);
 860         if (dss.dss_tv_fck)
 861                 clk_put(dss.dss_tv_fck);
 862         if (dss.dss_video_fck)
 863                 clk_put(dss.dss_video_fck);
 864
 865         return r;
 866 }
 867
 868 static void dss_put_clocks(void)
 869 {
 870         if (dss.dss_video_fck)
 871                 clk_put(dss.dss_video_fck);
 872         if (dss.dss_tv_fck)
 873                 clk_put(dss.dss_tv_fck);
 874         if (dss.dss_sys_clk)
 875                 clk_put(dss.dss_sys_clk);
 876         clk_put(dss.dss_fck);
 877         clk_put(dss.dss_ick);
 878 }
 879
 880 unsigned long dss_clk_get_rate(enum dss_clock clk)
 881 {
 882         switch (clk) {
 883         case DSS_CLK_ICK:
 884                 return clk_get_rate(dss.dss_ick);
 885         case DSS_CLK_FCK:
 886                 return clk_get_rate(dss.dss_fck);
 887         case DSS_CLK_SYSCK:
 888                 return clk_get_rate(dss.dss_sys_clk);
 889         case DSS_CLK_TVFCK:
 890                 return clk_get_rate(dss.dss_tv_fck);
 891         case DSS_CLK_VIDFCK:
 892                 return clk_get_rate(dss.dss_video_fck);
 893         }
 894
 895         BUG();
 896         return 0;
 897 }
 898
 899 static unsigned count_clk_bits(enum dss_clock clks)
 900 {
 901         unsigned num_clks = 0;
 902
 903         if (clks & DSS_CLK_ICK)
 904                 ++num_clks;
 905         if (clks & DSS_CLK_FCK)
 906                 ++num_clks;
 907         if (clks & DSS_CLK_SYSCK)
 908                 ++num_clks;
 909         if (clks & DSS_CLK_TVFCK)
 910                 ++num_clks;
 911         if (clks & DSS_CLK_VIDFCK)
 912                 ++num_clks;
 913
 914         return num_clks;
 915 }
 916
 917 static void dss_clk_enable_no_ctx(enum dss_clock clks)
 918 {
 919         unsigned num_clks = count_clk_bits(clks);
 920
 921         if (clks & DSS_CLK_ICK)
 922                 clk_enable(dss.dss_ick);
 923         if (clks & DSS_CLK_FCK)
 924                 clk_enable(dss.dss_fck);
 925         if ((clks & DSS_CLK_SYSCK) && dss.dss_sys_clk)
 926                 clk_enable(dss.dss_sys_clk);
 927         if ((clks & DSS_CLK_TVFCK) && dss.dss_tv_fck)
 928                 clk_enable(dss.dss_tv_fck);
 929         if ((clks & DSS_CLK_VIDFCK) && dss.dss_video_fck)
 930                 clk_enable(dss.dss_video_fck);
 931
 932         dss.num_clks_enabled += num_clks;
 933 }
 934
 935 void dss_clk_enable(enum dss_clock clks)
 936 {
 937         bool check_ctx = dss.num_clks_enabled == 0;
 938
 939         dss_clk_enable_no_ctx(clks);
 940
 941         /*
 942          * HACK: On omap4 the registers may not be accessible right after
 943          * enabling the clocks. At some point this will be handled by
 944          * pm_runtime, but for the time begin this should make things work.
 945          */
 946         if (cpu_is_omap44xx() && check_ctx)
 947                 udelay(10);
 948
 949         if (check_ctx && cpu_is_omap34xx() && dss_need_ctx_restore())
 950                 restore_all_ctx();
 951 }
 952
 953 static void dss_clk_disable_no_ctx(enum dss_clock clks)
 954 {
 955         unsigned num_clks = count_clk_bits(clks);
 956
 957         if (clks & DSS_CLK_ICK)
 958                 clk_disable(dss.dss_ick);
 959         if (clks & DSS_CLK_FCK)
 960                 clk_disable(dss.dss_fck);
 961         if ((clks & DSS_CLK_SYSCK) && dss.dss_sys_clk)
 962                 clk_disable(dss.dss_sys_clk);
 963         if ((clks & DSS_CLK_TVFCK) && dss.dss_tv_fck)
 964                 clk_disable(dss.dss_tv_fck);
 965         if ((clks & DSS_CLK_VIDFCK) && dss.dss_video_fck)
 966                 clk_disable(dss.dss_video_fck);
 967
 968         dss.num_clks_enabled -= num_clks;
 969 }
 970
 971 void dss_clk_disable(enum dss_clock clks)
 972 {
 973         if (cpu_is_omap34xx()) {
 974                 unsigned num_clks = count_clk_bits(clks);
 975
 976                 BUG_ON(dss.num_clks_enabled < num_clks);
 977
 978                 if (dss.num_clks_enabled == num_clks)
 979                         save_all_ctx();
 980         }
 981
 982         dss_clk_disable_no_ctx(clks);
 983 }
 984
 985 static void dss_clk_enable_all_no_ctx(void)
 986 {
 987         enum dss_clock clks;
 988
 989         clks = DSS_CLK_ICK | DSS_CLK_FCK | DSS_CLK_SYSCK | DSS_CLK_TVFCK;
 990         if (cpu_is_omap34xx())
 991                 clks |= DSS_CLK_VIDFCK;
 992         dss_clk_enable_no_ctx(clks);
 993 }
 994
 995 static void dss_clk_disable_all_no_ctx(void)
 996 {
 997         enum dss_clock clks;
 998
 999         clks = DSS_CLK_ICK | DSS_CLK_FCK | DSS_CLK_SYSCK | DSS_CLK_TVFCK;
1000         if (cpu_is_omap34xx())
1001                 clks |= DSS_CLK_VIDFCK;
1002         dss_clk_disable_no_ctx(clks);
1003 }
1004
1005 #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
1006 /* CLOCKS */
1007 static void core_dump_clocks(struct seq_file *s)
1008 {
1009         int i;
1010         struct clk *clocks[5] = {
1011                 dss.dss_ick,
1012                 dss.dss_fck,
1013                 dss.dss_sys_clk,
1014                 dss.dss_tv_fck,
1015                 dss.dss_video_fck
1016         };
1017
1018         seq_printf(s, "- CORE -\n");
1019
1020         seq_printf(s, "internal clk count\t\t%u\n", dss.num_clks_enabled);
1021
1022         for (i = 0; i < 5; i++) {
1023                 if (!clocks[i])
1024                         continue;
1025                 seq_printf(s, "%-15s\t%lu\t%d\n",
1026                                 clocks[i]->name,
1027                                 clk_get_rate(clocks[i]),
1028                                 clocks[i]->usecount);
1029         }
1030 }
1031 #endif /* defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) */
1032
1033 /* DEBUGFS */
1034 #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
1035 void dss_debug_dump_clocks(struct seq_file *s)
1036 {
1037         core_dump_clocks(s);
1038         dss_dump_clocks(s);
1039         dispc_dump_clocks(s);
1040 #ifdef CONFIG_OMAP2_DSS_DSI
1041         dsi_dump_clocks(s);
1042 #endif
1043 }
1044 #endif
1045
1046
1047 /* DSS HW IP initialisation */
1048 static int omap_dsshw_probe(struct platform_device *pdev)
1049 {
1050         int r;
1051
1052         dss.pdev = pdev;
1053
1054         r = dss_get_clocks();
1055         if (r)
1056                 goto err_clocks;
1057
1058         dss_clk_enable_all_no_ctx();
1059
1060         dss.ctx_id = dss_get_ctx_id();
1061         DSSDBG("initial ctx id %u\n", dss.ctx_id);
1062
1063         r = dss_init();
1064         if (r) {
1065                 DSSERR("Failed to initialize DSS\n");
1066                 goto err_dss;
1067         }
1068
1069         r = dpi_init();
1070         if (r) {
1071                 DSSERR("Failed to initialize DPI\n");
1072                 goto err_dpi;
1073         }
1074
1075         r = sdi_init();
1076         if (r) {
1077                 DSSERR("Failed to initialize SDI\n");
1078                 goto err_sdi;
1079         }
1080
1081         dss_clk_disable_all_no_ctx();
1082         return 0;
1083 err_sdi:
1084         dpi_exit();
1085 err_dpi:
1086         dss_exit();
1087 err_dss:
1088         dss_clk_disable_all_no_ctx();
1089         dss_put_clocks();
1090 err_clocks:
1091         return r;
1092 }
1093
1094 static int omap_dsshw_remove(struct platform_device *pdev)
1095 {
1096
1097         dss_exit();
1098
1099         /*
1100          * As part of hwmod changes, DSS is not the only controller of dss
1101          * clocks; hwmod framework itself will also enable clocks during hwmod
1102          * init for dss, and autoidle is set in h/w for DSS. Hence, there's no
1103          * need to disable clocks if their usecounts > 1.
1104          */
1105         WARN_ON(dss.num_clks_enabled > 0);
1106
1107         dss_put_clocks();
1108         return 0;
1109 }
1110
1111 static struct platform_driver omap_dsshw_driver = {
1112         .probe          = omap_dsshw_probe,
1113         .remove         = omap_dsshw_remove,
1114         .driver         = {
1115                 .name   = "omapdss_dss",
1116                 .owner  = THIS_MODULE,
1117         },
1118 };
1119
1120 int dss_init_platform_driver(void)
1121 {
1122         return platform_driver_register(&omap_dsshw_driver);
1123 }
1124
1125 void dss_uninit_platform_driver(void)
1126 {
1127         return platform_driver_unregister(&omap_dsshw_driver);
1128 }