drivers/video/omap2/dss/dss.h

   1 /*
   2  * linux/drivers/video/omap2/dss/dss.h
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #ifndef __OMAP2_DSS_H
  24 #define __OMAP2_DSS_H
  25
  26 #ifdef CONFIG_OMAP2_DSS_DEBUG_SUPPORT
  27 #define DEBUG
  28 #endif
  29
  30 #ifdef DEBUG
  31 extern unsigned int dss_debug;
  32 #ifdef DSS_SUBSYS_NAME
  33 #define DSSDBG(format, ...) \
  34         if (dss_debug) \
  35                 printk(KERN_DEBUG "omapdss " DSS_SUBSYS_NAME ": " format, \
  36                 ## __VA_ARGS__)
  37 #else
  38 #define DSSDBG(format, ...) \
  39         if (dss_debug) \
  40                 printk(KERN_DEBUG "omapdss: " format, ## __VA_ARGS__)
  41 #endif
  42
  43 #ifdef DSS_SUBSYS_NAME
  44 #define DSSDBGF(format, ...) \
  45         if (dss_debug) \
  46                 printk(KERN_DEBUG "omapdss " DSS_SUBSYS_NAME \
  47                                 ": %s(" format ")\n", \
  48                                 __func__, \
  49                                 ## __VA_ARGS__)
  50 #else
  51 #define DSSDBGF(format, ...) \
  52         if (dss_debug) \
  53                 printk(KERN_DEBUG "omapdss: " \
  54                                 ": %s(" format ")\n", \
  55                                 __func__, \
  56                                 ## __VA_ARGS__)
  57 #endif
  58
  59 #else /* DEBUG */
  60 #define DSSDBG(format, ...)
  61 #define DSSDBGF(format, ...)
  62 #endif
  63
  64
  65 #ifdef DSS_SUBSYS_NAME
  66 #define DSSERR(format, ...) \
  67         printk(KERN_ERR "omapdss " DSS_SUBSYS_NAME " error: " format, \
  68         ## __VA_ARGS__)
  69 #else
  70 #define DSSERR(format, ...) \
  71         printk(KERN_ERR "omapdss error: " format, ## __VA_ARGS__)
  72 #endif
  73
  74 #ifdef DSS_SUBSYS_NAME
  75 #define DSSINFO(format, ...) \
  76         printk(KERN_INFO "omapdss " DSS_SUBSYS_NAME ": " format, \
  77         ## __VA_ARGS__)
  78 #else
  79 #define DSSINFO(format, ...) \
  80         printk(KERN_INFO "omapdss: " format, ## __VA_ARGS__)
  81 #endif
  82
  83 #ifdef DSS_SUBSYS_NAME
  84 #define DSSWARN(format, ...) \
  85         printk(KERN_WARNING "omapdss " DSS_SUBSYS_NAME ": " format, \
  86         ## __VA_ARGS__)
  87 #else
  88 #define DSSWARN(format, ...) \
  89         printk(KERN_WARNING "omapdss: " format, ## __VA_ARGS__)
  90 #endif
  91
  92 /* OMAP TRM gives bitfields as start:end, where start is the higher bit
  93    number. For example 7:0 */
  94 #define FLD_MASK(start, end)    (((1 << ((start) - (end) + 1)) - 1) << (end))
  95 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
  96 #define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
  97 #define FLD_MOD(orig, val, start, end) \
  98         (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
  99
 100 enum omap_parallel_interface_mode {
 101         OMAP_DSS_PARALLELMODE_BYPASS,           /* MIPI DPI */
 102         OMAP_DSS_PARALLELMODE_RFBI,             /* MIPI DBI */
 103         OMAP_DSS_PARALLELMODE_DSI,
 104 };
 105
 106 enum dss_clock {
 107         DSS_CLK_ICK     = 1 << 0,       /* DSS_L3_ICLK and DSS_L4_ICLK */
 108         DSS_CLK_FCK     = 1 << 1,       /* DSS1_ALWON_FCLK */
 109         DSS_CLK_SYSCK   = 1 << 2,       /* DSS2_ALWON_FCLK */
 110         DSS_CLK_TVFCK   = 1 << 3,       /* DSS_TV_FCLK */
 111         DSS_CLK_VIDFCK  = 1 << 4,       /* DSS_96M_FCLK*/
 112 };
 113
 114 enum dss_hdmi_venc_clk_source_select {
 115         DSS_VENC_TV_CLK = 0,
 116         DSS_HDMI_M_PCLK = 1,
 117 };
 118
 119 struct dss_clock_info {
 120         /* rates that we get with dividers below */
 121         unsigned long fck;
 122
 123         /* dividers */
 124         u16 fck_div;
 125 };
 126
 127 struct dispc_clock_info {
 128         /* rates that we get with dividers below */
 129         unsigned long lck;
 130         unsigned long pck;
 131
 132         /* dividers */
 133         u16 lck_div;
 134         u16 pck_div;
 135 };
 136
 137 struct dsi_clock_info {
 138         /* rates that we get with dividers below */
 139         unsigned long fint;
 140         unsigned long clkin4ddr;
 141         unsigned long clkin;
 142         unsigned long dsi_pll_hsdiv_dispc_clk;  /* OMAP3: DSI1_PLL_CLK
 143                                                  * OMAP4: PLLx_CLK1 */
 144         unsigned long dsi_pll_hsdiv_dsi_clk;    /* OMAP3: DSI2_PLL_CLK
 145                                                  * OMAP4: PLLx_CLK2 */
 146         unsigned long lp_clk;
 147
 148         /* dividers */
 149         u16 regn;
 150         u16 regm;
 151         u16 regm_dispc; /* OMAP3: REGM3
 152                          * OMAP4: REGM4 */
 153         u16 regm_dsi;   /* OMAP3: REGM4
 154                          * OMAP4: REGM5 */
 155         u16 lp_clk_div;
 156
 157         u8 highfreq;
 158         bool use_sys_clk;
 159 };
 160
 161 /* HDMI PLL structure */
 162 struct hdmi_pll_info {
 163         u16 regn;
 164         u16 regm;
 165         u32 regmf;
 166         u16 regm2;
 167         u16 regsd;
 168         u16 dcofreq;
 169 };
 170
 171 struct seq_file;
 172 struct platform_device;
 173
 174 /* core */
 175 struct bus_type *dss_get_bus(void);
 176 struct regulator *dss_get_vdds_dsi(void);
 177 struct regulator *dss_get_vdds_sdi(void);
 178
 179 /* display */
 180 int dss_suspend_all_devices(void);
 181 int dss_resume_all_devices(void);
 182 void dss_disable_all_devices(void);
 183
 184 void dss_init_device(struct platform_device *pdev,
 185                 struct omap_dss_device *dssdev);
 186 void dss_uninit_device(struct platform_device *pdev,
 187                 struct omap_dss_device *dssdev);
 188 bool dss_use_replication(struct omap_dss_device *dssdev,
 189                 enum omap_color_mode mode);
 190 void default_get_overlay_fifo_thresholds(enum omap_plane plane,
 191                 u32 fifo_size, u32 burst_size,
 192                 u32 *fifo_low, u32 *fifo_high);
 193
 194 /* manager */
 195 int dss_init_overlay_managers(struct platform_device *pdev);
 196 void dss_uninit_overlay_managers(struct platform_device *pdev);
 197 int dss_mgr_wait_for_go_ovl(struct omap_overlay *ovl);
 198 void dss_setup_partial_planes(struct omap_dss_device *dssdev,
 199                                 u16 *x, u16 *y, u16 *w, u16 *h,
 200                                 bool enlarge_update_area);
 201 void dss_start_update(struct omap_dss_device *dssdev);
 202
 203 /* overlay */
 204 void dss_init_overlays(struct platform_device *pdev);
 205 void dss_uninit_overlays(struct platform_device *pdev);
 206 int dss_check_overlay(struct omap_overlay *ovl, struct omap_dss_device *dssdev);
 207 void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr);
 208 #ifdef L4_EXAMPLE
 209 void dss_overlay_setup_l4_manager(struct omap_overlay_manager *mgr);
 210 #endif
 211 void dss_recheck_connections(struct omap_dss_device *dssdev, bool force);
 212
 213 /* DSS */
 214 int dss_init_platform_driver(void);
 215 void dss_uninit_platform_driver(void);
 216
 217 void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select);
 218 void dss_save_context(void);
 219 void dss_restore_context(void);
 220 void dss_clk_enable(enum dss_clock clks);
 221 void dss_clk_disable(enum dss_clock clks);
 222 unsigned long dss_clk_get_rate(enum dss_clock clk);
 223 const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src);
 224 void dss_dump_clocks(struct seq_file *s);
 225
 226 void dss_dump_regs(struct seq_file *s);
 227 #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
 228 void dss_debug_dump_clocks(struct seq_file *s);
 229 #endif
 230
 231 void dss_sdi_init(u8 datapairs);
 232 int dss_sdi_enable(void);
 233 void dss_sdi_disable(void);
 234
 235 void dss_select_dispc_clk_source(enum omap_dss_clk_source clk_src);
 236 void dss_select_dsi_clk_source(int dsi_module,
 237                 enum omap_dss_clk_source clk_src);
 238 void dss_select_lcd_clk_source(enum omap_channel channel,
 239                 enum omap_dss_clk_source clk_src);
 240 enum omap_dss_clk_source dss_get_dispc_clk_source(void);
 241 enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module);
 242 enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel);
 243
 244 void dss_set_venc_output(enum omap_dss_venc_type type);
 245 void dss_set_dac_pwrdn_bgz(bool enable);
 246
 247 unsigned long dss_get_dpll4_rate(void);
 248 int dss_calc_clock_rates(struct dss_clock_info *cinfo);
 249 int dss_set_clock_div(struct dss_clock_info *cinfo);
 250 int dss_get_clock_div(struct dss_clock_info *cinfo);
 251 int dss_calc_clock_div(bool is_tft, unsigned long req_pck,
 252                 struct dss_clock_info *dss_cinfo,
 253                 struct dispc_clock_info *dispc_cinfo);
 254
 255 /* SDI */
 256 #ifdef CONFIG_OMAP2_DSS_SDI
 257 int sdi_init(void);
 258 void sdi_exit(void);
 259 int sdi_init_display(struct omap_dss_device *display);
 260 #else
 261 static inline int sdi_init(void)
 262 {
 263         return 0;
 264 }
 265 static inline void sdi_exit(void)
 266 {
 267 }
 268 #endif
 269
 270 /* DSI */
 271 #ifdef CONFIG_OMAP2_DSS_DSI
 272
 273 struct dentry;
 274 struct file_operations;
 275
 276 int dsi_init_platform_driver(void);
 277 void dsi_uninit_platform_driver(void);
 278
 279 void dsi_dump_clocks(struct seq_file *s);
 280 void dsi_create_debugfs_files_irq(struct dentry *debugfs_dir,
 281                 const struct file_operations *debug_fops);
 282 void dsi_create_debugfs_files_reg(struct dentry *debugfs_dir,
 283                 const struct file_operations *debug_fops);
 284
 285 void dsi_save_context(void);
 286 void dsi_restore_context(void);
 287
 288 int dsi_init_display(struct omap_dss_device *display);
 289 void dsi_irq_handler(void);
 290 unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev);
 291 int dsi_pll_set_clock_div(struct platform_device *dsidev,
 292                 struct dsi_clock_info *cinfo);
 293 int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev, bool is_tft,
 294                 unsigned long req_pck, struct dsi_clock_info *cinfo,
 295                 struct dispc_clock_info *dispc_cinfo);
 296 int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk,
 297                 bool enable_hsdiv);
 298 void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes);
 299 void dsi_get_overlay_fifo_thresholds(enum omap_plane plane,
 300                 u32 fifo_size, u32 burst_size,
 301                 u32 *fifo_low, u32 *fifo_high);
 302 void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev);
 303 void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev);
 304 struct platform_device *dsi_get_dsidev_from_id(int module);
 305 #else
 306 static inline int dsi_init_platform_driver(void)
 307 {
 308         return 0;
 309 }
 310 static inline void dsi_uninit_platform_driver(void)
 311 {
 312 }
 313 static inline unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
 314 {
 315         WARN("%s: DSI not compiled in, returning rate as 0\n", __func__);
 316         return 0;
 317 }
 318 static inline int dsi_pll_set_clock_div(struct platform_device *dsidev,
 319                 struct dsi_clock_info *cinfo)
 320 {
 321         WARN("%s: DSI not compiled in\n", __func__);
 322         return -ENODEV;
 323 }
 324 static inline int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev,
 325                 bool is_tft, unsigned long req_pck,
 326                 struct dsi_clock_info *dsi_cinfo,
 327                 struct dispc_clock_info *dispc_cinfo)
 328 {
 329         WARN("%s: DSI not compiled in\n", __func__);
 330         return -ENODEV;
 331 }
 332 static inline int dsi_pll_init(struct platform_device *dsidev,
 333                 bool enable_hsclk, bool enable_hsdiv)
 334 {
 335         WARN("%s: DSI not compiled in\n", __func__);
 336         return -ENODEV;
 337 }
 338 static inline void dsi_pll_uninit(struct platform_device *dsidev,
 339                 bool disconnect_lanes)
 340 {
 341 }
 342 static inline void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev)
 343 {
 344 }
 345 static inline void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev)
 346 {
 347 }
 348 static inline struct platform_device *dsi_get_dsidev_from_id(int module)
 349 {
 350         WARN("%s: DSI not compiled in, returning platform device as NULL\n",
 351                         __func__);
 352         return NULL;
 353 }
 354 #endif
 355
 356 /* DPI */
 357 #ifdef CONFIG_OMAP2_DSS_DPI
 358 int dpi_init(void);
 359 void dpi_exit(void);
 360 int dpi_init_display(struct omap_dss_device *dssdev);
 361 #else
 362 static inline int dpi_init(void)
 363 {
 364         return 0;
 365 }
 366 static inline void dpi_exit(void)
 367 {
 368 }
 369 #endif
 370
 371 /* DISPC */
 372 int dispc_init_platform_driver(void);
 373 void dispc_uninit_platform_driver(void);
 374 void dispc_dump_clocks(struct seq_file *s);
 375 void dispc_dump_irqs(struct seq_file *s);
 376 void dispc_dump_regs(struct seq_file *s);
 377 void dispc_irq_handler(void);
 378 void dispc_fake_vsync_irq(void);
 379
 380 void dispc_save_context(void);
 381 void dispc_restore_context(void);
 382
 383 void dispc_enable_sidle(void);
 384 void dispc_disable_sidle(void);
 385
 386 void dispc_lcd_enable_signal_polarity(bool act_high);
 387 void dispc_lcd_enable_signal(bool enable);
 388 void dispc_pck_free_enable(bool enable);
 389 void dispc_enable_fifohandcheck(enum omap_channel channel, bool enable);
 390
 391 void dispc_set_lcd_size(enum omap_channel channel, u16 width, u16 height);
 392 void dispc_set_digit_size(u16 width, u16 height);
 393 u32 dispc_get_plane_fifo_size(enum omap_plane plane);
 394 void dispc_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high);
 395 void dispc_enable_fifomerge(bool enable);
 396 u32 dispc_get_burst_size(enum omap_plane plane);
 397 void dispc_enable_cpr(enum omap_channel channel, bool enable);
 398 void dispc_set_cpr_coef(enum omap_channel channel,
 399                 struct omap_dss_cpr_coefs *coefs);
 400
 401 void dispc_set_plane_ba0(enum omap_plane plane, u32 paddr);
 402 void dispc_set_plane_ba1(enum omap_plane plane, u32 paddr);
 403 void dispc_set_plane_pos(enum omap_plane plane, u16 x, u16 y);
 404 void dispc_set_plane_size(enum omap_plane plane, u16 width, u16 height);
 405 void dispc_set_channel_out(enum omap_plane plane,
 406                 enum omap_channel channel_out);
 407
 408 void dispc_enable_gamma_table(bool enable);
 409 int dispc_setup_plane(enum omap_plane plane,
 410                       u32 paddr, u16 screen_width,
 411                       u16 pos_x, u16 pos_y,
 412                       u16 width, u16 height,
 413                       u16 out_width, u16 out_height,
 414                       enum omap_color_mode color_mode,
 415                       bool ilace,
 416                       enum omap_dss_rotation_type rotation_type,
 417                       u8 rotation, bool mirror,
 418                       u8 global_alpha, u8 pre_mult_alpha,
 419                       enum omap_channel channel,
 420                       u32 puv_addr);
 421
 422 bool dispc_go_busy(enum omap_channel channel);
 423 void dispc_go(enum omap_channel channel);
 424 void dispc_enable_channel(enum omap_channel channel, bool enable);
 425 bool dispc_is_channel_enabled(enum omap_channel channel);
 426 int dispc_enable_plane(enum omap_plane plane, bool enable);
 427 void dispc_enable_replication(enum omap_plane plane, bool enable);
 428
 429 void dispc_set_parallel_interface_mode(enum omap_channel channel,
 430                 enum omap_parallel_interface_mode mode);
 431 void dispc_set_tft_data_lines(enum omap_channel channel, u8 data_lines);
 432 void dispc_set_lcd_display_type(enum omap_channel channel,
 433                 enum omap_lcd_display_type type);
 434 void dispc_set_loadmode(enum omap_dss_load_mode mode);
 435
 436 void dispc_set_default_color(enum omap_channel channel, u32 color);
 437 u32 dispc_get_default_color(enum omap_channel channel);
 438 void dispc_set_trans_key(enum omap_channel ch,
 439                 enum omap_dss_trans_key_type type,
 440                 u32 trans_key);
 441 void dispc_get_trans_key(enum omap_channel ch,
 442                 enum omap_dss_trans_key_type *type,
 443                 u32 *trans_key);
 444 void dispc_enable_trans_key(enum omap_channel ch, bool enable);
 445 void dispc_enable_alpha_blending(enum omap_channel ch, bool enable);
 446 bool dispc_trans_key_enabled(enum omap_channel ch);
 447 bool dispc_alpha_blending_enabled(enum omap_channel ch);
 448
 449 bool dispc_lcd_timings_ok(struct omap_video_timings *timings);
 450 void dispc_set_lcd_timings(enum omap_channel channel,
 451                 struct omap_video_timings *timings);
 452 unsigned long dispc_fclk_rate(void);
 453 unsigned long dispc_lclk_rate(enum omap_channel channel);
 454 unsigned long dispc_pclk_rate(enum omap_channel channel);
 455 void dispc_set_pol_freq(enum omap_channel channel,
 456                 enum omap_panel_config config, u8 acbi, u8 acb);
 457 void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
 458                 struct dispc_clock_info *cinfo);
 459 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
 460                 struct dispc_clock_info *cinfo);
 461 int dispc_set_clock_div(enum omap_channel channel,
 462                 struct dispc_clock_info *cinfo);
 463 int dispc_get_clock_div(enum omap_channel channel,
 464                 struct dispc_clock_info *cinfo);
 465
 466
 467 /* VENC */
 468 #ifdef CONFIG_OMAP2_DSS_VENC
 469 int venc_init_platform_driver(void);
 470 void venc_uninit_platform_driver(void);
 471 void venc_dump_regs(struct seq_file *s);
 472 int venc_init_display(struct omap_dss_device *display);
 473 #else
 474 static inline int venc_init_platform_driver(void)
 475 {
 476         return 0;
 477 }
 478 static inline void venc_uninit_platform_driver(void)
 479 {
 480 }
 481 #endif
 482
 483 /* HDMI */
 484 #ifdef CONFIG_OMAP4_DSS_HDMI
 485 int hdmi_init_platform_driver(void);
 486 void hdmi_uninit_platform_driver(void);
 487 int hdmi_init_display(struct omap_dss_device *dssdev);
 488 #else
 489 static inline int hdmi_init_display(struct omap_dss_device *dssdev)
 490 {
 491         return 0;
 492 }
 493 static inline int hdmi_init_platform_driver(void)
 494 {
 495         return 0;
 496 }
 497 static inline void hdmi_uninit_platform_driver(void)
 498 {
 499 }
 500 #endif
 501 int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev);
 502 void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev);
 503 void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev);
 504 int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev,
 505                                         struct omap_video_timings *timings);
 506 int hdmi_panel_init(void);
 507 void hdmi_panel_exit(void);
 508
 509 /* RFBI */
 510 #ifdef CONFIG_OMAP2_DSS_RFBI
 511 int rfbi_init_platform_driver(void);
 512 void rfbi_uninit_platform_driver(void);
 513 void rfbi_dump_regs(struct seq_file *s);
 514 int rfbi_init_display(struct omap_dss_device *display);
 515 #else
 516 static inline int rfbi_init_platform_driver(void)
 517 {
 518         return 0;
 519 }
 520 static inline void rfbi_uninit_platform_driver(void)
 521 {
 522 }
 523 #endif
 524
 525
 526 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
 527 static inline void dss_collect_irq_stats(u32 irqstatus, unsigned *irq_arr)
 528 {
 529         int b;
 530         for (b = 0; b < 32; ++b) {
 531                 if (irqstatus & (1 << b))
 532                         irq_arr[b]++;
 533         }
 534 }
 535 #endif
 536
 537 #endif