4 * HDMI interface DSS driver setting for TI's OMAP4 family of processor.
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
7 * Mythri pk <mythripk@ti.com>
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
22 #define DSS_SUBSYS_NAME "HDMI"
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/err.h>
28 #include <linux/interrupt.h>
29 #include <linux/mutex.h>
30 #include <linux/delay.h>
31 #include <linux/string.h>
32 #include <linux/platform_device.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/clk.h>
35 #include <video/omapdss.h>
39 #include "dss_features.h"
42 #define HDMI_CORE_SYS 0x400
43 #define HDMI_CORE_AV 0x900
44 #define HDMI_PLLCTRL 0x200
45 #define HDMI_PHY 0x300
47 /* HDMI EDID Length move this */
48 #define HDMI_EDID_MAX_LENGTH 256
49 #define EDID_TIMING_DESCRIPTOR_SIZE 0x12
50 #define EDID_DESCRIPTOR_BLOCK0_ADDRESS 0x36
51 #define EDID_DESCRIPTOR_BLOCK1_ADDRESS 0x80
52 #define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR 4
53 #define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR 4
55 #define HDMI_DEFAULT_REGN 16
56 #define HDMI_DEFAULT_REGM2 1
60 struct platform_device *pdev;
61 struct hdmi_ip_data ip_data;
67 * Logic for the below structure :
68 * user enters the CEA or VESA timings by specifying the HDMI/DVI code.
69 * There is a correspondence between CEA/VESA timing and code, please
70 * refer to section 6.3 in HDMI 1.3 specification for timing code.
72 * In the below structure, cea_vesa_timings corresponds to all OMAP4
73 * supported CEA and VESA timing values.code_cea corresponds to the CEA
74 * code, It is used to get the timing from cea_vesa_timing array.Similarly
75 * with code_vesa. Code_index is used for back mapping, that is once EDID
76 * is read from the TV, EDID is parsed to find the timing values and then
77 * map it to corresponding CEA or VESA index.
80 static const struct hdmi_config cea_timings[] = {
81 { {640, 480, 25200, 96, 16, 48, 2, 10, 33, 0, 0, 0}, {1, HDMI_HDMI} },
82 { {720, 480, 27027, 62, 16, 60, 6, 9, 30, 0, 0, 0}, {2, HDMI_HDMI} },
83 { {1280, 720, 74250, 40, 110, 220, 5, 5, 20, 1, 1, 0}, {4, HDMI_HDMI} },
84 { {1920, 540, 74250, 44, 88, 148, 5, 2, 15, 1, 1, 1}, {5, HDMI_HDMI} },
85 { {1440, 240, 27027, 124, 38, 114, 3, 4, 15, 0, 0, 1}, {6, HDMI_HDMI} },
86 { {1920, 1080, 148500, 44, 88, 148, 5, 4, 36, 1, 1, 0}, {16, HDMI_HDMI} },
87 { {720, 576, 27000, 64, 12, 68, 5, 5, 39, 0, 0, 0}, {17, HDMI_HDMI} },
88 { {1280, 720, 74250, 40, 440, 220, 5, 5, 20, 1, 1, 0}, {19, HDMI_HDMI} },
89 { {1920, 540, 74250, 44, 528, 148, 5, 2, 15, 1, 1, 1}, {20, HDMI_HDMI} },
90 { {1440, 288, 27000, 126, 24, 138, 3, 2, 19, 0, 0, 1}, {21, HDMI_HDMI} },
91 { {1440, 576, 54000, 128, 24, 136, 5, 5, 39, 0, 0, 0}, {29, HDMI_HDMI} },
92 { {1920, 1080, 148500, 44, 528, 148, 5, 4, 36, 1, 1, 0}, {31, HDMI_HDMI} },
93 { {1920, 1080, 74250, 44, 638, 148, 5, 4, 36, 1, 1, 0}, {32, HDMI_HDMI} },
94 { {2880, 480, 108108, 248, 64, 240, 6, 9, 30, 0, 0, 0}, {35, HDMI_HDMI} },
95 { {2880, 576, 108000, 256, 48, 272, 5, 5, 39, 0, 0, 0}, {37, HDMI_HDMI} },
97 static const struct hdmi_config vesa_timings[] = {
99 { {640, 480, 25175, 96, 16, 48, 2 , 11, 31, 0, 0, 0}, {4, HDMI_DVI} },
100 { {800, 600, 40000, 128, 40, 88, 4 , 1, 23, 1, 1, 0}, {9, HDMI_DVI} },
101 { {848, 480, 33750, 112, 16, 112, 8 , 6, 23, 1, 1, 0}, {0xE, HDMI_DVI} },
102 { {1280, 768, 79500, 128, 64, 192, 7 , 3, 20, 1, 0, 0}, {0x17, HDMI_DVI} },
103 { {1280, 800, 83500, 128, 72, 200, 6 , 3, 22, 1, 0, 0}, {0x1C, HDMI_DVI} },
104 { {1360, 768, 85500, 112, 64, 256, 6 , 3, 18, 1, 1, 0}, {0x27, HDMI_DVI} },
105 { {1280, 960, 108000, 112, 96, 312, 3 , 1, 36, 1, 1, 0}, {0x20, HDMI_DVI} },
106 { {1280, 1024, 108000, 112, 48, 248, 3 , 1, 38, 1, 1, 0}, {0x23, HDMI_DVI} },
107 { {1024, 768, 65000, 136, 24, 160, 6, 3, 29, 0, 0, 0}, {0x10, HDMI_DVI} },
108 { {1400, 1050, 121750, 144, 88, 232, 4, 3, 32, 1, 0, 0}, {0x2A, HDMI_DVI} },
109 { {1440, 900, 106500, 152, 80, 232, 6, 3, 25, 1, 0, 0}, {0x2F, HDMI_DVI} },
110 { {1680, 1050, 146250, 176 , 104, 280, 6, 3, 30, 1, 0, 0}, {0x3A, HDMI_DVI} },
111 { {1366, 768, 85500, 143, 70, 213, 3, 3, 24, 1, 1, 0}, {0x51, HDMI_DVI} },
112 { {1920, 1080, 148500, 44, 148, 80, 5, 4, 36, 1, 1, 0}, {0x52, HDMI_DVI} },
113 { {1280, 768, 68250, 32, 48, 80, 7, 3, 12, 0, 1, 0}, {0x16, HDMI_DVI} },
114 { {1400, 1050, 101000, 32, 48, 80, 4, 3, 23, 0, 1, 0}, {0x29, HDMI_DVI} },
115 { {1680, 1050, 119000, 32, 48, 80, 6, 3, 21, 0, 1, 0}, {0x39, HDMI_DVI} },
116 { {1280, 800, 79500, 32, 48, 80, 6, 3, 14, 0, 1, 0}, {0x1B, HDMI_DVI} },
117 { {1280, 720, 74250, 40, 110, 220, 5, 5, 20, 1, 1, 0}, {0x55, HDMI_DVI} }
120 static int hdmi_runtime_get(void)
124 DSSDBG("hdmi_runtime_get\n");
126 r = pm_runtime_get_sync(&hdmi.pdev->dev);
134 static void hdmi_runtime_put(void)
138 DSSDBG("hdmi_runtime_put\n");
140 r = pm_runtime_put_sync(&hdmi.pdev->dev);
144 static int __init hdmi_init_display(struct omap_dss_device *dssdev)
146 DSSDBG("init_display\n");
148 dss_init_hdmi_ip_ops(&hdmi.ip_data);
152 static const struct hdmi_config *hdmi_find_timing(
153 const struct hdmi_config *timings_arr,
158 for (i = 0; i < len; i++) {
159 if (timings_arr[i].cm.code == hdmi.ip_data.cfg.cm.code)
160 return &timings_arr[i];
165 static const struct hdmi_config *hdmi_get_timings(void)
167 const struct hdmi_config *arr;
170 if (hdmi.ip_data.cfg.cm.mode == HDMI_DVI) {
172 len = ARRAY_SIZE(vesa_timings);
175 len = ARRAY_SIZE(cea_timings);
178 return hdmi_find_timing(arr, len);
181 static bool hdmi_timings_compare(struct omap_video_timings *timing1,
182 const struct hdmi_video_timings *timing2)
184 int timing1_vsync, timing1_hsync, timing2_vsync, timing2_hsync;
186 if ((timing2->pixel_clock == timing1->pixel_clock) &&
187 (timing2->x_res == timing1->x_res) &&
188 (timing2->y_res == timing1->y_res)) {
190 timing2_hsync = timing2->hfp + timing2->hsw + timing2->hbp;
191 timing1_hsync = timing1->hfp + timing1->hsw + timing1->hbp;
192 timing2_vsync = timing2->vfp + timing2->vsw + timing2->vbp;
193 timing1_vsync = timing2->vfp + timing2->vsw + timing2->vbp;
195 DSSDBG("timing1_hsync = %d timing1_vsync = %d"\
196 "timing2_hsync = %d timing2_vsync = %d\n",
197 timing1_hsync, timing1_vsync,
198 timing2_hsync, timing2_vsync);
200 if ((timing1_hsync == timing2_hsync) &&
201 (timing1_vsync == timing2_vsync)) {
208 static struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing)
211 struct hdmi_cm cm = {-1};
212 DSSDBG("hdmi_get_code\n");
214 for (i = 0; i < ARRAY_SIZE(cea_timings); i++) {
215 if (hdmi_timings_compare(timing, &cea_timings[i].timings)) {
216 cm = cea_timings[i].cm;
220 for (i = 0; i < ARRAY_SIZE(vesa_timings); i++) {
221 if (hdmi_timings_compare(timing, &vesa_timings[i].timings)) {
222 cm = vesa_timings[i].cm;
231 unsigned long hdmi_get_pixel_clock(void)
233 /* HDMI Pixel Clock in Mhz */
234 return hdmi.ip_data.cfg.timings.pixel_clock * 1000;
237 static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy,
238 struct hdmi_pll_info *pi)
240 unsigned long clkin, refclk;
243 clkin = clk_get_rate(hdmi.sys_clk) / 10000;
245 * Input clock is predivided by N + 1
246 * out put of which is reference clk
248 if (dssdev->clocks.hdmi.regn == 0)
249 pi->regn = HDMI_DEFAULT_REGN;
251 pi->regn = dssdev->clocks.hdmi.regn;
253 refclk = clkin / pi->regn;
255 if (dssdev->clocks.hdmi.regm2 == 0)
256 pi->regm2 = HDMI_DEFAULT_REGM2;
258 pi->regm2 = dssdev->clocks.hdmi.regm2;
261 * multiplier is pixel_clk/ref_clk
262 * Multiplying by 100 to avoid fractional part removal
264 pi->regm = phy * pi->regm2 / refclk;
267 * fractional multiplier is remainder of the difference between
268 * multiplier and actual phy(required pixel clock thus should be
269 * multiplied by 2^18(262144) divided by the reference clock
271 mf = (phy - pi->regm / pi->regm2 * refclk) * 262144;
272 pi->regmf = pi->regm2 * mf / refclk;
275 * Dcofreq should be set to 1 if required pixel clock
276 * is greater than 1000MHz
278 pi->dcofreq = phy > 1000 * 100;
279 pi->regsd = ((pi->regm * clkin / 10) / (pi->regn * 250) + 5) / 10;
281 /* Set the reference clock to sysclk reference */
282 pi->refsel = HDMI_REFSEL_SYSCLK;
284 DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf);
285 DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd);
288 static int hdmi_power_on(struct omap_dss_device *dssdev)
291 const struct hdmi_config *timing;
292 struct omap_video_timings *p;
295 r = hdmi_runtime_get();
299 dss_mgr_disable(dssdev->manager);
301 p = &dssdev->panel.timings;
303 DSSDBG("hdmi_power_on x_res= %d y_res = %d\n",
304 dssdev->panel.timings.x_res,
305 dssdev->panel.timings.y_res);
307 timing = hdmi_get_timings();
308 if (timing == NULL) {
309 /* HDMI code 4 corresponds to 640 * 480 VGA */
310 hdmi.ip_data.cfg.cm.code = 4;
311 /* DVI mode 1 corresponds to HDMI 0 to DVI */
312 hdmi.ip_data.cfg.cm.mode = HDMI_DVI;
313 hdmi.ip_data.cfg = vesa_timings[0];
315 hdmi.ip_data.cfg = *timing;
317 phy = p->pixel_clock;
319 hdmi_compute_pll(dssdev, phy, &hdmi.ip_data.pll_data);
321 hdmi.ip_data.ops->video_disable(&hdmi.ip_data);
323 /* config the PLL and PHY hdmi_set_pll_pwrfirst */
324 r = hdmi.ip_data.ops->pll_enable(&hdmi.ip_data);
326 DSSDBG("Failed to lock PLL\n");
330 r = hdmi.ip_data.ops->phy_enable(&hdmi.ip_data);
332 DSSDBG("Failed to start PHY\n");
336 hdmi.ip_data.ops->video_configure(&hdmi.ip_data);
338 /* Make selection of HDMI in DSS */
339 dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK);
341 /* Select the dispc clock source as PRCM clock, to ensure that it is not
342 * DSI PLL source as the clock selected by DSI PLL might not be
343 * sufficient for the resolution selected / that can be changed
344 * dynamically by user. This can be moved to single location , say
347 dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);
349 /* bypass TV gamma table */
350 dispc_enable_gamma_table(0);
353 dss_mgr_set_timings(dssdev->manager, &dssdev->panel.timings);
355 r = hdmi.ip_data.ops->video_enable(&hdmi.ip_data);
359 r = dss_mgr_enable(dssdev->manager);
366 hdmi.ip_data.ops->video_disable(&hdmi.ip_data);
368 hdmi.ip_data.ops->phy_disable(&hdmi.ip_data);
369 hdmi.ip_data.ops->pll_disable(&hdmi.ip_data);
375 static void hdmi_power_off(struct omap_dss_device *dssdev)
377 dss_mgr_disable(dssdev->manager);
379 hdmi.ip_data.ops->video_disable(&hdmi.ip_data);
380 hdmi.ip_data.ops->phy_disable(&hdmi.ip_data);
381 hdmi.ip_data.ops->pll_disable(&hdmi.ip_data);
385 int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev,
386 struct omap_video_timings *timings)
390 cm = hdmi_get_code(timings);
399 void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev)
403 cm = hdmi_get_code(&dssdev->panel.timings);
404 hdmi.ip_data.cfg.cm.code = cm.code;
405 hdmi.ip_data.cfg.cm.mode = cm.mode;
407 if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) {
410 hdmi_power_off(dssdev);
412 r = hdmi_power_on(dssdev);
414 DSSERR("failed to power on device\n");
416 dss_mgr_set_timings(dssdev->manager, &dssdev->panel.timings);
420 static void hdmi_dump_regs(struct seq_file *s)
422 mutex_lock(&hdmi.lock);
424 if (hdmi_runtime_get())
427 hdmi.ip_data.ops->dump_wrapper(&hdmi.ip_data, s);
428 hdmi.ip_data.ops->dump_pll(&hdmi.ip_data, s);
429 hdmi.ip_data.ops->dump_phy(&hdmi.ip_data, s);
430 hdmi.ip_data.ops->dump_core(&hdmi.ip_data, s);
433 mutex_unlock(&hdmi.lock);
436 int omapdss_hdmi_read_edid(u8 *buf, int len)
440 mutex_lock(&hdmi.lock);
442 r = hdmi_runtime_get();
445 r = hdmi.ip_data.ops->read_edid(&hdmi.ip_data, buf, len);
448 mutex_unlock(&hdmi.lock);
453 bool omapdss_hdmi_detect(void)
457 mutex_lock(&hdmi.lock);
459 r = hdmi_runtime_get();
462 r = hdmi.ip_data.ops->detect(&hdmi.ip_data);
465 mutex_unlock(&hdmi.lock);
470 int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev)
472 struct omap_dss_hdmi_data *priv = dssdev->data;
475 DSSDBG("ENTER hdmi_display_enable\n");
477 mutex_lock(&hdmi.lock);
479 if (dssdev->manager == NULL) {
480 DSSERR("failed to enable display: no manager\n");
485 hdmi.ip_data.hpd_gpio = priv->hpd_gpio;
487 r = omap_dss_start_device(dssdev);
489 DSSERR("failed to start device\n");
493 if (dssdev->platform_enable) {
494 r = dssdev->platform_enable(dssdev);
496 DSSERR("failed to enable GPIO's\n");
501 r = hdmi_power_on(dssdev);
503 DSSERR("failed to power on device\n");
507 mutex_unlock(&hdmi.lock);
511 if (dssdev->platform_disable)
512 dssdev->platform_disable(dssdev);
514 omap_dss_stop_device(dssdev);
516 mutex_unlock(&hdmi.lock);
520 void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev)
522 DSSDBG("Enter hdmi_display_disable\n");
524 mutex_lock(&hdmi.lock);
526 hdmi_power_off(dssdev);
528 if (dssdev->platform_disable)
529 dssdev->platform_disable(dssdev);
531 omap_dss_stop_device(dssdev);
533 mutex_unlock(&hdmi.lock);
536 static int hdmi_get_clocks(struct platform_device *pdev)
540 clk = clk_get(&pdev->dev, "sys_clk");
542 DSSERR("can't get sys_clk\n");
551 static void hdmi_put_clocks(void)
554 clk_put(hdmi.sys_clk);
557 #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
558 int hdmi_compute_acr(u32 sample_freq, u32 *n, u32 *cts)
561 bool deep_color_correct = false;
562 u32 pclk = hdmi.ip_data.cfg.timings.pixel_clock;
564 if (n == NULL || cts == NULL)
567 /* TODO: When implemented, query deep color mode here. */
571 * When using deep color, the default N value (as in the HDMI
572 * specification) yields to an non-integer CTS. Hence, we
573 * modify it while keeping the restrictions described in
574 * section 7.2.1 of the HDMI 1.4a specification.
576 switch (sample_freq) {
581 if (deep_color == 125)
582 if (pclk == 27027 || pclk == 74250)
583 deep_color_correct = true;
584 if (deep_color == 150)
586 deep_color_correct = true;
591 if (deep_color == 125)
593 deep_color_correct = true;
599 if (deep_color_correct) {
600 switch (sample_freq) {
626 switch (sample_freq) {
652 /* Calculate CTS. See HDMI 1.3a or 1.4a specifications */
653 *cts = pclk * (*n / 128) * deep_color / (sample_freq / 10);
658 int hdmi_audio_enable(void)
660 DSSDBG("audio_enable\n");
662 return hdmi.ip_data.ops->audio_enable(&hdmi.ip_data);
665 void hdmi_audio_disable(void)
667 DSSDBG("audio_disable\n");
669 hdmi.ip_data.ops->audio_disable(&hdmi.ip_data);
672 int hdmi_audio_start(void)
674 DSSDBG("audio_start\n");
676 return hdmi.ip_data.ops->audio_start(&hdmi.ip_data);
679 void hdmi_audio_stop(void)
681 DSSDBG("audio_stop\n");
683 hdmi.ip_data.ops->audio_stop(&hdmi.ip_data);
686 bool hdmi_mode_has_audio(void)
688 if (hdmi.ip_data.cfg.cm.mode == HDMI_HDMI)
694 int hdmi_audio_config(struct omap_dss_audio *audio)
696 return hdmi.ip_data.ops->audio_config(&hdmi.ip_data, audio);
701 static void __init hdmi_probe_pdata(struct platform_device *pdev)
703 struct omap_dss_board_info *pdata = pdev->dev.platform_data;
706 for (i = 0; i < pdata->num_devices; ++i) {
707 struct omap_dss_device *dssdev = pdata->devices[i];
709 if (dssdev->type != OMAP_DISPLAY_TYPE_HDMI)
712 r = hdmi_init_display(dssdev);
714 DSSERR("device %s init failed: %d\n", dssdev->name, r);
718 r = omap_dss_register_device(dssdev, &pdev->dev, i);
720 DSSERR("device %s register failed: %d\n",
725 /* HDMI HW IP initialisation */
726 static int __init omapdss_hdmihw_probe(struct platform_device *pdev)
728 struct resource *hdmi_mem;
733 mutex_init(&hdmi.lock);
735 hdmi_mem = platform_get_resource(hdmi.pdev, IORESOURCE_MEM, 0);
737 DSSERR("can't get IORESOURCE_MEM HDMI\n");
741 /* Base address taken from platform */
742 hdmi.ip_data.base_wp = ioremap(hdmi_mem->start,
743 resource_size(hdmi_mem));
744 if (!hdmi.ip_data.base_wp) {
745 DSSERR("can't ioremap WP\n");
749 r = hdmi_get_clocks(pdev);
751 iounmap(hdmi.ip_data.base_wp);
755 pm_runtime_enable(&pdev->dev);
757 hdmi.ip_data.core_sys_offset = HDMI_CORE_SYS;
758 hdmi.ip_data.core_av_offset = HDMI_CORE_AV;
759 hdmi.ip_data.pll_offset = HDMI_PLLCTRL;
760 hdmi.ip_data.phy_offset = HDMI_PHY;
764 dss_debugfs_create_file("hdmi", hdmi_dump_regs);
766 hdmi_probe_pdata(pdev);
771 static int __exit omapdss_hdmihw_remove(struct platform_device *pdev)
773 omap_dss_unregister_child_devices(&pdev->dev);
777 pm_runtime_disable(&pdev->dev);
781 iounmap(hdmi.ip_data.base_wp);
786 static int hdmi_runtime_suspend(struct device *dev)
788 clk_disable(hdmi.sys_clk);
795 static int hdmi_runtime_resume(struct device *dev)
799 r = dispc_runtime_get();
803 clk_enable(hdmi.sys_clk);
808 static const struct dev_pm_ops hdmi_pm_ops = {
809 .runtime_suspend = hdmi_runtime_suspend,
810 .runtime_resume = hdmi_runtime_resume,
813 static struct platform_driver omapdss_hdmihw_driver = {
814 .remove = __exit_p(omapdss_hdmihw_remove),
816 .name = "omapdss_hdmi",
817 .owner = THIS_MODULE,
822 int __init hdmi_init_platform_driver(void)
824 return platform_driver_probe(&omapdss_hdmihw_driver, omapdss_hdmihw_probe);
827 void __exit hdmi_uninit_platform_driver(void)
829 platform_driver_unregister(&omapdss_hdmihw_driver);