4 * HDMI interface DSS driver setting for TI's OMAP4 family of processor.
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
7 * Mythri pk <mythripk@ti.com>
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
22 #define DSS_SUBSYS_NAME "HDMI"
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/err.h>
28 #include <linux/interrupt.h>
29 #include <linux/mutex.h>
30 #include <linux/delay.h>
31 #include <linux/string.h>
32 #include <linux/platform_device.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/clk.h>
35 #include <linux/gpio.h>
36 #include <linux/regulator/consumer.h>
37 #include <video/omapdss.h>
41 #include "dss_features.h"
44 #define HDMI_CORE_SYS 0x400
45 #define HDMI_CORE_AV 0x900
46 #define HDMI_PLLCTRL 0x200
47 #define HDMI_PHY 0x300
49 /* HDMI EDID Length move this */
50 #define HDMI_EDID_MAX_LENGTH 256
51 #define EDID_TIMING_DESCRIPTOR_SIZE 0x12
52 #define EDID_DESCRIPTOR_BLOCK0_ADDRESS 0x36
53 #define EDID_DESCRIPTOR_BLOCK1_ADDRESS 0x80
54 #define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR 4
55 #define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR 4
57 #define HDMI_DEFAULT_REGN 16
58 #define HDMI_DEFAULT_REGM2 1
62 struct platform_device *pdev;
64 struct hdmi_ip_data ip_data;
67 struct regulator *vdda_hdmi_dac_reg;
73 struct omap_dss_output output;
77 * Logic for the below structure :
78 * user enters the CEA or VESA timings by specifying the HDMI/DVI code.
79 * There is a correspondence between CEA/VESA timing and code, please
80 * refer to section 6.3 in HDMI 1.3 specification for timing code.
82 * In the below structure, cea_vesa_timings corresponds to all OMAP4
83 * supported CEA and VESA timing values.code_cea corresponds to the CEA
84 * code, It is used to get the timing from cea_vesa_timing array.Similarly
85 * with code_vesa. Code_index is used for back mapping, that is once EDID
86 * is read from the TV, EDID is parsed to find the timing values and then
87 * map it to corresponding CEA or VESA index.
90 static const struct hdmi_config cea_timings[] = {
92 { 640, 480, 25200, 96, 16, 48, 2, 10, 33,
93 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
98 { 720, 480, 27027, 62, 16, 60, 6, 9, 30,
99 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
104 { 1280, 720, 74250, 40, 110, 220, 5, 5, 20,
105 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
110 { 1920, 540, 74250, 44, 88, 148, 5, 2, 15,
111 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
116 { 1440, 240, 27027, 124, 38, 114, 3, 4, 15,
117 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
122 { 1920, 1080, 148500, 44, 88, 148, 5, 4, 36,
123 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
128 { 720, 576, 27000, 64, 12, 68, 5, 5, 39,
129 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
134 { 1280, 720, 74250, 40, 440, 220, 5, 5, 20,
135 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
140 { 1920, 540, 74250, 44, 528, 148, 5, 2, 15,
141 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
146 { 1440, 288, 27000, 126, 24, 138, 3, 2, 19,
147 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
152 { 1440, 576, 54000, 128, 24, 136, 5, 5, 39,
153 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
158 { 1920, 1080, 148500, 44, 528, 148, 5, 4, 36,
159 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
164 { 1920, 1080, 74250, 44, 638, 148, 5, 4, 36,
165 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
170 { 2880, 480, 108108, 248, 64, 240, 6, 9, 30,
171 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
176 { 2880, 576, 108000, 256, 48, 272, 5, 5, 39,
177 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
183 static const struct hdmi_config vesa_timings[] = {
186 { 640, 480, 25175, 96, 16, 48, 2, 11, 31,
187 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
192 { 800, 600, 40000, 128, 40, 88, 4, 1, 23,
193 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
198 { 848, 480, 33750, 112, 16, 112, 8, 6, 23,
199 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
204 { 1280, 768, 79500, 128, 64, 192, 7, 3, 20,
205 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
210 { 1280, 800, 83500, 128, 72, 200, 6, 3, 22,
211 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
216 { 1360, 768, 85500, 112, 64, 256, 6, 3, 18,
217 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
222 { 1280, 960, 108000, 112, 96, 312, 3, 1, 36,
223 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
228 { 1280, 1024, 108000, 112, 48, 248, 3, 1, 38,
229 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
234 { 1024, 768, 65000, 136, 24, 160, 6, 3, 29,
235 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
240 { 1400, 1050, 121750, 144, 88, 232, 4, 3, 32,
241 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
246 { 1440, 900, 106500, 152, 80, 232, 6, 3, 25,
247 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
252 { 1680, 1050, 146250, 176 , 104, 280, 6, 3, 30,
253 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
258 { 1366, 768, 85500, 143, 70, 213, 3, 3, 24,
259 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
264 { 1920, 1080, 148500, 44, 148, 80, 5, 4, 36,
265 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
270 { 1280, 768, 68250, 32, 48, 80, 7, 3, 12,
271 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
276 { 1400, 1050, 101000, 32, 48, 80, 4, 3, 23,
277 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
282 { 1680, 1050, 119000, 32, 48, 80, 6, 3, 21,
283 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
288 { 1280, 800, 79500, 32, 48, 80, 6, 3, 14,
289 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
294 { 1280, 720, 74250, 40, 110, 220, 5, 5, 20,
295 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
300 { 1920, 1200, 154000, 32, 48, 80, 6, 3, 26,
301 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
307 static int hdmi_runtime_get(void)
311 DSSDBG("hdmi_runtime_get\n");
313 r = pm_runtime_get_sync(&hdmi.pdev->dev);
321 static void hdmi_runtime_put(void)
325 DSSDBG("hdmi_runtime_put\n");
327 r = pm_runtime_put_sync(&hdmi.pdev->dev);
328 WARN_ON(r < 0 && r != -ENOSYS);
331 static int __init hdmi_init_display(struct omap_dss_device *dssdev)
335 struct gpio gpios[] = {
336 { hdmi.ct_cp_hpd_gpio, GPIOF_OUT_INIT_LOW, "hdmi_ct_cp_hpd" },
337 { hdmi.ls_oe_gpio, GPIOF_OUT_INIT_LOW, "hdmi_ls_oe" },
338 { hdmi.hpd_gpio, GPIOF_DIR_IN, "hdmi_hpd" },
341 DSSDBG("init_display\n");
343 dss_init_hdmi_ip_ops(&hdmi.ip_data, omapdss_get_version());
345 if (hdmi.vdda_hdmi_dac_reg == NULL) {
346 struct regulator *reg;
348 reg = devm_regulator_get(&hdmi.pdev->dev, "vdda_hdmi_dac");
350 /* DT HACK: try VDAC to make omapdss work for o4 sdp/panda */
352 reg = devm_regulator_get(&hdmi.pdev->dev, "VDAC");
355 DSSERR("can't get VDDA_HDMI_DAC regulator\n");
359 hdmi.vdda_hdmi_dac_reg = reg;
362 r = gpio_request_array(gpios, ARRAY_SIZE(gpios));
369 static void hdmi_uninit_display(struct omap_dss_device *dssdev)
371 DSSDBG("uninit_display\n");
373 gpio_free(hdmi.ct_cp_hpd_gpio);
374 gpio_free(hdmi.ls_oe_gpio);
375 gpio_free(hdmi.hpd_gpio);
378 static const struct hdmi_config *hdmi_find_timing(
379 const struct hdmi_config *timings_arr,
384 for (i = 0; i < len; i++) {
385 if (timings_arr[i].cm.code == hdmi.ip_data.cfg.cm.code)
386 return &timings_arr[i];
391 static const struct hdmi_config *hdmi_get_timings(void)
393 const struct hdmi_config *arr;
396 if (hdmi.ip_data.cfg.cm.mode == HDMI_DVI) {
398 len = ARRAY_SIZE(vesa_timings);
401 len = ARRAY_SIZE(cea_timings);
404 return hdmi_find_timing(arr, len);
407 static bool hdmi_timings_compare(struct omap_video_timings *timing1,
408 const struct omap_video_timings *timing2)
410 int timing1_vsync, timing1_hsync, timing2_vsync, timing2_hsync;
412 if ((DIV_ROUND_CLOSEST(timing2->pixel_clock, 1000) ==
413 DIV_ROUND_CLOSEST(timing1->pixel_clock, 1000)) &&
414 (timing2->x_res == timing1->x_res) &&
415 (timing2->y_res == timing1->y_res)) {
417 timing2_hsync = timing2->hfp + timing2->hsw + timing2->hbp;
418 timing1_hsync = timing1->hfp + timing1->hsw + timing1->hbp;
419 timing2_vsync = timing2->vfp + timing2->vsw + timing2->vbp;
420 timing1_vsync = timing2->vfp + timing2->vsw + timing2->vbp;
422 DSSDBG("timing1_hsync = %d timing1_vsync = %d"\
423 "timing2_hsync = %d timing2_vsync = %d\n",
424 timing1_hsync, timing1_vsync,
425 timing2_hsync, timing2_vsync);
427 if ((timing1_hsync == timing2_hsync) &&
428 (timing1_vsync == timing2_vsync)) {
435 static struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing)
438 struct hdmi_cm cm = {-1};
439 DSSDBG("hdmi_get_code\n");
441 for (i = 0; i < ARRAY_SIZE(cea_timings); i++) {
442 if (hdmi_timings_compare(timing, &cea_timings[i].timings)) {
443 cm = cea_timings[i].cm;
447 for (i = 0; i < ARRAY_SIZE(vesa_timings); i++) {
448 if (hdmi_timings_compare(timing, &vesa_timings[i].timings)) {
449 cm = vesa_timings[i].cm;
458 unsigned long hdmi_get_pixel_clock(void)
460 /* HDMI Pixel Clock in Mhz */
461 return hdmi.ip_data.cfg.timings.pixel_clock * 1000;
464 static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy,
465 struct hdmi_pll_info *pi)
467 unsigned long clkin, refclk;
470 clkin = clk_get_rate(hdmi.sys_clk) / 10000;
472 * Input clock is predivided by N + 1
473 * out put of which is reference clk
475 if (dssdev->clocks.hdmi.regn == 0)
476 pi->regn = HDMI_DEFAULT_REGN;
478 pi->regn = dssdev->clocks.hdmi.regn;
480 refclk = clkin / pi->regn;
482 if (dssdev->clocks.hdmi.regm2 == 0)
483 pi->regm2 = HDMI_DEFAULT_REGM2;
485 pi->regm2 = dssdev->clocks.hdmi.regm2;
488 * multiplier is pixel_clk/ref_clk
489 * Multiplying by 100 to avoid fractional part removal
491 pi->regm = phy * pi->regm2 / refclk;
494 * fractional multiplier is remainder of the difference between
495 * multiplier and actual phy(required pixel clock thus should be
496 * multiplied by 2^18(262144) divided by the reference clock
498 mf = (phy - pi->regm / pi->regm2 * refclk) * 262144;
499 pi->regmf = pi->regm2 * mf / refclk;
502 * Dcofreq should be set to 1 if required pixel clock
503 * is greater than 1000MHz
505 pi->dcofreq = phy > 1000 * 100;
506 pi->regsd = ((pi->regm * clkin / 10) / (pi->regn * 250) + 5) / 10;
508 /* Set the reference clock to sysclk reference */
509 pi->refsel = HDMI_REFSEL_SYSCLK;
511 DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf);
512 DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd);
515 static int hdmi_power_on_core(struct omap_dss_device *dssdev)
519 gpio_set_value(hdmi.ct_cp_hpd_gpio, 1);
520 gpio_set_value(hdmi.ls_oe_gpio, 1);
522 /* wait 300us after CT_CP_HPD for the 5V power output to reach 90% */
525 r = regulator_enable(hdmi.vdda_hdmi_dac_reg);
527 goto err_vdac_enable;
529 r = hdmi_runtime_get();
531 goto err_runtime_get;
533 /* Make selection of HDMI in DSS */
534 dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK);
539 regulator_disable(hdmi.vdda_hdmi_dac_reg);
541 gpio_set_value(hdmi.ct_cp_hpd_gpio, 0);
542 gpio_set_value(hdmi.ls_oe_gpio, 0);
546 static void hdmi_power_off_core(struct omap_dss_device *dssdev)
549 regulator_disable(hdmi.vdda_hdmi_dac_reg);
550 gpio_set_value(hdmi.ct_cp_hpd_gpio, 0);
551 gpio_set_value(hdmi.ls_oe_gpio, 0);
554 static int hdmi_power_on_full(struct omap_dss_device *dssdev)
557 struct omap_video_timings *p;
558 struct omap_overlay_manager *mgr = dssdev->output->manager;
561 r = hdmi_power_on_core(dssdev);
565 dss_mgr_disable(mgr);
567 p = &hdmi.ip_data.cfg.timings;
569 DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res);
571 phy = p->pixel_clock;
573 hdmi_compute_pll(dssdev, phy, &hdmi.ip_data.pll_data);
575 hdmi.ip_data.ops->video_disable(&hdmi.ip_data);
577 /* config the PLL and PHY hdmi_set_pll_pwrfirst */
578 r = hdmi.ip_data.ops->pll_enable(&hdmi.ip_data);
580 DSSDBG("Failed to lock PLL\n");
584 r = hdmi.ip_data.ops->phy_enable(&hdmi.ip_data);
586 DSSDBG("Failed to start PHY\n");
590 hdmi.ip_data.ops->video_configure(&hdmi.ip_data);
592 /* bypass TV gamma table */
593 dispc_enable_gamma_table(0);
596 dss_mgr_set_timings(mgr, p);
598 r = hdmi.ip_data.ops->video_enable(&hdmi.ip_data);
602 r = dss_mgr_enable(mgr);
609 hdmi.ip_data.ops->video_disable(&hdmi.ip_data);
611 hdmi.ip_data.ops->phy_disable(&hdmi.ip_data);
613 hdmi.ip_data.ops->pll_disable(&hdmi.ip_data);
615 hdmi_power_off_core(dssdev);
619 static void hdmi_power_off_full(struct omap_dss_device *dssdev)
621 struct omap_overlay_manager *mgr = dssdev->output->manager;
623 dss_mgr_disable(mgr);
625 hdmi.ip_data.ops->video_disable(&hdmi.ip_data);
626 hdmi.ip_data.ops->phy_disable(&hdmi.ip_data);
627 hdmi.ip_data.ops->pll_disable(&hdmi.ip_data);
629 hdmi_power_off_core(dssdev);
632 int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev,
633 struct omap_video_timings *timings)
637 cm = hdmi_get_code(timings);
646 void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev,
647 struct omap_video_timings *timings)
650 const struct hdmi_config *t;
652 mutex_lock(&hdmi.lock);
654 cm = hdmi_get_code(timings);
655 hdmi.ip_data.cfg.cm = cm;
657 t = hdmi_get_timings();
659 hdmi.ip_data.cfg = *t;
661 mutex_unlock(&hdmi.lock);
664 static void hdmi_dump_regs(struct seq_file *s)
666 mutex_lock(&hdmi.lock);
668 if (hdmi_runtime_get()) {
669 mutex_unlock(&hdmi.lock);
673 hdmi.ip_data.ops->dump_wrapper(&hdmi.ip_data, s);
674 hdmi.ip_data.ops->dump_pll(&hdmi.ip_data, s);
675 hdmi.ip_data.ops->dump_phy(&hdmi.ip_data, s);
676 hdmi.ip_data.ops->dump_core(&hdmi.ip_data, s);
679 mutex_unlock(&hdmi.lock);
682 int omapdss_hdmi_read_edid(u8 *buf, int len)
686 mutex_lock(&hdmi.lock);
688 r = hdmi_runtime_get();
691 r = hdmi.ip_data.ops->read_edid(&hdmi.ip_data, buf, len);
694 mutex_unlock(&hdmi.lock);
699 bool omapdss_hdmi_detect(void)
703 mutex_lock(&hdmi.lock);
705 r = hdmi_runtime_get();
708 r = hdmi.ip_data.ops->detect(&hdmi.ip_data);
711 mutex_unlock(&hdmi.lock);
716 int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev)
718 struct omap_dss_output *out = dssdev->output;
721 DSSDBG("ENTER hdmi_display_enable\n");
723 mutex_lock(&hdmi.lock);
725 if (out == NULL || out->manager == NULL) {
726 DSSERR("failed to enable display: no output/manager\n");
731 hdmi.ip_data.hpd_gpio = hdmi.hpd_gpio;
733 r = omap_dss_start_device(dssdev);
735 DSSERR("failed to start device\n");
739 r = hdmi_power_on_full(dssdev);
741 DSSERR("failed to power on device\n");
745 mutex_unlock(&hdmi.lock);
749 omap_dss_stop_device(dssdev);
751 mutex_unlock(&hdmi.lock);
755 void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev)
757 DSSDBG("Enter hdmi_display_disable\n");
759 mutex_lock(&hdmi.lock);
761 hdmi_power_off_full(dssdev);
763 omap_dss_stop_device(dssdev);
765 mutex_unlock(&hdmi.lock);
768 int omapdss_hdmi_core_enable(struct omap_dss_device *dssdev)
772 DSSDBG("ENTER omapdss_hdmi_core_enable\n");
774 mutex_lock(&hdmi.lock);
776 hdmi.ip_data.hpd_gpio = hdmi.hpd_gpio;
778 r = hdmi_power_on_core(dssdev);
780 DSSERR("failed to power on device\n");
784 mutex_unlock(&hdmi.lock);
788 mutex_unlock(&hdmi.lock);
792 void omapdss_hdmi_core_disable(struct omap_dss_device *dssdev)
794 DSSDBG("Enter omapdss_hdmi_core_disable\n");
796 mutex_lock(&hdmi.lock);
798 hdmi_power_off_core(dssdev);
800 mutex_unlock(&hdmi.lock);
803 static int hdmi_get_clocks(struct platform_device *pdev)
807 clk = clk_get(&pdev->dev, "sys_clk");
809 DSSERR("can't get sys_clk\n");
818 static void hdmi_put_clocks(void)
821 clk_put(hdmi.sys_clk);
824 #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
825 int hdmi_compute_acr(u32 sample_freq, u32 *n, u32 *cts)
828 bool deep_color_correct = false;
829 u32 pclk = hdmi.ip_data.cfg.timings.pixel_clock;
831 if (n == NULL || cts == NULL)
834 /* TODO: When implemented, query deep color mode here. */
838 * When using deep color, the default N value (as in the HDMI
839 * specification) yields to an non-integer CTS. Hence, we
840 * modify it while keeping the restrictions described in
841 * section 7.2.1 of the HDMI 1.4a specification.
843 switch (sample_freq) {
848 if (deep_color == 125)
849 if (pclk == 27027 || pclk == 74250)
850 deep_color_correct = true;
851 if (deep_color == 150)
853 deep_color_correct = true;
858 if (deep_color == 125)
860 deep_color_correct = true;
866 if (deep_color_correct) {
867 switch (sample_freq) {
893 switch (sample_freq) {
919 /* Calculate CTS. See HDMI 1.3a or 1.4a specifications */
920 *cts = pclk * (*n / 128) * deep_color / (sample_freq / 10);
925 int hdmi_audio_enable(void)
927 DSSDBG("audio_enable\n");
929 return hdmi.ip_data.ops->audio_enable(&hdmi.ip_data);
932 void hdmi_audio_disable(void)
934 DSSDBG("audio_disable\n");
936 hdmi.ip_data.ops->audio_disable(&hdmi.ip_data);
939 int hdmi_audio_start(void)
941 DSSDBG("audio_start\n");
943 return hdmi.ip_data.ops->audio_start(&hdmi.ip_data);
946 void hdmi_audio_stop(void)
948 DSSDBG("audio_stop\n");
950 hdmi.ip_data.ops->audio_stop(&hdmi.ip_data);
953 bool hdmi_mode_has_audio(void)
955 if (hdmi.ip_data.cfg.cm.mode == HDMI_HDMI)
961 int hdmi_audio_config(struct omap_dss_audio *audio)
963 return hdmi.ip_data.ops->audio_config(&hdmi.ip_data, audio);
968 static struct omap_dss_device * __init hdmi_find_dssdev(struct platform_device *pdev)
970 struct omap_dss_board_info *pdata = pdev->dev.platform_data;
971 const char *def_disp_name = omapdss_get_default_display_name();
972 struct omap_dss_device *def_dssdev;
977 for (i = 0; i < pdata->num_devices; ++i) {
978 struct omap_dss_device *dssdev = pdata->devices[i];
980 if (dssdev->type != OMAP_DISPLAY_TYPE_HDMI)
983 if (def_dssdev == NULL)
986 if (def_disp_name != NULL &&
987 strcmp(dssdev->name, def_disp_name) == 0) {
996 static void __init hdmi_probe_pdata(struct platform_device *pdev)
998 struct omap_dss_device *plat_dssdev;
999 struct omap_dss_device *dssdev;
1000 struct omap_dss_hdmi_data *priv;
1003 plat_dssdev = hdmi_find_dssdev(pdev);
1008 dssdev = dss_alloc_and_init_device(&pdev->dev);
1012 dss_copy_device_pdata(dssdev, plat_dssdev);
1014 priv = dssdev->data;
1016 hdmi.ct_cp_hpd_gpio = priv->ct_cp_hpd_gpio;
1017 hdmi.ls_oe_gpio = priv->ls_oe_gpio;
1018 hdmi.hpd_gpio = priv->hpd_gpio;
1020 dssdev->channel = OMAP_DSS_CHANNEL_DIGIT;
1022 r = hdmi_init_display(dssdev);
1024 DSSERR("device %s init failed: %d\n", dssdev->name, r);
1025 dss_put_device(dssdev);
1029 r = omapdss_output_set_device(&hdmi.output, dssdev);
1031 DSSERR("failed to connect output to new device: %s\n",
1033 dss_put_device(dssdev);
1037 r = dss_add_device(dssdev);
1039 DSSERR("device %s register failed: %d\n", dssdev->name, r);
1040 omapdss_output_unset_device(&hdmi.output);
1041 hdmi_uninit_display(dssdev);
1042 dss_put_device(dssdev);
1047 static void __init hdmi_init_output(struct platform_device *pdev)
1049 struct omap_dss_output *out = &hdmi.output;
1052 out->id = OMAP_DSS_OUTPUT_HDMI;
1053 out->type = OMAP_DISPLAY_TYPE_HDMI;
1055 dss_register_output(out);
1058 static void __exit hdmi_uninit_output(struct platform_device *pdev)
1060 struct omap_dss_output *out = &hdmi.output;
1062 dss_unregister_output(out);
1065 /* HDMI HW IP initialisation */
1066 static int __init omapdss_hdmihw_probe(struct platform_device *pdev)
1068 struct resource *res;
1073 mutex_init(&hdmi.lock);
1074 mutex_init(&hdmi.ip_data.lock);
1076 res = platform_get_resource(hdmi.pdev, IORESOURCE_MEM, 0);
1078 DSSERR("can't get IORESOURCE_MEM HDMI\n");
1082 /* Base address taken from platform */
1083 hdmi.ip_data.base_wp = devm_ioremap_resource(&pdev->dev, res);
1084 if (IS_ERR(hdmi.ip_data.base_wp))
1085 return PTR_ERR(hdmi.ip_data.base_wp);
1087 r = hdmi_get_clocks(pdev);
1089 DSSERR("can't get clocks\n");
1093 pm_runtime_enable(&pdev->dev);
1095 hdmi.ip_data.core_sys_offset = HDMI_CORE_SYS;
1096 hdmi.ip_data.core_av_offset = HDMI_CORE_AV;
1097 hdmi.ip_data.pll_offset = HDMI_PLLCTRL;
1098 hdmi.ip_data.phy_offset = HDMI_PHY;
1100 r = hdmi_panel_init();
1102 DSSERR("can't init panel\n");
1103 goto err_panel_init;
1106 dss_debugfs_create_file("hdmi", hdmi_dump_regs);
1108 hdmi_init_output(pdev);
1110 hdmi_probe_pdata(pdev);
1119 static int __exit hdmi_remove_child(struct device *dev, void *data)
1121 struct omap_dss_device *dssdev = to_dss_device(dev);
1122 hdmi_uninit_display(dssdev);
1126 static int __exit omapdss_hdmihw_remove(struct platform_device *pdev)
1128 device_for_each_child(&pdev->dev, NULL, hdmi_remove_child);
1130 dss_unregister_child_devices(&pdev->dev);
1134 hdmi_uninit_output(pdev);
1136 pm_runtime_disable(&pdev->dev);
1143 static int hdmi_runtime_suspend(struct device *dev)
1145 clk_disable_unprepare(hdmi.sys_clk);
1147 dispc_runtime_put();
1152 static int hdmi_runtime_resume(struct device *dev)
1156 r = dispc_runtime_get();
1160 clk_prepare_enable(hdmi.sys_clk);
1165 static const struct dev_pm_ops hdmi_pm_ops = {
1166 .runtime_suspend = hdmi_runtime_suspend,
1167 .runtime_resume = hdmi_runtime_resume,
1170 static struct platform_driver omapdss_hdmihw_driver = {
1171 .remove = __exit_p(omapdss_hdmihw_remove),
1173 .name = "omapdss_hdmi",
1174 .owner = THIS_MODULE,
1179 int __init hdmi_init_platform_driver(void)
1181 return platform_driver_probe(&omapdss_hdmihw_driver, omapdss_hdmihw_probe);
1184 void __exit hdmi_uninit_platform_driver(void)
1186 platform_driver_unregister(&omapdss_hdmihw_driver);