4 * HDMI interface DSS driver setting for TI's OMAP4 family of processor.
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
7 * Mythri pk <mythripk@ti.com>
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
22 #define DSS_SUBSYS_NAME "HDMI"
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/err.h>
28 #include <linux/interrupt.h>
29 #include <linux/mutex.h>
30 #include <linux/delay.h>
31 #include <linux/string.h>
32 #include <linux/platform_device.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/clk.h>
35 #include <video/omapdss.h>
36 #if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
37 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
38 #include <sound/soc.h>
39 #include <sound/pcm_params.h>
40 #include "ti_hdmi_4xxx_ip.h"
45 #include "dss_features.h"
48 #define HDMI_CORE_SYS 0x400
49 #define HDMI_CORE_AV 0x900
50 #define HDMI_PLLCTRL 0x200
51 #define HDMI_PHY 0x300
53 /* HDMI EDID Length move this */
54 #define HDMI_EDID_MAX_LENGTH 256
55 #define EDID_TIMING_DESCRIPTOR_SIZE 0x12
56 #define EDID_DESCRIPTOR_BLOCK0_ADDRESS 0x36
57 #define EDID_DESCRIPTOR_BLOCK1_ADDRESS 0x80
58 #define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR 4
59 #define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR 4
61 #define OMAP_HDMI_TIMINGS_NB 34
63 #define HDMI_DEFAULT_REGN 16
64 #define HDMI_DEFAULT_REGM2 1
68 struct omap_display_platform_data *pdata;
69 struct platform_device *pdev;
70 struct hdmi_ip_data ip_data;
78 * Logic for the below structure :
79 * user enters the CEA or VESA timings by specifying the HDMI/DVI code.
80 * There is a correspondence between CEA/VESA timing and code, please
81 * refer to section 6.3 in HDMI 1.3 specification for timing code.
83 * In the below structure, cea_vesa_timings corresponds to all OMAP4
84 * supported CEA and VESA timing values.code_cea corresponds to the CEA
85 * code, It is used to get the timing from cea_vesa_timing array.Similarly
86 * with code_vesa. Code_index is used for back mapping, that is once EDID
87 * is read from the TV, EDID is parsed to find the timing values and then
88 * map it to corresponding CEA or VESA index.
91 static const struct hdmi_timings cea_vesa_timings[OMAP_HDMI_TIMINGS_NB] = {
92 { {640, 480, 25200, 96, 16, 48, 2, 10, 33} , 0 , 0},
93 { {1280, 720, 74250, 40, 440, 220, 5, 5, 20}, 1, 1},
94 { {1280, 720, 74250, 40, 110, 220, 5, 5, 20}, 1, 1},
95 { {720, 480, 27027, 62, 16, 60, 6, 9, 30}, 0, 0},
96 { {2880, 576, 108000, 256, 48, 272, 5, 5, 39}, 0, 0},
97 { {1440, 240, 27027, 124, 38, 114, 3, 4, 15}, 0, 0},
98 { {1440, 288, 27000, 126, 24, 138, 3, 2, 19}, 0, 0},
99 { {1920, 540, 74250, 44, 528, 148, 5, 2, 15}, 1, 1},
100 { {1920, 540, 74250, 44, 88, 148, 5, 2, 15}, 1, 1},
101 { {1920, 1080, 148500, 44, 88, 148, 5, 4, 36}, 1, 1},
102 { {720, 576, 27000, 64, 12, 68, 5, 5, 39}, 0, 0},
103 { {1440, 576, 54000, 128, 24, 136, 5, 5, 39}, 0, 0},
104 { {1920, 1080, 148500, 44, 528, 148, 5, 4, 36}, 1, 1},
105 { {2880, 480, 108108, 248, 64, 240, 6, 9, 30}, 0, 0},
106 { {1920, 1080, 74250, 44, 638, 148, 5, 4, 36}, 1, 1},
108 { {640, 480, 25175, 96, 16, 48, 2 , 11, 31}, 0, 0},
109 { {800, 600, 40000, 128, 40, 88, 4 , 1, 23}, 1, 1},
110 { {848, 480, 33750, 112, 16, 112, 8 , 6, 23}, 1, 1},
111 { {1280, 768, 79500, 128, 64, 192, 7 , 3, 20}, 1, 0},
112 { {1280, 800, 83500, 128, 72, 200, 6 , 3, 22}, 1, 0},
113 { {1360, 768, 85500, 112, 64, 256, 6 , 3, 18}, 1, 1},
114 { {1280, 960, 108000, 112, 96, 312, 3 , 1, 36}, 1, 1},
115 { {1280, 1024, 108000, 112, 48, 248, 3 , 1, 38}, 1, 1},
116 { {1024, 768, 65000, 136, 24, 160, 6, 3, 29}, 0, 0},
117 { {1400, 1050, 121750, 144, 88, 232, 4, 3, 32}, 1, 0},
118 { {1440, 900, 106500, 152, 80, 232, 6, 3, 25}, 1, 0},
119 { {1680, 1050, 146250, 176 , 104, 280, 6, 3, 30}, 1, 0},
120 { {1366, 768, 85500, 143, 70, 213, 3, 3, 24}, 1, 1},
121 { {1920, 1080, 148500, 44, 148, 80, 5, 4, 36}, 1, 1},
122 { {1280, 768, 68250, 32, 48, 80, 7, 3, 12}, 0, 1},
123 { {1400, 1050, 101000, 32, 48, 80, 4, 3, 23}, 0, 1},
124 { {1680, 1050, 119000, 32, 48, 80, 6, 3, 21}, 0, 1},
125 { {1280, 800, 79500, 32, 48, 80, 6, 3, 14}, 0, 1},
126 { {1280, 720, 74250, 40, 110, 220, 5, 5, 20}, 1, 1}
130 * This is a static mapping array which maps the timing values
131 * with corresponding CEA / VESA code
133 static const int code_index[OMAP_HDMI_TIMINGS_NB] = {
134 1, 19, 4, 2, 37, 6, 21, 20, 5, 16, 17, 29, 31, 35, 32,
135 /* <--15 CEA 17--> vesa*/
136 4, 9, 0xE, 0x17, 0x1C, 0x27, 0x20, 0x23, 0x10, 0x2A,
137 0X2F, 0x3A, 0X51, 0X52, 0x16, 0x29, 0x39, 0x1B
141 * This is reverse static mapping which maps the CEA / VESA code
142 * to the corresponding timing values
144 static const int code_cea[39] = {
145 -1, 0, 3, 3, 2, 8, 5, 5, -1, -1,
146 -1, -1, -1, -1, -1, -1, 9, 10, 10, 1,
147 7, 6, 6, -1, -1, -1, -1, -1, -1, 11,
148 11, 12, 14, -1, -1, 13, 13, 4, 4
151 static const int code_vesa[85] = {
152 -1, -1, -1, -1, 15, -1, -1, -1, -1, 16,
153 -1, -1, -1, -1, 17, -1, 23, -1, -1, -1,
154 -1, -1, 29, 18, -1, -1, -1, 32, 19, -1,
155 -1, -1, 21, -1, -1, 22, -1, -1, -1, 20,
156 -1, 30, 24, -1, -1, -1, -1, 25, -1, -1,
157 -1, -1, -1, -1, -1, -1, -1, 31, 26, -1,
158 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
159 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
162 static int hdmi_runtime_get(void)
166 DSSDBG("hdmi_runtime_get\n");
168 r = pm_runtime_get_sync(&hdmi.pdev->dev);
170 return r < 0 ? r : 0;
173 static void hdmi_runtime_put(void)
177 DSSDBG("hdmi_runtime_put\n");
179 r = pm_runtime_put(&hdmi.pdev->dev);
183 int hdmi_init_display(struct omap_dss_device *dssdev)
185 DSSDBG("init_display\n");
187 dss_init_hdmi_ip_ops(&hdmi.ip_data);
191 static int get_timings_index(void)
196 code = code_vesa[hdmi.code];
198 code = code_cea[hdmi.code];
201 /* HDMI code 4 corresponds to 640 * 480 VGA */
203 /* DVI mode 1 corresponds to HDMI 0 to DVI */
204 hdmi.mode = HDMI_DVI;
206 code = code_vesa[hdmi.code];
211 static struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing)
213 int i = 0, code = -1, temp_vsync = 0, temp_hsync = 0;
214 int timing_vsync = 0, timing_hsync = 0;
215 struct hdmi_video_timings temp;
216 struct hdmi_cm cm = {-1};
217 DSSDBG("hdmi_get_code\n");
219 for (i = 0; i < OMAP_HDMI_TIMINGS_NB; i++) {
220 temp = cea_vesa_timings[i].timings;
221 if ((temp.pixel_clock == timing->pixel_clock) &&
222 (temp.x_res == timing->x_res) &&
223 (temp.y_res == timing->y_res)) {
225 temp_hsync = temp.hfp + temp.hsw + temp.hbp;
226 timing_hsync = timing->hfp + timing->hsw + timing->hbp;
227 temp_vsync = temp.vfp + temp.vsw + temp.vbp;
228 timing_vsync = timing->vfp + timing->vsw + timing->vbp;
230 DSSDBG("temp_hsync = %d , temp_vsync = %d"
231 "timing_hsync = %d, timing_vsync = %d\n",
232 temp_hsync, temp_hsync,
233 timing_hsync, timing_vsync);
235 if ((temp_hsync == timing_hsync) &&
236 (temp_vsync == timing_vsync)) {
238 cm.code = code_index[i];
243 DSSDBG("Hdmi_code = %d mode = %d\n",
253 static void update_hdmi_timings(struct hdmi_config *cfg,
254 struct omap_video_timings *timings, int code)
256 cfg->timings.timings.x_res = timings->x_res;
257 cfg->timings.timings.y_res = timings->y_res;
258 cfg->timings.timings.hbp = timings->hbp;
259 cfg->timings.timings.hfp = timings->hfp;
260 cfg->timings.timings.hsw = timings->hsw;
261 cfg->timings.timings.vbp = timings->vbp;
262 cfg->timings.timings.vfp = timings->vfp;
263 cfg->timings.timings.vsw = timings->vsw;
264 cfg->timings.timings.pixel_clock = timings->pixel_clock;
265 cfg->timings.vsync_pol = cea_vesa_timings[code].vsync_pol;
266 cfg->timings.hsync_pol = cea_vesa_timings[code].hsync_pol;
269 unsigned long hdmi_get_pixel_clock(void)
271 /* HDMI Pixel Clock in Mhz */
272 return hdmi.ip_data.cfg.timings.timings.pixel_clock * 1000;
275 static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy,
276 struct hdmi_pll_info *pi)
278 unsigned long clkin, refclk;
281 clkin = clk_get_rate(hdmi.sys_clk) / 10000;
283 * Input clock is predivided by N + 1
284 * out put of which is reference clk
286 if (dssdev->clocks.hdmi.regn == 0)
287 pi->regn = HDMI_DEFAULT_REGN;
289 pi->regn = dssdev->clocks.hdmi.regn;
291 refclk = clkin / pi->regn;
294 * multiplier is pixel_clk/ref_clk
295 * Multiplying by 100 to avoid fractional part removal
297 pi->regm = (phy * 100 / (refclk)) / 100;
299 if (dssdev->clocks.hdmi.regm2 == 0)
300 pi->regm2 = HDMI_DEFAULT_REGM2;
302 pi->regm2 = dssdev->clocks.hdmi.regm2;
305 * fractional multiplier is remainder of the difference between
306 * multiplier and actual phy(required pixel clock thus should be
307 * multiplied by 2^18(262144) divided by the reference clock
309 mf = (phy - pi->regm * refclk) * 262144;
310 pi->regmf = mf / (refclk);
313 * Dcofreq should be set to 1 if required pixel clock
314 * is greater than 1000MHz
316 pi->dcofreq = phy > 1000 * 100;
317 pi->regsd = ((pi->regm * clkin / 10) / (pi->regn * 250) + 5) / 10;
319 /* Set the reference clock to sysclk reference */
320 pi->refsel = HDMI_REFSEL_SYSCLK;
322 DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf);
323 DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd);
326 static int hdmi_power_on(struct omap_dss_device *dssdev)
329 struct omap_video_timings *p;
332 r = hdmi_runtime_get();
336 dss_mgr_disable(dssdev->manager);
338 p = &dssdev->panel.timings;
340 DSSDBG("hdmi_power_on x_res= %d y_res = %d\n",
341 dssdev->panel.timings.x_res,
342 dssdev->panel.timings.y_res);
344 code = get_timings_index();
345 update_hdmi_timings(&hdmi.ip_data.cfg, p, code);
347 phy = p->pixel_clock;
349 hdmi_compute_pll(dssdev, phy, &hdmi.ip_data.pll_data);
351 hdmi.ip_data.ops->video_enable(&hdmi.ip_data, 0);
353 /* config the PLL and PHY hdmi_set_pll_pwrfirst */
354 r = hdmi.ip_data.ops->pll_enable(&hdmi.ip_data);
356 DSSDBG("Failed to lock PLL\n");
360 r = hdmi.ip_data.ops->phy_enable(&hdmi.ip_data);
362 DSSDBG("Failed to start PHY\n");
366 hdmi.ip_data.cfg.cm.mode = hdmi.mode;
367 hdmi.ip_data.cfg.cm.code = hdmi.code;
368 hdmi.ip_data.ops->video_configure(&hdmi.ip_data);
370 /* Make selection of HDMI in DSS */
371 dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK);
373 /* Select the dispc clock source as PRCM clock, to ensure that it is not
374 * DSI PLL source as the clock selected by DSI PLL might not be
375 * sufficient for the resolution selected / that can be changed
376 * dynamically by user. This can be moved to single location , say
379 dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);
381 /* bypass TV gamma table */
382 dispc_enable_gamma_table(0);
385 dispc_set_digit_size(dssdev->panel.timings.x_res,
386 dssdev->panel.timings.y_res);
388 hdmi.ip_data.ops->video_enable(&hdmi.ip_data, 1);
390 r = dss_mgr_enable(dssdev->manager);
397 hdmi.ip_data.ops->video_enable(&hdmi.ip_data, 0);
398 hdmi.ip_data.ops->phy_disable(&hdmi.ip_data);
399 hdmi.ip_data.ops->pll_disable(&hdmi.ip_data);
405 static void hdmi_power_off(struct omap_dss_device *dssdev)
407 dss_mgr_disable(dssdev->manager);
409 hdmi.ip_data.ops->video_enable(&hdmi.ip_data, 0);
410 hdmi.ip_data.ops->phy_disable(&hdmi.ip_data);
411 hdmi.ip_data.ops->pll_disable(&hdmi.ip_data);
415 int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev,
416 struct omap_video_timings *timings)
420 cm = hdmi_get_code(timings);
429 void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev)
433 cm = hdmi_get_code(&dssdev->panel.timings);
437 if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) {
440 hdmi_power_off(dssdev);
442 r = hdmi_power_on(dssdev);
444 DSSERR("failed to power on device\n");
448 void hdmi_dump_regs(struct seq_file *s)
450 mutex_lock(&hdmi.lock);
452 if (hdmi_runtime_get())
455 hdmi.ip_data.ops->dump_wrapper(&hdmi.ip_data, s);
456 hdmi.ip_data.ops->dump_pll(&hdmi.ip_data, s);
457 hdmi.ip_data.ops->dump_phy(&hdmi.ip_data, s);
458 hdmi.ip_data.ops->dump_core(&hdmi.ip_data, s);
461 mutex_unlock(&hdmi.lock);
464 int omapdss_hdmi_read_edid(u8 *buf, int len)
468 mutex_lock(&hdmi.lock);
470 r = hdmi_runtime_get();
473 r = hdmi.ip_data.ops->read_edid(&hdmi.ip_data, buf, len);
476 mutex_unlock(&hdmi.lock);
481 bool omapdss_hdmi_detect(void)
485 mutex_lock(&hdmi.lock);
487 r = hdmi_runtime_get();
490 r = hdmi.ip_data.ops->detect(&hdmi.ip_data);
493 mutex_unlock(&hdmi.lock);
498 int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev)
502 DSSDBG("ENTER hdmi_display_enable\n");
504 mutex_lock(&hdmi.lock);
506 if (dssdev->manager == NULL) {
507 DSSERR("failed to enable display: no manager\n");
512 r = omap_dss_start_device(dssdev);
514 DSSERR("failed to start device\n");
518 if (dssdev->platform_enable) {
519 r = dssdev->platform_enable(dssdev);
521 DSSERR("failed to enable GPIO's\n");
526 r = hdmi_power_on(dssdev);
528 DSSERR("failed to power on device\n");
532 mutex_unlock(&hdmi.lock);
536 if (dssdev->platform_disable)
537 dssdev->platform_disable(dssdev);
539 omap_dss_stop_device(dssdev);
541 mutex_unlock(&hdmi.lock);
545 void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev)
547 DSSDBG("Enter hdmi_display_disable\n");
549 mutex_lock(&hdmi.lock);
551 hdmi_power_off(dssdev);
553 if (dssdev->platform_disable)
554 dssdev->platform_disable(dssdev);
556 omap_dss_stop_device(dssdev);
558 mutex_unlock(&hdmi.lock);
561 #if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
562 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
564 static int hdmi_audio_trigger(struct snd_pcm_substream *substream, int cmd,
565 struct snd_soc_dai *dai)
567 struct snd_soc_pcm_runtime *rtd = substream->private_data;
568 struct snd_soc_codec *codec = rtd->codec;
569 struct platform_device *pdev = to_platform_device(codec->dev);
570 struct hdmi_ip_data *ip_data = snd_soc_codec_get_drvdata(codec);
573 if (!(ip_data->ops) && !(ip_data->ops->audio_enable)) {
574 dev_err(&pdev->dev, "Cannot enable/disable audio\n");
579 case SNDRV_PCM_TRIGGER_START:
580 case SNDRV_PCM_TRIGGER_RESUME:
581 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
582 ip_data->ops->audio_enable(ip_data, true);
584 case SNDRV_PCM_TRIGGER_STOP:
585 case SNDRV_PCM_TRIGGER_SUSPEND:
586 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
587 ip_data->ops->audio_enable(ip_data, false);
595 static int hdmi_audio_hw_params(struct snd_pcm_substream *substream,
596 struct snd_pcm_hw_params *params,
597 struct snd_soc_dai *dai)
599 struct snd_soc_pcm_runtime *rtd = substream->private_data;
600 struct snd_soc_codec *codec = rtd->codec;
601 struct hdmi_ip_data *ip_data = snd_soc_codec_get_drvdata(codec);
602 struct hdmi_audio_format audio_format;
603 struct hdmi_audio_dma audio_dma;
604 struct hdmi_core_audio_config core_cfg;
605 struct hdmi_core_infoframe_audio aud_if_cfg;
607 enum hdmi_core_audio_sample_freq sample_freq;
609 switch (params_format(params)) {
610 case SNDRV_PCM_FORMAT_S16_LE:
611 core_cfg.i2s_cfg.word_max_length =
612 HDMI_AUDIO_I2S_MAX_WORD_20BITS;
613 core_cfg.i2s_cfg.word_length = HDMI_AUDIO_I2S_CHST_WORD_16_BITS;
614 core_cfg.i2s_cfg.in_length_bits =
615 HDMI_AUDIO_I2S_INPUT_LENGTH_16;
616 core_cfg.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_LEFT;
617 audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_TWOSAMPLES;
618 audio_format.sample_size = HDMI_AUDIO_SAMPLE_16BITS;
619 audio_format.justification = HDMI_AUDIO_JUSTIFY_LEFT;
620 audio_dma.transfer_size = 0x10;
622 case SNDRV_PCM_FORMAT_S24_LE:
623 core_cfg.i2s_cfg.word_max_length =
624 HDMI_AUDIO_I2S_MAX_WORD_24BITS;
625 core_cfg.i2s_cfg.word_length = HDMI_AUDIO_I2S_CHST_WORD_24_BITS;
626 core_cfg.i2s_cfg.in_length_bits =
627 HDMI_AUDIO_I2S_INPUT_LENGTH_24;
628 audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_ONESAMPLE;
629 audio_format.sample_size = HDMI_AUDIO_SAMPLE_24BITS;
630 audio_format.justification = HDMI_AUDIO_JUSTIFY_RIGHT;
631 core_cfg.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_RIGHT;
632 audio_dma.transfer_size = 0x20;
638 switch (params_rate(params)) {
640 sample_freq = HDMI_AUDIO_FS_32000;
643 sample_freq = HDMI_AUDIO_FS_44100;
646 sample_freq = HDMI_AUDIO_FS_48000;
652 err = hdmi_config_audio_acr(ip_data, params_rate(params), &n, &cts);
656 /* Audio wrapper config */
657 audio_format.stereo_channels = HDMI_AUDIO_STEREO_ONECHANNEL;
658 audio_format.active_chnnls_msk = 0x03;
659 audio_format.type = HDMI_AUDIO_TYPE_LPCM;
660 audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST;
661 /* Disable start/stop signals of IEC 60958 blocks */
662 audio_format.en_sig_blk_strt_end = HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF;
664 audio_dma.block_size = 0xC0;
665 audio_dma.mode = HDMI_AUDIO_TRANSF_DMA;
666 audio_dma.fifo_threshold = 0x20; /* in number of samples */
668 hdmi_wp_audio_config_dma(ip_data, &audio_dma);
669 hdmi_wp_audio_config_format(ip_data, &audio_format);
674 core_cfg.i2s_cfg.en_high_bitrate_aud = false;
675 /* Only used with high bitrate audio */
676 core_cfg.i2s_cfg.cbit_order = false;
677 /* Serial data and word select should change on sck rising edge */
678 core_cfg.i2s_cfg.sck_edge_mode = HDMI_AUDIO_I2S_SCK_EDGE_RISING;
679 core_cfg.i2s_cfg.vbit = HDMI_AUDIO_I2S_VBIT_FOR_PCM;
680 /* Set I2S word select polarity */
681 core_cfg.i2s_cfg.ws_polarity = HDMI_AUDIO_I2S_WS_POLARITY_LOW_IS_LEFT;
682 core_cfg.i2s_cfg.direction = HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST;
683 /* Set serial data to word select shift. See Phillips spec. */
684 core_cfg.i2s_cfg.shift = HDMI_AUDIO_I2S_FIRST_BIT_SHIFT;
685 /* Enable one of the four available serial data channels */
686 core_cfg.i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN;
688 /* Core audio config */
689 core_cfg.freq_sample = sample_freq;
692 if (dss_has_feature(FEAT_HDMI_CTS_SWMODE)) {
693 core_cfg.aud_par_busclk = 0;
694 core_cfg.cts_mode = HDMI_AUDIO_CTS_MODE_SW;
695 core_cfg.use_mclk = false;
697 core_cfg.aud_par_busclk = (((128 * 31) - 1) << 8);
698 core_cfg.cts_mode = HDMI_AUDIO_CTS_MODE_HW;
699 core_cfg.use_mclk = true;
700 core_cfg.mclk_mode = HDMI_AUDIO_MCLK_128FS;
702 core_cfg.layout = HDMI_AUDIO_LAYOUT_2CH;
703 core_cfg.en_spdif = false;
704 /* Use sample frequency from channel status word */
705 core_cfg.fs_override = true;
706 /* Enable ACR packets */
707 core_cfg.en_acr_pkt = true;
708 /* Disable direct streaming digital audio */
709 core_cfg.en_dsd_audio = false;
710 /* Use parallel audio interface */
711 core_cfg.en_parallel_aud_input = true;
713 hdmi_core_audio_config(ip_data, &core_cfg);
717 * info frame audio see doc CEA861-D page 74
719 aud_if_cfg.db1_coding_type = HDMI_INFOFRAME_AUDIO_DB1CT_FROM_STREAM;
720 aud_if_cfg.db1_channel_count = 2;
721 aud_if_cfg.db2_sample_freq = HDMI_INFOFRAME_AUDIO_DB2SF_FROM_STREAM;
722 aud_if_cfg.db2_sample_size = HDMI_INFOFRAME_AUDIO_DB2SS_FROM_STREAM;
723 aud_if_cfg.db4_channel_alloc = 0x00;
724 aud_if_cfg.db5_downmix_inh = false;
725 aud_if_cfg.db5_lsv = 0;
727 hdmi_core_audio_infoframe_config(ip_data, &aud_if_cfg);
731 static int hdmi_audio_startup(struct snd_pcm_substream *substream,
732 struct snd_soc_dai *dai)
735 pr_err("Current video settings do not support audio.\n");
741 static int hdmi_audio_codec_probe(struct snd_soc_codec *codec)
743 struct hdmi_ip_data *priv = &hdmi.ip_data;
745 snd_soc_codec_set_drvdata(codec, priv);
749 static struct snd_soc_codec_driver hdmi_audio_codec_drv = {
750 .probe = hdmi_audio_codec_probe,
753 static struct snd_soc_dai_ops hdmi_audio_codec_ops = {
754 .hw_params = hdmi_audio_hw_params,
755 .trigger = hdmi_audio_trigger,
756 .startup = hdmi_audio_startup,
759 static struct snd_soc_dai_driver hdmi_codec_dai_drv = {
760 .name = "hdmi-audio-codec",
764 .rates = SNDRV_PCM_RATE_32000 |
765 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
766 .formats = SNDRV_PCM_FMTBIT_S16_LE |
767 SNDRV_PCM_FMTBIT_S24_LE,
769 .ops = &hdmi_audio_codec_ops,
773 static int hdmi_get_clocks(struct platform_device *pdev)
777 clk = clk_get(&pdev->dev, "sys_clk");
779 DSSERR("can't get sys_clk\n");
788 static void hdmi_put_clocks(void)
791 clk_put(hdmi.sys_clk);
794 /* HDMI HW IP initialisation */
795 static int omapdss_hdmihw_probe(struct platform_device *pdev)
797 struct resource *hdmi_mem;
800 hdmi.pdata = pdev->dev.platform_data;
803 mutex_init(&hdmi.lock);
805 hdmi_mem = platform_get_resource(hdmi.pdev, IORESOURCE_MEM, 0);
807 DSSERR("can't get IORESOURCE_MEM HDMI\n");
811 /* Base address taken from platform */
812 hdmi.ip_data.base_wp = ioremap(hdmi_mem->start,
813 resource_size(hdmi_mem));
814 if (!hdmi.ip_data.base_wp) {
815 DSSERR("can't ioremap WP\n");
819 r = hdmi_get_clocks(pdev);
821 iounmap(hdmi.ip_data.base_wp);
825 pm_runtime_enable(&pdev->dev);
827 hdmi.ip_data.core_sys_offset = HDMI_CORE_SYS;
828 hdmi.ip_data.core_av_offset = HDMI_CORE_AV;
829 hdmi.ip_data.pll_offset = HDMI_PLLCTRL;
830 hdmi.ip_data.phy_offset = HDMI_PHY;
834 #if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
835 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
837 /* Register ASoC codec DAI */
838 r = snd_soc_register_codec(&pdev->dev, &hdmi_audio_codec_drv,
839 &hdmi_codec_dai_drv, 1);
841 DSSERR("can't register ASoC HDMI audio codec\n");
848 static int omapdss_hdmihw_remove(struct platform_device *pdev)
852 #if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
853 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
854 snd_soc_unregister_codec(&pdev->dev);
857 pm_runtime_disable(&pdev->dev);
861 iounmap(hdmi.ip_data.base_wp);
866 static int hdmi_runtime_suspend(struct device *dev)
868 clk_disable(hdmi.sys_clk);
876 static int hdmi_runtime_resume(struct device *dev)
880 r = dss_runtime_get();
884 r = dispc_runtime_get();
889 clk_enable(hdmi.sys_clk);
899 static const struct dev_pm_ops hdmi_pm_ops = {
900 .runtime_suspend = hdmi_runtime_suspend,
901 .runtime_resume = hdmi_runtime_resume,
904 static struct platform_driver omapdss_hdmihw_driver = {
905 .probe = omapdss_hdmihw_probe,
906 .remove = omapdss_hdmihw_remove,
908 .name = "omapdss_hdmi",
909 .owner = THIS_MODULE,
914 int hdmi_init_platform_driver(void)
916 return platform_driver_register(&omapdss_hdmihw_driver);
919 void hdmi_uninit_platform_driver(void)
921 return platform_driver_unregister(&omapdss_hdmihw_driver);