2 * linux/drivers/video/omap2/dss/venc.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * VENC settings from TI's DSS driver
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
22 #define DSS_SUBSYS_NAME "VENC"
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/clk.h>
27 #include <linux/err.h>
29 #include <linux/mutex.h>
30 #include <linux/completion.h>
31 #include <linux/delay.h>
32 #include <linux/string.h>
33 #include <linux/seq_file.h>
34 #include <linux/platform_device.h>
35 #include <linux/regulator/consumer.h>
37 #include <plat/display.h>
43 #define VENC_REV_ID 0x00
44 #define VENC_STATUS 0x04
45 #define VENC_F_CONTROL 0x08
46 #define VENC_VIDOUT_CTRL 0x10
47 #define VENC_SYNC_CTRL 0x14
48 #define VENC_LLEN 0x1C
49 #define VENC_FLENS 0x20
50 #define VENC_HFLTR_CTRL 0x24
51 #define VENC_CC_CARR_WSS_CARR 0x28
52 #define VENC_C_PHASE 0x2C
53 #define VENC_GAIN_U 0x30
54 #define VENC_GAIN_V 0x34
55 #define VENC_GAIN_Y 0x38
56 #define VENC_BLACK_LEVEL 0x3C
57 #define VENC_BLANK_LEVEL 0x40
58 #define VENC_X_COLOR 0x44
59 #define VENC_M_CONTROL 0x48
60 #define VENC_BSTAMP_WSS_DATA 0x4C
61 #define VENC_S_CARR 0x50
62 #define VENC_LINE21 0x54
63 #define VENC_LN_SEL 0x58
64 #define VENC_L21__WC_CTL 0x5C
65 #define VENC_HTRIGGER_VTRIGGER 0x60
66 #define VENC_SAVID__EAVID 0x64
67 #define VENC_FLEN__FAL 0x68
68 #define VENC_LAL__PHASE_RESET 0x6C
69 #define VENC_HS_INT_START_STOP_X 0x70
70 #define VENC_HS_EXT_START_STOP_X 0x74
71 #define VENC_VS_INT_START_X 0x78
72 #define VENC_VS_INT_STOP_X__VS_INT_START_Y 0x7C
73 #define VENC_VS_INT_STOP_Y__VS_EXT_START_X 0x80
74 #define VENC_VS_EXT_STOP_X__VS_EXT_START_Y 0x84
75 #define VENC_VS_EXT_STOP_Y 0x88
76 #define VENC_AVID_START_STOP_X 0x90
77 #define VENC_AVID_START_STOP_Y 0x94
78 #define VENC_FID_INT_START_X__FID_INT_START_Y 0xA0
79 #define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X 0xA4
80 #define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y 0xA8
81 #define VENC_TVDETGP_INT_START_STOP_X 0xB0
82 #define VENC_TVDETGP_INT_START_STOP_Y 0xB4
83 #define VENC_GEN_CTRL 0xB8
84 #define VENC_OUTPUT_CONTROL 0xC4
85 #define VENC_OUTPUT_TEST 0xC8
86 #define VENC_DAC_B__DAC_C 0xC8
109 u32 htrigger_vtrigger;
112 u32 lal__phase_reset;
113 u32 hs_int_start_stop_x;
114 u32 hs_ext_start_stop_x;
116 u32 vs_int_stop_x__vs_int_start_y;
117 u32 vs_int_stop_y__vs_ext_start_x;
118 u32 vs_ext_stop_x__vs_ext_start_y;
120 u32 avid_start_stop_x;
121 u32 avid_start_stop_y;
122 u32 fid_int_start_x__fid_int_start_y;
123 u32 fid_int_offset_y__fid_ext_start_x;
124 u32 fid_ext_start_y__fid_ext_offset_y;
125 u32 tvdetgp_int_start_stop_x;
126 u32 tvdetgp_int_start_stop_y;
131 static const struct venc_config venc_config_pal_trm = {
135 .llen = 0x35F, /* 863 */
136 .flens = 0x270, /* 624 */
138 .cc_carr_wss_carr = 0x2F7225ED,
147 .bstamp_wss_data = 0x3F,
148 .s_carr = 0x2A098ACB,
150 .ln_sel = 0x01290015,
151 .l21__wc_ctl = 0x0000F603,
152 .htrigger_vtrigger = 0,
154 .savid__eavid = 0x06A70108,
155 .flen__fal = 0x00180270,
156 .lal__phase_reset = 0x00040135,
157 .hs_int_start_stop_x = 0x00880358,
158 .hs_ext_start_stop_x = 0x000F035F,
159 .vs_int_start_x = 0x01A70000,
160 .vs_int_stop_x__vs_int_start_y = 0x000001A7,
161 .vs_int_stop_y__vs_ext_start_x = 0x01AF0000,
162 .vs_ext_stop_x__vs_ext_start_y = 0x000101AF,
163 .vs_ext_stop_y = 0x00000025,
164 .avid_start_stop_x = 0x03530083,
165 .avid_start_stop_y = 0x026C002E,
166 .fid_int_start_x__fid_int_start_y = 0x0001008A,
167 .fid_int_offset_y__fid_ext_start_x = 0x002E0138,
168 .fid_ext_start_y__fid_ext_offset_y = 0x01380001,
170 .tvdetgp_int_start_stop_x = 0x00140001,
171 .tvdetgp_int_start_stop_y = 0x00010001,
172 .gen_ctrl = 0x00FF0000,
176 static const struct venc_config venc_config_ntsc_trm = {
183 .cc_carr_wss_carr = 0x043F2631,
192 .bstamp_wss_data = 0x38,
193 .s_carr = 0x21F07C1F,
195 .ln_sel = 0x01310011,
196 .l21__wc_ctl = 0x0000F003,
197 .htrigger_vtrigger = 0,
199 .savid__eavid = 0x069300F4,
200 .flen__fal = 0x0016020C,
201 .lal__phase_reset = 0x00060107,
202 .hs_int_start_stop_x = 0x008E0350,
203 .hs_ext_start_stop_x = 0x000F0359,
204 .vs_int_start_x = 0x01A00000,
205 .vs_int_stop_x__vs_int_start_y = 0x020701A0,
206 .vs_int_stop_y__vs_ext_start_x = 0x01AC0024,
207 .vs_ext_stop_x__vs_ext_start_y = 0x020D01AC,
208 .vs_ext_stop_y = 0x00000006,
209 .avid_start_stop_x = 0x03480078,
210 .avid_start_stop_y = 0x02060024,
211 .fid_int_start_x__fid_int_start_y = 0x0001008A,
212 .fid_int_offset_y__fid_ext_start_x = 0x01AC0106,
213 .fid_ext_start_y__fid_ext_offset_y = 0x01060006,
215 .tvdetgp_int_start_stop_x = 0x00140001,
216 .tvdetgp_int_start_stop_y = 0x00010001,
217 .gen_ctrl = 0x00F90000,
220 static const struct venc_config venc_config_pal_bdghi = {
228 .htrigger_vtrigger = 0,
229 .tvdetgp_int_start_stop_x = 0x00140001,
230 .tvdetgp_int_start_stop_y = 0x00010001,
231 .gen_ctrl = 0x00FB0000,
235 .cc_carr_wss_carr = 0x2F7625ED,
242 .m_control = 0<<2 | 1<<1,
243 .bstamp_wss_data = 0x42,
244 .s_carr = 0x2a098acb,
245 .l21__wc_ctl = 0<<13 | 0x16<<8 | 0<<0,
246 .savid__eavid = 0x06A70108,
247 .flen__fal = 23<<16 | 624<<0,
248 .lal__phase_reset = 2<<17 | 310<<0,
249 .hs_int_start_stop_x = 0x00920358,
250 .hs_ext_start_stop_x = 0x000F035F,
251 .vs_int_start_x = 0x1a7<<16,
252 .vs_int_stop_x__vs_int_start_y = 0x000601A7,
253 .vs_int_stop_y__vs_ext_start_x = 0x01AF0036,
254 .vs_ext_stop_x__vs_ext_start_y = 0x27101af,
255 .vs_ext_stop_y = 0x05,
256 .avid_start_stop_x = 0x03530082,
257 .avid_start_stop_y = 0x0270002E,
258 .fid_int_start_x__fid_int_start_y = 0x0005008A,
259 .fid_int_offset_y__fid_ext_start_x = 0x002E0138,
260 .fid_ext_start_y__fid_ext_offset_y = 0x01380005,
263 const struct omap_video_timings omap_dss_pal_timings = {
266 .pixel_clock = 13500,
274 EXPORT_SYMBOL(omap_dss_pal_timings);
276 const struct omap_video_timings omap_dss_ntsc_timings = {
279 .pixel_clock = 13500,
287 EXPORT_SYMBOL(omap_dss_ntsc_timings);
290 struct platform_device *pdev;
292 struct mutex venc_lock;
294 struct regulator *vdda_dac_reg;
297 static inline void venc_write_reg(int idx, u32 val)
299 __raw_writel(val, venc.base + idx);
302 static inline u32 venc_read_reg(int idx)
304 u32 l = __raw_readl(venc.base + idx);
308 static void venc_write_config(const struct venc_config *config)
310 DSSDBG("write venc conf\n");
312 venc_write_reg(VENC_LLEN, config->llen);
313 venc_write_reg(VENC_FLENS, config->flens);
314 venc_write_reg(VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr);
315 venc_write_reg(VENC_C_PHASE, config->c_phase);
316 venc_write_reg(VENC_GAIN_U, config->gain_u);
317 venc_write_reg(VENC_GAIN_V, config->gain_v);
318 venc_write_reg(VENC_GAIN_Y, config->gain_y);
319 venc_write_reg(VENC_BLACK_LEVEL, config->black_level);
320 venc_write_reg(VENC_BLANK_LEVEL, config->blank_level);
321 venc_write_reg(VENC_M_CONTROL, config->m_control);
322 venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data |
324 venc_write_reg(VENC_S_CARR, config->s_carr);
325 venc_write_reg(VENC_L21__WC_CTL, config->l21__wc_ctl);
326 venc_write_reg(VENC_SAVID__EAVID, config->savid__eavid);
327 venc_write_reg(VENC_FLEN__FAL, config->flen__fal);
328 venc_write_reg(VENC_LAL__PHASE_RESET, config->lal__phase_reset);
329 venc_write_reg(VENC_HS_INT_START_STOP_X, config->hs_int_start_stop_x);
330 venc_write_reg(VENC_HS_EXT_START_STOP_X, config->hs_ext_start_stop_x);
331 venc_write_reg(VENC_VS_INT_START_X, config->vs_int_start_x);
332 venc_write_reg(VENC_VS_INT_STOP_X__VS_INT_START_Y,
333 config->vs_int_stop_x__vs_int_start_y);
334 venc_write_reg(VENC_VS_INT_STOP_Y__VS_EXT_START_X,
335 config->vs_int_stop_y__vs_ext_start_x);
336 venc_write_reg(VENC_VS_EXT_STOP_X__VS_EXT_START_Y,
337 config->vs_ext_stop_x__vs_ext_start_y);
338 venc_write_reg(VENC_VS_EXT_STOP_Y, config->vs_ext_stop_y);
339 venc_write_reg(VENC_AVID_START_STOP_X, config->avid_start_stop_x);
340 venc_write_reg(VENC_AVID_START_STOP_Y, config->avid_start_stop_y);
341 venc_write_reg(VENC_FID_INT_START_X__FID_INT_START_Y,
342 config->fid_int_start_x__fid_int_start_y);
343 venc_write_reg(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X,
344 config->fid_int_offset_y__fid_ext_start_x);
345 venc_write_reg(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y,
346 config->fid_ext_start_y__fid_ext_offset_y);
348 venc_write_reg(VENC_DAC_B__DAC_C, venc_read_reg(VENC_DAC_B__DAC_C));
349 venc_write_reg(VENC_VIDOUT_CTRL, config->vidout_ctrl);
350 venc_write_reg(VENC_HFLTR_CTRL, config->hfltr_ctrl);
351 venc_write_reg(VENC_X_COLOR, config->x_color);
352 venc_write_reg(VENC_LINE21, config->line21);
353 venc_write_reg(VENC_LN_SEL, config->ln_sel);
354 venc_write_reg(VENC_HTRIGGER_VTRIGGER, config->htrigger_vtrigger);
355 venc_write_reg(VENC_TVDETGP_INT_START_STOP_X,
356 config->tvdetgp_int_start_stop_x);
357 venc_write_reg(VENC_TVDETGP_INT_START_STOP_Y,
358 config->tvdetgp_int_start_stop_y);
359 venc_write_reg(VENC_GEN_CTRL, config->gen_ctrl);
360 venc_write_reg(VENC_F_CONTROL, config->f_control);
361 venc_write_reg(VENC_SYNC_CTRL, config->sync_ctrl);
364 static void venc_reset(void)
368 venc_write_reg(VENC_F_CONTROL, 1<<8);
369 while (venc_read_reg(VENC_F_CONTROL) & (1<<8)) {
371 DSSERR("Failed to reset venc\n");
376 /* the magical sleep that makes things work */
380 static void venc_enable_clocks(int enable)
383 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK | DSS_CLK_TVFCK |
386 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK | DSS_CLK_TVFCK |
390 static const struct venc_config *venc_timings_to_config(
391 struct omap_video_timings *timings)
393 if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0)
394 return &venc_config_pal_trm;
396 if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0)
397 return &venc_config_ntsc_trm;
402 static void venc_power_on(struct omap_dss_device *dssdev)
406 venc_enable_clocks(1);
409 venc_write_config(venc_timings_to_config(&dssdev->panel.timings));
411 dss_set_venc_output(dssdev->phy.venc.type);
412 dss_set_dac_pwrdn_bgz(1);
416 if (dssdev->phy.venc.type == OMAP_DSS_VENC_TYPE_COMPOSITE)
419 l |= (1 << 0) | (1 << 2);
421 if (dssdev->phy.venc.invert_polarity == false)
424 venc_write_reg(VENC_OUTPUT_CONTROL, l);
426 dispc_set_digit_size(dssdev->panel.timings.x_res,
427 dssdev->panel.timings.y_res/2);
429 regulator_enable(venc.vdda_dac_reg);
431 if (dssdev->platform_enable)
432 dssdev->platform_enable(dssdev);
434 dssdev->manager->enable(dssdev->manager);
437 static void venc_power_off(struct omap_dss_device *dssdev)
439 venc_write_reg(VENC_OUTPUT_CONTROL, 0);
440 dss_set_dac_pwrdn_bgz(0);
442 dssdev->manager->disable(dssdev->manager);
444 if (dssdev->platform_disable)
445 dssdev->platform_disable(dssdev);
447 regulator_disable(venc.vdda_dac_reg);
449 venc_enable_clocks(0);
457 static int venc_panel_probe(struct omap_dss_device *dssdev)
459 dssdev->panel.timings = omap_dss_pal_timings;
464 static void venc_panel_remove(struct omap_dss_device *dssdev)
468 static int venc_panel_enable(struct omap_dss_device *dssdev)
472 DSSDBG("venc_enable_display\n");
474 mutex_lock(&venc.venc_lock);
476 if (dssdev->state != OMAP_DSS_DISPLAY_DISABLED) {
481 venc_power_on(dssdev);
485 dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
487 /* wait couple of vsyncs until enabling the LCD */
491 mutex_unlock(&venc.venc_lock);
496 static void venc_panel_disable(struct omap_dss_device *dssdev)
498 DSSDBG("venc_disable_display\n");
500 mutex_lock(&venc.venc_lock);
502 if (dssdev->state == OMAP_DSS_DISPLAY_DISABLED)
505 if (dssdev->state == OMAP_DSS_DISPLAY_SUSPENDED) {
506 /* suspended is the same as disabled with venc */
507 dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
511 venc_power_off(dssdev);
513 /* wait at least 5 vsyncs after disabling the LCD */
516 dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
518 mutex_unlock(&venc.venc_lock);
521 static int venc_panel_suspend(struct omap_dss_device *dssdev)
523 venc_panel_disable(dssdev);
527 static int venc_panel_resume(struct omap_dss_device *dssdev)
529 return venc_panel_enable(dssdev);
532 static enum omap_dss_update_mode venc_get_update_mode(
533 struct omap_dss_device *dssdev)
535 return OMAP_DSS_UPDATE_AUTO;
538 static int venc_set_update_mode(struct omap_dss_device *dssdev,
539 enum omap_dss_update_mode mode)
541 if (mode != OMAP_DSS_UPDATE_AUTO)
546 static void venc_get_timings(struct omap_dss_device *dssdev,
547 struct omap_video_timings *timings)
549 *timings = dssdev->panel.timings;
552 static void venc_set_timings(struct omap_dss_device *dssdev,
553 struct omap_video_timings *timings)
555 DSSDBG("venc_set_timings\n");
557 /* Reset WSS data when the TV standard changes. */
558 if (memcmp(&dssdev->panel.timings, timings, sizeof(*timings)))
561 dssdev->panel.timings = *timings;
562 if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) {
563 /* turn the venc off and on to get new timings to use */
564 venc_panel_disable(dssdev);
565 venc_panel_enable(dssdev);
569 static int venc_check_timings(struct omap_dss_device *dssdev,
570 struct omap_video_timings *timings)
572 DSSDBG("venc_check_timings\n");
574 if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0)
577 if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0)
583 static u32 venc_get_wss(struct omap_dss_device *dssdev)
585 /* Invert due to VENC_L21_WC_CTL:INV=1 */
586 return (venc.wss_data >> 8) ^ 0xfffff;
589 static int venc_set_wss(struct omap_dss_device *dssdev, u32 wss)
591 const struct venc_config *config;
593 DSSDBG("venc_set_wss\n");
595 mutex_lock(&venc.venc_lock);
597 config = venc_timings_to_config(&dssdev->panel.timings);
599 /* Invert due to VENC_L21_WC_CTL:INV=1 */
600 venc.wss_data = (wss ^ 0xfffff) << 8;
602 venc_enable_clocks(1);
604 venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data |
607 venc_enable_clocks(0);
609 mutex_unlock(&venc.venc_lock);
614 static struct omap_dss_driver venc_driver = {
615 .probe = venc_panel_probe,
616 .remove = venc_panel_remove,
618 .enable = venc_panel_enable,
619 .disable = venc_panel_disable,
620 .suspend = venc_panel_suspend,
621 .resume = venc_panel_resume,
623 .get_resolution = omapdss_default_get_resolution,
624 .get_recommended_bpp = omapdss_default_get_recommended_bpp,
626 .set_update_mode = venc_set_update_mode,
627 .get_update_mode = venc_get_update_mode,
629 .get_timings = venc_get_timings,
630 .set_timings = venc_set_timings,
631 .check_timings = venc_check_timings,
633 .get_wss = venc_get_wss,
634 .set_wss = venc_set_wss,
638 .owner = THIS_MODULE,
643 int venc_init_display(struct omap_dss_device *dssdev)
645 DSSDBG("init_display\n");
647 if (venc.vdda_dac_reg == NULL) {
648 struct regulator *vdda_dac;
650 vdda_dac = regulator_get(&venc.pdev->dev, "vdda_dac");
652 if (IS_ERR(vdda_dac)) {
653 DSSERR("can't get VDDA_DAC regulator\n");
654 return PTR_ERR(vdda_dac);
657 venc.vdda_dac_reg = vdda_dac;
663 void venc_dump_regs(struct seq_file *s)
665 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, venc_read_reg(r))
667 venc_enable_clocks(1);
669 DUMPREG(VENC_F_CONTROL);
670 DUMPREG(VENC_VIDOUT_CTRL);
671 DUMPREG(VENC_SYNC_CTRL);
674 DUMPREG(VENC_HFLTR_CTRL);
675 DUMPREG(VENC_CC_CARR_WSS_CARR);
676 DUMPREG(VENC_C_PHASE);
677 DUMPREG(VENC_GAIN_U);
678 DUMPREG(VENC_GAIN_V);
679 DUMPREG(VENC_GAIN_Y);
680 DUMPREG(VENC_BLACK_LEVEL);
681 DUMPREG(VENC_BLANK_LEVEL);
682 DUMPREG(VENC_X_COLOR);
683 DUMPREG(VENC_M_CONTROL);
684 DUMPREG(VENC_BSTAMP_WSS_DATA);
685 DUMPREG(VENC_S_CARR);
686 DUMPREG(VENC_LINE21);
687 DUMPREG(VENC_LN_SEL);
688 DUMPREG(VENC_L21__WC_CTL);
689 DUMPREG(VENC_HTRIGGER_VTRIGGER);
690 DUMPREG(VENC_SAVID__EAVID);
691 DUMPREG(VENC_FLEN__FAL);
692 DUMPREG(VENC_LAL__PHASE_RESET);
693 DUMPREG(VENC_HS_INT_START_STOP_X);
694 DUMPREG(VENC_HS_EXT_START_STOP_X);
695 DUMPREG(VENC_VS_INT_START_X);
696 DUMPREG(VENC_VS_INT_STOP_X__VS_INT_START_Y);
697 DUMPREG(VENC_VS_INT_STOP_Y__VS_EXT_START_X);
698 DUMPREG(VENC_VS_EXT_STOP_X__VS_EXT_START_Y);
699 DUMPREG(VENC_VS_EXT_STOP_Y);
700 DUMPREG(VENC_AVID_START_STOP_X);
701 DUMPREG(VENC_AVID_START_STOP_Y);
702 DUMPREG(VENC_FID_INT_START_X__FID_INT_START_Y);
703 DUMPREG(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X);
704 DUMPREG(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y);
705 DUMPREG(VENC_TVDETGP_INT_START_STOP_X);
706 DUMPREG(VENC_TVDETGP_INT_START_STOP_Y);
707 DUMPREG(VENC_GEN_CTRL);
708 DUMPREG(VENC_OUTPUT_CONTROL);
709 DUMPREG(VENC_OUTPUT_TEST);
711 venc_enable_clocks(0);
716 /* VENC HW IP initialisation */
717 static int omap_venchw_probe(struct platform_device *pdev)
720 struct resource *venc_mem;
724 mutex_init(&venc.venc_lock);
728 venc_mem = platform_get_resource(venc.pdev, IORESOURCE_MEM, 0);
730 DSSERR("can't get IORESOURCE_MEM VENC\n");
733 venc.base = ioremap(venc_mem->start, resource_size(venc_mem));
735 DSSERR("can't ioremap VENC\n");
739 venc_enable_clocks(1);
741 rev_id = (u8)(venc_read_reg(VENC_REV_ID) & 0xff);
742 dev_dbg(&pdev->dev, "OMAP VENC rev %d\n", rev_id);
744 venc_enable_clocks(0);
746 return omap_dss_register_driver(&venc_driver);
749 static int omap_venchw_remove(struct platform_device *pdev)
751 if (venc.vdda_dac_reg != NULL) {
752 regulator_put(venc.vdda_dac_reg);
753 venc.vdda_dac_reg = NULL;
755 omap_dss_unregister_driver(&venc_driver);
761 static struct platform_driver omap_venchw_driver = {
762 .probe = omap_venchw_probe,
763 .remove = omap_venchw_remove,
765 .name = "omapdss_venc",
766 .owner = THIS_MODULE,
770 int venc_init_platform_driver(void)
772 if (cpu_is_omap44xx())
775 return platform_driver_register(&omap_venchw_driver);
778 void venc_uninit_platform_driver(void)
780 if (cpu_is_omap44xx())
783 return platform_driver_unregister(&omap_venchw_driver);