drivers/video/omap3_dss.c

   1 /*
   2  * (C) Copyright 2010
   3  * Texas Instruments, <www.ti.com>
   4  * Syed Mohammed Khasim <khasim@ti.com>
   5  *
   6  * Referred to Linux Kernel DSS driver files for OMAP3 by
   7  * Tomi Valkeinen from drivers/video/omap2/dss/
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation's version 2 and any
  15  * later version the License.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 #include <common.h>
  29 #include <asm/io.h>
  30 #include <asm/arch/dss.h>
  31 #include <video_fb.h>
  32
  33 /*
  34  * Configure VENC for a given Mode (NTSC / PAL)
  35  */
  36 void omap3_dss_venc_config(const struct venc_regs *venc_cfg,
  37                                 u32 height, u32 width)
  38 {
  39         struct venc_regs *venc = (struct venc_regs *) OMAP3_VENC_BASE;
  40         struct dss_regs *dss = (struct dss_regs *) OMAP3_DSS_BASE;
  41         struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE;
  42
  43         writel(venc_cfg->status, &venc->status);
  44         writel(venc_cfg->f_control, &venc->f_control);
  45         writel(venc_cfg->vidout_ctrl, &venc->vidout_ctrl);
  46         writel(venc_cfg->sync_ctrl, &venc->sync_ctrl);
  47         writel(venc_cfg->llen, &venc->llen);
  48         writel(venc_cfg->flens, &venc->flens);
  49         writel(venc_cfg->hfltr_ctrl, &venc->hfltr_ctrl);
  50         writel(venc_cfg->cc_carr_wss_carr, &venc->cc_carr_wss_carr);
  51         writel(venc_cfg->c_phase, &venc->c_phase);
  52         writel(venc_cfg->gain_u, &venc->gain_u);
  53         writel(venc_cfg->gain_v, &venc->gain_v);
  54         writel(venc_cfg->gain_y, &venc->gain_y);
  55         writel(venc_cfg->black_level, &venc->black_level);
  56         writel(venc_cfg->blank_level, &venc->blank_level);
  57         writel(venc_cfg->x_color, &venc->x_color);
  58         writel(venc_cfg->m_control, &venc->m_control);
  59         writel(venc_cfg->bstamp_wss_data, &venc->bstamp_wss_data);
  60         writel(venc_cfg->s_carr, &venc->s_carr);
  61         writel(venc_cfg->line21, &venc->line21);
  62         writel(venc_cfg->ln_sel, &venc->ln_sel);
  63         writel(venc_cfg->l21__wc_ctl, &venc->l21__wc_ctl);
  64         writel(venc_cfg->htrigger_vtrigger, &venc->htrigger_vtrigger);
  65         writel(venc_cfg->savid__eavid, &venc->savid__eavid);
  66         writel(venc_cfg->flen__fal, &venc->flen__fal);
  67         writel(venc_cfg->lal__phase_reset, &venc->lal__phase_reset);
  68         writel(venc_cfg->hs_int_start_stop_x,
  69                                 &venc->hs_int_start_stop_x);
  70         writel(venc_cfg->hs_ext_start_stop_x,
  71                                 &venc->hs_ext_start_stop_x);
  72         writel(venc_cfg->vs_int_start_x, &venc->vs_int_start_x);
  73         writel(venc_cfg->vs_int_stop_x__vs_int_start_y,
  74                         &venc->vs_int_stop_x__vs_int_start_y);
  75         writel(venc_cfg->vs_int_stop_y__vs_ext_start_x,
  76                         &venc->vs_int_stop_y__vs_ext_start_x);
  77         writel(venc_cfg->vs_ext_stop_x__vs_ext_start_y,
  78                         &venc->vs_ext_stop_x__vs_ext_start_y);
  79         writel(venc_cfg->vs_ext_stop_y, &venc->vs_ext_stop_y);
  80         writel(venc_cfg->avid_start_stop_x, &venc->avid_start_stop_x);
  81         writel(venc_cfg->avid_start_stop_y, &venc->avid_start_stop_y);
  82         writel(venc_cfg->fid_int_start_x__fid_int_start_y,
  83                                 &venc->fid_int_start_x__fid_int_start_y);
  84         writel(venc_cfg->fid_int_offset_y__fid_ext_start_x,
  85                                 &venc->fid_int_offset_y__fid_ext_start_x);
  86         writel(venc_cfg->fid_ext_start_y__fid_ext_offset_y,
  87                                 &venc->fid_ext_start_y__fid_ext_offset_y);
  88         writel(venc_cfg->tvdetgp_int_start_stop_x,
  89                                 &venc->tvdetgp_int_start_stop_x);
  90         writel(venc_cfg->tvdetgp_int_start_stop_y,
  91                                 &venc->tvdetgp_int_start_stop_y);
  92         writel(venc_cfg->gen_ctrl, &venc->gen_ctrl);
  93         writel(venc_cfg->output_control, &venc->output_control);
  94         writel(venc_cfg->dac_b__dac_c, &venc->dac_b__dac_c);
  95
  96         /* Configure DSS for VENC Settings */
  97         writel(VENC_DSS_CONFIG, &dss->control);
  98
  99         /* Configure height and width for Digital out */
 100         writel(((height << DIG_LPP_SHIFT) | width), &dispc->size_dig);
 101 }
 102
 103 /*
 104  * Configure Panel Specific Parameters
 105  */
 106 void omap3_dss_panel_config(const struct panel_config *panel_cfg)
 107 {
 108         struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE;
 109         struct dss_regs *dss = (struct dss_regs *) OMAP3_DSS_BASE;
 110
 111         writel(DSS_SOFTRESET, &dss->sysconfig);
 112         while (!(readl(&dss->sysstatus) & DSS_RESETDONE))
 113                 ;
 114
 115         writel(panel_cfg->timing_h, &dispc->timing_h);
 116         writel(panel_cfg->timing_v, &dispc->timing_v);
 117         writel(panel_cfg->pol_freq, &dispc->pol_freq);
 118         writel(panel_cfg->divisor, &dispc->divisor);
 119         writel(panel_cfg->lcd_size, &dispc->size_lcd);
 120         writel((panel_cfg->load_mode << FRAME_MODE_SHIFT), &dispc->config);
 121         writel(((panel_cfg->panel_type << TFTSTN_SHIFT) |
 122                 (panel_cfg->data_lines << DATALINES_SHIFT)), &dispc->control);
 123         writel(panel_cfg->panel_color, &dispc->default_color0);
 124         writel((u32) panel_cfg->frame_buffer, &dispc->gfx_ba0);
 125
 126         if (!panel_cfg->frame_buffer)
 127                 return;
 128
 129         writel(panel_cfg->load_mode << LOADMODE_SHIFT, &dispc->config);
 130         writel(8 << GFX_FORMAT_SHIFT | GFX_ENABLE, &dispc->gfx_attributes);
 131         writel(1, &dispc->gfx_row_inc);
 132         writel(1, &dispc->gfx_pixel_inc);
 133         writel(panel_cfg->lcd_size, &dispc->gfx_size);
 134 }
 135
 136 /*
 137  * Enable LCD and DIGITAL OUT in DSS
 138  */
 139 void omap3_dss_enable(void)
 140 {
 141         struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE;
 142         u32 l = 0;
 143
 144         l = readl(&dispc->control);
 145         l |= DISPC_ENABLE;
 146         writel(l, &dispc->control);
 147 }
 148
 149 #ifdef CONFIG_CFB_CONSOLE
 150 int __board_video_init(void)
 151 {
 152         return -1;
 153 }
 154
 155 int board_video_init(void)
 156                         __attribute__((weak, alias("__board_video_init")));
 157
 158 void *video_hw_init(void)
 159 {
 160         static GraphicDevice dssfb;
 161         GraphicDevice *pGD = &dssfb;
 162         struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE;
 163
 164         if (board_video_init() || !readl(&dispc->gfx_ba0))
 165                 return NULL;
 166
 167         pGD->winSizeX = (readl(&dispc->size_lcd) & 0x7FF) + 1;
 168         pGD->winSizeY = ((readl(&dispc->size_lcd) >> 16) & 0x7FF) + 1;
 169         pGD->gdfBytesPP = 4;
 170         pGD->gdfIndex = GDF_32BIT_X888RGB;
 171         pGD->frameAdrs = readl(&dispc->gfx_ba0);
 172
 173         return pGD;
 174 }
 175 #endif