drivers/video/pm3fb.c

   1 /*
   2  *  linux/drivers/video/pm3fb.c -- 3DLabs Permedia3 frame buffer device
   3  *
   4  *  Copyright (C) 2001 Romain Dolbeau <romain@dolbeau.org>.
   5  *
   6  *  Ported to 2.6 kernel on 1 May 2007 by Krzysztof Helt <krzysztof.h1@wp.pl>
   7  *      based on pm2fb.c
   8  *
   9  *  Based on code written by:
  10  *         Sven Luther, <luther@dpt-info.u-strasbg.fr>
  11  *         Alan Hourihane, <alanh@fairlite.demon.co.uk>
  12  *         Russell King, <rmk@arm.linux.org.uk>
  13  *  Based on linux/drivers/video/skeletonfb.c:
  14  *      Copyright (C) 1997 Geert Uytterhoeven
  15  *  Based on linux/driver/video/pm2fb.c:
  16  *      Copyright (C) 1998-1999 Ilario Nardinocchi (nardinoc@CS.UniBO.IT)
  17  *      Copyright (C) 1999 Jakub Jelinek (jakub@redhat.com)
  18  *
  19  *  This file is subject to the terms and conditions of the GNU General Public
  20  *  License. See the file COPYING in the main directory of this archive for
  21  *  more details.
  22  *
  23  */
  24
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/errno.h>
  28 #include <linux/string.h>
  29 #include <linux/mm.h>
  30 #include <linux/slab.h>
  31 #include <linux/delay.h>
  32 #include <linux/fb.h>
  33 #include <linux/init.h>
  34 #include <linux/pci.h>
  35
  36 #include <video/pm3fb.h>
  37
  38 #if !defined(CONFIG_PCI)
  39 #error "Only generic PCI cards supported."
  40 #endif
  41
  42 #undef PM3FB_MASTER_DEBUG
  43 #ifdef PM3FB_MASTER_DEBUG
  44 #define DPRINTK(a,b...) printk(KERN_DEBUG "pm3fb: %s: " a, __FUNCTION__ , ## b)
  45 #else
  46 #define DPRINTK(a,b...)
  47 #endif
  48
  49 #define PM3_PIXMAP_SIZE (2048 * 4)
  50
  51 /*
  52  * Driver data
  53  */
  54 static char *mode_option __devinitdata;
  55
  56 /*
  57  * This structure defines the hardware state of the graphics card. Normally
  58  * you place this in a header file in linux/include/video. This file usually
  59  * also includes register information. That allows other driver subsystems
  60  * and userland applications the ability to use the same header file to
  61  * avoid duplicate work and easy porting of software.
  62  */
  63 struct pm3_par {
  64         unsigned char   __iomem *v_regs;/* virtual address of p_regs */
  65         u32             video;          /* video flags before blanking */
  66         u32             base;           /* screen base (xoffset+yoffset) in 128 bits unit */
  67         u32             palette[16];
  68 };
  69
  70 /*
  71  * Here we define the default structs fb_fix_screeninfo and fb_var_screeninfo
  72  * if we don't use modedb. If we do use modedb see pm3fb_init how to use it
  73  * to get a fb_var_screeninfo. Otherwise define a default var as well.
  74  */
  75 static struct fb_fix_screeninfo pm3fb_fix __devinitdata = {
  76         .id =           "Permedia3",
  77         .type =         FB_TYPE_PACKED_PIXELS,
  78         .visual =       FB_VISUAL_PSEUDOCOLOR,
  79         .xpanstep =     1,
  80         .ypanstep =     1,
  81         .ywrapstep =    0,
  82         .accel =        FB_ACCEL_3DLABS_PERMEDIA3,
  83 };
  84
  85 /*
  86  * Utility functions
  87  */
  88
  89 static inline u32 PM3_READ_REG(struct pm3_par *par, s32 off)
  90 {
  91         return fb_readl(par->v_regs + off);
  92 }
  93
  94 static inline void PM3_WRITE_REG(struct pm3_par *par, s32 off, u32 v)
  95 {
  96         fb_writel(v, par->v_regs + off);
  97 }
  98
  99 static inline void PM3_WAIT(struct pm3_par *par, u32 n)
 100 {
 101         while (PM3_READ_REG(par, PM3InFIFOSpace) < n);
 102 }
 103
 104 static inline void PM3_WRITE_DAC_REG(struct pm3_par *par, unsigned r, u8 v)
 105 {
 106         PM3_WAIT(par, 3);
 107         PM3_WRITE_REG(par, PM3RD_IndexHigh, (r >> 8) & 0xff);
 108         PM3_WRITE_REG(par, PM3RD_IndexLow, r & 0xff);
 109         wmb();
 110         PM3_WRITE_REG(par, PM3RD_IndexedData, v);
 111         wmb();
 112 }
 113
 114 static inline void pm3fb_set_color(struct pm3_par *par, unsigned char regno,
 115                         unsigned char r, unsigned char g, unsigned char b)
 116 {
 117         PM3_WAIT(par, 4);
 118         PM3_WRITE_REG(par, PM3RD_PaletteWriteAddress, regno);
 119         wmb();
 120         PM3_WRITE_REG(par, PM3RD_PaletteData, r);
 121         wmb();
 122         PM3_WRITE_REG(par, PM3RD_PaletteData, g);
 123         wmb();
 124         PM3_WRITE_REG(par, PM3RD_PaletteData, b);
 125         wmb();
 126 }
 127
 128 static void pm3fb_clear_colormap(struct pm3_par *par,
 129                         unsigned char r, unsigned char g, unsigned char b)
 130 {
 131         int i;
 132
 133         for (i = 0; i < 256 ; i++)
 134                 pm3fb_set_color(par, i, r, g, b);
 135
 136 }
 137
 138 /* Calculating various clock parameter */
 139 static void pm3fb_calculate_clock(unsigned long reqclock,
 140                                 unsigned char *prescale,
 141                                 unsigned char *feedback,
 142                                 unsigned char *postscale)
 143 {
 144         int f, pre, post;
 145         unsigned long freq;
 146         long freqerr = 1000;
 147         long currerr;
 148
 149         for (f = 1; f < 256; f++) {
 150                 for (pre = 1; pre < 256; pre++) {
 151                         for (post = 0; post < 5; post++) {
 152                                 freq = ((2*PM3_REF_CLOCK * f) >> post) / pre;
 153                                 currerr = (reqclock > freq)
 154                                         ? reqclock - freq
 155                                         : freq - reqclock;
 156                                 if (currerr < freqerr) {
 157                                         freqerr = currerr;
 158                                         *feedback = f;
 159                                         *prescale = pre;
 160                                         *postscale = post;
 161                                 }
 162                         }
 163                 }
 164         }
 165 }
 166
 167 static inline int pm3fb_depth(const struct fb_var_screeninfo *var)
 168 {
 169         if ( var->bits_per_pixel == 16 )
 170                 return var->red.length + var->green.length
 171                         + var->blue.length;
 172
 173         return var->bits_per_pixel;
 174 }
 175
 176 static inline int pm3fb_shift_bpp(unsigned bpp, int v)
 177 {
 178         switch (bpp) {
 179         case 8:
 180                 return (v >> 4);
 181         case 16:
 182                 return (v >> 3);
 183         case 32:
 184                 return (v >> 2);
 185         }
 186         DPRINTK("Unsupported depth %u\n", bpp);
 187         return 0;
 188 }
 189
 190 /* acceleration */
 191 static int pm3fb_sync(struct fb_info *info)
 192 {
 193         struct pm3_par *par = info->par;
 194
 195         PM3_WAIT(par, 2);
 196         PM3_WRITE_REG(par, PM3FilterMode, PM3FilterModeSync);
 197         PM3_WRITE_REG(par, PM3Sync, 0);
 198         mb();
 199         do {
 200                 while ((PM3_READ_REG(par, PM3OutFIFOWords)) == 0);
 201                 rmb();
 202         } while ((PM3_READ_REG(par, PM3OutputFifo)) != PM3Sync_Tag);
 203
 204         return 0;
 205 }
 206
 207 static void pm3fb_init_engine(struct fb_info *info)
 208 {
 209         struct pm3_par *par = info->par;
 210         const u32 width = (info->var.xres_virtual + 7) & ~7;
 211
 212         PM3_WAIT(par, 50);
 213         PM3_WRITE_REG(par, PM3FilterMode, PM3FilterModeSync);
 214         PM3_WRITE_REG(par, PM3StatisticMode, 0x0);
 215         PM3_WRITE_REG(par, PM3DeltaMode, 0x0);
 216         PM3_WRITE_REG(par, PM3RasterizerMode, 0x0);
 217         PM3_WRITE_REG(par, PM3ScissorMode, 0x0);
 218         PM3_WRITE_REG(par, PM3LineStippleMode, 0x0);
 219         PM3_WRITE_REG(par, PM3AreaStippleMode, 0x0);
 220         PM3_WRITE_REG(par, PM3GIDMode, 0x0);
 221         PM3_WRITE_REG(par, PM3DepthMode, 0x0);
 222         PM3_WRITE_REG(par, PM3StencilMode, 0x0);
 223         PM3_WRITE_REG(par, PM3StencilData, 0x0);
 224         PM3_WRITE_REG(par, PM3ColorDDAMode, 0x0);
 225         PM3_WRITE_REG(par, PM3TextureCoordMode, 0x0);
 226         PM3_WRITE_REG(par, PM3TextureIndexMode0, 0x0);
 227         PM3_WRITE_REG(par, PM3TextureIndexMode1, 0x0);
 228         PM3_WRITE_REG(par, PM3TextureReadMode, 0x0);
 229         PM3_WRITE_REG(par, PM3LUTMode, 0x0);
 230         PM3_WRITE_REG(par, PM3TextureFilterMode, 0x0);
 231         PM3_WRITE_REG(par, PM3TextureCompositeMode, 0x0);
 232         PM3_WRITE_REG(par, PM3TextureApplicationMode, 0x0);
 233         PM3_WRITE_REG(par, PM3TextureCompositeColorMode1, 0x0);
 234         PM3_WRITE_REG(par, PM3TextureCompositeAlphaMode1, 0x0);
 235         PM3_WRITE_REG(par, PM3TextureCompositeColorMode0, 0x0);
 236         PM3_WRITE_REG(par, PM3TextureCompositeAlphaMode0, 0x0);
 237         PM3_WRITE_REG(par, PM3FogMode, 0x0);
 238         PM3_WRITE_REG(par, PM3ChromaTestMode, 0x0);
 239         PM3_WRITE_REG(par, PM3AlphaTestMode, 0x0);
 240         PM3_WRITE_REG(par, PM3AntialiasMode, 0x0);
 241         PM3_WRITE_REG(par, PM3YUVMode, 0x0);
 242         PM3_WRITE_REG(par, PM3AlphaBlendColorMode, 0x0);
 243         PM3_WRITE_REG(par, PM3AlphaBlendAlphaMode, 0x0);
 244         PM3_WRITE_REG(par, PM3DitherMode, 0x0);
 245         PM3_WRITE_REG(par, PM3LogicalOpMode, 0x0);
 246         PM3_WRITE_REG(par, PM3RouterMode, 0x0);
 247         PM3_WRITE_REG(par, PM3Window, 0x0);
 248
 249         PM3_WRITE_REG(par, PM3Config2D, 0x0);
 250
 251         PM3_WRITE_REG(par, PM3SpanColorMask, 0xffffffff);
 252
 253         PM3_WRITE_REG(par, PM3XBias, 0x0);
 254         PM3_WRITE_REG(par, PM3YBias, 0x0);
 255         PM3_WRITE_REG(par, PM3DeltaControl, 0x0);
 256
 257         PM3_WRITE_REG(par, PM3BitMaskPattern, 0xffffffff);
 258
 259         PM3_WRITE_REG(par, PM3FBDestReadEnables,
 260                            PM3FBDestReadEnables_E(0xff) |
 261                            PM3FBDestReadEnables_R(0xff) |
 262                            PM3FBDestReadEnables_ReferenceAlpha(0xff));
 263         PM3_WRITE_REG(par, PM3FBDestReadBufferAddr0, 0x0);
 264         PM3_WRITE_REG(par, PM3FBDestReadBufferOffset0, 0x0);
 265         PM3_WRITE_REG(par, PM3FBDestReadBufferWidth0,
 266                            PM3FBDestReadBufferWidth_Width(width));
 267
 268         PM3_WRITE_REG(par, PM3FBDestReadMode,
 269                            PM3FBDestReadMode_ReadEnable |
 270                            PM3FBDestReadMode_Enable0);
 271         PM3_WRITE_REG(par, PM3FBSourceReadBufferAddr, 0x0);
 272         PM3_WRITE_REG(par, PM3FBSourceReadBufferOffset, 0x0);
 273         PM3_WRITE_REG(par, PM3FBSourceReadBufferWidth,
 274                            PM3FBSourceReadBufferWidth_Width(width));
 275         PM3_WRITE_REG(par, PM3FBSourceReadMode,
 276                            PM3FBSourceReadMode_Blocking |
 277                            PM3FBSourceReadMode_ReadEnable);
 278
 279         PM3_WAIT(par, 2);
 280         {
 281                 /* invert bits in bitmask */
 282                 unsigned long rm = 1 | (3 << 7);
 283                 switch (info->var.bits_per_pixel) {
 284                 case 8:
 285                         PM3_WRITE_REG(par, PM3PixelSize,
 286                                            PM3PixelSize_GLOBAL_8BIT);
 287 #ifdef __BIG_ENDIAN
 288                         rm |= 3 << 15;
 289 #endif
 290                         break;
 291                 case 16:
 292                         PM3_WRITE_REG(par, PM3PixelSize,
 293                                            PM3PixelSize_GLOBAL_16BIT);
 294 #ifdef __BIG_ENDIAN
 295                         rm |= 2 << 15;
 296 #endif
 297                         break;
 298                 case 32:
 299                         PM3_WRITE_REG(par, PM3PixelSize,
 300                                            PM3PixelSize_GLOBAL_32BIT);
 301                         break;
 302                 default:
 303                         DPRINTK(1, "Unsupported depth %d\n",
 304                                 info->var.bits_per_pixel);
 305                         break;
 306                 }
 307                 PM3_WRITE_REG(par, PM3RasterizerMode, rm);
 308         }
 309
 310         PM3_WAIT(par, 20);
 311         PM3_WRITE_REG(par, PM3FBSoftwareWriteMask, 0xffffffff);
 312         PM3_WRITE_REG(par, PM3FBHardwareWriteMask, 0xffffffff);
 313         PM3_WRITE_REG(par, PM3FBWriteMode,
 314                            PM3FBWriteMode_WriteEnable |
 315                            PM3FBWriteMode_OpaqueSpan |
 316                            PM3FBWriteMode_Enable0);
 317         PM3_WRITE_REG(par, PM3FBWriteBufferAddr0, 0x0);
 318         PM3_WRITE_REG(par, PM3FBWriteBufferOffset0, 0x0);
 319         PM3_WRITE_REG(par, PM3FBWriteBufferWidth0,
 320                            PM3FBWriteBufferWidth_Width(width));
 321
 322         PM3_WRITE_REG(par, PM3SizeOfFramebuffer, 0x0);
 323         {
 324                 /* size in lines of FB */
 325                 unsigned long sofb = info->screen_size /
 326                         info->fix.line_length;
 327                 if (sofb > 4095)
 328                         PM3_WRITE_REG(par, PM3SizeOfFramebuffer, 4095);
 329                 else
 330                         PM3_WRITE_REG(par, PM3SizeOfFramebuffer, sofb);
 331
 332                 switch (info->var.bits_per_pixel) {
 333                 case 8:
 334                         PM3_WRITE_REG(par, PM3DitherMode,
 335                                            (1 << 10) | (2 << 3));
 336                         break;
 337                 case 16:
 338                         PM3_WRITE_REG(par, PM3DitherMode,
 339                                            (1 << 10) | (1 << 3));
 340                         break;
 341                 case 32:
 342                         PM3_WRITE_REG(par, PM3DitherMode,
 343                                            (1 << 10) | (0 << 3));
 344                         break;
 345                 default:
 346                         DPRINTK(1, "Unsupported depth %d\n",
 347                                 info->current_par->depth);
 348                         break;
 349                 }
 350         }
 351
 352         PM3_WRITE_REG(par, PM3dXDom, 0x0);
 353         PM3_WRITE_REG(par, PM3dXSub, 0x0);
 354         PM3_WRITE_REG(par, PM3dY, (1 << 16));
 355         PM3_WRITE_REG(par, PM3StartXDom, 0x0);
 356         PM3_WRITE_REG(par, PM3StartXSub, 0x0);
 357         PM3_WRITE_REG(par, PM3StartY, 0x0);
 358         PM3_WRITE_REG(par, PM3Count, 0x0);
 359
 360 /* Disable LocalBuffer. better safe than sorry */
 361         PM3_WRITE_REG(par, PM3LBDestReadMode, 0x0);
 362         PM3_WRITE_REG(par, PM3LBDestReadEnables, 0x0);
 363         PM3_WRITE_REG(par, PM3LBSourceReadMode, 0x0);
 364         PM3_WRITE_REG(par, PM3LBWriteMode, 0x0);
 365
 366         pm3fb_sync(info);
 367 }
 368
 369 static void pm3fb_fillrect (struct fb_info *info,
 370                                 const struct fb_fillrect *region)
 371 {
 372         struct pm3_par *par = info->par;
 373         struct fb_fillrect modded;
 374         int vxres, vyres;
 375         u32 color = (info->fix.visual == FB_VISUAL_TRUECOLOR) ?
 376                 ((u32*)info->pseudo_palette)[region->color] : region->color;
 377
 378         if (info->state != FBINFO_STATE_RUNNING)
 379                 return;
 380         if ((info->flags & FBINFO_HWACCEL_DISABLED) ||
 381                 region->rop != ROP_COPY ) {
 382                 cfb_fillrect(info, region);
 383                 return;
 384         }
 385
 386         vxres = info->var.xres_virtual;
 387         vyres = info->var.yres_virtual;
 388
 389         memcpy(&modded, region, sizeof(struct fb_fillrect));
 390
 391         if(!modded.width || !modded.height ||
 392            modded.dx >= vxres || modded.dy >= vyres)
 393                 return;
 394
 395         if(modded.dx + modded.width  > vxres)
 396                 modded.width  = vxres - modded.dx;
 397         if(modded.dy + modded.height > vyres)
 398                 modded.height = vyres - modded.dy;
 399
 400         if(info->var.bits_per_pixel == 8)
 401                 color |= color << 8;
 402         if(info->var.bits_per_pixel <= 16)
 403                 color |= color << 16;
 404
 405         PM3_WAIT(par, 4);
 406         /* ROP Ox3 is GXcopy */
 407         PM3_WRITE_REG(par, PM3Config2D,
 408                         PM3Config2D_UseConstantSource |
 409                         PM3Config2D_ForegroundROPEnable |
 410                         (PM3Config2D_ForegroundROP(0x3)) |
 411                         PM3Config2D_FBWriteEnable);
 412
 413         PM3_WRITE_REG(par, PM3ForegroundColor, color);
 414
 415         PM3_WRITE_REG(par, PM3RectanglePosition,
 416                         (PM3RectanglePosition_XOffset(modded.dx)) |
 417                         (PM3RectanglePosition_YOffset(modded.dy)));
 418
 419         PM3_WRITE_REG(par, PM3Render2D,
 420                       PM3Render2D_XPositive |
 421                       PM3Render2D_YPositive |
 422                       PM3Render2D_Operation_Normal |
 423                       PM3Render2D_SpanOperation |
 424                       (PM3Render2D_Width(modded.width)) |
 425                       (PM3Render2D_Height(modded.height)));
 426 }
 427
 428 static void pm3fb_copyarea(struct fb_info *info,
 429                                 const struct fb_copyarea *area)
 430 {
 431         struct pm3_par *par = info->par;
 432         struct fb_copyarea modded;
 433         u32 vxres, vyres;
 434         int x_align, o_x, o_y;
 435
 436         if (info->state != FBINFO_STATE_RUNNING)
 437                 return;
 438         if (info->flags & FBINFO_HWACCEL_DISABLED) {
 439                 cfb_copyarea(info, area);
 440                 return;
 441         }
 442
 443         memcpy(&modded, area, sizeof(struct fb_copyarea));
 444
 445         vxres = info->var.xres_virtual;
 446         vyres = info->var.yres_virtual;
 447
 448         if(!modded.width || !modded.height ||
 449            modded.sx >= vxres || modded.sy >= vyres ||
 450            modded.dx >= vxres || modded.dy >= vyres)
 451                 return;
 452
 453         if(modded.sx + modded.width > vxres)
 454                 modded.width = vxres - modded.sx;
 455         if(modded.dx + modded.width > vxres)
 456                 modded.width = vxres - modded.dx;
 457         if(modded.sy + modded.height > vyres)
 458                 modded.height = vyres - modded.sy;
 459         if(modded.dy + modded.height > vyres)
 460                 modded.height = vyres - modded.dy;
 461
 462         o_x = modded.sx - modded.dx;    /*(sx > dx ) ? (sx - dx) : (dx - sx); */
 463         o_y = modded.sy - modded.dy;    /*(sy > dy ) ? (sy - dy) : (dy - sy); */
 464
 465         x_align = (modded.sx & 0x1f);
 466
 467         PM3_WAIT(par, 6);
 468
 469         PM3_WRITE_REG(par, PM3Config2D,
 470                         PM3Config2D_UserScissorEnable |
 471                         PM3Config2D_ForegroundROPEnable |
 472                         PM3Config2D_Blocking |
 473                         (PM3Config2D_ForegroundROP(0x3)) | /* Ox3 is GXcopy */
 474                         PM3Config2D_FBWriteEnable);
 475
 476         PM3_WRITE_REG(par, PM3ScissorMinXY,
 477                         ((modded.dy & 0x0fff) << 16) | (modded.dx & 0x0fff));
 478         PM3_WRITE_REG(par, PM3ScissorMaxXY,
 479                         (((modded.dy + modded.height) & 0x0fff) << 16) |
 480                         ((modded.dx + modded.width) & 0x0fff));
 481
 482         PM3_WRITE_REG(par, PM3FBSourceReadBufferOffset,
 483                         PM3FBSourceReadBufferOffset_XOffset(o_x) |
 484                         PM3FBSourceReadBufferOffset_YOffset(o_y));
 485
 486         PM3_WRITE_REG(par, PM3RectanglePosition,
 487                         (PM3RectanglePosition_XOffset(modded.dx - x_align)) |
 488                         (PM3RectanglePosition_YOffset(modded.dy)));
 489
 490         PM3_WRITE_REG(par, PM3Render2D,
 491                         ((modded.sx > modded.dx) ? PM3Render2D_XPositive : 0) |
 492                         ((modded.sy > modded.dy) ? PM3Render2D_YPositive : 0) |
 493                         PM3Render2D_Operation_Normal |
 494                         PM3Render2D_SpanOperation |
 495                         PM3Render2D_FBSourceReadEnable |
 496                         (PM3Render2D_Width(modded.width + x_align)) |
 497                         (PM3Render2D_Height(modded.height)));
 498 }
 499
 500 static void pm3fb_imageblit(struct fb_info *info, const struct fb_image *image)
 501 {
 502         struct pm3_par *par = info->par;
 503         u32 height = image->height;
 504         u32 fgx, bgx;
 505         const u32 *src = (const u32*)image->data;
 506
 507         switch (info->fix.visual) {
 508                 case FB_VISUAL_PSEUDOCOLOR:
 509                         fgx = image->fg_color;
 510                         bgx = image->bg_color;
 511                         break;
 512                 case FB_VISUAL_TRUECOLOR:
 513                 default:
 514                         fgx = par->palette[image->fg_color];
 515                         bgx = par->palette[image->bg_color];
 516                         break;
 517         }
 518         if (image->depth != 1) {
 519                 return cfb_imageblit(info, image);
 520         }
 521         if (info->var.bits_per_pixel == 8) {
 522                 fgx |= fgx << 8;
 523                 bgx |= bgx << 8;
 524         }
 525         if (info->var.bits_per_pixel <= 16) {
 526                 fgx |= fgx << 16;
 527                 bgx |= bgx << 16;
 528         }
 529
 530         PM3_WAIT(par, 7);
 531
 532         PM3_WRITE_REG(par, PM3ForegroundColor, fgx);
 533         PM3_WRITE_REG(par, PM3BackgroundColor, bgx);
 534
 535         /* ROP Ox3 is GXcopy */
 536         PM3_WRITE_REG(par, PM3Config2D,
 537                         PM3Config2D_UserScissorEnable |
 538                         PM3Config2D_UseConstantSource |
 539                         PM3Config2D_ForegroundROPEnable |
 540                         (PM3Config2D_ForegroundROP(0x3)) |
 541                         PM3Config2D_OpaqueSpan |
 542                         PM3Config2D_FBWriteEnable);
 543         PM3_WRITE_REG(par, PM3ScissorMinXY,
 544                         ((image->dy & 0x0fff) << 16) | (image->dx & 0x0fff));
 545         PM3_WRITE_REG(par, PM3ScissorMaxXY,
 546                         (((image->dy + image->height) & 0x0fff) << 16) |
 547                         ((image->dx + image->width) & 0x0fff));
 548         PM3_WRITE_REG(par, PM3RectanglePosition,
 549                         (PM3RectanglePosition_XOffset(image->dx)) |
 550                         (PM3RectanglePosition_YOffset(image->dy)));
 551         PM3_WRITE_REG(par, PM3Render2D,
 552                         PM3Render2D_XPositive |
 553                         PM3Render2D_YPositive |
 554                         PM3Render2D_Operation_SyncOnBitMask |
 555                         PM3Render2D_SpanOperation |
 556                         (PM3Render2D_Width(image->width)) |
 557                         (PM3Render2D_Height(image->height)));
 558
 559
 560         while (height--) {
 561                 int width = ((image->width + 7) >> 3) + info->pixmap.scan_align;
 562                 width >>= 2;
 563
 564                 while (width >= PM3_FIFO_SIZE) {
 565                         int i = PM3_FIFO_SIZE - 1;
 566
 567                         PM3_WAIT(par, PM3_FIFO_SIZE);
 568                         while (i--) {
 569                                 PM3_WRITE_REG(par, PM3BitMaskPattern, *src);
 570                                 src++;
 571                         }
 572                         width -= PM3_FIFO_SIZE - 1;
 573                 }
 574
 575                 PM3_WAIT(par, width + 1);
 576                 while (width--) {
 577                         PM3_WRITE_REG(par, PM3BitMaskPattern, *src);
 578                         src++;
 579                 }
 580         }
 581 }
 582 /* end of acceleration functions */
 583
 584 /* write the mode to registers */
 585 static void pm3fb_write_mode(struct fb_info *info)
 586 {
 587         struct pm3_par *par = info->par;
 588         char tempsync = 0x00, tempmisc = 0x00;
 589         const u32 hsstart = info->var.right_margin;
 590         const u32 hsend = hsstart + info->var.hsync_len;
 591         const u32 hbend = hsend + info->var.left_margin;
 592         const u32 xres = (info->var.xres + 31) & ~31;
 593         const u32 htotal = xres + hbend;
 594         const u32 vsstart = info->var.lower_margin;
 595         const u32 vsend = vsstart + info->var.vsync_len;
 596         const u32 vbend = vsend + info->var.upper_margin;
 597         const u32 vtotal = info->var.yres + vbend;
 598         const u32 width = (info->var.xres_virtual + 7) & ~7;
 599         const unsigned bpp = info->var.bits_per_pixel;
 600
 601         PM3_WAIT(par, 20);
 602         PM3_WRITE_REG(par, PM3MemBypassWriteMask, 0xffffffff);
 603         PM3_WRITE_REG(par, PM3Aperture0, 0x00000000);
 604         PM3_WRITE_REG(par, PM3Aperture1, 0x00000000);
 605         PM3_WRITE_REG(par, PM3FIFODis, 0x00000007);
 606
 607         PM3_WRITE_REG(par, PM3HTotal,
 608                            pm3fb_shift_bpp(bpp, htotal - 1));
 609         PM3_WRITE_REG(par, PM3HsEnd,
 610                            pm3fb_shift_bpp(bpp, hsend));
 611         PM3_WRITE_REG(par, PM3HsStart,
 612                            pm3fb_shift_bpp(bpp, hsstart));
 613         PM3_WRITE_REG(par, PM3HbEnd,
 614                            pm3fb_shift_bpp(bpp, hbend));
 615         PM3_WRITE_REG(par, PM3HgEnd,
 616                            pm3fb_shift_bpp(bpp, hbend));
 617         PM3_WRITE_REG(par, PM3ScreenStride,
 618                            pm3fb_shift_bpp(bpp, width));
 619         PM3_WRITE_REG(par, PM3VTotal, vtotal - 1);
 620         PM3_WRITE_REG(par, PM3VsEnd, vsend - 1);
 621         PM3_WRITE_REG(par, PM3VsStart, vsstart - 1);
 622         PM3_WRITE_REG(par, PM3VbEnd, vbend);
 623
 624         switch (bpp) {
 625         case 8:
 626                 PM3_WRITE_REG(par, PM3ByAperture1Mode,
 627                                    PM3ByApertureMode_PIXELSIZE_8BIT);
 628                 PM3_WRITE_REG(par, PM3ByAperture2Mode,
 629                                    PM3ByApertureMode_PIXELSIZE_8BIT);
 630                 break;
 631
 632         case 16:
 633 #ifndef __BIG_ENDIAN
 634                 PM3_WRITE_REG(par, PM3ByAperture1Mode,
 635                                    PM3ByApertureMode_PIXELSIZE_16BIT);
 636                 PM3_WRITE_REG(par, PM3ByAperture2Mode,
 637                                    PM3ByApertureMode_PIXELSIZE_16BIT);
 638 #else
 639                 PM3_WRITE_REG(par, PM3ByAperture1Mode,
 640                                    PM3ByApertureMode_PIXELSIZE_16BIT |
 641                                    PM3ByApertureMode_BYTESWAP_BADC);
 642                 PM3_WRITE_REG(par, PM3ByAperture2Mode,
 643                                    PM3ByApertureMode_PIXELSIZE_16BIT |
 644                                    PM3ByApertureMode_BYTESWAP_BADC);
 645 #endif /* ! __BIG_ENDIAN */
 646                 break;
 647
 648         case 32:
 649 #ifndef __BIG_ENDIAN
 650                 PM3_WRITE_REG(par, PM3ByAperture1Mode,
 651                                    PM3ByApertureMode_PIXELSIZE_32BIT);
 652                 PM3_WRITE_REG(par, PM3ByAperture2Mode,
 653                                    PM3ByApertureMode_PIXELSIZE_32BIT);
 654 #else
 655                 PM3_WRITE_REG(par, PM3ByAperture1Mode,
 656                                    PM3ByApertureMode_PIXELSIZE_32BIT |
 657                                    PM3ByApertureMode_BYTESWAP_DCBA);
 658                 PM3_WRITE_REG(par, PM3ByAperture2Mode,
 659                                    PM3ByApertureMode_PIXELSIZE_32BIT |
 660                                    PM3ByApertureMode_BYTESWAP_DCBA);
 661 #endif /* ! __BIG_ENDIAN */
 662                 break;
 663
 664         default:
 665                 DPRINTK("Unsupported depth %d\n", bpp);
 666                 break;
 667         }
 668
 669         /*
 670          * Oxygen VX1 - it appears that setting PM3VideoControl and
 671          * then PM3RD_SyncControl to the same SYNC settings undoes
 672          * any net change - they seem to xor together.  Only set the
 673          * sync options in PM3RD_SyncControl.  --rmk
 674          */
 675         {
 676                 unsigned int video = par->video;
 677
 678                 video &= ~(PM3VideoControl_HSYNC_MASK |
 679                            PM3VideoControl_VSYNC_MASK);
 680                 video |= PM3VideoControl_HSYNC_ACTIVE_HIGH |
 681                          PM3VideoControl_VSYNC_ACTIVE_HIGH;
 682                 PM3_WRITE_REG(par, PM3VideoControl, video);
 683         }
 684         PM3_WRITE_REG(par, PM3VClkCtl,
 685                            (PM3_READ_REG(par, PM3VClkCtl) & 0xFFFFFFFC));
 686         PM3_WRITE_REG(par, PM3ScreenBase, par->base);
 687         PM3_WRITE_REG(par, PM3ChipConfig,
 688                            (PM3_READ_REG(par, PM3ChipConfig) & 0xFFFFFFFD));
 689
 690         wmb();
 691         {
 692                 unsigned char uninitialized_var(m);     /* ClkPreScale */
 693                 unsigned char uninitialized_var(n);     /* ClkFeedBackScale */
 694                 unsigned char uninitialized_var(p);     /* ClkPostScale */
 695                 unsigned long pixclock = PICOS2KHZ(info->var.pixclock);
 696
 697                 (void)pm3fb_calculate_clock(pixclock, &m, &n, &p);
 698
 699                 DPRINTK("Pixclock: %ld, Pre: %d, Feedback: %d, Post: %d\n",
 700                         pixclock, (int) m, (int) n, (int) p);
 701
 702                 PM3_WRITE_DAC_REG(par, PM3RD_DClk0PreScale, m);
 703                 PM3_WRITE_DAC_REG(par, PM3RD_DClk0FeedbackScale, n);
 704                 PM3_WRITE_DAC_REG(par, PM3RD_DClk0PostScale, p);
 705         }
 706         /*
 707            PM3_WRITE_DAC_REG(par, PM3RD_IndexControl, 0x00);
 708          */
 709         /*
 710            PM3_SLOW_WRITE_REG(par, PM3RD_IndexControl, 0x00);
 711          */
 712         if ((par->video & PM3VideoControl_HSYNC_MASK) ==
 713             PM3VideoControl_HSYNC_ACTIVE_HIGH)
 714                 tempsync |= PM3RD_SyncControl_HSYNC_ACTIVE_HIGH;
 715         if ((par->video & PM3VideoControl_VSYNC_MASK) ==
 716             PM3VideoControl_VSYNC_ACTIVE_HIGH)
 717                 tempsync |= PM3RD_SyncControl_VSYNC_ACTIVE_HIGH;
 718
 719         PM3_WRITE_DAC_REG(par, PM3RD_SyncControl, tempsync);
 720         DPRINTK("PM3RD_SyncControl: %d\n", tempsync);
 721
 722         PM3_WRITE_DAC_REG(par, PM3RD_DACControl, 0x00);
 723
 724         switch (pm3fb_depth(&info->var)) {
 725         case 8:
 726                 PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
 727                                   PM3RD_PixelSize_8_BIT_PIXELS);
 728                 PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
 729                                   PM3RD_ColorFormat_CI8_COLOR |
 730                                   PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW);
 731                 tempmisc |= PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
 732                 break;
 733         case 12:
 734                 PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
 735                                   PM3RD_PixelSize_16_BIT_PIXELS);
 736                 PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
 737                                   PM3RD_ColorFormat_4444_COLOR |
 738                                   PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW |
 739                                   PM3RD_ColorFormat_LINEAR_COLOR_EXT_ENABLE);
 740                 tempmisc |= PM3RD_MiscControl_DIRECTCOLOR_ENABLE |
 741                         PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
 742                 break;
 743         case 15:
 744                 PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
 745                                   PM3RD_PixelSize_16_BIT_PIXELS);
 746                 PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
 747                                   PM3RD_ColorFormat_5551_FRONT_COLOR |
 748                                   PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW |
 749                                   PM3RD_ColorFormat_LINEAR_COLOR_EXT_ENABLE);
 750                 tempmisc |= PM3RD_MiscControl_DIRECTCOLOR_ENABLE |
 751                         PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
 752                 break;
 753         case 16:
 754                 PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
 755                                   PM3RD_PixelSize_16_BIT_PIXELS);
 756                 PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
 757                                   PM3RD_ColorFormat_565_FRONT_COLOR |
 758                                   PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW |
 759                                   PM3RD_ColorFormat_LINEAR_COLOR_EXT_ENABLE);
 760                 tempmisc |= PM3RD_MiscControl_DIRECTCOLOR_ENABLE |
 761                         PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
 762                 break;
 763         case 32:
 764                 PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
 765                                   PM3RD_PixelSize_32_BIT_PIXELS);
 766                 PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
 767                                   PM3RD_ColorFormat_8888_COLOR |
 768                                   PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW);
 769                 tempmisc |= PM3RD_MiscControl_DIRECTCOLOR_ENABLE |
 770                         PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
 771                 break;
 772         }
 773         PM3_WRITE_DAC_REG(par, PM3RD_MiscControl, tempmisc);
 774 }
 775
 776 /*
 777  * hardware independent functions
 778  */
 779 static int pm3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
 780 {
 781         u32 lpitch;
 782         unsigned bpp = var->red.length + var->green.length
 783                         + var->blue.length + var->transp.length;
 784
 785         if ( bpp != var->bits_per_pixel ) {
 786                 /* set predefined mode for bits_per_pixel settings */
 787
 788                 switch(var->bits_per_pixel) {
 789                 case 8:
 790                         var->red.length = var->green.length = var->blue.length = 8;
 791                         var->red.offset = var->green.offset = var->blue.offset = 0;
 792                         var->transp.offset = 0;
 793                         var->transp.length = 0;
 794                         break;
 795                 case 16:
 796                         var->red.length = var->blue.length = 5;
 797                         var->green.length = 6;
 798                         var->transp.length = 0;
 799                         break;
 800                 case 32:
 801                         var->red.length = var->green.length = var->blue.length = 8;
 802                         var->transp.length = 8;
 803                         break;
 804                 default:
 805                         DPRINTK("depth not supported: %u\n", var->bits_per_pixel);
 806                         return -EINVAL;
 807                 }
 808         }
 809         /* it is assumed BGRA order */
 810         if (var->bits_per_pixel > 8 )
 811         {
 812                 var->blue.offset = 0;
 813                 var->green.offset = var->blue.length;
 814                 var->red.offset = var->green.offset + var->green.length;
 815                 var->transp.offset = var->red.offset + var->red.length;
 816         }
 817         var->height = var->width = -1;
 818
 819         if (var->xres != var->xres_virtual) {
 820                 DPRINTK("virtual x resolution != physical x resolution not supported\n");
 821                 return -EINVAL;
 822         }
 823
 824         if (var->yres > var->yres_virtual) {
 825                 DPRINTK("virtual y resolution < physical y resolution not possible\n");
 826                 return -EINVAL;
 827         }
 828
 829         if (var->xoffset) {
 830                 DPRINTK("xoffset not supported\n");
 831                 return -EINVAL;
 832         }
 833
 834         if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
 835                 DPRINTK("interlace not supported\n");
 836                 return -EINVAL;
 837         }
 838
 839         var->xres = (var->xres + 31) & ~31; /* could sometimes be 8 */
 840         lpitch = var->xres * ((var->bits_per_pixel + 7)>>3);
 841
 842         if (var->xres < 200 || var->xres > 2048) {
 843                 DPRINTK("width not supported: %u\n", var->xres);
 844                 return -EINVAL;
 845         }
 846
 847         if (var->yres < 200 || var->yres > 4095) {
 848                 DPRINTK("height not supported: %u\n", var->yres);
 849                 return -EINVAL;
 850         }
 851
 852         if (lpitch * var->yres_virtual > info->fix.smem_len) {
 853                 DPRINTK("no memory for screen (%ux%ux%u)\n",
 854                         var->xres, var->yres_virtual, var->bits_per_pixel);
 855                 return -EINVAL;
 856         }
 857
 858         if (PICOS2KHZ(var->pixclock) > PM3_MAX_PIXCLOCK) {
 859                 DPRINTK("pixclock too high (%ldKHz)\n", PICOS2KHZ(var->pixclock));
 860                 return -EINVAL;
 861         }
 862
 863         var->accel_flags = 0;   /* Can't mmap if this is on */
 864
 865         DPRINTK("Checking graphics mode at %dx%d depth %d\n",
 866                 var->xres, var->yres, var->bits_per_pixel);
 867         return 0;
 868 }
 869
 870 static int pm3fb_set_par(struct fb_info *info)
 871 {
 872         struct pm3_par *par = info->par;
 873         const u32 xres = (info->var.xres + 31) & ~31;
 874         const unsigned bpp = info->var.bits_per_pixel;
 875
 876         par->base = pm3fb_shift_bpp(bpp,(info->var.yoffset * xres)
 877                                         + info->var.xoffset);
 878         par->video = 0;
 879
 880         if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
 881                 par->video |= PM3VideoControl_HSYNC_ACTIVE_HIGH;
 882         else
 883                 par->video |= PM3VideoControl_HSYNC_ACTIVE_LOW;
 884
 885         if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
 886                 par->video |= PM3VideoControl_VSYNC_ACTIVE_HIGH;
 887         else
 888                 par->video |= PM3VideoControl_VSYNC_ACTIVE_LOW;
 889
 890         if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE)
 891                 par->video |= PM3VideoControl_LINE_DOUBLE_ON;
 892         else
 893                 par->video |= PM3VideoControl_LINE_DOUBLE_OFF;
 894
 895         if ((info->var.activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW)
 896                 par->video |= PM3VideoControl_ENABLE;
 897         else {
 898                 par->video &= ~PM3VideoControl_ENABLE;
 899                 DPRINTK("PM3Video disabled\n");
 900         }
 901         switch (bpp) {
 902         case 8:
 903                 par->video |= PM3VideoControl_PIXELSIZE_8BIT;
 904                 break;
 905         case 16:
 906                 par->video |= PM3VideoControl_PIXELSIZE_16BIT;
 907                 break;
 908         case 32:
 909                 par->video |= PM3VideoControl_PIXELSIZE_32BIT;
 910                 break;
 911         default:
 912                 DPRINTK("Unsupported depth\n");
 913                 break;
 914         }
 915
 916         info->fix.visual =
 917                 (bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
 918         info->fix.line_length = ((info->var.xres_virtual + 7)  & ~7)
 919                                         * bpp / 8;
 920
 921 /*      pm3fb_clear_memory(info, 0);*/
 922         pm3fb_clear_colormap(par, 0, 0, 0);
 923         PM3_WRITE_DAC_REG(par, PM3RD_CursorMode, 0);
 924         pm3fb_init_engine(info);
 925         pm3fb_write_mode(info);
 926         return 0;
 927 }
 928
 929 static int pm3fb_setcolreg(unsigned regno, unsigned red, unsigned green,
 930                            unsigned blue, unsigned transp,
 931                            struct fb_info *info)
 932 {
 933         struct pm3_par *par = info->par;
 934
 935         if (regno >= 256)  /* no. of hw registers */
 936            return -EINVAL;
 937
 938         /* grayscale works only partially under directcolor */
 939         if (info->var.grayscale) {
 940            /* grayscale = 0.30*R + 0.59*G + 0.11*B */
 941            red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
 942         }
 943
 944         /* Directcolor:
 945          *   var->{color}.offset contains start of bitfield
 946          *   var->{color}.length contains length of bitfield
 947          *   {hardwarespecific} contains width of DAC
 948          *   pseudo_palette[X] is programmed to (X << red.offset) |
 949          *                                      (X << green.offset) |
 950          *                                      (X << blue.offset)
 951          *   RAMDAC[X] is programmed to (red, green, blue)
 952          *   color depth = SUM(var->{color}.length)
 953          *
 954          * Pseudocolor:
 955          *      var->{color}.offset is 0
 956          *      var->{color}.length contains width of DAC or the number of unique
 957          *                      colors available (color depth)
 958          *      pseudo_palette is not used
 959          *      RAMDAC[X] is programmed to (red, green, blue)
 960          *      color depth = var->{color}.length
 961          */
 962
 963         /*
 964          * This is the point where the color is converted to something that
 965          * is acceptable by the hardware.
 966          */
 967 #define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16)
 968         red = CNVT_TOHW(red, info->var.red.length);
 969         green = CNVT_TOHW(green, info->var.green.length);
 970         blue = CNVT_TOHW(blue, info->var.blue.length);
 971         transp = CNVT_TOHW(transp, info->var.transp.length);
 972 #undef CNVT_TOHW
 973
 974         if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
 975         info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
 976                 u32 v;
 977
 978                 if (regno >= 16)
 979                         return -EINVAL;
 980
 981                 v = (red << info->var.red.offset) |
 982                         (green << info->var.green.offset) |
 983                         (blue << info->var.blue.offset) |
 984                         (transp << info->var.transp.offset);
 985
 986                 switch (info->var.bits_per_pixel) {
 987                 case 8:
 988                         break;
 989                 case 16:
 990                 case 32:
 991                         ((u32*)(info->pseudo_palette))[regno] = v;
 992                         break;
 993                 }
 994                 return 0;
 995         }
 996         else if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR)
 997                 pm3fb_set_color(par, regno, red, green, blue);
 998
 999         return 0;
1000 }
1001
1002 static int pm3fb_pan_display(struct fb_var_screeninfo *var,
1003                                  struct fb_info *info)
1004 {
1005         struct pm3_par *par = info->par;
1006         const u32 xres = (var->xres + 31) & ~31;
1007
1008         par->base = pm3fb_shift_bpp(var->bits_per_pixel,
1009                                         (var->yoffset * xres)
1010                                         + var->xoffset);
1011         PM3_WAIT(par, 1);
1012         PM3_WRITE_REG(par, PM3ScreenBase, par->base);
1013         return 0;
1014 }
1015
1016 static int pm3fb_blank(int blank_mode, struct fb_info *info)
1017 {
1018         struct pm3_par *par = info->par;
1019         u32 video = par->video;
1020
1021         /*
1022          * Oxygen VX1 - it appears that setting PM3VideoControl and
1023          * then PM3RD_SyncControl to the same SYNC settings undoes
1024          * any net change - they seem to xor together.  Only set the
1025          * sync options in PM3RD_SyncControl.  --rmk
1026          */
1027         video &= ~(PM3VideoControl_HSYNC_MASK |
1028                    PM3VideoControl_VSYNC_MASK);
1029         video |= PM3VideoControl_HSYNC_ACTIVE_HIGH |
1030                  PM3VideoControl_VSYNC_ACTIVE_HIGH;
1031
1032         switch (blank_mode) {
1033         case FB_BLANK_UNBLANK:
1034                 video |= PM3VideoControl_ENABLE;
1035                 break;
1036         case FB_BLANK_NORMAL:
1037                 video &= ~(PM3VideoControl_ENABLE);
1038                 break;
1039         case FB_BLANK_HSYNC_SUSPEND:
1040                 video &= ~(PM3VideoControl_HSYNC_MASK |
1041                           PM3VideoControl_BLANK_ACTIVE_LOW);
1042                 break;
1043         case FB_BLANK_VSYNC_SUSPEND:
1044                 video &= ~(PM3VideoControl_VSYNC_MASK |
1045                           PM3VideoControl_BLANK_ACTIVE_LOW);
1046                 break;
1047         case FB_BLANK_POWERDOWN:
1048                 video &= ~(PM3VideoControl_HSYNC_MASK |
1049                           PM3VideoControl_VSYNC_MASK |
1050                           PM3VideoControl_BLANK_ACTIVE_LOW);
1051                 break;
1052         default:
1053                 DPRINTK("Unsupported blanking %d\n", blank_mode);
1054                 return 1;
1055         }
1056
1057         PM3_WAIT(par, 1);
1058         PM3_WRITE_REG(par,PM3VideoControl, video);
1059         return 0;
1060 }
1061
1062         /*
1063          *  Frame buffer operations
1064          */
1065
1066 static struct fb_ops pm3fb_ops = {
1067         .owner          = THIS_MODULE,
1068         .fb_check_var   = pm3fb_check_var,
1069         .fb_set_par     = pm3fb_set_par,
1070         .fb_setcolreg   = pm3fb_setcolreg,
1071         .fb_pan_display = pm3fb_pan_display,
1072         .fb_fillrect    = pm3fb_fillrect,
1073         .fb_copyarea    = pm3fb_copyarea,
1074         .fb_imageblit   = pm3fb_imageblit,
1075         .fb_blank       = pm3fb_blank,
1076         .fb_sync        = pm3fb_sync,
1077 };
1078
1079 /* ------------------------------------------------------------------------- */
1080
1081         /*
1082          *  Initialization
1083          */
1084
1085 /* mmio register are already mapped when this function is called */
1086 /* the pm3fb_fix.smem_start is also set */
1087 static unsigned long pm3fb_size_memory(struct pm3_par *par)
1088 {
1089         unsigned long   memsize = 0, tempBypass, i, temp1, temp2;
1090         unsigned char   __iomem *screen_mem;
1091
1092         pm3fb_fix.smem_len = 64 * 1024l * 1024; /* request full aperture size */
1093         /* Linear frame buffer - request region and map it. */
1094         if (!request_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len,
1095                                  "pm3fb smem")) {
1096                 printk(KERN_WARNING "pm3fb: Can't reserve smem.\n");
1097                 return 0;
1098         }
1099         screen_mem =
1100                 ioremap_nocache(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
1101         if (!screen_mem) {
1102                 printk(KERN_WARNING "pm3fb: Can't ioremap smem area.\n");
1103                 release_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
1104                 return 0;
1105         }
1106
1107         /* TODO: card-specific stuff, *before* accessing *any* FB memory */
1108         /* For Appian Jeronimo 2000 board second head */
1109
1110         tempBypass = PM3_READ_REG(par, PM3MemBypassWriteMask);
1111
1112         DPRINTK("PM3MemBypassWriteMask was: 0x%08lx\n", tempBypass);
1113
1114         PM3_WAIT(par, 1);
1115         PM3_WRITE_REG(par, PM3MemBypassWriteMask, 0xFFFFFFFF);
1116
1117         /* pm3 split up memory, replicates, and do a lot of nasty stuff IMHO ;-) */
1118         for (i = 0; i < 32; i++) {
1119                 fb_writel(i * 0x00345678,
1120                           (screen_mem + (i * 1048576)));
1121                 mb();
1122                 temp1 = fb_readl((screen_mem + (i * 1048576)));
1123
1124                 /* Let's check for wrapover, write will fail at 16MB boundary */
1125                 if (temp1 == (i * 0x00345678))
1126                         memsize = i;
1127                 else
1128                         break;
1129         }
1130
1131         DPRINTK("First detect pass already got %ld MB\n", memsize + 1);
1132
1133         if (memsize + 1 == i) {
1134                 for (i = 0; i < 32; i++) {
1135                         /* Clear first 32MB ; 0 is 0, no need to byteswap */
1136                         writel(0x0000000, (screen_mem + (i * 1048576)));
1137                 }
1138                 wmb();
1139
1140                 for (i = 32; i < 64; i++) {
1141                         fb_writel(i * 0x00345678,
1142                                   (screen_mem + (i * 1048576)));
1143                         mb();
1144                         temp1 =
1145                             fb_readl((screen_mem + (i * 1048576)));
1146                         temp2 =
1147                             fb_readl((screen_mem + ((i - 32) * 1048576)));
1148                         /* different value, different RAM... */
1149                         if ((temp1 == (i * 0x00345678)) && (temp2 == 0))
1150                                 memsize = i;
1151                         else
1152                                 break;
1153                 }
1154         }
1155         DPRINTK("Second detect pass got %ld MB\n", memsize + 1);
1156
1157         PM3_WAIT(par, 1);
1158         PM3_WRITE_REG(par, PM3MemBypassWriteMask, tempBypass);
1159
1160         iounmap(screen_mem);
1161         release_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
1162         memsize = 1048576 * (memsize + 1);
1163
1164         DPRINTK("Returning 0x%08lx bytes\n", memsize);
1165
1166         return memsize;
1167 }
1168
1169 static int __devinit pm3fb_probe(struct pci_dev *dev,
1170                                   const struct pci_device_id *ent)
1171 {
1172         struct fb_info *info;
1173         struct pm3_par *par;
1174         struct device* device = &dev->dev; /* for pci drivers */
1175         int err, retval = -ENXIO;
1176
1177         err = pci_enable_device(dev);
1178         if (err) {
1179                 printk(KERN_WARNING "pm3fb: Can't enable PCI dev: %d\n", err);
1180                 return err;
1181         }
1182         /*
1183          * Dynamically allocate info and par
1184          */
1185         info = framebuffer_alloc(sizeof(struct pm3_par), device);
1186
1187         if (!info)
1188                 return -ENOMEM;
1189         par = info->par;
1190
1191         /*
1192          * Here we set the screen_base to the virtual memory address
1193          * for the framebuffer.
1194          */
1195         pm3fb_fix.mmio_start = pci_resource_start(dev, 0);
1196         pm3fb_fix.mmio_len = PM3_REGS_SIZE;
1197
1198         /* Registers - request region and map it. */
1199         if (!request_mem_region(pm3fb_fix.mmio_start, pm3fb_fix.mmio_len,
1200                                  "pm3fb regbase")) {
1201                 printk(KERN_WARNING "pm3fb: Can't reserve regbase.\n");
1202                 goto err_exit_neither;
1203         }
1204         par->v_regs =
1205                 ioremap_nocache(pm3fb_fix.mmio_start, pm3fb_fix.mmio_len);
1206         if (!par->v_regs) {
1207                 printk(KERN_WARNING "pm3fb: Can't remap %s register area.\n",
1208                         pm3fb_fix.id);
1209                 release_mem_region(pm3fb_fix.mmio_start, pm3fb_fix.mmio_len);
1210                 goto err_exit_neither;
1211         }
1212
1213 #if defined(__BIG_ENDIAN)
1214         pm3fb_fix.mmio_start += PM3_REGS_SIZE;
1215         DPRINTK("Adjusting register base for big-endian.\n");
1216 #endif
1217         /* Linear frame buffer - request region and map it. */
1218         pm3fb_fix.smem_start = pci_resource_start(dev, 1);
1219         pm3fb_fix.smem_len = pm3fb_size_memory(par);
1220         if (!pm3fb_fix.smem_len)
1221         {
1222                 printk(KERN_WARNING "pm3fb: Can't find memory on board.\n");
1223                 goto err_exit_mmio;
1224         }
1225         if (!request_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len,
1226                                  "pm3fb smem")) {
1227                 printk(KERN_WARNING "pm3fb: Can't reserve smem.\n");
1228                 goto err_exit_mmio;
1229         }
1230         info->screen_base =
1231                 ioremap_nocache(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
1232         if (!info->screen_base) {
1233                 printk(KERN_WARNING "pm3fb: Can't ioremap smem area.\n");
1234                 release_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
1235                 goto err_exit_mmio;
1236         }
1237         info->screen_size = pm3fb_fix.smem_len;
1238
1239         info->fbops = &pm3fb_ops;
1240
1241         par->video = PM3_READ_REG(par, PM3VideoControl);
1242
1243         info->fix = pm3fb_fix;
1244         info->pseudo_palette = par->palette;
1245         info->flags = FBINFO_DEFAULT |
1246 /*                      FBINFO_HWACCEL_YPAN |*/
1247                         FBINFO_HWACCEL_COPYAREA |
1248                         FBINFO_HWACCEL_IMAGEBLIT |
1249                         FBINFO_HWACCEL_FILLRECT;
1250
1251         info->pixmap.addr = kmalloc(PM3_PIXMAP_SIZE, GFP_KERNEL);
1252         if (!info->pixmap.addr) {
1253                 retval = -ENOMEM;
1254                 goto err_exit_pixmap;
1255         }
1256         info->pixmap.size = PM3_PIXMAP_SIZE;
1257         info->pixmap.buf_align = 4;
1258         info->pixmap.scan_align = 4;
1259         info->pixmap.access_align = 32;
1260         info->pixmap.flags = FB_PIXMAP_SYSTEM;
1261
1262         /*
1263          * This should give a reasonable default video mode. The following is
1264          * done when we can set a video mode.
1265          */
1266         if (!mode_option)
1267                 mode_option = "640x480@60";
1268
1269         retval = fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 8);
1270
1271         if (!retval || retval == 4) {
1272                 retval = -EINVAL;
1273                 goto err_exit_both;
1274         }
1275
1276         if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) {
1277                 retval = -ENOMEM;
1278                 goto err_exit_both;
1279         }
1280
1281         /*
1282          * For drivers that can...
1283          */
1284         pm3fb_check_var(&info->var, info);
1285
1286         if (register_framebuffer(info) < 0) {
1287                 retval = -EINVAL;
1288                 goto err_exit_all;
1289         }
1290         printk(KERN_INFO "fb%d: %s frame buffer device\n", info->node,
1291            info->fix.id);
1292         pci_set_drvdata(dev, info);
1293         return 0;
1294
1295  err_exit_all:
1296         fb_dealloc_cmap(&info->cmap);
1297  err_exit_both:
1298         kfree(info->pixmap.addr);
1299  err_exit_pixmap:
1300         iounmap(info->screen_base);
1301         release_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
1302  err_exit_mmio:
1303         iounmap(par->v_regs);
1304         release_mem_region(pm3fb_fix.mmio_start, pm3fb_fix.mmio_len);
1305  err_exit_neither:
1306         framebuffer_release(info);
1307         return retval;
1308 }
1309
1310         /*
1311          *  Cleanup
1312          */
1313 static void __devexit pm3fb_remove(struct pci_dev *dev)
1314 {
1315         struct fb_info *info = pci_get_drvdata(dev);
1316
1317         if (info) {
1318                 struct fb_fix_screeninfo *fix = &info->fix;
1319                 struct pm3_par *par = info->par;
1320
1321                 unregister_framebuffer(info);
1322                 fb_dealloc_cmap(&info->cmap);
1323
1324                 iounmap(info->screen_base);
1325                 release_mem_region(fix->smem_start, fix->smem_len);
1326                 iounmap(par->v_regs);
1327                 release_mem_region(fix->mmio_start, fix->mmio_len);
1328
1329                 pci_set_drvdata(dev, NULL);
1330                 kfree(info->pixmap.addr);
1331                 framebuffer_release(info);
1332         }
1333 }
1334
1335 static struct pci_device_id pm3fb_id_table[] = {
1336         { PCI_VENDOR_ID_3DLABS, 0x0a,
1337           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
1338         { 0, }
1339 };
1340
1341 /* For PCI drivers */
1342 static struct pci_driver pm3fb_driver = {
1343         .name =         "pm3fb",
1344         .id_table =     pm3fb_id_table,
1345         .probe =        pm3fb_probe,
1346         .remove =       __devexit_p(pm3fb_remove),
1347 };
1348
1349 MODULE_DEVICE_TABLE(pci, pm3fb_id_table);
1350
1351 static int __init pm3fb_init(void)
1352 {
1353 #ifndef MODULE
1354         if (fb_get_options("pm3fb", NULL))
1355                 return -ENODEV;
1356 #endif
1357         return pci_register_driver(&pm3fb_driver);
1358 }
1359
1360 static void __exit pm3fb_exit(void)
1361 {
1362         pci_unregister_driver(&pm3fb_driver);
1363 }
1364
1365 module_init(pm3fb_init);
1366 module_exit(pm3fb_exit);
1367
1368 MODULE_LICENSE("GPL");