2 * linux/drivers/video/pxafb.c
4 * Copyright (C) 1999 Eric A. Thomas.
5 * Copyright (C) 2004 Jean-Frederic Clere.
6 * Copyright (C) 2004 Ian Campbell.
7 * Copyright (C) 2004 Jeff Lackey.
8 * Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
10 * Based on acornfb.c Copyright (C) Russell King.
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file COPYING in the main directory of this archive for
16 * Intel PXA250/210 LCD Controller Frame Buffer Driver
18 * Please direct your questions and comments on this driver to the following
21 * linux-arm-kernel@lists.arm.linux.org.uk
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/kernel.h>
28 #include <linux/sched.h>
29 #include <linux/errno.h>
30 #include <linux/string.h>
31 #include <linux/interrupt.h>
32 #include <linux/slab.h>
35 #include <linux/delay.h>
36 #include <linux/init.h>
37 #include <linux/ioport.h>
38 #include <linux/cpufreq.h>
39 #include <linux/platform_device.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/clk.h>
42 #include <linux/err.h>
43 #include <linux/completion.h>
44 #include <linux/mutex.h>
45 #include <linux/kthread.h>
46 #include <linux/freezer.h>
48 #include <mach/hardware.h>
51 #include <asm/div64.h>
52 #include <mach/pxa-regs.h>
53 #include <mach/bitfield.h>
54 #include <mach/pxafb.h>
57 * Complain if VAR is out of range.
63 /* Bits which should not be set in machine configuration structures */
64 #define LCCR0_INVALID_CONFIG_MASK (LCCR0_OUM | LCCR0_BM | LCCR0_QDM |\
65 LCCR0_DIS | LCCR0_EFM | LCCR0_IUM |\
66 LCCR0_SFM | LCCR0_LDM | LCCR0_ENB)
68 #define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP | LCCR3_VSP |\
69 LCCR3_PCD | LCCR3_BPP)
71 static int pxafb_activate_var(struct fb_var_screeninfo *var,
73 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state);
75 static inline unsigned long
76 lcd_readl(struct pxafb_info *fbi, unsigned int off)
78 return __raw_readl(fbi->mmio_base + off);
82 lcd_writel(struct pxafb_info *fbi, unsigned int off, unsigned long val)
84 __raw_writel(val, fbi->mmio_base + off);
87 static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state)
91 local_irq_save(flags);
93 * We need to handle two requests being made at the same time.
94 * There are two important cases:
95 * 1. When we are changing VT (C_REENABLE) while unblanking
96 * (C_ENABLE) We must perform the unblanking, which will
97 * do our REENABLE for us.
98 * 2. When we are blanking, but immediately unblank before
99 * we have blanked. We do the "REENABLE" thing here as
100 * well, just to be sure.
102 if (fbi->task_state == C_ENABLE && state == C_REENABLE)
104 if (fbi->task_state == C_DISABLE && state == C_ENABLE)
107 if (state != (u_int)-1) {
108 fbi->task_state = state;
109 schedule_work(&fbi->task);
111 local_irq_restore(flags);
114 static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
117 chan >>= 16 - bf->length;
118 return chan << bf->offset;
122 pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
123 u_int trans, struct fb_info *info)
125 struct pxafb_info *fbi = (struct pxafb_info *)info;
128 if (regno >= fbi->palette_size)
131 if (fbi->fb.var.grayscale) {
132 fbi->palette_cpu[regno] = ((blue >> 8) & 0x00ff);
136 switch (fbi->lccr4 & LCCR4_PAL_FOR_MASK) {
137 case LCCR4_PAL_FOR_0:
138 val = ((red >> 0) & 0xf800);
139 val |= ((green >> 5) & 0x07e0);
140 val |= ((blue >> 11) & 0x001f);
141 fbi->palette_cpu[regno] = val;
143 case LCCR4_PAL_FOR_1:
144 val = ((red << 8) & 0x00f80000);
145 val |= ((green >> 0) & 0x0000fc00);
146 val |= ((blue >> 8) & 0x000000f8);
147 ((u32 *)(fbi->palette_cpu))[regno] = val;
149 case LCCR4_PAL_FOR_2:
150 val = ((red << 8) & 0x00fc0000);
151 val |= ((green >> 0) & 0x0000fc00);
152 val |= ((blue >> 8) & 0x000000fc);
153 ((u32 *)(fbi->palette_cpu))[regno] = val;
161 pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
162 u_int trans, struct fb_info *info)
164 struct pxafb_info *fbi = (struct pxafb_info *)info;
169 * If inverse mode was selected, invert all the colours
170 * rather than the register number. The register number
171 * is what you poke into the framebuffer to produce the
172 * colour you requested.
174 if (fbi->cmap_inverse) {
176 green = 0xffff - green;
177 blue = 0xffff - blue;
181 * If greyscale is true, then we convert the RGB value
182 * to greyscale no matter what visual we are using.
184 if (fbi->fb.var.grayscale)
185 red = green = blue = (19595 * red + 38470 * green +
188 switch (fbi->fb.fix.visual) {
189 case FB_VISUAL_TRUECOLOR:
191 * 16-bit True Colour. We encode the RGB value
192 * according to the RGB bitfield information.
195 u32 *pal = fbi->fb.pseudo_palette;
197 val = chan_to_field(red, &fbi->fb.var.red);
198 val |= chan_to_field(green, &fbi->fb.var.green);
199 val |= chan_to_field(blue, &fbi->fb.var.blue);
206 case FB_VISUAL_STATIC_PSEUDOCOLOR:
207 case FB_VISUAL_PSEUDOCOLOR:
208 ret = pxafb_setpalettereg(regno, red, green, blue, trans, info);
216 * pxafb_bpp_to_lccr3():
217 * Convert a bits per pixel value to the correct bit pattern for LCCR3
219 static int pxafb_bpp_to_lccr3(struct fb_var_screeninfo *var)
222 switch (var->bits_per_pixel) {
223 case 1: ret = LCCR3_1BPP; break;
224 case 2: ret = LCCR3_2BPP; break;
225 case 4: ret = LCCR3_4BPP; break;
226 case 8: ret = LCCR3_8BPP; break;
227 case 16: ret = LCCR3_16BPP; break;
229 switch (var->red.length + var->green.length +
230 var->blue.length + var->transp.length) {
231 case 18: ret = LCCR3_18BPP_P | LCCR3_PDFOR_3; break;
232 case 19: ret = LCCR3_19BPP_P; break;
236 switch (var->red.length + var->green.length +
237 var->blue.length + var->transp.length) {
238 case 18: ret = LCCR3_18BPP | LCCR3_PDFOR_3; break;
239 case 19: ret = LCCR3_19BPP; break;
240 case 24: ret = LCCR3_24BPP | LCCR3_PDFOR_3; break;
241 case 25: ret = LCCR3_25BPP; break;
248 #ifdef CONFIG_CPU_FREQ
250 * pxafb_display_dma_period()
251 * Calculate the minimum period (in picoseconds) between two DMA
252 * requests for the LCD controller. If we hit this, it means we're
253 * doing nothing but LCD DMA.
255 static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var)
258 * Period = pixclock * bits_per_byte * bytes_per_transfer
259 * / memory_bits_per_pixel;
261 return var->pixclock * 8 * 16 / var->bits_per_pixel;
266 * Select the smallest mode that allows the desired resolution to be
267 * displayed. If desired parameters can be rounded up.
269 static struct pxafb_mode_info *pxafb_getmode(struct pxafb_mach_info *mach,
270 struct fb_var_screeninfo *var)
272 struct pxafb_mode_info *mode = NULL;
273 struct pxafb_mode_info *modelist = mach->modes;
274 unsigned int best_x = 0xffffffff, best_y = 0xffffffff;
277 for (i = 0; i < mach->num_modes; i++) {
278 if (modelist[i].xres >= var->xres &&
279 modelist[i].yres >= var->yres &&
280 modelist[i].xres < best_x &&
281 modelist[i].yres < best_y &&
282 modelist[i].bpp >= var->bits_per_pixel) {
283 best_x = modelist[i].xres;
284 best_y = modelist[i].yres;
292 static void pxafb_setmode(struct fb_var_screeninfo *var,
293 struct pxafb_mode_info *mode)
295 var->xres = mode->xres;
296 var->yres = mode->yres;
297 var->bits_per_pixel = mode->bpp;
298 var->pixclock = mode->pixclock;
299 var->hsync_len = mode->hsync_len;
300 var->left_margin = mode->left_margin;
301 var->right_margin = mode->right_margin;
302 var->vsync_len = mode->vsync_len;
303 var->upper_margin = mode->upper_margin;
304 var->lower_margin = mode->lower_margin;
305 var->sync = mode->sync;
306 var->grayscale = mode->cmap_greyscale;
307 var->xres_virtual = var->xres;
308 var->yres_virtual = var->yres;
313 * Get the video params out of 'var'. If a value doesn't fit, round it up,
314 * if it's too big, return -EINVAL.
316 * Round up in the following order: bits_per_pixel, xres,
317 * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
318 * bitfields, horizontal timing, vertical timing.
320 static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
322 struct pxafb_info *fbi = (struct pxafb_info *)info;
323 struct pxafb_mach_info *inf = fbi->dev->platform_data;
325 if (var->xres < MIN_XRES)
326 var->xres = MIN_XRES;
327 if (var->yres < MIN_YRES)
328 var->yres = MIN_YRES;
330 if (inf->fixed_modes) {
331 struct pxafb_mode_info *mode;
333 mode = pxafb_getmode(inf, var);
336 pxafb_setmode(var, mode);
338 if (var->xres > inf->modes->xres)
340 if (var->yres > inf->modes->yres)
342 if (var->bits_per_pixel > inf->modes->bpp)
347 max(var->xres_virtual, var->xres);
349 max(var->yres_virtual, var->yres);
352 * Setup the RGB parameters for this display.
354 * The pixel packing format is described on page 7-11 of the
355 * PXA2XX Developer's Manual.
357 if (var->bits_per_pixel == 16) {
358 var->red.offset = 11; var->red.length = 5;
359 var->green.offset = 5; var->green.length = 6;
360 var->blue.offset = 0; var->blue.length = 5;
361 var->transp.offset = var->transp.length = 0;
362 } else if (var->bits_per_pixel > 16) {
363 struct pxafb_mode_info *mode;
365 mode = pxafb_getmode(inf, var);
369 switch (mode->depth) {
370 case 18: /* RGB666 */
371 var->transp.offset = var->transp.length = 0;
372 var->red.offset = 12; var->red.length = 6;
373 var->green.offset = 6; var->green.length = 6;
374 var->blue.offset = 0; var->blue.length = 6;
376 case 19: /* RGBT666 */
377 var->transp.offset = 18; var->transp.length = 1;
378 var->red.offset = 12; var->red.length = 6;
379 var->green.offset = 6; var->green.length = 6;
380 var->blue.offset = 0; var->blue.length = 6;
382 case 24: /* RGB888 */
383 var->transp.offset = var->transp.length = 0;
384 var->red.offset = 16; var->red.length = 8;
385 var->green.offset = 8; var->green.length = 8;
386 var->blue.offset = 0; var->blue.length = 8;
388 case 25: /* RGBT888 */
389 var->transp.offset = 24; var->transp.length = 1;
390 var->red.offset = 16; var->red.length = 8;
391 var->green.offset = 8; var->green.length = 8;
392 var->blue.offset = 0; var->blue.length = 8;
398 var->red.offset = var->green.offset = 0;
399 var->blue.offset = var->transp.offset = 0;
401 var->green.length = 8;
402 var->blue.length = 8;
403 var->transp.length = 0;
406 #ifdef CONFIG_CPU_FREQ
407 pr_debug("pxafb: dma period = %d ps\n",
408 pxafb_display_dma_period(var));
414 static inline void pxafb_set_truecolor(u_int is_true_color)
416 /* do your machine-specific setup if needed */
421 * Set the user defined part of the display for the specified console
423 static int pxafb_set_par(struct fb_info *info)
425 struct pxafb_info *fbi = (struct pxafb_info *)info;
426 struct fb_var_screeninfo *var = &info->var;
428 if (var->bits_per_pixel >= 16)
429 fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
430 else if (!fbi->cmap_static)
431 fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
434 * Some people have weird ideas about wanting static
435 * pseudocolor maps. I suspect their user space
436 * applications are broken.
438 fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
441 fbi->fb.fix.line_length = var->xres_virtual *
442 var->bits_per_pixel / 8;
443 if (var->bits_per_pixel >= 16)
444 fbi->palette_size = 0;
446 fbi->palette_size = var->bits_per_pixel == 1 ?
447 4 : 1 << var->bits_per_pixel;
449 fbi->palette_cpu = (u16 *)&fbi->dma_buff->palette[0];
452 * Set (any) board control register to handle new color depth
454 pxafb_set_truecolor(fbi->fb.fix.visual == FB_VISUAL_TRUECOLOR);
456 if (fbi->fb.var.bits_per_pixel >= 16)
457 fb_dealloc_cmap(&fbi->fb.cmap);
459 fb_alloc_cmap(&fbi->fb.cmap, 1<<fbi->fb.var.bits_per_pixel, 0);
461 pxafb_activate_var(var, fbi);
468 * Blank the display by setting all palette values to zero. Note, the
469 * 16 bpp mode does not really use the palette, so this will not
470 * blank the display in all modes.
472 static int pxafb_blank(int blank, struct fb_info *info)
474 struct pxafb_info *fbi = (struct pxafb_info *)info;
478 case FB_BLANK_POWERDOWN:
479 case FB_BLANK_VSYNC_SUSPEND:
480 case FB_BLANK_HSYNC_SUSPEND:
481 case FB_BLANK_NORMAL:
482 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
483 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
484 for (i = 0; i < fbi->palette_size; i++)
485 pxafb_setpalettereg(i, 0, 0, 0, 0, info);
487 pxafb_schedule_work(fbi, C_DISABLE);
488 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
491 case FB_BLANK_UNBLANK:
492 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
493 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
494 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
495 fb_set_cmap(&fbi->fb.cmap, info);
496 pxafb_schedule_work(fbi, C_ENABLE);
501 static int pxafb_mmap(struct fb_info *info,
502 struct vm_area_struct *vma)
504 struct pxafb_info *fbi = (struct pxafb_info *)info;
505 unsigned long off = vma->vm_pgoff << PAGE_SHIFT;
507 if (off < info->fix.smem_len) {
508 vma->vm_pgoff += fbi->video_offset / PAGE_SIZE;
509 return dma_mmap_writecombine(fbi->dev, vma, fbi->map_cpu,
510 fbi->map_dma, fbi->map_size);
515 static struct fb_ops pxafb_ops = {
516 .owner = THIS_MODULE,
517 .fb_check_var = pxafb_check_var,
518 .fb_set_par = pxafb_set_par,
519 .fb_setcolreg = pxafb_setcolreg,
520 .fb_fillrect = cfb_fillrect,
521 .fb_copyarea = cfb_copyarea,
522 .fb_imageblit = cfb_imageblit,
523 .fb_blank = pxafb_blank,
524 .fb_mmap = pxafb_mmap,
528 * Calculate the PCD value from the clock rate (in picoseconds).
529 * We take account of the PPCR clock setting.
530 * From PXA Developer's Manual:
541 * LCLK = LCD/Memory Clock
544 * PixelClock here is in Hz while the pixclock argument given is the
545 * period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 )
547 * The function get_lclk_frequency_10khz returns LCLK in units of
548 * 10khz. Calling the result of this function lclk gives us the
551 * PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 )
552 * -------------------------------------- - 1
555 * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below.
557 static inline unsigned int get_pcd(struct pxafb_info *fbi,
558 unsigned int pixclock)
560 unsigned long long pcd;
562 /* FIXME: Need to take into account Double Pixel Clock mode
563 * (DPC) bit? or perhaps set it based on the various clock
565 pcd = (unsigned long long)(clk_get_rate(fbi->clk) / 10000);
567 do_div(pcd, 100000000 * 2);
568 /* no need for this, since we should subtract 1 anyway. they cancel */
569 /* pcd += 1; */ /* make up for integer math truncations */
570 return (unsigned int)pcd;
574 * Some touchscreens need hsync information from the video driver to
575 * function correctly. We export it here. Note that 'hsync_time' and
576 * the value returned from pxafb_get_hsync_time() is the *reciprocal*
577 * of the hsync period in seconds.
579 static inline void set_hsync_time(struct pxafb_info *fbi, unsigned int pcd)
583 if ((pcd == 0) || (fbi->fb.var.hsync_len == 0)) {
588 htime = clk_get_rate(fbi->clk) / (pcd * fbi->fb.var.hsync_len);
590 fbi->hsync_time = htime;
593 unsigned long pxafb_get_hsync_time(struct device *dev)
595 struct pxafb_info *fbi = dev_get_drvdata(dev);
597 /* If display is blanked/suspended, hsync isn't active */
598 if (!fbi || (fbi->state != C_ENABLE))
601 return fbi->hsync_time;
603 EXPORT_SYMBOL(pxafb_get_hsync_time);
605 static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
606 unsigned int offset, size_t size)
608 struct pxafb_dma_descriptor *dma_desc, *pal_desc;
609 unsigned int dma_desc_off, pal_desc_off;
611 if (dma < 0 || dma >= DMA_MAX)
614 dma_desc = &fbi->dma_buff->dma_desc[dma];
615 dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[dma]);
617 dma_desc->fsadr = fbi->screen_dma + offset;
619 dma_desc->ldcmd = size;
621 if (pal < 0 || pal >= PAL_MAX) {
622 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
623 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
625 pal_desc = &fbi->dma_buff->pal_desc[pal];
626 pal_desc_off = offsetof(struct pxafb_dma_buff, pal_desc[pal]);
628 pal_desc->fsadr = fbi->dma_buff_phys + pal * PALETTE_SIZE;
631 if ((fbi->lccr4 & LCCR4_PAL_FOR_MASK) == LCCR4_PAL_FOR_0)
632 pal_desc->ldcmd = fbi->palette_size * sizeof(u16);
634 pal_desc->ldcmd = fbi->palette_size * sizeof(u32);
636 pal_desc->ldcmd |= LDCMD_PAL;
638 /* flip back and forth between palette and frame buffer */
639 pal_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
640 dma_desc->fdadr = fbi->dma_buff_phys + pal_desc_off;
641 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
647 #ifdef CONFIG_FB_PXA_SMARTPANEL
648 static int setup_smart_dma(struct pxafb_info *fbi)
650 struct pxafb_dma_descriptor *dma_desc;
651 unsigned long dma_desc_off, cmd_buff_off;
653 dma_desc = &fbi->dma_buff->dma_desc[DMA_CMD];
654 dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[DMA_CMD]);
655 cmd_buff_off = offsetof(struct pxafb_dma_buff, cmd_buff);
657 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
658 dma_desc->fsadr = fbi->dma_buff_phys + cmd_buff_off;
660 dma_desc->ldcmd = fbi->n_smart_cmds * sizeof(uint16_t);
662 fbi->fdadr[DMA_CMD] = dma_desc->fdadr;
666 int pxafb_smart_flush(struct fb_info *info)
668 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
672 /* disable controller until all registers are set up */
673 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
675 /* 1. make it an even number of commands to align on 32-bit boundary
676 * 2. add the interrupt command to the end of the chain so we can
677 * keep track of the end of the transfer
680 while (fbi->n_smart_cmds & 1)
681 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_NOOP;
683 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_INTERRUPT;
684 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_WAIT_FOR_VSYNC;
685 setup_smart_dma(fbi);
687 /* continue to execute next command */
688 prsr = lcd_readl(fbi, PRSR) | PRSR_ST_OK | PRSR_CON_NT;
689 lcd_writel(fbi, PRSR, prsr);
691 /* stop the processor in case it executed "wait for sync" cmd */
692 lcd_writel(fbi, CMDCR, 0x0001);
694 /* don't send interrupts for fifo underruns on channel 6 */
695 lcd_writel(fbi, LCCR5, LCCR5_IUM(6));
697 lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
698 lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
699 lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
700 lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
701 lcd_writel(fbi, FDADR6, fbi->fdadr[6]);
704 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
706 if (wait_for_completion_timeout(&fbi->command_done, HZ/2) == 0) {
707 pr_warning("%s: timeout waiting for command done\n",
713 prsr = lcd_readl(fbi, PRSR) & ~(PRSR_ST_OK | PRSR_CON_NT);
714 lcd_writel(fbi, PRSR, prsr);
715 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
716 lcd_writel(fbi, FDADR6, 0);
717 fbi->n_smart_cmds = 0;
721 int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
724 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
726 /* leave 2 commands for INTERRUPT and WAIT_FOR_SYNC */
727 for (i = 0; i < n_cmds; i++) {
728 if (fbi->n_smart_cmds == CMD_BUFF_SIZE - 8)
729 pxafb_smart_flush(info);
731 fbi->smart_cmds[fbi->n_smart_cmds++] = *cmds++;
737 static unsigned int __smart_timing(unsigned time_ns, unsigned long lcd_clk)
739 unsigned int t = (time_ns * (lcd_clk / 1000000) / 1000);
740 return (t == 0) ? 1 : t;
743 static void setup_smart_timing(struct pxafb_info *fbi,
744 struct fb_var_screeninfo *var)
746 struct pxafb_mach_info *inf = fbi->dev->platform_data;
747 struct pxafb_mode_info *mode = &inf->modes[0];
748 unsigned long lclk = clk_get_rate(fbi->clk);
749 unsigned t1, t2, t3, t4;
751 t1 = max(mode->a0csrd_set_hld, mode->a0cswr_set_hld);
752 t2 = max(mode->rd_pulse_width, mode->wr_pulse_width);
753 t3 = mode->op_hold_time;
754 t4 = mode->cmd_inh_time;
757 LCCR1_DisWdth(var->xres) |
758 LCCR1_BegLnDel(__smart_timing(t1, lclk)) |
759 LCCR1_EndLnDel(__smart_timing(t2, lclk)) |
760 LCCR1_HorSnchWdth(__smart_timing(t3, lclk));
762 fbi->reg_lccr2 = LCCR2_DisHght(var->yres);
763 fbi->reg_lccr3 = LCCR3_PixClkDiv(__smart_timing(t4, lclk));
765 /* FIXME: make this configurable */
769 static int pxafb_smart_thread(void *arg)
771 struct pxafb_info *fbi = arg;
772 struct pxafb_mach_info *inf = fbi->dev->platform_data;
774 if (!fbi || !inf->smart_update) {
775 pr_err("%s: not properly initialized, thread terminated\n",
780 pr_debug("%s(): task starting\n", __func__);
783 while (!kthread_should_stop()) {
788 if (fbi->state == C_ENABLE) {
789 inf->smart_update(&fbi->fb);
790 complete(&fbi->refresh_done);
793 set_current_state(TASK_INTERRUPTIBLE);
794 schedule_timeout(30 * HZ / 1000);
797 pr_debug("%s(): task ending\n", __func__);
801 static int pxafb_smart_init(struct pxafb_info *fbi)
803 if (!(fbi->lccr0 | LCCR0_LCDT))
806 fbi->smart_thread = kthread_run(pxafb_smart_thread, fbi,
808 if (IS_ERR(fbi->smart_thread)) {
809 printk(KERN_ERR "%s: unable to create kernel thread\n",
811 return PTR_ERR(fbi->smart_thread);
817 int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
822 int pxafb_smart_flush(struct fb_info *info)
826 #endif /* CONFIG_FB_SMART_PANEL */
828 static void setup_parallel_timing(struct pxafb_info *fbi,
829 struct fb_var_screeninfo *var)
831 unsigned int lines_per_panel, pcd = get_pcd(fbi, var->pixclock);
834 LCCR1_DisWdth(var->xres) +
835 LCCR1_HorSnchWdth(var->hsync_len) +
836 LCCR1_BegLnDel(var->left_margin) +
837 LCCR1_EndLnDel(var->right_margin);
840 * If we have a dual scan LCD, we need to halve
841 * the YRES parameter.
843 lines_per_panel = var->yres;
844 if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual)
845 lines_per_panel /= 2;
848 LCCR2_DisHght(lines_per_panel) +
849 LCCR2_VrtSnchWdth(var->vsync_len) +
850 LCCR2_BegFrmDel(var->upper_margin) +
851 LCCR2_EndFrmDel(var->lower_margin);
853 fbi->reg_lccr3 = fbi->lccr3 |
854 (var->sync & FB_SYNC_HOR_HIGH_ACT ?
855 LCCR3_HorSnchH : LCCR3_HorSnchL) |
856 (var->sync & FB_SYNC_VERT_HIGH_ACT ?
857 LCCR3_VrtSnchH : LCCR3_VrtSnchL);
860 fbi->reg_lccr3 |= LCCR3_PixClkDiv(pcd);
861 set_hsync_time(fbi, pcd);
866 * pxafb_activate_var():
867 * Configures LCD Controller based on entries in var parameter.
868 * Settings are only written to the controller if changes were made.
870 static int pxafb_activate_var(struct fb_var_screeninfo *var,
871 struct pxafb_info *fbi)
877 if (!(fbi->lccr0 & LCCR0_LCDT)) {
878 if (var->xres < 16 || var->xres > 1024)
879 printk(KERN_ERR "%s: invalid xres %d\n",
880 fbi->fb.fix.id, var->xres);
881 switch (var->bits_per_pixel) {
891 printk(KERN_ERR "%s: invalid bit depth %d\n",
892 fbi->fb.fix.id, var->bits_per_pixel);
896 if (var->hsync_len < 1 || var->hsync_len > 64)
897 printk(KERN_ERR "%s: invalid hsync_len %d\n",
898 fbi->fb.fix.id, var->hsync_len);
899 if (var->left_margin < 1 || var->left_margin > 255)
900 printk(KERN_ERR "%s: invalid left_margin %d\n",
901 fbi->fb.fix.id, var->left_margin);
902 if (var->right_margin < 1 || var->right_margin > 255)
903 printk(KERN_ERR "%s: invalid right_margin %d\n",
904 fbi->fb.fix.id, var->right_margin);
905 if (var->yres < 1 || var->yres > 1024)
906 printk(KERN_ERR "%s: invalid yres %d\n",
907 fbi->fb.fix.id, var->yres);
908 if (var->vsync_len < 1 || var->vsync_len > 64)
909 printk(KERN_ERR "%s: invalid vsync_len %d\n",
910 fbi->fb.fix.id, var->vsync_len);
911 if (var->upper_margin < 0 || var->upper_margin > 255)
912 printk(KERN_ERR "%s: invalid upper_margin %d\n",
913 fbi->fb.fix.id, var->upper_margin);
914 if (var->lower_margin < 0 || var->lower_margin > 255)
915 printk(KERN_ERR "%s: invalid lower_margin %d\n",
916 fbi->fb.fix.id, var->lower_margin);
919 /* Update shadow copy atomically */
920 local_irq_save(flags);
922 #ifdef CONFIG_FB_PXA_SMARTPANEL
923 if (fbi->lccr0 & LCCR0_LCDT)
924 setup_smart_timing(fbi, var);
927 setup_parallel_timing(fbi, var);
929 fbi->reg_lccr0 = fbi->lccr0 |
930 (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM |
931 LCCR0_QDM | LCCR0_BM | LCCR0_OUM);
933 fbi->reg_lccr3 |= pxafb_bpp_to_lccr3(var);
935 nbytes = var->yres * fbi->fb.fix.line_length;
937 if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual) {
939 setup_frame_dma(fbi, DMA_LOWER, PAL_NONE, nbytes, nbytes);
942 if ((var->bits_per_pixel >= 16) || (fbi->lccr0 & LCCR0_LCDT))
943 setup_frame_dma(fbi, DMA_BASE, PAL_NONE, 0, nbytes);
945 setup_frame_dma(fbi, DMA_BASE, PAL_BASE, 0, nbytes);
947 fbi->reg_lccr4 = lcd_readl(fbi, LCCR4) & ~LCCR4_PAL_FOR_MASK;
948 fbi->reg_lccr4 |= (fbi->lccr4 & LCCR4_PAL_FOR_MASK);
949 local_irq_restore(flags);
952 * Only update the registers if the controller is enabled
953 * and something has changed.
955 if ((lcd_readl(fbi, LCCR0) != fbi->reg_lccr0) ||
956 (lcd_readl(fbi, LCCR1) != fbi->reg_lccr1) ||
957 (lcd_readl(fbi, LCCR2) != fbi->reg_lccr2) ||
958 (lcd_readl(fbi, LCCR3) != fbi->reg_lccr3) ||
959 (lcd_readl(fbi, FDADR0) != fbi->fdadr[0]) ||
960 (lcd_readl(fbi, FDADR1) != fbi->fdadr[1]))
961 pxafb_schedule_work(fbi, C_REENABLE);
967 * NOTE! The following functions are purely helpers for set_ctrlr_state.
968 * Do not call them directly; set_ctrlr_state does the correct serialisation
969 * to ensure that things happen in the right way 100% of time time.
972 static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on)
974 pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff");
976 if (fbi->backlight_power)
977 fbi->backlight_power(on);
980 static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on)
982 pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff");
985 fbi->lcd_power(on, &fbi->fb.var);
988 static void pxafb_enable_controller(struct pxafb_info *fbi)
990 pr_debug("pxafb: Enabling LCD controller\n");
991 pr_debug("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr[0]);
992 pr_debug("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr[1]);
993 pr_debug("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0);
994 pr_debug("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1);
995 pr_debug("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2);
996 pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3);
998 /* enable LCD controller clock */
999 clk_enable(fbi->clk);
1001 if (fbi->lccr0 & LCCR0_LCDT)
1004 /* Sequence from 11.7.10 */
1005 lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
1006 lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
1007 lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
1008 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
1010 lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
1011 lcd_writel(fbi, FDADR1, fbi->fdadr[1]);
1012 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
1015 static void pxafb_disable_controller(struct pxafb_info *fbi)
1019 #ifdef CONFIG_FB_PXA_SMARTPANEL
1020 if (fbi->lccr0 & LCCR0_LCDT) {
1021 wait_for_completion_timeout(&fbi->refresh_done,
1027 /* Clear LCD Status Register */
1028 lcd_writel(fbi, LCSR, 0xffffffff);
1030 lccr0 = lcd_readl(fbi, LCCR0) & ~LCCR0_LDM;
1031 lcd_writel(fbi, LCCR0, lccr0);
1032 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_DIS);
1034 wait_for_completion_timeout(&fbi->disable_done, 200 * HZ / 1000);
1036 /* disable LCD controller clock */
1037 clk_disable(fbi->clk);
1041 * pxafb_handle_irq: Handle 'LCD DONE' interrupts.
1043 static irqreturn_t pxafb_handle_irq(int irq, void *dev_id)
1045 struct pxafb_info *fbi = dev_id;
1046 unsigned int lccr0, lcsr = lcd_readl(fbi, LCSR);
1048 if (lcsr & LCSR_LDD) {
1049 lccr0 = lcd_readl(fbi, LCCR0);
1050 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_LDM);
1051 complete(&fbi->disable_done);
1054 #ifdef CONFIG_FB_PXA_SMARTPANEL
1055 if (lcsr & LCSR_CMD_INT)
1056 complete(&fbi->command_done);
1059 lcd_writel(fbi, LCSR, lcsr);
1064 * This function must be called from task context only, since it will
1065 * sleep when disabling the LCD controller, or if we get two contending
1066 * processes trying to alter state.
1068 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
1072 mutex_lock(&fbi->ctrlr_lock);
1074 old_state = fbi->state;
1077 * Hack around fbcon initialisation.
1079 if (old_state == C_STARTUP && state == C_REENABLE)
1083 case C_DISABLE_CLKCHANGE:
1085 * Disable controller for clock change. If the
1086 * controller is already disabled, then do nothing.
1088 if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
1090 /* TODO __pxafb_lcd_power(fbi, 0); */
1091 pxafb_disable_controller(fbi);
1098 * Disable controller
1100 if (old_state != C_DISABLE) {
1102 __pxafb_backlight_power(fbi, 0);
1103 __pxafb_lcd_power(fbi, 0);
1104 if (old_state != C_DISABLE_CLKCHANGE)
1105 pxafb_disable_controller(fbi);
1109 case C_ENABLE_CLKCHANGE:
1111 * Enable the controller after clock change. Only
1112 * do this if we were disabled for the clock change.
1114 if (old_state == C_DISABLE_CLKCHANGE) {
1115 fbi->state = C_ENABLE;
1116 pxafb_enable_controller(fbi);
1117 /* TODO __pxafb_lcd_power(fbi, 1); */
1123 * Re-enable the controller only if it was already
1124 * enabled. This is so we reprogram the control
1127 if (old_state == C_ENABLE) {
1128 __pxafb_lcd_power(fbi, 0);
1129 pxafb_disable_controller(fbi);
1130 pxafb_enable_controller(fbi);
1131 __pxafb_lcd_power(fbi, 1);
1137 * Re-enable the controller after PM. This is not
1138 * perfect - think about the case where we were doing
1139 * a clock change, and we suspended half-way through.
1141 if (old_state != C_DISABLE_PM)
1147 * Power up the LCD screen, enable controller, and
1148 * turn on the backlight.
1150 if (old_state != C_ENABLE) {
1151 fbi->state = C_ENABLE;
1152 pxafb_enable_controller(fbi);
1153 __pxafb_lcd_power(fbi, 1);
1154 __pxafb_backlight_power(fbi, 1);
1158 mutex_unlock(&fbi->ctrlr_lock);
1162 * Our LCD controller task (which is called when we blank or unblank)
1165 static void pxafb_task(struct work_struct *work)
1167 struct pxafb_info *fbi =
1168 container_of(work, struct pxafb_info, task);
1169 u_int state = xchg(&fbi->task_state, -1);
1171 set_ctrlr_state(fbi, state);
1174 #ifdef CONFIG_CPU_FREQ
1176 * CPU clock speed change handler. We need to adjust the LCD timing
1177 * parameters when the CPU clock is adjusted by the power management
1180 * TODO: Determine why f->new != 10*get_lclk_frequency_10khz()
1183 pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data)
1185 struct pxafb_info *fbi = TO_INF(nb, freq_transition);
1186 /* TODO struct cpufreq_freqs *f = data; */
1190 case CPUFREQ_PRECHANGE:
1191 set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
1194 case CPUFREQ_POSTCHANGE:
1195 pcd = get_pcd(fbi, fbi->fb.var.pixclock);
1196 set_hsync_time(fbi, pcd);
1197 fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) |
1198 LCCR3_PixClkDiv(pcd);
1199 set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
1206 pxafb_freq_policy(struct notifier_block *nb, unsigned long val, void *data)
1208 struct pxafb_info *fbi = TO_INF(nb, freq_policy);
1209 struct fb_var_screeninfo *var = &fbi->fb.var;
1210 struct cpufreq_policy *policy = data;
1213 case CPUFREQ_ADJUST:
1214 case CPUFREQ_INCOMPATIBLE:
1215 pr_debug("min dma period: %d ps, "
1216 "new clock %d kHz\n", pxafb_display_dma_period(var),
1218 /* TODO: fill in min/max values */
1227 * Power management hooks. Note that we won't be called from IRQ context,
1228 * unlike the blank functions above, so we may sleep.
1230 static int pxafb_suspend(struct platform_device *dev, pm_message_t state)
1232 struct pxafb_info *fbi = platform_get_drvdata(dev);
1234 set_ctrlr_state(fbi, C_DISABLE_PM);
1238 static int pxafb_resume(struct platform_device *dev)
1240 struct pxafb_info *fbi = platform_get_drvdata(dev);
1242 set_ctrlr_state(fbi, C_ENABLE_PM);
1246 #define pxafb_suspend NULL
1247 #define pxafb_resume NULL
1251 * pxafb_map_video_memory():
1252 * Allocates the DRAM memory for the frame buffer. This buffer is
1253 * remapped into a non-cached, non-buffered, memory region to
1254 * allow palette and pixel writes to occur without flushing the
1255 * cache. Once this area is remapped, all virtual memory
1256 * access to the video memory should occur at the new region.
1258 static int __devinit pxafb_map_video_memory(struct pxafb_info *fbi)
1261 * We reserve one page for the palette, plus the size
1262 * of the framebuffer.
1264 fbi->video_offset = PAGE_ALIGN(sizeof(struct pxafb_dma_buff));
1265 fbi->map_size = PAGE_ALIGN(fbi->fb.fix.smem_len + fbi->video_offset);
1266 fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size,
1267 &fbi->map_dma, GFP_KERNEL);
1270 /* prevent initial garbage on screen */
1271 memset(fbi->map_cpu, 0, fbi->map_size);
1272 fbi->fb.screen_base = fbi->map_cpu + fbi->video_offset;
1273 fbi->screen_dma = fbi->map_dma + fbi->video_offset;
1276 * FIXME: this is actually the wrong thing to place in
1277 * smem_start. But fbdev suffers from the problem that
1278 * it needs an API which doesn't exist (in this case,
1279 * dma_writecombine_mmap)
1281 fbi->fb.fix.smem_start = fbi->screen_dma;
1282 fbi->palette_size = fbi->fb.var.bits_per_pixel == 8 ? 256 : 16;
1284 fbi->dma_buff = (void *) fbi->map_cpu;
1285 fbi->dma_buff_phys = fbi->map_dma;
1286 fbi->palette_cpu = (u16 *) fbi->dma_buff->palette;
1288 pr_debug("pxafb: palette_mem_size = 0x%08x\n", fbi->palette_size*sizeof(u16));
1290 #ifdef CONFIG_FB_PXA_SMARTPANEL
1291 fbi->smart_cmds = (uint16_t *) fbi->dma_buff->cmd_buff;
1292 fbi->n_smart_cmds = 0;
1296 return fbi->map_cpu ? 0 : -ENOMEM;
1299 static void pxafb_decode_mode_info(struct pxafb_info *fbi,
1300 struct pxafb_mode_info *modes,
1301 unsigned int num_modes)
1303 unsigned int i, smemlen;
1305 pxafb_setmode(&fbi->fb.var, &modes[0]);
1307 for (i = 0; i < num_modes; i++) {
1308 smemlen = modes[i].xres * modes[i].yres * modes[i].bpp / 8;
1309 if (smemlen > fbi->fb.fix.smem_len)
1310 fbi->fb.fix.smem_len = smemlen;
1314 static void pxafb_decode_mach_info(struct pxafb_info *fbi,
1315 struct pxafb_mach_info *inf)
1317 unsigned int lcd_conn = inf->lcd_conn;
1319 fbi->cmap_inverse = inf->cmap_inverse;
1320 fbi->cmap_static = inf->cmap_static;
1322 switch (lcd_conn & LCD_TYPE_MASK) {
1323 case LCD_TYPE_MONO_STN:
1324 fbi->lccr0 = LCCR0_CMS;
1326 case LCD_TYPE_MONO_DSTN:
1327 fbi->lccr0 = LCCR0_CMS | LCCR0_SDS;
1329 case LCD_TYPE_COLOR_STN:
1332 case LCD_TYPE_COLOR_DSTN:
1333 fbi->lccr0 = LCCR0_SDS;
1335 case LCD_TYPE_COLOR_TFT:
1336 fbi->lccr0 = LCCR0_PAS;
1338 case LCD_TYPE_SMART_PANEL:
1339 fbi->lccr0 = LCCR0_LCDT | LCCR0_PAS;
1342 /* fall back to backward compatibility way */
1343 fbi->lccr0 = inf->lccr0;
1344 fbi->lccr3 = inf->lccr3;
1345 fbi->lccr4 = inf->lccr4;
1349 if (lcd_conn == LCD_MONO_STN_8BPP)
1350 fbi->lccr0 |= LCCR0_DPD;
1352 fbi->lccr0 |= (lcd_conn & LCD_ALTERNATE_MAPPING) ? LCCR0_LDDALT : 0;
1354 fbi->lccr3 = LCCR3_Acb((inf->lcd_conn >> 10) & 0xff);
1355 fbi->lccr3 |= (lcd_conn & LCD_BIAS_ACTIVE_LOW) ? LCCR3_OEP : 0;
1356 fbi->lccr3 |= (lcd_conn & LCD_PCLK_EDGE_FALL) ? LCCR3_PCP : 0;
1359 pxafb_decode_mode_info(fbi, inf->modes, inf->num_modes);
1362 static struct pxafb_info * __devinit pxafb_init_fbinfo(struct device *dev)
1364 struct pxafb_info *fbi;
1366 struct pxafb_mach_info *inf = dev->platform_data;
1368 /* Alloc the pxafb_info and pseudo_palette in one step */
1369 fbi = kmalloc(sizeof(struct pxafb_info) + sizeof(u32) * 16, GFP_KERNEL);
1373 memset(fbi, 0, sizeof(struct pxafb_info));
1376 fbi->clk = clk_get(dev, "LCDCLK");
1377 if (IS_ERR(fbi->clk)) {
1382 strcpy(fbi->fb.fix.id, PXA_NAME);
1384 fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS;
1385 fbi->fb.fix.type_aux = 0;
1386 fbi->fb.fix.xpanstep = 0;
1387 fbi->fb.fix.ypanstep = 0;
1388 fbi->fb.fix.ywrapstep = 0;
1389 fbi->fb.fix.accel = FB_ACCEL_NONE;
1391 fbi->fb.var.nonstd = 0;
1392 fbi->fb.var.activate = FB_ACTIVATE_NOW;
1393 fbi->fb.var.height = -1;
1394 fbi->fb.var.width = -1;
1395 fbi->fb.var.accel_flags = 0;
1396 fbi->fb.var.vmode = FB_VMODE_NONINTERLACED;
1398 fbi->fb.fbops = &pxafb_ops;
1399 fbi->fb.flags = FBINFO_DEFAULT;
1403 addr = addr + sizeof(struct pxafb_info);
1404 fbi->fb.pseudo_palette = addr;
1406 fbi->state = C_STARTUP;
1407 fbi->task_state = (u_char)-1;
1409 pxafb_decode_mach_info(fbi, inf);
1411 init_waitqueue_head(&fbi->ctrlr_wait);
1412 INIT_WORK(&fbi->task, pxafb_task);
1413 mutex_init(&fbi->ctrlr_lock);
1414 init_completion(&fbi->disable_done);
1415 #ifdef CONFIG_FB_PXA_SMARTPANEL
1416 init_completion(&fbi->command_done);
1417 init_completion(&fbi->refresh_done);
1423 #ifdef CONFIG_FB_PXA_PARAMETERS
1424 static int __devinit parse_opt_mode(struct device *dev, const char *this_opt)
1426 struct pxafb_mach_info *inf = dev->platform_data;
1428 const char *name = this_opt+5;
1429 unsigned int namelen = strlen(name);
1430 int res_specified = 0, bpp_specified = 0;
1431 unsigned int xres = 0, yres = 0, bpp = 0;
1432 int yres_specified = 0;
1434 for (i = namelen-1; i >= 0; i--) {
1438 if (!bpp_specified && !yres_specified) {
1439 bpp = simple_strtoul(&name[i+1], NULL, 0);
1445 if (!yres_specified) {
1446 yres = simple_strtoul(&name[i+1], NULL, 0);
1457 if (i < 0 && yres_specified) {
1458 xres = simple_strtoul(name, NULL, 0);
1462 if (res_specified) {
1463 dev_info(dev, "overriding resolution: %dx%d\n", xres, yres);
1464 inf->modes[0].xres = xres; inf->modes[0].yres = yres;
1473 inf->modes[0].bpp = bpp;
1474 dev_info(dev, "overriding bit depth: %d\n", bpp);
1477 dev_err(dev, "Depth %d is not valid\n", bpp);
1483 static int __devinit parse_opt(struct device *dev, char *this_opt)
1485 struct pxafb_mach_info *inf = dev->platform_data;
1486 struct pxafb_mode_info *mode = &inf->modes[0];
1491 if (!strncmp(this_opt, "mode:", 5)) {
1492 return parse_opt_mode(dev, this_opt);
1493 } else if (!strncmp(this_opt, "pixclock:", 9)) {
1494 mode->pixclock = simple_strtoul(this_opt+9, NULL, 0);
1495 sprintf(s, "pixclock: %ld\n", mode->pixclock);
1496 } else if (!strncmp(this_opt, "left:", 5)) {
1497 mode->left_margin = simple_strtoul(this_opt+5, NULL, 0);
1498 sprintf(s, "left: %u\n", mode->left_margin);
1499 } else if (!strncmp(this_opt, "right:", 6)) {
1500 mode->right_margin = simple_strtoul(this_opt+6, NULL, 0);
1501 sprintf(s, "right: %u\n", mode->right_margin);
1502 } else if (!strncmp(this_opt, "upper:", 6)) {
1503 mode->upper_margin = simple_strtoul(this_opt+6, NULL, 0);
1504 sprintf(s, "upper: %u\n", mode->upper_margin);
1505 } else if (!strncmp(this_opt, "lower:", 6)) {
1506 mode->lower_margin = simple_strtoul(this_opt+6, NULL, 0);
1507 sprintf(s, "lower: %u\n", mode->lower_margin);
1508 } else if (!strncmp(this_opt, "hsynclen:", 9)) {
1509 mode->hsync_len = simple_strtoul(this_opt+9, NULL, 0);
1510 sprintf(s, "hsynclen: %u\n", mode->hsync_len);
1511 } else if (!strncmp(this_opt, "vsynclen:", 9)) {
1512 mode->vsync_len = simple_strtoul(this_opt+9, NULL, 0);
1513 sprintf(s, "vsynclen: %u\n", mode->vsync_len);
1514 } else if (!strncmp(this_opt, "hsync:", 6)) {
1515 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1516 sprintf(s, "hsync: Active Low\n");
1517 mode->sync &= ~FB_SYNC_HOR_HIGH_ACT;
1519 sprintf(s, "hsync: Active High\n");
1520 mode->sync |= FB_SYNC_HOR_HIGH_ACT;
1522 } else if (!strncmp(this_opt, "vsync:", 6)) {
1523 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1524 sprintf(s, "vsync: Active Low\n");
1525 mode->sync &= ~FB_SYNC_VERT_HIGH_ACT;
1527 sprintf(s, "vsync: Active High\n");
1528 mode->sync |= FB_SYNC_VERT_HIGH_ACT;
1530 } else if (!strncmp(this_opt, "dpc:", 4)) {
1531 if (simple_strtoul(this_opt+4, NULL, 0) == 0) {
1532 sprintf(s, "double pixel clock: false\n");
1533 inf->lccr3 &= ~LCCR3_DPC;
1535 sprintf(s, "double pixel clock: true\n");
1536 inf->lccr3 |= LCCR3_DPC;
1538 } else if (!strncmp(this_opt, "outputen:", 9)) {
1539 if (simple_strtoul(this_opt+9, NULL, 0) == 0) {
1540 sprintf(s, "output enable: active low\n");
1541 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnL;
1543 sprintf(s, "output enable: active high\n");
1544 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnH;
1546 } else if (!strncmp(this_opt, "pixclockpol:", 12)) {
1547 if (simple_strtoul(this_opt+12, NULL, 0) == 0) {
1548 sprintf(s, "pixel clock polarity: falling edge\n");
1549 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixFlEdg;
1551 sprintf(s, "pixel clock polarity: rising edge\n");
1552 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixRsEdg;
1554 } else if (!strncmp(this_opt, "color", 5)) {
1555 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color;
1556 } else if (!strncmp(this_opt, "mono", 4)) {
1557 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono;
1558 } else if (!strncmp(this_opt, "active", 6)) {
1559 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act;
1560 } else if (!strncmp(this_opt, "passive", 7)) {
1561 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas;
1562 } else if (!strncmp(this_opt, "single", 6)) {
1563 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl;
1564 } else if (!strncmp(this_opt, "dual", 4)) {
1565 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual;
1566 } else if (!strncmp(this_opt, "4pix", 4)) {
1567 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono;
1568 } else if (!strncmp(this_opt, "8pix", 4)) {
1569 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono;
1571 dev_err(dev, "unknown option: %s\n", this_opt);
1576 dev_info(dev, "override %s", s);
1581 static int __devinit pxafb_parse_options(struct device *dev, char *options)
1586 if (!options || !*options)
1589 dev_dbg(dev, "options are \"%s\"\n", options ? options : "null");
1591 /* could be made table driven or similar?... */
1592 while ((this_opt = strsep(&options, ",")) != NULL) {
1593 ret = parse_opt(dev, this_opt);
1600 static char g_options[256] __devinitdata = "";
1603 static int __init pxafb_setup_options(void)
1605 char *options = NULL;
1607 if (fb_get_options("pxafb", &options))
1611 strlcpy(g_options, options, sizeof(g_options));
1616 #define pxafb_setup_options() (0)
1618 module_param_string(options, g_options, sizeof(g_options), 0);
1619 MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.txt)");
1623 #define pxafb_parse_options(...) (0)
1624 #define pxafb_setup_options() (0)
1628 /* Check for various illegal bit-combinations. Currently only
1629 * a warning is given. */
1630 static void __devinit pxafb_check_options(struct device *dev,
1631 struct pxafb_mach_info *inf)
1636 if (inf->lccr0 & LCCR0_INVALID_CONFIG_MASK)
1637 dev_warn(dev, "machine LCCR0 setting contains "
1638 "illegal bits: %08x\n",
1639 inf->lccr0 & LCCR0_INVALID_CONFIG_MASK);
1640 if (inf->lccr3 & LCCR3_INVALID_CONFIG_MASK)
1641 dev_warn(dev, "machine LCCR3 setting contains "
1642 "illegal bits: %08x\n",
1643 inf->lccr3 & LCCR3_INVALID_CONFIG_MASK);
1644 if (inf->lccr0 & LCCR0_DPD &&
1645 ((inf->lccr0 & LCCR0_PAS) != LCCR0_Pas ||
1646 (inf->lccr0 & LCCR0_SDS) != LCCR0_Sngl ||
1647 (inf->lccr0 & LCCR0_CMS) != LCCR0_Mono))
1648 dev_warn(dev, "Double Pixel Data (DPD) mode is "
1649 "only valid in passive mono"
1650 " single panel mode\n");
1651 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Act &&
1652 (inf->lccr0 & LCCR0_SDS) == LCCR0_Dual)
1653 dev_warn(dev, "Dual panel only valid in passive mode\n");
1654 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Pas &&
1655 (inf->modes->upper_margin || inf->modes->lower_margin))
1656 dev_warn(dev, "Upper and lower margins must be 0 in "
1660 #define pxafb_check_options(...) do {} while (0)
1663 static int __devinit pxafb_probe(struct platform_device *dev)
1665 struct pxafb_info *fbi;
1666 struct pxafb_mach_info *inf;
1670 dev_dbg(&dev->dev, "pxafb_probe\n");
1672 inf = dev->dev.platform_data;
1678 ret = pxafb_parse_options(&dev->dev, g_options);
1682 pxafb_check_options(&dev->dev, inf);
1684 dev_dbg(&dev->dev, "got a %dx%dx%d LCD\n",
1688 if (inf->modes->xres == 0 ||
1689 inf->modes->yres == 0 ||
1690 inf->modes->bpp == 0) {
1691 dev_err(&dev->dev, "Invalid resolution or bit depth\n");
1696 fbi = pxafb_init_fbinfo(&dev->dev);
1698 /* only reason for pxafb_init_fbinfo to fail is kmalloc */
1699 dev_err(&dev->dev, "Failed to initialize framebuffer device\n");
1704 fbi->backlight_power = inf->pxafb_backlight_power;
1705 fbi->lcd_power = inf->pxafb_lcd_power;
1707 r = platform_get_resource(dev, IORESOURCE_MEM, 0);
1709 dev_err(&dev->dev, "no I/O memory resource defined\n");
1714 r = request_mem_region(r->start, r->end - r->start + 1, dev->name);
1716 dev_err(&dev->dev, "failed to request I/O memory\n");
1721 fbi->mmio_base = ioremap(r->start, r->end - r->start + 1);
1722 if (fbi->mmio_base == NULL) {
1723 dev_err(&dev->dev, "failed to map I/O memory\n");
1725 goto failed_free_res;
1728 /* Initialize video memory */
1729 ret = pxafb_map_video_memory(fbi);
1731 dev_err(&dev->dev, "Failed to allocate video RAM: %d\n", ret);
1733 goto failed_free_io;
1736 irq = platform_get_irq(dev, 0);
1738 dev_err(&dev->dev, "no IRQ defined\n");
1740 goto failed_free_mem;
1743 ret = request_irq(irq, pxafb_handle_irq, IRQF_DISABLED, "LCD", fbi);
1745 dev_err(&dev->dev, "request_irq failed: %d\n", ret);
1747 goto failed_free_mem;
1750 #ifdef CONFIG_FB_PXA_SMARTPANEL
1751 ret = pxafb_smart_init(fbi);
1753 dev_err(&dev->dev, "failed to initialize smartpanel\n");
1754 goto failed_free_irq;
1758 * This makes sure that our colour bitfield
1759 * descriptors are correctly initialised.
1761 ret = pxafb_check_var(&fbi->fb.var, &fbi->fb);
1763 dev_err(&dev->dev, "failed to get suitable mode\n");
1764 goto failed_free_irq;
1767 ret = pxafb_set_par(&fbi->fb);
1769 dev_err(&dev->dev, "Failed to set parameters\n");
1770 goto failed_free_irq;
1773 platform_set_drvdata(dev, fbi);
1775 ret = register_framebuffer(&fbi->fb);
1778 "Failed to register framebuffer device: %d\n", ret);
1779 goto failed_free_cmap;
1782 #ifdef CONFIG_CPU_FREQ
1783 fbi->freq_transition.notifier_call = pxafb_freq_transition;
1784 fbi->freq_policy.notifier_call = pxafb_freq_policy;
1785 cpufreq_register_notifier(&fbi->freq_transition,
1786 CPUFREQ_TRANSITION_NOTIFIER);
1787 cpufreq_register_notifier(&fbi->freq_policy,
1788 CPUFREQ_POLICY_NOTIFIER);
1792 * Ok, now enable the LCD controller
1794 set_ctrlr_state(fbi, C_ENABLE);
1799 if (fbi->fb.cmap.len)
1800 fb_dealloc_cmap(&fbi->fb.cmap);
1804 dma_free_writecombine(&dev->dev, fbi->map_size,
1805 fbi->map_cpu, fbi->map_dma);
1807 iounmap(fbi->mmio_base);
1809 release_mem_region(r->start, r->end - r->start + 1);
1812 platform_set_drvdata(dev, NULL);
1818 static int __devexit pxafb_remove(struct platform_device *dev)
1820 struct pxafb_info *fbi = platform_get_drvdata(dev);
1823 struct fb_info *info;
1830 unregister_framebuffer(info);
1832 pxafb_disable_controller(fbi);
1834 if (fbi->fb.cmap.len)
1835 fb_dealloc_cmap(&fbi->fb.cmap);
1837 irq = platform_get_irq(dev, 0);
1840 dma_free_writecombine(&dev->dev, fbi->map_size,
1841 fbi->map_cpu, fbi->map_dma);
1843 iounmap(fbi->mmio_base);
1845 r = platform_get_resource(dev, IORESOURCE_MEM, 0);
1846 release_mem_region(r->start, r->end - r->start + 1);
1854 static struct platform_driver pxafb_driver = {
1855 .probe = pxafb_probe,
1856 .remove = pxafb_remove,
1857 .suspend = pxafb_suspend,
1858 .resume = pxafb_resume,
1860 .owner = THIS_MODULE,
1861 .name = "pxa2xx-fb",
1865 static int __init pxafb_init(void)
1867 if (pxafb_setup_options())
1870 return platform_driver_register(&pxafb_driver);
1873 static void __exit pxafb_exit(void)
1875 platform_driver_unregister(&pxafb_driver);
1878 module_init(pxafb_init);
1879 module_exit(pxafb_exit);
1881 MODULE_DESCRIPTION("loadable framebuffer driver for PXA");
1882 MODULE_LICENSE("GPL");