2 * linux/drivers/video/riva/fbdev.c - nVidia RIVA 128/TNT/TNT2 fb driver
4 * Maintained by Ani Joshi <ajoshi@shell.unixbox.com>
6 * Copyright 1999-2000 Jeff Garzik
10 * Ani Joshi: Lots of debugging and cleanup work, really helped
11 * get the driver going
13 * Ferenc Bakonyi: Bug fixes, cleanup, modularization
15 * Jindrich Makovicka: Accel code help, hw cursor, mtrr
17 * Paul Richards: Bug fixes, updates
19 * Initial template from skeletonfb.c, created 28 Dec 1997 by Geert Uytterhoeven
20 * Includes riva_hw.c from nVidia, see copyright below.
21 * KGI code provided the basis for state storage, init, and mode switching.
23 * This file is subject to the terms and conditions of the GNU General Public
24 * License. See the file COPYING in the main directory of this archive
27 * Known bugs and issues:
28 * restoring text mode fails
29 * doublescan modes are broken
32 #include <linux/module.h>
33 #include <linux/kernel.h>
34 #include <linux/errno.h>
35 #include <linux/string.h>
37 #include <linux/slab.h>
38 #include <linux/delay.h>
40 #include <linux/init.h>
41 #include <linux/pci.h>
42 #include <linux/backlight.h>
48 #include <asm/pci-bridge.h>
50 #ifdef CONFIG_PMAC_BACKLIGHT
51 #include <asm/machdep.h>
52 #include <asm/backlight.h>
58 #ifndef CONFIG_PCI /* sanity check */
59 #error This driver requires PCI support.
62 /* version number of this driver */
63 #define RIVAFB_VERSION "0.9.5b"
65 /* ------------------------------------------------------------------------- *
67 * various helpful macros and constants
69 * ------------------------------------------------------------------------- */
70 #ifdef CONFIG_FB_RIVA_DEBUG
71 #define NVTRACE printk
73 #define NVTRACE if(0) printk
76 #define NVTRACE_ENTER(...) NVTRACE("%s START\n", __FUNCTION__)
77 #define NVTRACE_LEAVE(...) NVTRACE("%s END\n", __FUNCTION__)
79 #ifdef CONFIG_FB_RIVA_DEBUG
80 #define assert(expr) \
82 printk( "Assertion failed! %s,%s,%s,line=%d\n",\
83 #expr,__FILE__,__FUNCTION__,__LINE__); \
90 #define PFX "rivafb: "
92 /* macro that allows you to set overflow bits */
93 #define SetBitField(value,from,to) SetBF(to,GetBF(value,from))
94 #define SetBit(n) (1<<(n))
95 #define Set8Bits(value) ((value)&0xff)
97 /* HW cursor parameters */
100 /* ------------------------------------------------------------------------- *
104 * ------------------------------------------------------------------------- */
106 static int rivafb_blank(int blank, struct fb_info *info);
108 /* ------------------------------------------------------------------------- *
110 * card identification
112 * ------------------------------------------------------------------------- */
114 static struct pci_device_id rivafb_pci_tbl[] = {
115 { PCI_VENDOR_ID_NVIDIA_SGS, PCI_DEVICE_ID_NVIDIA_SGS_RIVA128,
116 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
117 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT,
118 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
119 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT2,
120 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
121 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UTNT2,
122 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
123 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_VTNT2,
124 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
125 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UVTNT2,
126 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
127 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_ITNT2,
128 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
129 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR,
130 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
131 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR,
132 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
133 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO,
134 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
135 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX,
136 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
137 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2,
138 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
139 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO,
140 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
141 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR,
142 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
143 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS,
144 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
145 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2,
146 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
147 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA,
148 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
149 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO,
150 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
151 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460,
152 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
153 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440,
154 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
155 // NF2/IGP version, GeForce 4 MX, NV18
156 { PCI_VENDOR_ID_NVIDIA, 0x01f0,
157 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
158 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420,
159 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
160 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO,
161 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
162 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO,
163 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
164 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32,
165 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
166 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL,
167 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
168 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64,
169 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
170 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_200,
171 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
172 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL,
173 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
174 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL,
175 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
176 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_IGEFORCE2,
177 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
178 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3,
179 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
180 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_1,
181 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
182 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_2,
183 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
184 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_DDC,
185 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
186 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600,
187 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
188 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400,
189 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
190 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200,
191 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
192 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL,
193 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
194 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL,
195 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
196 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL,
197 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
198 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200,
199 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
200 { 0, } /* terminate list */
202 MODULE_DEVICE_TABLE(pci, rivafb_pci_tbl);
204 /* ------------------------------------------------------------------------- *
208 * ------------------------------------------------------------------------- */
210 /* command line data, set in rivafb_setup() */
211 static int flatpanel __devinitdata = -1; /* Autodetect later */
212 static int forceCRTC __devinitdata = -1;
213 static int noaccel __devinitdata = 0;
215 static int nomtrr __devinitdata = 0;
218 static char *mode_option __devinitdata = NULL;
219 static int strictmode = 0;
221 static struct fb_fix_screeninfo __devinitdata rivafb_fix = {
222 .type = FB_TYPE_PACKED_PIXELS,
227 static struct fb_var_screeninfo __devinitdata rivafb_default_var = {
237 .activate = FB_ACTIVATE_NOW,
247 .vmode = FB_VMODE_NONINTERLACED
251 static const struct riva_regs reg_template = {
252 {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* ATTR */
253 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
254 0x41, 0x01, 0x0F, 0x00, 0x00},
255 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* CRT */
256 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00,
257 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE3, /* 0x10 */
258 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
259 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x20 */
260 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
261 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x30 */
262 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
265 {0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, /* GRA */
267 {0x03, 0x01, 0x0F, 0x00, 0x0E}, /* SEQ */
274 #ifdef CONFIG_FB_RIVA_BACKLIGHT
275 /* We do not have any information about which values are allowed, thus
276 * we used safe values.
278 #define MIN_LEVEL 0x158
279 #define MAX_LEVEL 0x534
280 #define LEVEL_STEP ((MAX_LEVEL - MIN_LEVEL) / FB_BACKLIGHT_MAX)
282 static struct backlight_properties riva_bl_data;
284 /* Call with fb_info->bl_mutex held */
285 static int riva_bl_get_level_brightness(struct riva_par *par,
288 struct fb_info *info = pci_get_drvdata(par->pdev);
291 /* Get and convert the value */
292 nlevel = MIN_LEVEL + info->bl_curve[level] * LEVEL_STEP;
296 else if (nlevel < MIN_LEVEL)
298 else if (nlevel > MAX_LEVEL)
304 /* Call with fb_info->bl_mutex held */
305 static int __riva_bl_update_status(struct backlight_device *bd)
307 struct riva_par *par = class_get_devdata(&bd->class_dev);
308 U032 tmp_pcrt, tmp_pmc;
311 if (bd->props->power != FB_BLANK_UNBLANK ||
312 bd->props->fb_blank != FB_BLANK_UNBLANK)
315 level = bd->props->brightness;
317 tmp_pmc = par->riva.PMC[0x10F0/4] & 0x0000FFFF;
318 tmp_pcrt = par->riva.PCRTC0[0x081C/4] & 0xFFFFFFFC;
321 tmp_pmc |= (1 << 31); /* backlight bit */
322 tmp_pmc |= riva_bl_get_level_brightness(par, level) << 16; /* level */
324 par->riva.PCRTC0[0x081C/4] = tmp_pcrt;
325 par->riva.PMC[0x10F0/4] = tmp_pmc;
330 static int riva_bl_update_status(struct backlight_device *bd)
332 struct riva_par *par = class_get_devdata(&bd->class_dev);
333 struct fb_info *info = pci_get_drvdata(par->pdev);
336 mutex_lock(&info->bl_mutex);
337 ret = __riva_bl_update_status(bd);
338 mutex_unlock(&info->bl_mutex);
343 static int riva_bl_get_brightness(struct backlight_device *bd)
345 return bd->props->brightness;
348 static struct backlight_properties riva_bl_data = {
349 .owner = THIS_MODULE,
350 .get_brightness = riva_bl_get_brightness,
351 .update_status = riva_bl_update_status,
352 .max_brightness = (FB_BACKLIGHT_LEVELS - 1),
355 static void riva_bl_set_power(struct fb_info *info, int power)
357 mutex_lock(&info->bl_mutex);
358 up(&info->bl_dev->sem);
359 info->bl_dev->props->power = power;
360 __riva_bl_update_status(info->bl_dev);
361 down(&info->bl_dev->sem);
362 mutex_unlock(&info->bl_mutex);
365 static void riva_bl_init(struct riva_par *par)
367 struct fb_info *info = pci_get_drvdata(par->pdev);
368 struct backlight_device *bd;
374 #ifdef CONFIG_PMAC_BACKLIGHT
375 if (!machine_is(powermac) ||
376 !pmac_has_backlight_type("mnca"))
380 snprintf(name, sizeof(name), "rivabl%d", info->node);
382 bd = backlight_device_register(name, par, &riva_bl_data);
385 printk("riva: Backlight registration failed\n");
389 mutex_lock(&info->bl_mutex);
391 fb_bl_default_curve(info, 0,
392 0x158 * FB_BACKLIGHT_MAX / MAX_LEVEL,
393 0x534 * FB_BACKLIGHT_MAX / MAX_LEVEL);
394 mutex_unlock(&info->bl_mutex);
397 bd->props->brightness = riva_bl_data.max_brightness;
398 bd->props->power = FB_BLANK_UNBLANK;
399 bd->props->update_status(bd);
402 #ifdef CONFIG_PMAC_BACKLIGHT
403 mutex_lock(&pmac_backlight_mutex);
406 mutex_unlock(&pmac_backlight_mutex);
409 printk("riva: Backlight initialized (%s)\n", name);
417 static void riva_bl_exit(struct riva_par *par)
419 struct fb_info *info = pci_get_drvdata(par->pdev);
421 #ifdef CONFIG_PMAC_BACKLIGHT
422 mutex_lock(&pmac_backlight_mutex);
425 mutex_lock(&info->bl_mutex);
427 #ifdef CONFIG_PMAC_BACKLIGHT
428 if (pmac_backlight == info->bl_dev)
429 pmac_backlight = NULL;
432 backlight_device_unregister(info->bl_dev);
434 printk("riva: Backlight unloaded\n");
436 mutex_unlock(&info->bl_mutex);
438 #ifdef CONFIG_PMAC_BACKLIGHT
439 mutex_unlock(&pmac_backlight_mutex);
443 static inline void riva_bl_init(struct riva_par *par) {}
444 static inline void riva_bl_exit(struct riva_par *par) {}
445 static inline void riva_bl_set_power(struct fb_info *info, int power) {}
446 #endif /* CONFIG_FB_RIVA_BACKLIGHT */
448 /* ------------------------------------------------------------------------- *
452 * ------------------------------------------------------------------------- */
454 static inline void CRTCout(struct riva_par *par, unsigned char index,
457 VGA_WR08(par->riva.PCIO, 0x3d4, index);
458 VGA_WR08(par->riva.PCIO, 0x3d5, val);
461 static inline unsigned char CRTCin(struct riva_par *par,
464 VGA_WR08(par->riva.PCIO, 0x3d4, index);
465 return (VGA_RD08(par->riva.PCIO, 0x3d5));
468 static inline void GRAout(struct riva_par *par, unsigned char index,
471 VGA_WR08(par->riva.PVIO, 0x3ce, index);
472 VGA_WR08(par->riva.PVIO, 0x3cf, val);
475 static inline unsigned char GRAin(struct riva_par *par,
478 VGA_WR08(par->riva.PVIO, 0x3ce, index);
479 return (VGA_RD08(par->riva.PVIO, 0x3cf));
482 static inline void SEQout(struct riva_par *par, unsigned char index,
485 VGA_WR08(par->riva.PVIO, 0x3c4, index);
486 VGA_WR08(par->riva.PVIO, 0x3c5, val);
489 static inline unsigned char SEQin(struct riva_par *par,
492 VGA_WR08(par->riva.PVIO, 0x3c4, index);
493 return (VGA_RD08(par->riva.PVIO, 0x3c5));
496 static inline void ATTRout(struct riva_par *par, unsigned char index,
499 VGA_WR08(par->riva.PCIO, 0x3c0, index);
500 VGA_WR08(par->riva.PCIO, 0x3c0, val);
503 static inline unsigned char ATTRin(struct riva_par *par,
506 VGA_WR08(par->riva.PCIO, 0x3c0, index);
507 return (VGA_RD08(par->riva.PCIO, 0x3c1));
510 static inline void MISCout(struct riva_par *par, unsigned char val)
512 VGA_WR08(par->riva.PVIO, 0x3c2, val);
515 static inline unsigned char MISCin(struct riva_par *par)
517 return (VGA_RD08(par->riva.PVIO, 0x3cc));
520 static u8 byte_rev[256] = {
521 0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0,
522 0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0,
523 0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8,
524 0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8,
525 0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4,
526 0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4,
527 0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec,
528 0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc,
529 0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2,
530 0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2,
531 0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea,
532 0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa,
533 0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6,
534 0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6,
535 0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee,
536 0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe,
537 0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1,
538 0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1,
539 0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9,
540 0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9,
541 0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5,
542 0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5,
543 0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed,
544 0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd,
545 0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3,
546 0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3,
547 0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb,
548 0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb,
549 0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7,
550 0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7,
551 0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef,
552 0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff,
555 static inline void reverse_order(u32 *l)
558 *a = byte_rev[*a], a++;
559 *a = byte_rev[*a], a++;
560 *a = byte_rev[*a], a++;
564 /* ------------------------------------------------------------------------- *
568 * ------------------------------------------------------------------------- */
571 * rivafb_load_cursor_image - load cursor image to hardware
572 * @data: address to monochrome bitmap (1 = foreground color, 0 = background)
573 * @par: pointer to private data
574 * @w: width of cursor image in pixels
575 * @h: height of cursor image in scanlines
576 * @bg: background color (ARGB1555) - alpha bit determines opacity
577 * @fg: foreground color (ARGB1555)
580 * Loads cursor image based on a monochrome source and mask bitmap. The
581 * image bits determines the color of the pixel, 0 for background, 1 for
582 * foreground. Only the affected region (as determined by @w and @h
583 * parameters) will be updated.
588 static void rivafb_load_cursor_image(struct riva_par *par, u8 *data8,
589 u16 bg, u16 fg, u32 w, u32 h)
593 u32 *data = (u32 *)data8;
594 bg = le16_to_cpu(bg);
595 fg = le16_to_cpu(fg);
599 for (i = 0; i < h; i++) {
603 for (j = 0; j < w/2; j++) {
605 #if defined (__BIG_ENDIAN)
606 tmp = (b & (1 << 31)) ? fg << 16 : bg << 16;
608 tmp |= (b & (1 << 31)) ? fg : bg;
611 tmp = (b & 1) ? fg : bg;
613 tmp |= (b & 1) ? fg << 16 : bg << 16;
616 writel(tmp, &par->riva.CURSOR[k++]);
618 k += (MAX_CURS - w)/2;
622 /* ------------------------------------------------------------------------- *
624 * general utility functions
626 * ------------------------------------------------------------------------- */
629 * riva_wclut - set CLUT entry
630 * @chip: pointer to RIVA_HW_INST object
631 * @regnum: register number
632 * @red: red component
633 * @green: green component
634 * @blue: blue component
637 * Sets color register @regnum.
642 static void riva_wclut(RIVA_HW_INST *chip,
643 unsigned char regnum, unsigned char red,
644 unsigned char green, unsigned char blue)
646 VGA_WR08(chip->PDIO, 0x3c8, regnum);
647 VGA_WR08(chip->PDIO, 0x3c9, red);
648 VGA_WR08(chip->PDIO, 0x3c9, green);
649 VGA_WR08(chip->PDIO, 0x3c9, blue);
653 * riva_rclut - read fromCLUT register
654 * @chip: pointer to RIVA_HW_INST object
655 * @regnum: register number
656 * @red: red component
657 * @green: green component
658 * @blue: blue component
661 * Reads red, green, and blue from color register @regnum.
666 static void riva_rclut(RIVA_HW_INST *chip,
667 unsigned char regnum, unsigned char *red,
668 unsigned char *green, unsigned char *blue)
671 VGA_WR08(chip->PDIO, 0x3c7, regnum);
672 *red = VGA_RD08(chip->PDIO, 0x3c9);
673 *green = VGA_RD08(chip->PDIO, 0x3c9);
674 *blue = VGA_RD08(chip->PDIO, 0x3c9);
678 * riva_save_state - saves current chip state
679 * @par: pointer to riva_par object containing info for current riva board
680 * @regs: pointer to riva_regs object
683 * Saves current chip state to @regs.
689 static void riva_save_state(struct riva_par *par, struct riva_regs *regs)
694 par->riva.LockUnlock(&par->riva, 0);
696 par->riva.UnloadStateExt(&par->riva, ®s->ext);
698 regs->misc_output = MISCin(par);
700 for (i = 0; i < NUM_CRT_REGS; i++)
701 regs->crtc[i] = CRTCin(par, i);
703 for (i = 0; i < NUM_ATC_REGS; i++)
704 regs->attr[i] = ATTRin(par, i);
706 for (i = 0; i < NUM_GRC_REGS; i++)
707 regs->gra[i] = GRAin(par, i);
709 for (i = 0; i < NUM_SEQ_REGS; i++)
710 regs->seq[i] = SEQin(par, i);
715 * riva_load_state - loads current chip state
716 * @par: pointer to riva_par object containing info for current riva board
717 * @regs: pointer to riva_regs object
720 * Loads chip state from @regs.
723 * riva_load_video_mode()
728 static void riva_load_state(struct riva_par *par, struct riva_regs *regs)
730 RIVA_HW_STATE *state = ®s->ext;
734 CRTCout(par, 0x11, 0x00);
736 par->riva.LockUnlock(&par->riva, 0);
738 par->riva.LoadStateExt(&par->riva, state);
740 MISCout(par, regs->misc_output);
742 for (i = 0; i < NUM_CRT_REGS; i++) {
748 CRTCout(par, i, regs->crtc[i]);
752 for (i = 0; i < NUM_ATC_REGS; i++)
753 ATTRout(par, i, regs->attr[i]);
755 for (i = 0; i < NUM_GRC_REGS; i++)
756 GRAout(par, i, regs->gra[i]);
758 for (i = 0; i < NUM_SEQ_REGS; i++)
759 SEQout(par, i, regs->seq[i]);
764 * riva_load_video_mode - calculate timings
765 * @info: pointer to fb_info object containing info for current riva board
768 * Calculate some timings and then send em off to riva_load_state().
773 static void riva_load_video_mode(struct fb_info *info)
775 int bpp, width, hDisplaySize, hDisplay, hStart,
776 hEnd, hTotal, height, vDisplay, vStart, vEnd, vTotal, dotClock;
777 int hBlankStart, hBlankEnd, vBlankStart, vBlankEnd;
778 struct riva_par *par = info->par;
779 struct riva_regs newmode;
782 /* time to calculate */
783 rivafb_blank(1, info);
785 bpp = info->var.bits_per_pixel;
786 if (bpp == 16 && info->var.green.length == 5)
788 width = info->var.xres_virtual;
789 hDisplaySize = info->var.xres;
790 hDisplay = (hDisplaySize / 8) - 1;
791 hStart = (hDisplaySize + info->var.right_margin) / 8 - 1;
792 hEnd = (hDisplaySize + info->var.right_margin +
793 info->var.hsync_len) / 8 - 1;
794 hTotal = (hDisplaySize + info->var.right_margin +
795 info->var.hsync_len + info->var.left_margin) / 8 - 5;
796 hBlankStart = hDisplay;
797 hBlankEnd = hTotal + 4;
799 height = info->var.yres_virtual;
800 vDisplay = info->var.yres - 1;
801 vStart = info->var.yres + info->var.lower_margin - 1;
802 vEnd = info->var.yres + info->var.lower_margin +
803 info->var.vsync_len - 1;
804 vTotal = info->var.yres + info->var.lower_margin +
805 info->var.vsync_len + info->var.upper_margin + 2;
806 vBlankStart = vDisplay;
807 vBlankEnd = vTotal + 1;
808 dotClock = 1000000000 / info->var.pixclock;
810 memcpy(&newmode, ®_template, sizeof(struct riva_regs));
812 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED)
815 if (par->FlatPanel) {
818 vBlankStart = vStart;
821 hBlankEnd = hTotal + 4;
824 newmode.crtc[0x0] = Set8Bits (hTotal);
825 newmode.crtc[0x1] = Set8Bits (hDisplay);
826 newmode.crtc[0x2] = Set8Bits (hBlankStart);
827 newmode.crtc[0x3] = SetBitField (hBlankEnd, 4: 0, 4:0) | SetBit (7);
828 newmode.crtc[0x4] = Set8Bits (hStart);
829 newmode.crtc[0x5] = SetBitField (hBlankEnd, 5: 5, 7:7)
830 | SetBitField (hEnd, 4: 0, 4:0);
831 newmode.crtc[0x6] = SetBitField (vTotal, 7: 0, 7:0);
832 newmode.crtc[0x7] = SetBitField (vTotal, 8: 8, 0:0)
833 | SetBitField (vDisplay, 8: 8, 1:1)
834 | SetBitField (vStart, 8: 8, 2:2)
835 | SetBitField (vBlankStart, 8: 8, 3:3)
837 | SetBitField (vTotal, 9: 9, 5:5)
838 | SetBitField (vDisplay, 9: 9, 6:6)
839 | SetBitField (vStart, 9: 9, 7:7);
840 newmode.crtc[0x9] = SetBitField (vBlankStart, 9: 9, 5:5)
842 newmode.crtc[0x10] = Set8Bits (vStart);
843 newmode.crtc[0x11] = SetBitField (vEnd, 3: 0, 3:0)
845 newmode.crtc[0x12] = Set8Bits (vDisplay);
846 newmode.crtc[0x13] = (width / 8) * ((bpp + 1) / 8);
847 newmode.crtc[0x15] = Set8Bits (vBlankStart);
848 newmode.crtc[0x16] = Set8Bits (vBlankEnd);
850 newmode.ext.screen = SetBitField(hBlankEnd,6:6,4:4)
851 | SetBitField(vBlankStart,10:10,3:3)
852 | SetBitField(vStart,10:10,2:2)
853 | SetBitField(vDisplay,10:10,1:1)
854 | SetBitField(vTotal,10:10,0:0);
855 newmode.ext.horiz = SetBitField(hTotal,8:8,0:0)
856 | SetBitField(hDisplay,8:8,1:1)
857 | SetBitField(hBlankStart,8:8,2:2)
858 | SetBitField(hStart,8:8,3:3);
859 newmode.ext.extra = SetBitField(vTotal,11:11,0:0)
860 | SetBitField(vDisplay,11:11,2:2)
861 | SetBitField(vStart,11:11,4:4)
862 | SetBitField(vBlankStart,11:11,6:6);
864 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
865 int tmp = (hTotal >> 1) & ~1;
866 newmode.ext.interlace = Set8Bits(tmp);
867 newmode.ext.horiz |= SetBitField(tmp, 8:8,4:4);
869 newmode.ext.interlace = 0xff; /* interlace off */
871 if (par->riva.Architecture >= NV_ARCH_10)
872 par->riva.CURSOR = (U032 __iomem *)(info->screen_base + par->riva.CursorStart);
874 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
875 newmode.misc_output &= ~0x40;
877 newmode.misc_output |= 0x40;
878 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
879 newmode.misc_output &= ~0x80;
881 newmode.misc_output |= 0x80;
883 par->riva.CalcStateExt(&par->riva, &newmode.ext, bpp, width,
884 hDisplaySize, height, dotClock);
886 newmode.ext.scale = NV_RD32(par->riva.PRAMDAC, 0x00000848) &
888 if (par->FlatPanel == 1) {
889 newmode.ext.pixel |= (1 << 7);
890 newmode.ext.scale |= (1 << 8);
892 if (par->SecondCRTC) {
893 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) &
895 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) |
897 newmode.ext.crtcOwner = 3;
898 newmode.ext.pllsel |= 0x20000800;
899 newmode.ext.vpll2 = newmode.ext.vpll;
900 } else if (par->riva.twoHeads) {
901 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) |
903 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) &
905 newmode.ext.crtcOwner = 0;
906 newmode.ext.vpll2 = NV_RD32(par->riva.PRAMDAC0, 0x00000520);
908 if (par->FlatPanel == 1) {
909 newmode.ext.pixel |= (1 << 7);
910 newmode.ext.scale |= (1 << 8);
912 newmode.ext.cursorConfig = 0x02000100;
913 par->current_state = newmode;
914 riva_load_state(par, &par->current_state);
915 par->riva.LockUnlock(&par->riva, 0); /* important for HW cursor */
916 rivafb_blank(0, info);
920 static void riva_update_var(struct fb_var_screeninfo *var, struct fb_videomode *modedb)
923 var->xres = var->xres_virtual = modedb->xres;
924 var->yres = modedb->yres;
925 if (var->yres_virtual < var->yres)
926 var->yres_virtual = var->yres;
927 var->xoffset = var->yoffset = 0;
928 var->pixclock = modedb->pixclock;
929 var->left_margin = modedb->left_margin;
930 var->right_margin = modedb->right_margin;
931 var->upper_margin = modedb->upper_margin;
932 var->lower_margin = modedb->lower_margin;
933 var->hsync_len = modedb->hsync_len;
934 var->vsync_len = modedb->vsync_len;
935 var->sync = modedb->sync;
936 var->vmode = modedb->vmode;
941 * rivafb_do_maximize -
942 * @info: pointer to fb_info object containing info for current riva board
951 * -EINVAL on failure, 0 on success
957 static int rivafb_do_maximize(struct fb_info *info,
958 struct fb_var_screeninfo *var,
974 /* use highest possible virtual resolution */
975 if (var->xres_virtual == -1 && var->yres_virtual == -1) {
976 printk(KERN_WARNING PFX
977 "using maximum available virtual resolution\n");
978 for (i = 0; modes[i].xres != -1; i++) {
979 if (modes[i].xres * nom / den * modes[i].yres <
983 if (modes[i].xres == -1) {
985 "could not find a virtual resolution that fits into video memory!!\n");
986 NVTRACE("EXIT - EINVAL error\n");
989 var->xres_virtual = modes[i].xres;
990 var->yres_virtual = modes[i].yres;
993 "virtual resolution set to maximum of %dx%d\n",
994 var->xres_virtual, var->yres_virtual);
995 } else if (var->xres_virtual == -1) {
996 var->xres_virtual = (info->fix.smem_len * den /
997 (nom * var->yres_virtual)) & ~15;
998 printk(KERN_WARNING PFX
999 "setting virtual X resolution to %d\n", var->xres_virtual);
1000 } else if (var->yres_virtual == -1) {
1001 var->xres_virtual = (var->xres_virtual + 15) & ~15;
1002 var->yres_virtual = info->fix.smem_len * den /
1003 (nom * var->xres_virtual);
1004 printk(KERN_WARNING PFX
1005 "setting virtual Y resolution to %d\n", var->yres_virtual);
1007 var->xres_virtual = (var->xres_virtual + 15) & ~15;
1008 if (var->xres_virtual * nom / den * var->yres_virtual > info->fix.smem_len) {
1010 "mode %dx%dx%d rejected...resolution too high to fit into video memory!\n",
1011 var->xres, var->yres, var->bits_per_pixel);
1012 NVTRACE("EXIT - EINVAL error\n");
1017 if (var->xres_virtual * nom / den >= 8192) {
1018 printk(KERN_WARNING PFX
1019 "virtual X resolution (%d) is too high, lowering to %d\n",
1020 var->xres_virtual, 8192 * den / nom - 16);
1021 var->xres_virtual = 8192 * den / nom - 16;
1024 if (var->xres_virtual < var->xres) {
1026 "virtual X resolution (%d) is smaller than real\n", var->xres_virtual);
1030 if (var->yres_virtual < var->yres) {
1032 "virtual Y resolution (%d) is smaller than real\n", var->yres_virtual);
1035 if (var->yres_virtual > 0x7fff/nom)
1036 var->yres_virtual = 0x7fff/nom;
1037 if (var->xres_virtual > 0x7fff/nom)
1038 var->xres_virtual = 0x7fff/nom;
1044 riva_set_pattern(struct riva_par *par, int clr0, int clr1, int pat0, int pat1)
1046 RIVA_FIFO_FREE(par->riva, Patt, 4);
1047 NV_WR32(&par->riva.Patt->Color0, 0, clr0);
1048 NV_WR32(&par->riva.Patt->Color1, 0, clr1);
1049 NV_WR32(par->riva.Patt->Monochrome, 0, pat0);
1050 NV_WR32(par->riva.Patt->Monochrome, 4, pat1);
1053 /* acceleration routines */
1054 static inline void wait_for_idle(struct riva_par *par)
1056 while (par->riva.Busy(&par->riva));
1060 * Set ROP. Translate X rop into ROP3. Internal routine.
1063 riva_set_rop_solid(struct riva_par *par, int rop)
1065 riva_set_pattern(par, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
1066 RIVA_FIFO_FREE(par->riva, Rop, 1);
1067 NV_WR32(&par->riva.Rop->Rop3, 0, rop);
1071 static void riva_setup_accel(struct fb_info *info)
1073 struct riva_par *par = info->par;
1075 RIVA_FIFO_FREE(par->riva, Clip, 2);
1076 NV_WR32(&par->riva.Clip->TopLeft, 0, 0x0);
1077 NV_WR32(&par->riva.Clip->WidthHeight, 0,
1078 (info->var.xres_virtual & 0xffff) |
1079 (info->var.yres_virtual << 16));
1080 riva_set_rop_solid(par, 0xcc);
1085 * riva_get_cmap_len - query current color map length
1086 * @var: standard kernel fb changeable data
1089 * Get current color map length.
1092 * Length of color map
1095 * rivafb_setcolreg()
1097 static int riva_get_cmap_len(const struct fb_var_screeninfo *var)
1099 int rc = 256; /* reasonable default */
1101 switch (var->green.length) {
1103 rc = 256; /* 256 entries (2^8), 8 bpp and RGB8888 */
1106 rc = 32; /* 32 entries (2^5), 16 bpp, RGB555 */
1109 rc = 64; /* 64 entries (2^6), 16 bpp, RGB565 */
1112 /* should not occur */
1118 /* ------------------------------------------------------------------------- *
1120 * framebuffer operations
1122 * ------------------------------------------------------------------------- */
1124 static int rivafb_open(struct fb_info *info, int user)
1126 struct riva_par *par = info->par;
1127 int cnt = atomic_read(&par->ref_count);
1132 memset(&par->state, 0, sizeof(struct vgastate));
1133 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS;
1134 /* save the DAC for Riva128 */
1135 if (par->riva.Architecture == NV_ARCH_03)
1136 par->state.flags |= VGA_SAVE_CMAP;
1137 save_vga(&par->state);
1139 /* vgaHWunlock() + riva unlock (0x7F) */
1140 CRTCout(par, 0x11, 0xFF);
1141 par->riva.LockUnlock(&par->riva, 0);
1143 riva_save_state(par, &par->initial_state);
1145 atomic_inc(&par->ref_count);
1150 static int rivafb_release(struct fb_info *info, int user)
1152 struct riva_par *par = info->par;
1153 int cnt = atomic_read(&par->ref_count);
1159 par->riva.LockUnlock(&par->riva, 0);
1160 par->riva.LoadStateExt(&par->riva, &par->initial_state.ext);
1161 riva_load_state(par, &par->initial_state);
1163 restore_vga(&par->state);
1165 par->riva.LockUnlock(&par->riva, 1);
1167 atomic_dec(&par->ref_count);
1172 static int rivafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1174 struct fb_videomode *mode;
1175 struct riva_par *par = info->par;
1176 int nom, den; /* translating from pixels->bytes */
1180 switch (var->bits_per_pixel) {
1182 var->red.offset = var->green.offset = var->blue.offset = 0;
1183 var->red.length = var->green.length = var->blue.length = 8;
1184 var->bits_per_pixel = 8;
1188 var->green.length = 5;
1191 var->bits_per_pixel = 16;
1192 /* The Riva128 supports RGB555 only */
1193 if (par->riva.Architecture == NV_ARCH_03)
1194 var->green.length = 5;
1195 if (var->green.length == 5) {
1196 /* 0rrrrrgg gggbbbbb */
1197 var->red.offset = 10;
1198 var->green.offset = 5;
1199 var->blue.offset = 0;
1200 var->red.length = 5;
1201 var->green.length = 5;
1202 var->blue.length = 5;
1204 /* rrrrrggg gggbbbbb */
1205 var->red.offset = 11;
1206 var->green.offset = 5;
1207 var->blue.offset = 0;
1208 var->red.length = 5;
1209 var->green.length = 6;
1210 var->blue.length = 5;
1216 var->red.length = var->green.length = var->blue.length = 8;
1217 var->bits_per_pixel = 32;
1218 var->red.offset = 16;
1219 var->green.offset = 8;
1220 var->blue.offset = 0;
1226 "mode %dx%dx%d rejected...color depth not supported.\n",
1227 var->xres, var->yres, var->bits_per_pixel);
1228 NVTRACE("EXIT, returning -EINVAL\n");
1233 if (!info->monspecs.vfmax || !info->monspecs.hfmax ||
1234 !info->monspecs.dclkmax || !fb_validate_mode(var, info))
1238 /* calculate modeline if supported by monitor */
1239 if (!mode_valid && info->monspecs.gtf) {
1240 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
1245 mode = fb_find_best_mode(var, &info->modelist);
1247 riva_update_var(var, mode);
1252 if (!mode_valid && info->monspecs.modedb_len)
1255 if (var->xres_virtual < var->xres)
1256 var->xres_virtual = var->xres;
1257 if (var->yres_virtual <= var->yres)
1258 var->yres_virtual = -1;
1259 if (rivafb_do_maximize(info, var, nom, den) < 0)
1262 if (var->xoffset < 0)
1264 if (var->yoffset < 0)
1267 /* truncate xoffset and yoffset to maximum if too high */
1268 if (var->xoffset > var->xres_virtual - var->xres)
1269 var->xoffset = var->xres_virtual - var->xres - 1;
1271 if (var->yoffset > var->yres_virtual - var->yres)
1272 var->yoffset = var->yres_virtual - var->yres - 1;
1274 var->red.msb_right =
1275 var->green.msb_right =
1276 var->blue.msb_right =
1277 var->transp.offset = var->transp.length = var->transp.msb_right = 0;
1282 static int rivafb_set_par(struct fb_info *info)
1284 struct riva_par *par = info->par;
1287 /* vgaHWunlock() + riva unlock (0x7F) */
1288 CRTCout(par, 0x11, 0xFF);
1289 par->riva.LockUnlock(&par->riva, 0);
1290 riva_load_video_mode(info);
1291 if(!(info->flags & FBINFO_HWACCEL_DISABLED))
1292 riva_setup_accel(info);
1294 par->cursor_reset = 1;
1295 info->fix.line_length = (info->var.xres_virtual * (info->var.bits_per_pixel >> 3));
1296 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1297 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1299 if (info->flags & FBINFO_HWACCEL_DISABLED)
1300 info->pixmap.scan_align = 1;
1302 info->pixmap.scan_align = 4;
1308 * rivafb_pan_display
1309 * @var: standard kernel fb changeable data
1311 * @info: pointer to fb_info object containing info for current riva board
1314 * Pan (or wrap, depending on the `vmode' field) the display using the
1315 * `xoffset' and `yoffset' fields of the `var' structure.
1316 * If the values don't fit, return -EINVAL.
1318 * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1320 static int rivafb_pan_display(struct fb_var_screeninfo *var,
1321 struct fb_info *info)
1323 struct riva_par *par = info->par;
1327 base = var->yoffset * info->fix.line_length + var->xoffset;
1328 par->riva.SetStartAddress(&par->riva, base);
1333 static int rivafb_blank(int blank, struct fb_info *info)
1335 struct riva_par *par= info->par;
1336 unsigned char tmp, vesa;
1338 tmp = SEQin(par, 0x01) & ~0x20; /* screen on/off */
1339 vesa = CRTCin(par, 0x1a) & ~0xc0; /* sync on/off */
1347 case FB_BLANK_UNBLANK:
1348 case FB_BLANK_NORMAL:
1350 case FB_BLANK_VSYNC_SUSPEND:
1353 case FB_BLANK_HSYNC_SUSPEND:
1356 case FB_BLANK_POWERDOWN:
1361 SEQout(par, 0x01, tmp);
1362 CRTCout(par, 0x1a, vesa);
1364 riva_bl_set_power(info, blank);
1373 * @regno: register index
1374 * @red: red component
1375 * @green: green component
1376 * @blue: blue component
1377 * @transp: transparency
1378 * @info: pointer to fb_info object containing info for current riva board
1381 * Set a single color register. The values supplied have a 16 bit
1385 * Return != 0 for invalid regno.
1388 * fbcmap.c:fb_set_cmap()
1390 static int rivafb_setcolreg(unsigned regno, unsigned red, unsigned green,
1391 unsigned blue, unsigned transp,
1392 struct fb_info *info)
1394 struct riva_par *par = info->par;
1395 RIVA_HW_INST *chip = &par->riva;
1398 if (regno >= riva_get_cmap_len(&info->var))
1401 if (info->var.grayscale) {
1402 /* gray = 0.30*R + 0.59*G + 0.11*B */
1403 red = green = blue =
1404 (red * 77 + green * 151 + blue * 28) >> 8;
1407 if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
1408 ((u32 *) info->pseudo_palette)[regno] =
1409 (regno << info->var.red.offset) |
1410 (regno << info->var.green.offset) |
1411 (regno << info->var.blue.offset);
1413 * The Riva128 2D engine requires color information in
1414 * TrueColor format even if framebuffer is in DirectColor
1416 if (par->riva.Architecture == NV_ARCH_03) {
1417 switch (info->var.bits_per_pixel) {
1419 par->palette[regno] = ((red & 0xf800) >> 1) |
1420 ((green & 0xf800) >> 6) |
1421 ((blue & 0xf800) >> 11);
1424 par->palette[regno] = ((red & 0xff00) << 8) |
1425 ((green & 0xff00)) |
1426 ((blue & 0xff00) >> 8);
1432 switch (info->var.bits_per_pixel) {
1434 /* "transparent" stuff is completely ignored. */
1435 riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8);
1438 if (info->var.green.length == 5) {
1439 for (i = 0; i < 8; i++) {
1440 riva_wclut(chip, regno*8+i, red >> 8,
1441 green >> 8, blue >> 8);
1447 for (i = 0; i < 8; i++) {
1448 riva_wclut(chip, regno*8+i,
1449 red >> 8, green >> 8,
1453 riva_rclut(chip, regno*4, &r, &g, &b);
1454 for (i = 0; i < 4; i++)
1455 riva_wclut(chip, regno*4+i, r,
1460 riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8);
1470 * rivafb_fillrect - hardware accelerated color fill function
1471 * @info: pointer to fb_info structure
1472 * @rect: pointer to fb_fillrect structure
1475 * This function fills up a region of framebuffer memory with a solid
1476 * color with a choice of two different ROP's, copy or invert.
1481 static void rivafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
1483 struct riva_par *par = info->par;
1484 u_int color, rop = 0;
1486 if ((info->flags & FBINFO_HWACCEL_DISABLED)) {
1487 cfb_fillrect(info, rect);
1491 if (info->var.bits_per_pixel == 8)
1492 color = rect->color;
1494 if (par->riva.Architecture != NV_ARCH_03)
1495 color = ((u32 *)info->pseudo_palette)[rect->color];
1497 color = par->palette[rect->color];
1500 switch (rect->rop) {
1510 riva_set_rop_solid(par, rop);
1512 RIVA_FIFO_FREE(par->riva, Bitmap, 1);
1513 NV_WR32(&par->riva.Bitmap->Color1A, 0, color);
1515 RIVA_FIFO_FREE(par->riva, Bitmap, 2);
1516 NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].TopLeft, 0,
1517 (rect->dx << 16) | rect->dy);
1519 NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].WidthHeight, 0,
1520 (rect->width << 16) | rect->height);
1522 riva_set_rop_solid(par, 0xcc);
1527 * rivafb_copyarea - hardware accelerated blit function
1528 * @info: pointer to fb_info structure
1529 * @region: pointer to fb_copyarea structure
1532 * This copies an area of pixels from one location to another
1537 static void rivafb_copyarea(struct fb_info *info, const struct fb_copyarea *region)
1539 struct riva_par *par = info->par;
1541 if ((info->flags & FBINFO_HWACCEL_DISABLED)) {
1542 cfb_copyarea(info, region);
1546 RIVA_FIFO_FREE(par->riva, Blt, 3);
1547 NV_WR32(&par->riva.Blt->TopLeftSrc, 0,
1548 (region->sy << 16) | region->sx);
1549 NV_WR32(&par->riva.Blt->TopLeftDst, 0,
1550 (region->dy << 16) | region->dx);
1552 NV_WR32(&par->riva.Blt->WidthHeight, 0,
1553 (region->height << 16) | region->width);
1557 static inline void convert_bgcolor_16(u32 *col)
1559 *col = ((*col & 0x0000F800) << 8)
1560 | ((*col & 0x00007E0) << 5)
1561 | ((*col & 0x0000001F) << 3)
1567 * rivafb_imageblit: hardware accelerated color expand function
1568 * @info: pointer to fb_info structure
1569 * @image: pointer to fb_image structure
1572 * If the source is a monochrome bitmap, the function fills up a a region
1573 * of framebuffer memory with pixels whose color is determined by the bit
1574 * setting of the bitmap, 1 - foreground, 0 - background.
1576 * If the source is not a monochrome bitmap, color expansion is not done.
1577 * In this case, it is channeled to a software function.
1582 static void rivafb_imageblit(struct fb_info *info,
1583 const struct fb_image *image)
1585 struct riva_par *par = info->par;
1586 u32 fgx = 0, bgx = 0, width, tmp;
1587 u8 *cdat = (u8 *) image->data;
1588 volatile u32 __iomem *d;
1591 if ((info->flags & FBINFO_HWACCEL_DISABLED) || image->depth != 1) {
1592 cfb_imageblit(info, image);
1596 switch (info->var.bits_per_pixel) {
1598 fgx = image->fg_color;
1599 bgx = image->bg_color;
1603 if (par->riva.Architecture != NV_ARCH_03) {
1604 fgx = ((u32 *)info->pseudo_palette)[image->fg_color];
1605 bgx = ((u32 *)info->pseudo_palette)[image->bg_color];
1607 fgx = par->palette[image->fg_color];
1608 bgx = par->palette[image->bg_color];
1610 if (info->var.green.length == 6)
1611 convert_bgcolor_16(&bgx);
1615 RIVA_FIFO_FREE(par->riva, Bitmap, 7);
1616 NV_WR32(&par->riva.Bitmap->ClipE.TopLeft, 0,
1617 (image->dy << 16) | (image->dx & 0xFFFF));
1618 NV_WR32(&par->riva.Bitmap->ClipE.BottomRight, 0,
1619 (((image->dy + image->height) << 16) |
1620 ((image->dx + image->width) & 0xffff)));
1621 NV_WR32(&par->riva.Bitmap->Color0E, 0, bgx);
1622 NV_WR32(&par->riva.Bitmap->Color1E, 0, fgx);
1623 NV_WR32(&par->riva.Bitmap->WidthHeightInE, 0,
1624 (image->height << 16) | ((image->width + 31) & ~31));
1625 NV_WR32(&par->riva.Bitmap->WidthHeightOutE, 0,
1626 (image->height << 16) | ((image->width + 31) & ~31));
1627 NV_WR32(&par->riva.Bitmap->PointE, 0,
1628 (image->dy << 16) | (image->dx & 0xFFFF));
1630 d = &par->riva.Bitmap->MonochromeData01E;
1632 width = (image->width + 31)/32;
1633 size = width * image->height;
1634 while (size >= 16) {
1635 RIVA_FIFO_FREE(par->riva, Bitmap, 16);
1636 for (i = 0; i < 16; i++) {
1637 tmp = *((u32 *)cdat);
1638 cdat = (u8 *)((u32 *)cdat + 1);
1639 reverse_order(&tmp);
1640 NV_WR32(d, i*4, tmp);
1645 RIVA_FIFO_FREE(par->riva, Bitmap, size);
1646 for (i = 0; i < size; i++) {
1647 tmp = *((u32 *) cdat);
1648 cdat = (u8 *)((u32 *)cdat + 1);
1649 reverse_order(&tmp);
1650 NV_WR32(d, i*4, tmp);
1656 * rivafb_cursor - hardware cursor function
1657 * @info: pointer to info structure
1658 * @cursor: pointer to fbcursor structure
1661 * A cursor function that supports displaying a cursor image via hardware.
1662 * Within the kernel, copy and invert rops are supported. If exported
1663 * to user space, only the copy rop will be supported.
1668 static int rivafb_cursor(struct fb_info *info, struct fb_cursor *cursor)
1670 struct riva_par *par = info->par;
1671 u8 data[MAX_CURS * MAX_CURS/8];
1672 int i, set = cursor->set;
1675 if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS)
1678 par->riva.ShowHideCursor(&par->riva, 0);
1680 if (par->cursor_reset) {
1681 set = FB_CUR_SETALL;
1682 par->cursor_reset = 0;
1685 if (set & FB_CUR_SETSIZE)
1686 memset_io(par->riva.CURSOR, 0, MAX_CURS * MAX_CURS * 2);
1688 if (set & FB_CUR_SETPOS) {
1691 yy = cursor->image.dy - info->var.yoffset;
1692 xx = cursor->image.dx - info->var.xoffset;
1696 NV_WR32(par->riva.PRAMDAC, 0x0000300, temp);
1700 if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) {
1701 u32 bg_idx = cursor->image.bg_color;
1702 u32 fg_idx = cursor->image.fg_color;
1703 u32 s_pitch = (cursor->image.width+7) >> 3;
1704 u32 d_pitch = MAX_CURS/8;
1705 u8 *dat = (u8 *) cursor->image.data;
1706 u8 *msk = (u8 *) cursor->mask;
1709 src = kmalloc(s_pitch * cursor->image.height, GFP_ATOMIC);
1712 switch (cursor->rop) {
1714 for (i = 0; i < s_pitch * cursor->image.height; i++)
1715 src[i] = dat[i] ^ msk[i];
1719 for (i = 0; i < s_pitch * cursor->image.height; i++)
1720 src[i] = dat[i] & msk[i];
1724 fb_pad_aligned_buffer(data, d_pitch, src, s_pitch,
1725 cursor->image.height);
1727 bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) |
1728 ((info->cmap.green[bg_idx] & 0xf8) << 2) |
1729 ((info->cmap.blue[bg_idx] & 0xf8) >> 3) |
1732 fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
1733 ((info->cmap.green[fg_idx] & 0xf8) << 2) |
1734 ((info->cmap.blue[fg_idx] & 0xf8) >> 3) |
1737 par->riva.LockUnlock(&par->riva, 0);
1739 rivafb_load_cursor_image(par, data, bg, fg,
1740 cursor->image.width,
1741 cursor->image.height);
1747 par->riva.ShowHideCursor(&par->riva, 1);
1752 static int rivafb_sync(struct fb_info *info)
1754 struct riva_par *par = info->par;
1760 /* ------------------------------------------------------------------------- *
1762 * initialization helper functions
1764 * ------------------------------------------------------------------------- */
1766 /* kernel interface */
1767 static struct fb_ops riva_fb_ops = {
1768 .owner = THIS_MODULE,
1769 .fb_open = rivafb_open,
1770 .fb_release = rivafb_release,
1771 .fb_check_var = rivafb_check_var,
1772 .fb_set_par = rivafb_set_par,
1773 .fb_setcolreg = rivafb_setcolreg,
1774 .fb_pan_display = rivafb_pan_display,
1775 .fb_blank = rivafb_blank,
1776 .fb_fillrect = rivafb_fillrect,
1777 .fb_copyarea = rivafb_copyarea,
1778 .fb_imageblit = rivafb_imageblit,
1779 .fb_cursor = rivafb_cursor,
1780 .fb_sync = rivafb_sync,
1783 static int __devinit riva_set_fbinfo(struct fb_info *info)
1785 unsigned int cmap_len;
1786 struct riva_par *par = info->par;
1789 info->flags = FBINFO_DEFAULT
1790 | FBINFO_HWACCEL_XPAN
1791 | FBINFO_HWACCEL_YPAN
1792 | FBINFO_HWACCEL_COPYAREA
1793 | FBINFO_HWACCEL_FILLRECT
1794 | FBINFO_HWACCEL_IMAGEBLIT;
1796 /* Accel seems to not work properly on NV30 yet...*/
1797 if ((par->riva.Architecture == NV_ARCH_30) || noaccel) {
1798 printk(KERN_DEBUG PFX "disabling acceleration\n");
1799 info->flags |= FBINFO_HWACCEL_DISABLED;
1802 info->var = rivafb_default_var;
1803 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1804 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1806 info->pseudo_palette = par->pseudo_palette;
1808 cmap_len = riva_get_cmap_len(&info->var);
1809 fb_alloc_cmap(&info->cmap, cmap_len, 0);
1811 info->pixmap.size = 8 * 1024;
1812 info->pixmap.buf_align = 4;
1813 info->pixmap.access_align = 32;
1814 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1815 info->var.yres_virtual = -1;
1817 return (rivafb_check_var(&info->var, info));
1820 #ifdef CONFIG_PPC_OF
1821 static int __devinit riva_get_EDID_OF(struct fb_info *info, struct pci_dev *pd)
1823 struct riva_par *par = info->par;
1824 struct device_node *dp;
1825 unsigned char *pedid = NULL;
1826 unsigned char *disptype = NULL;
1827 static char *propnames[] = {
1828 "DFP,EDID", "LCD,EDID", "EDID", "EDID1", "EDID,B", "EDID,A", NULL };
1832 dp = pci_device_to_OF_node(pd);
1833 for (; dp != NULL; dp = dp->child) {
1834 disptype = (unsigned char *)get_property(dp, "display-type", NULL);
1835 if (disptype == NULL)
1837 if (strncmp(disptype, "LCD", 3) != 0)
1839 for (i = 0; propnames[i] != NULL; ++i) {
1840 pedid = (unsigned char *)
1841 get_property(dp, propnames[i], NULL);
1842 if (pedid != NULL) {
1844 NVTRACE("LCD found.\n");
1852 #endif /* CONFIG_PPC_OF */
1854 #if defined(CONFIG_FB_RIVA_I2C) && !defined(CONFIG_PPC_OF)
1855 static int __devinit riva_get_EDID_i2c(struct fb_info *info)
1857 struct riva_par *par = info->par;
1858 struct fb_var_screeninfo var;
1862 riva_create_i2c_busses(par);
1863 for (i = 0; i < par->bus; i++) {
1864 riva_probe_i2c_connector(par, i+1, &par->EDID);
1865 if (par->EDID && !fb_parse_edid(par->EDID, &var)) {
1866 printk(PFX "Found EDID Block from BUS %i\n", i);
1872 return (par->EDID) ? 1 : 0;
1874 #endif /* CONFIG_FB_RIVA_I2C */
1876 static void __devinit riva_update_default_var(struct fb_var_screeninfo *var,
1877 struct fb_info *info)
1879 struct fb_monspecs *specs = &info->monspecs;
1880 struct fb_videomode modedb;
1883 /* respect mode options */
1885 fb_find_mode(var, info, mode_option,
1886 specs->modedb, specs->modedb_len,
1888 } else if (specs->modedb != NULL) {
1889 /* get preferred timing */
1890 if (info->monspecs.misc & FB_MISC_1ST_DETAIL) {
1893 for (i = 0; i < specs->modedb_len; i++) {
1894 if (specs->modedb[i].flag & FB_MODE_IS_FIRST) {
1895 modedb = specs->modedb[i];
1900 /* otherwise, get first mode in database */
1901 modedb = specs->modedb[0];
1903 var->bits_per_pixel = 8;
1904 riva_update_var(var, &modedb);
1910 static void __devinit riva_get_EDID(struct fb_info *info, struct pci_dev *pdev)
1913 #ifdef CONFIG_PPC_OF
1914 if (!riva_get_EDID_OF(info, pdev))
1915 printk(PFX "could not retrieve EDID from OF\n");
1916 #elif defined(CONFIG_FB_RIVA_I2C)
1917 if (!riva_get_EDID_i2c(info))
1918 printk(PFX "could not retrieve EDID from DDC/I2C\n");
1924 static void __devinit riva_get_edidinfo(struct fb_info *info)
1926 struct fb_var_screeninfo *var = &rivafb_default_var;
1927 struct riva_par *par = info->par;
1929 fb_edid_to_monspecs(par->EDID, &info->monspecs);
1930 fb_videomode_to_modelist(info->monspecs.modedb, info->monspecs.modedb_len,
1932 riva_update_default_var(var, info);
1934 /* if user specified flatpanel, we respect that */
1935 if (info->monspecs.input & FB_DISP_DDI)
1939 /* ------------------------------------------------------------------------- *
1943 * ------------------------------------------------------------------------- */
1945 static u32 __devinit riva_get_arch(struct pci_dev *pd)
1949 switch (pd->device & 0x0ff0) {
1950 case 0x0100: /* GeForce 256 */
1951 case 0x0110: /* GeForce2 MX */
1952 case 0x0150: /* GeForce2 */
1953 case 0x0170: /* GeForce4 MX */
1954 case 0x0180: /* GeForce4 MX (8x AGP) */
1955 case 0x01A0: /* nForce */
1956 case 0x01F0: /* nForce2 */
1959 case 0x0200: /* GeForce3 */
1960 case 0x0250: /* GeForce4 Ti */
1961 case 0x0280: /* GeForce4 Ti (8x AGP) */
1964 case 0x0300: /* GeForceFX 5800 */
1965 case 0x0310: /* GeForceFX 5600 */
1966 case 0x0320: /* GeForceFX 5200 */
1967 case 0x0330: /* GeForceFX 5900 */
1968 case 0x0340: /* GeForceFX 5700 */
1971 case 0x0020: /* TNT, TNT2 */
1974 case 0x0010: /* Riva128 */
1977 default: /* unknown architecture */
1983 static int __devinit rivafb_probe(struct pci_dev *pd,
1984 const struct pci_device_id *ent)
1986 struct riva_par *default_par;
1987 struct fb_info *info;
1993 info = framebuffer_alloc(sizeof(struct riva_par), &pd->dev);
1995 printk (KERN_ERR PFX "could not allocate memory\n");
1999 default_par = info->par;
2000 default_par->pdev = pd;
2002 info->pixmap.addr = kmalloc(8 * 1024, GFP_KERNEL);
2003 if (info->pixmap.addr == NULL) {
2005 goto err_framebuffer_release;
2007 memset(info->pixmap.addr, 0, 8 * 1024);
2009 ret = pci_enable_device(pd);
2011 printk(KERN_ERR PFX "cannot enable PCI device\n");
2012 goto err_free_pixmap;
2015 ret = pci_request_regions(pd, "rivafb");
2017 printk(KERN_ERR PFX "cannot request PCI regions\n");
2018 goto err_disable_device;
2021 default_par->riva.Architecture = riva_get_arch(pd);
2023 default_par->Chipset = (pd->vendor << 16) | pd->device;
2024 printk(KERN_INFO PFX "nVidia device/chipset %X\n",default_par->Chipset);
2026 if(default_par->riva.Architecture == 0) {
2027 printk(KERN_ERR PFX "unknown NV_ARCH\n");
2029 goto err_release_region;
2031 if(default_par->riva.Architecture == NV_ARCH_10 ||
2032 default_par->riva.Architecture == NV_ARCH_20 ||
2033 default_par->riva.Architecture == NV_ARCH_30) {
2034 sprintf(rivafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4);
2036 sprintf(rivafb_fix.id, "NV%x", default_par->riva.Architecture);
2039 default_par->FlatPanel = flatpanel;
2041 printk(KERN_INFO PFX "flatpanel support enabled\n");
2042 default_par->forceCRTC = forceCRTC;
2044 rivafb_fix.mmio_len = pci_resource_len(pd, 0);
2045 rivafb_fix.smem_len = pci_resource_len(pd, 1);
2048 /* enable IO and mem if not already done */
2051 pci_read_config_word(pd, PCI_COMMAND, &cmd);
2052 cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
2053 pci_write_config_word(pd, PCI_COMMAND, cmd);
2056 rivafb_fix.mmio_start = pci_resource_start(pd, 0);
2057 rivafb_fix.smem_start = pci_resource_start(pd, 1);
2059 default_par->ctrl_base = ioremap(rivafb_fix.mmio_start,
2060 rivafb_fix.mmio_len);
2061 if (!default_par->ctrl_base) {
2062 printk(KERN_ERR PFX "cannot ioremap MMIO base\n");
2064 goto err_release_region;
2067 switch (default_par->riva.Architecture) {
2069 /* Riva128's PRAMIN is in the "framebuffer" space
2070 * Since these cards were never made with more than 8 megabytes
2071 * we can safely allocate this separately.
2073 default_par->riva.PRAMIN = ioremap(rivafb_fix.smem_start + 0x00C00000, 0x00008000);
2074 if (!default_par->riva.PRAMIN) {
2075 printk(KERN_ERR PFX "cannot ioremap PRAMIN region\n");
2077 goto err_iounmap_ctrl_base;
2084 default_par->riva.PCRTC0 =
2085 (u32 __iomem *)(default_par->ctrl_base + 0x00600000);
2086 default_par->riva.PRAMIN =
2087 (u32 __iomem *)(default_par->ctrl_base + 0x00710000);
2090 riva_common_setup(default_par);
2092 if (default_par->riva.Architecture == NV_ARCH_03) {
2093 default_par->riva.PCRTC = default_par->riva.PCRTC0
2094 = default_par->riva.PGRAPH;
2097 rivafb_fix.smem_len = riva_get_memlen(default_par) * 1024;
2098 default_par->dclk_max = riva_get_maxdclk(default_par) * 1000;
2099 info->screen_base = ioremap(rivafb_fix.smem_start,
2100 rivafb_fix.smem_len);
2101 if (!info->screen_base) {
2102 printk(KERN_ERR PFX "cannot ioremap FB base\n");
2104 goto err_iounmap_pramin;
2109 default_par->mtrr.vram = mtrr_add(rivafb_fix.smem_start,
2110 rivafb_fix.smem_len,
2111 MTRR_TYPE_WRCOMB, 1);
2112 if (default_par->mtrr.vram < 0) {
2113 printk(KERN_ERR PFX "unable to setup MTRR\n");
2115 default_par->mtrr.vram_valid = 1;
2116 /* let there be speed */
2117 printk(KERN_INFO PFX "RIVA MTRR set to ON\n");
2120 #endif /* CONFIG_MTRR */
2122 info->fbops = &riva_fb_ops;
2123 info->fix = rivafb_fix;
2124 riva_get_EDID(info, pd);
2125 riva_get_edidinfo(info);
2127 ret=riva_set_fbinfo(info);
2129 printk(KERN_ERR PFX "error setting initial video mode\n");
2130 goto err_iounmap_screen_base;
2133 fb_destroy_modedb(info->monspecs.modedb);
2134 info->monspecs.modedb = NULL;
2136 pci_set_drvdata(pd, info);
2137 riva_bl_init(info->par);
2138 ret = register_framebuffer(info);
2141 "error registering riva framebuffer\n");
2142 goto err_iounmap_screen_base;
2145 printk(KERN_INFO PFX
2146 "PCI nVidia %s framebuffer ver %s (%dMB @ 0x%lX)\n",
2149 info->fix.smem_len / (1024 * 1024),
2150 info->fix.smem_start);
2155 err_iounmap_screen_base:
2156 #ifdef CONFIG_FB_RIVA_I2C
2157 riva_delete_i2c_busses(info->par);
2159 iounmap(info->screen_base);
2161 if (default_par->riva.Architecture == NV_ARCH_03)
2162 iounmap(default_par->riva.PRAMIN);
2163 err_iounmap_ctrl_base:
2164 iounmap(default_par->ctrl_base);
2166 pci_release_regions(pd);
2169 kfree(info->pixmap.addr);
2170 err_framebuffer_release:
2171 framebuffer_release(info);
2176 static void __exit rivafb_remove(struct pci_dev *pd)
2178 struct fb_info *info = pci_get_drvdata(pd);
2179 struct riva_par *par = info->par;
2185 #ifdef CONFIG_FB_RIVA_I2C
2186 riva_delete_i2c_busses(par);
2190 unregister_framebuffer(info);
2192 if (par->mtrr.vram_valid)
2193 mtrr_del(par->mtrr.vram, info->fix.smem_start,
2194 info->fix.smem_len);
2195 #endif /* CONFIG_MTRR */
2197 iounmap(par->ctrl_base);
2198 iounmap(info->screen_base);
2199 if (par->riva.Architecture == NV_ARCH_03)
2200 iounmap(par->riva.PRAMIN);
2201 pci_release_regions(pd);
2202 kfree(info->pixmap.addr);
2203 framebuffer_release(info);
2204 pci_set_drvdata(pd, NULL);
2208 /* ------------------------------------------------------------------------- *
2212 * ------------------------------------------------------------------------- */
2215 static int __init rivafb_setup(char *options)
2220 if (!options || !*options)
2223 while ((this_opt = strsep(&options, ",")) != NULL) {
2224 if (!strncmp(this_opt, "forceCRTC", 9)) {
2228 if (!*p || !*(++p)) continue;
2229 forceCRTC = *p - '0';
2230 if (forceCRTC < 0 || forceCRTC > 1)
2232 } else if (!strncmp(this_opt, "flatpanel", 9)) {
2235 } else if (!strncmp(this_opt, "nomtrr", 6)) {
2238 } else if (!strncmp(this_opt, "strictmode", 10)) {
2240 } else if (!strncmp(this_opt, "noaccel", 7)) {
2243 mode_option = this_opt;
2248 #endif /* !MODULE */
2250 static struct pci_driver rivafb_driver = {
2252 .id_table = rivafb_pci_tbl,
2253 .probe = rivafb_probe,
2254 .remove = __exit_p(rivafb_remove),
2259 /* ------------------------------------------------------------------------- *
2263 * ------------------------------------------------------------------------- */
2265 static int __devinit rivafb_init(void)
2268 char *option = NULL;
2270 if (fb_get_options("rivafb", &option))
2272 rivafb_setup(option);
2274 return pci_register_driver(&rivafb_driver);
2278 module_init(rivafb_init);
2281 static void __exit rivafb_exit(void)
2283 pci_unregister_driver(&rivafb_driver);
2286 module_exit(rivafb_exit);
2289 module_param(noaccel, bool, 0);
2290 MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
2291 module_param(flatpanel, int, 0);
2292 MODULE_PARM_DESC(flatpanel, "Enables experimental flat panel support for some chipsets. (0 or 1=enabled) (default=0)");
2293 module_param(forceCRTC, int, 0);
2294 MODULE_PARM_DESC(forceCRTC, "Forces usage of a particular CRTC in case autodetection fails. (0 or 1) (default=autodetect)");
2296 module_param(nomtrr, bool, 0);
2297 MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) (default=0)");
2299 module_param(strictmode, bool, 0);
2300 MODULE_PARM_DESC(strictmode, "Only use video modes from EDID");
2302 MODULE_AUTHOR("Ani Joshi, maintainer");
2303 MODULE_DESCRIPTION("Framebuffer driver for nVidia Riva 128, TNT, TNT2, and the GeForce series");
2304 MODULE_LICENSE("GPL");