1 /* linux/drivers/video/s3c-fb.c
3 * Copyright 2008 Openmoko Inc.
4 * Copyright 2008-2010 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
8 * Samsung SoC Framebuffer driver
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software FoundatIon.
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/platform_device.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/slab.h>
20 #include <linux/init.h>
21 #include <linux/clk.h>
24 #include <linux/uaccess.h>
25 #include <linux/interrupt.h>
26 #include <linux/pm_runtime.h>
29 #include <plat/regs-fb-v4.h>
32 /* This driver will export a number of framebuffer interfaces depending
33 * on the configuration passed in via the platform data. Each fb instance
34 * maps to a hardware window. Currently there is no support for runtime
35 * setting of the alpha-blending functions that each window has, so only
36 * window 0 is actually useful.
38 * Window 0 is treated specially, it is used for the basis of the LCD
39 * output timings and as the control for the output power-down state.
42 /* note, the previous use of <mach/regs-fb.h> to get platform specific data
43 * has been replaced by using the platform device name to pick the correct
44 * configuration data for the system.
47 #ifdef CONFIG_FB_S3C_DEBUG_REGWRITE
49 #define writel(v, r) do { \
50 printk(KERN_DEBUG "%s: %08x => %p\n", __func__, (unsigned int)v, r); \
53 #endif /* FB_S3C_DEBUG_REGWRITE */
56 #define S3C_FB_VSYNC_IRQ_EN 0
58 #define VSYNC_TIMEOUT_MSEC 50
62 #define VALID_BPP(x) (1 << ((x) - 1))
64 #define OSD_BASE(win, variant) ((variant).osd + ((win) * (variant).osd_stride))
65 #define VIDOSD_A(win, variant) (OSD_BASE(win, variant) + 0x00)
66 #define VIDOSD_B(win, variant) (OSD_BASE(win, variant) + 0x04)
67 #define VIDOSD_C(win, variant) (OSD_BASE(win, variant) + 0x08)
68 #define VIDOSD_D(win, variant) (OSD_BASE(win, variant) + 0x0C)
71 * struct s3c_fb_variant - fb variant information
72 * @is_2443: Set if S3C2443/S3C2416 style hardware.
73 * @nr_windows: The number of windows.
74 * @vidtcon: The base for the VIDTCONx registers
75 * @wincon: The base for the WINxCON registers.
76 * @winmap: The base for the WINxMAP registers.
77 * @keycon: The abse for the WxKEYCON registers.
78 * @buf_start: Offset of buffer start registers.
79 * @buf_size: Offset of buffer size registers.
80 * @buf_end: Offset of buffer end registers.
81 * @osd: The base for the OSD registers.
82 * @palette: Address of palette memory, or 0 if none.
83 * @has_prtcon: Set if has PRTCON register.
84 * @has_shadowcon: Set if has SHADOWCON register.
85 * @has_blendcon: Set if has BLENDCON register.
86 * @has_clksel: Set if VIDCON0 register has CLKSEL bit.
87 * @has_fixvclk: Set if VIDCON1 register has FIXVCLK bits.
89 struct s3c_fb_variant {
90 unsigned int is_2443:1;
91 unsigned short nr_windows;
92 unsigned short vidtcon;
93 unsigned short wincon;
94 unsigned short winmap;
95 unsigned short keycon;
96 unsigned short buf_start;
97 unsigned short buf_end;
98 unsigned short buf_size;
100 unsigned short osd_stride;
101 unsigned short palette[S3C_FB_MAX_WIN];
103 unsigned int has_prtcon:1;
104 unsigned int has_shadowcon:1;
105 unsigned int has_blendcon:1;
106 unsigned int has_clksel:1;
107 unsigned int has_fixvclk:1;
111 * struct s3c_fb_win_variant
112 * @has_osd_c: Set if has OSD C register.
113 * @has_osd_d: Set if has OSD D register.
114 * @has_osd_alpha: Set if can change alpha transparency for a window.
115 * @palette_sz: Size of palette in entries.
116 * @palette_16bpp: Set if palette is 16bits wide.
117 * @osd_size_off: If != 0, supports setting up OSD for a window; the appropriate
118 * register is located at the given offset from OSD_BASE.
119 * @valid_bpp: 1 bit per BPP setting to show valid bits-per-pixel.
121 * valid_bpp bit x is set if (x+1)BPP is supported.
123 struct s3c_fb_win_variant {
124 unsigned int has_osd_c:1;
125 unsigned int has_osd_d:1;
126 unsigned int has_osd_alpha:1;
127 unsigned int palette_16bpp:1;
128 unsigned short osd_size_off;
129 unsigned short palette_sz;
134 * struct s3c_fb_driverdata - per-device type driver data for init time.
135 * @variant: The variant information for this driver.
136 * @win: The window information for each window.
138 struct s3c_fb_driverdata {
139 struct s3c_fb_variant variant;
140 struct s3c_fb_win_variant *win[S3C_FB_MAX_WIN];
144 * struct s3c_fb_palette - palette information
146 * @g: Green bitfield.
148 * @a: Alpha bitfield.
150 struct s3c_fb_palette {
151 struct fb_bitfield r;
152 struct fb_bitfield g;
153 struct fb_bitfield b;
154 struct fb_bitfield a;
158 * struct s3c_fb_win - per window private data for each framebuffer.
159 * @windata: The platform data supplied for the window configuration.
160 * @parent: The hardware that this window is part of.
161 * @fbinfo: Pointer pack to the framebuffer info for this window.
162 * @varint: The variant information for this window.
163 * @palette_buffer: Buffer/cache to hold palette entries.
164 * @pseudo_palette: For use in TRUECOLOUR modes for entries 0..15/
165 * @index: The window number of this window.
166 * @palette: The bitfields for changing r/g/b into a hardware palette entry.
169 struct s3c_fb_pd_win *windata;
170 struct s3c_fb *parent;
171 struct fb_info *fbinfo;
172 struct s3c_fb_palette palette;
173 struct s3c_fb_win_variant variant;
176 u32 pseudo_palette[16];
181 * struct s3c_fb_vsync - vsync information
182 * @wait: a queue for processes waiting for vsync
183 * @count: vsync interrupt count
185 struct s3c_fb_vsync {
186 wait_queue_head_t wait;
191 * struct s3c_fb - overall hardware state of the hardware
192 * @slock: The spinlock protection for this data sturcture.
193 * @dev: The device that we bound to, for printing, etc.
194 * @bus_clk: The clk (hclk) feeding our interface and possibly pixclk.
195 * @lcd_clk: The clk (sclk) feeding pixclk.
196 * @regs: The mapped hardware registers.
197 * @variant: Variant information for this hardware.
198 * @enabled: A bitmask of enabled hardware windows.
199 * @output_on: Flag if the physical output is enabled.
200 * @pdata: The platform configuration data passed with the device.
201 * @windows: The hardware windows that have been claimed.
202 * @irq_no: IRQ line number
203 * @irq_flags: irq flags
204 * @vsync_info: VSYNC-related information (count, queues...)
212 struct s3c_fb_variant variant;
214 unsigned char enabled;
217 struct s3c_fb_platdata *pdata;
218 struct s3c_fb_win *windows[S3C_FB_MAX_WIN];
221 unsigned long irq_flags;
222 struct s3c_fb_vsync vsync_info;
226 * s3c_fb_validate_win_bpp - validate the bits-per-pixel for this mode.
227 * @win: The device window.
228 * @bpp: The bit depth.
230 static bool s3c_fb_validate_win_bpp(struct s3c_fb_win *win, unsigned int bpp)
232 return win->variant.valid_bpp & VALID_BPP(bpp);
236 * s3c_fb_check_var() - framebuffer layer request to verify a given mode.
237 * @var: The screen information to verify.
238 * @info: The framebuffer device.
240 * Framebuffer layer call to verify the given information and allow us to
241 * update various information depending on the hardware capabilities.
243 static int s3c_fb_check_var(struct fb_var_screeninfo *var,
244 struct fb_info *info)
246 struct s3c_fb_win *win = info->par;
247 struct s3c_fb *sfb = win->parent;
249 dev_dbg(sfb->dev, "checking parameters\n");
251 var->xres_virtual = max(var->xres_virtual, var->xres);
252 var->yres_virtual = max(var->yres_virtual, var->yres);
254 if (!s3c_fb_validate_win_bpp(win, var->bits_per_pixel)) {
255 dev_dbg(sfb->dev, "win %d: unsupported bpp %d\n",
256 win->index, var->bits_per_pixel);
260 /* always ensure these are zero, for drop through cases below */
261 var->transp.offset = 0;
262 var->transp.length = 0;
264 switch (var->bits_per_pixel) {
269 if (sfb->variant.palette[win->index] != 0) {
270 /* non palletised, A:1,R:2,G:3,B:2 mode */
272 var->green.offset = 2;
273 var->blue.offset = 0;
275 var->green.length = 3;
276 var->blue.length = 2;
277 var->transp.offset = 7;
278 var->transp.length = 1;
281 var->red.length = var->bits_per_pixel;
282 var->green = var->red;
283 var->blue = var->red;
288 /* 666 with one bit alpha/transparency */
289 var->transp.offset = 18;
290 var->transp.length = 1;
292 var->bits_per_pixel = 32;
295 var->red.offset = 12;
296 var->green.offset = 6;
297 var->blue.offset = 0;
299 var->green.length = 6;
300 var->blue.length = 6;
304 /* 16 bpp, 565 format */
305 var->red.offset = 11;
306 var->green.offset = 5;
307 var->blue.offset = 0;
309 var->green.length = 6;
310 var->blue.length = 5;
316 var->transp.length = var->bits_per_pixel - 24;
317 var->transp.offset = 24;
320 /* our 24bpp is unpacked, so 32bpp */
321 var->bits_per_pixel = 32;
322 var->red.offset = 16;
324 var->green.offset = 8;
325 var->green.length = 8;
326 var->blue.offset = 0;
327 var->blue.length = 8;
331 dev_err(sfb->dev, "invalid bpp\n");
334 dev_dbg(sfb->dev, "%s: verified parameters\n", __func__);
339 * s3c_fb_calc_pixclk() - calculate the divider to create the pixel clock.
340 * @sfb: The hardware state.
341 * @pixclock: The pixel clock wanted, in picoseconds.
343 * Given the specified pixel clock, work out the necessary divider to get
344 * close to the output frequency.
346 static int s3c_fb_calc_pixclk(struct s3c_fb *sfb, unsigned int pixclk)
349 unsigned long long tmp;
352 if (sfb->variant.has_clksel)
353 clk = clk_get_rate(sfb->bus_clk);
355 clk = clk_get_rate(sfb->lcd_clk);
357 tmp = (unsigned long long)clk;
360 do_div(tmp, 1000000000UL);
361 result = (unsigned int)tmp / 1000;
363 dev_dbg(sfb->dev, "pixclk=%u, clk=%lu, div=%d (%lu)\n",
364 pixclk, clk, result, clk / result);
370 * s3c_fb_align_word() - align pixel count to word boundary
371 * @bpp: The number of bits per pixel
372 * @pix: The value to be aligned.
374 * Align the given pixel count so that it will start on an 32bit word
377 static int s3c_fb_align_word(unsigned int bpp, unsigned int pix)
384 pix_per_word = (8 * 32) / bpp;
385 return ALIGN(pix, pix_per_word);
389 * vidosd_set_size() - set OSD size for a window
391 * @win: the window to set OSD size for
392 * @size: OSD size register value
394 static void vidosd_set_size(struct s3c_fb_win *win, u32 size)
396 struct s3c_fb *sfb = win->parent;
398 /* OSD can be set up if osd_size_off != 0 for this window */
399 if (win->variant.osd_size_off)
400 writel(size, sfb->regs + OSD_BASE(win->index, sfb->variant)
401 + win->variant.osd_size_off);
405 * vidosd_set_alpha() - set alpha transparency for a window
407 * @win: the window to set OSD size for
408 * @alpha: alpha register value
410 static void vidosd_set_alpha(struct s3c_fb_win *win, u32 alpha)
412 struct s3c_fb *sfb = win->parent;
414 if (win->variant.has_osd_alpha)
415 writel(alpha, sfb->regs + VIDOSD_C(win->index, sfb->variant));
419 * shadow_protect_win() - disable updating values from shadow registers at vsync
421 * @win: window to protect registers for
422 * @protect: 1 to protect (disable updates)
424 static void shadow_protect_win(struct s3c_fb_win *win, bool protect)
426 struct s3c_fb *sfb = win->parent;
430 if (sfb->variant.has_prtcon) {
431 writel(PRTCON_PROTECT, sfb->regs + PRTCON);
432 } else if (sfb->variant.has_shadowcon) {
433 reg = readl(sfb->regs + SHADOWCON);
434 writel(reg | SHADOWCON_WINx_PROTECT(win->index),
435 sfb->regs + SHADOWCON);
438 if (sfb->variant.has_prtcon) {
439 writel(0, sfb->regs + PRTCON);
440 } else if (sfb->variant.has_shadowcon) {
441 reg = readl(sfb->regs + SHADOWCON);
442 writel(reg & ~SHADOWCON_WINx_PROTECT(win->index),
443 sfb->regs + SHADOWCON);
449 * s3c_fb_enable() - Set the state of the main LCD output
450 * @sfb: The main framebuffer state.
451 * @enable: The state to set.
453 static void s3c_fb_enable(struct s3c_fb *sfb, int enable)
455 u32 vidcon0 = readl(sfb->regs + VIDCON0);
457 if (enable && !sfb->output_on)
458 pm_runtime_get_sync(sfb->dev);
461 vidcon0 |= VIDCON0_ENVID | VIDCON0_ENVID_F;
463 /* see the note in the framebuffer datasheet about
464 * why you cannot take both of these bits down at the
467 if (vidcon0 & VIDCON0_ENVID) {
468 vidcon0 |= VIDCON0_ENVID;
469 vidcon0 &= ~VIDCON0_ENVID_F;
473 writel(vidcon0, sfb->regs + VIDCON0);
475 if (!enable && sfb->output_on)
476 pm_runtime_put_sync(sfb->dev);
478 sfb->output_on = enable;
482 * s3c_fb_set_par() - framebuffer request to set new framebuffer state.
483 * @info: The framebuffer to change.
485 * Framebuffer layer request to set a new mode for the specified framebuffer
487 static int s3c_fb_set_par(struct fb_info *info)
489 struct fb_var_screeninfo *var = &info->var;
490 struct s3c_fb_win *win = info->par;
491 struct s3c_fb *sfb = win->parent;
492 void __iomem *regs = sfb->regs;
493 void __iomem *buf = regs;
494 int win_no = win->index;
500 dev_dbg(sfb->dev, "setting framebuffer parameters\n");
502 pm_runtime_get_sync(sfb->dev);
504 shadow_protect_win(win, 1);
506 switch (var->bits_per_pixel) {
511 info->fix.visual = FB_VISUAL_TRUECOLOR;
514 if (win->variant.palette_sz >= 256)
515 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
517 info->fix.visual = FB_VISUAL_TRUECOLOR;
520 info->fix.visual = FB_VISUAL_MONO01;
523 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
527 info->fix.line_length = (var->xres_virtual * var->bits_per_pixel) / 8;
529 info->fix.xpanstep = info->var.xres_virtual > info->var.xres ? 1 : 0;
530 info->fix.ypanstep = info->var.yres_virtual > info->var.yres ? 1 : 0;
532 /* disable the window whilst we update it */
533 writel(0, regs + WINCON(win_no));
535 /* use platform specified window as the basis for the lcd timings */
537 if (win_no == sfb->pdata->default_win) {
538 clkdiv = s3c_fb_calc_pixclk(sfb, var->pixclock);
540 data = sfb->pdata->vidcon0;
541 data &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR);
544 data |= VIDCON0_CLKVAL_F(clkdiv-1) | VIDCON0_CLKDIR;
546 data &= ~VIDCON0_CLKDIR; /* 1:1 clock */
548 /* write the timing data to the panel */
550 if (sfb->variant.is_2443)
553 writel(data, regs + VIDCON0);
555 s3c_fb_enable(sfb, 1);
557 data = VIDTCON0_VBPD(var->upper_margin - 1) |
558 VIDTCON0_VFPD(var->lower_margin - 1) |
559 VIDTCON0_VSPW(var->vsync_len - 1);
561 writel(data, regs + sfb->variant.vidtcon);
563 data = VIDTCON1_HBPD(var->left_margin - 1) |
564 VIDTCON1_HFPD(var->right_margin - 1) |
565 VIDTCON1_HSPW(var->hsync_len - 1);
568 writel(data, regs + sfb->variant.vidtcon + 4);
570 data = VIDTCON2_LINEVAL(var->yres - 1) |
571 VIDTCON2_HOZVAL(var->xres - 1);
572 writel(data, regs + sfb->variant.vidtcon + 8);
575 /* write the buffer address */
577 /* start and end registers stride is 8 */
578 buf = regs + win_no * 8;
580 writel(info->fix.smem_start, buf + sfb->variant.buf_start);
582 data = info->fix.smem_start + info->fix.line_length * var->yres;
583 writel(data, buf + sfb->variant.buf_end);
585 pagewidth = (var->xres * var->bits_per_pixel) >> 3;
586 data = VIDW_BUF_SIZE_OFFSET(info->fix.line_length - pagewidth) |
587 VIDW_BUF_SIZE_PAGEWIDTH(pagewidth);
588 writel(data, regs + sfb->variant.buf_size + (win_no * 4));
590 /* write 'OSD' registers to control position of framebuffer */
592 data = VIDOSDxA_TOPLEFT_X(0) | VIDOSDxA_TOPLEFT_Y(0);
593 writel(data, regs + VIDOSD_A(win_no, sfb->variant));
595 data = VIDOSDxB_BOTRIGHT_X(s3c_fb_align_word(var->bits_per_pixel,
597 VIDOSDxB_BOTRIGHT_Y(var->yres - 1);
599 writel(data, regs + VIDOSD_B(win_no, sfb->variant));
601 data = var->xres * var->yres;
603 alpha = VIDISD14C_ALPHA1_R(0xf) |
604 VIDISD14C_ALPHA1_G(0xf) |
605 VIDISD14C_ALPHA1_B(0xf);
607 vidosd_set_alpha(win, alpha);
608 vidosd_set_size(win, data);
610 /* Enable DMA channel for this window */
611 if (sfb->variant.has_shadowcon) {
612 data = readl(sfb->regs + SHADOWCON);
613 data |= SHADOWCON_CHx_ENABLE(win_no);
614 writel(data, sfb->regs + SHADOWCON);
617 data = WINCONx_ENWIN;
618 sfb->enabled |= (1 << win->index);
620 /* note, since we have to round up the bits-per-pixel, we end up
621 * relying on the bitfield information for r/g/b/a to work out
622 * exactly which mode of operation is intended. */
624 switch (var->bits_per_pixel) {
626 data |= WINCON0_BPPMODE_1BPP;
627 data |= WINCONx_BITSWP;
628 data |= WINCONx_BURSTLEN_4WORD;
631 data |= WINCON0_BPPMODE_2BPP;
632 data |= WINCONx_BITSWP;
633 data |= WINCONx_BURSTLEN_8WORD;
636 data |= WINCON0_BPPMODE_4BPP;
637 data |= WINCONx_BITSWP;
638 data |= WINCONx_BURSTLEN_8WORD;
641 if (var->transp.length != 0)
642 data |= WINCON1_BPPMODE_8BPP_1232;
644 data |= WINCON0_BPPMODE_8BPP_PALETTE;
645 data |= WINCONx_BURSTLEN_8WORD;
646 data |= WINCONx_BYTSWP;
649 if (var->transp.length != 0)
650 data |= WINCON1_BPPMODE_16BPP_A1555;
652 data |= WINCON0_BPPMODE_16BPP_565;
653 data |= WINCONx_HAWSWP;
654 data |= WINCONx_BURSTLEN_16WORD;
658 if (var->red.length == 6) {
659 if (var->transp.length != 0)
660 data |= WINCON1_BPPMODE_19BPP_A1666;
662 data |= WINCON1_BPPMODE_18BPP_666;
663 } else if (var->transp.length == 1)
664 data |= WINCON1_BPPMODE_25BPP_A1888
666 else if ((var->transp.length == 4) ||
667 (var->transp.length == 8))
668 data |= WINCON1_BPPMODE_28BPP_A4888
669 | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
671 data |= WINCON0_BPPMODE_24BPP_888;
673 data |= WINCONx_WSWP;
674 data |= WINCONx_BURSTLEN_16WORD;
678 /* Enable the colour keying for the window below this one */
680 u32 keycon0_data = 0, keycon1_data = 0;
681 void __iomem *keycon = regs + sfb->variant.keycon;
683 keycon0_data = ~(WxKEYCON0_KEYBL_EN |
685 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
687 keycon1_data = WxKEYCON1_COLVAL(0xffffff);
689 keycon += (win_no - 1) * 8;
691 writel(keycon0_data, keycon + WKEYCON0);
692 writel(keycon1_data, keycon + WKEYCON1);
695 writel(data, regs + sfb->variant.wincon + (win_no * 4));
696 writel(0x0, regs + sfb->variant.winmap + (win_no * 4));
698 /* Set alpha value width */
699 if (sfb->variant.has_blendcon) {
700 data = readl(sfb->regs + BLENDCON);
701 data &= ~BLENDCON_NEW_MASK;
702 if (var->transp.length > 4)
703 data |= BLENDCON_NEW_8BIT_ALPHA_VALUE;
705 data |= BLENDCON_NEW_4BIT_ALPHA_VALUE;
706 writel(data, sfb->regs + BLENDCON);
709 shadow_protect_win(win, 0);
711 pm_runtime_put_sync(sfb->dev);
717 * s3c_fb_update_palette() - set or schedule a palette update.
718 * @sfb: The hardware information.
719 * @win: The window being updated.
720 * @reg: The palette index being changed.
721 * @value: The computed palette value.
723 * Change the value of a palette register, either by directly writing to
724 * the palette (this requires the palette RAM to be disconnected from the
725 * hardware whilst this is in progress) or schedule the update for later.
727 * At the moment, since we have no VSYNC interrupt support, we simply set
728 * the palette entry directly.
730 static void s3c_fb_update_palette(struct s3c_fb *sfb,
731 struct s3c_fb_win *win,
735 void __iomem *palreg;
738 palreg = sfb->regs + sfb->variant.palette[win->index];
740 dev_dbg(sfb->dev, "%s: win %d, reg %d (%p): %08x\n",
741 __func__, win->index, reg, palreg, value);
743 win->palette_buffer[reg] = value;
745 palcon = readl(sfb->regs + WPALCON);
746 writel(palcon | WPALCON_PAL_UPDATE, sfb->regs + WPALCON);
748 if (win->variant.palette_16bpp)
749 writew(value, palreg + (reg * 2));
751 writel(value, palreg + (reg * 4));
753 writel(palcon, sfb->regs + WPALCON);
756 static inline unsigned int chan_to_field(unsigned int chan,
757 struct fb_bitfield *bf)
760 chan >>= 16 - bf->length;
761 return chan << bf->offset;
765 * s3c_fb_setcolreg() - framebuffer layer request to change palette.
766 * @regno: The palette index to change.
767 * @red: The red field for the palette data.
768 * @green: The green field for the palette data.
769 * @blue: The blue field for the palette data.
770 * @trans: The transparency (alpha) field for the palette data.
771 * @info: The framebuffer being changed.
773 static int s3c_fb_setcolreg(unsigned regno,
774 unsigned red, unsigned green, unsigned blue,
775 unsigned transp, struct fb_info *info)
777 struct s3c_fb_win *win = info->par;
778 struct s3c_fb *sfb = win->parent;
781 dev_dbg(sfb->dev, "%s: win %d: %d => rgb=%d/%d/%d\n",
782 __func__, win->index, regno, red, green, blue);
784 pm_runtime_get_sync(sfb->dev);
786 switch (info->fix.visual) {
787 case FB_VISUAL_TRUECOLOR:
788 /* true-colour, use pseudo-palette */
791 u32 *pal = info->pseudo_palette;
793 val = chan_to_field(red, &info->var.red);
794 val |= chan_to_field(green, &info->var.green);
795 val |= chan_to_field(blue, &info->var.blue);
801 case FB_VISUAL_PSEUDOCOLOR:
802 if (regno < win->variant.palette_sz) {
803 val = chan_to_field(red, &win->palette.r);
804 val |= chan_to_field(green, &win->palette.g);
805 val |= chan_to_field(blue, &win->palette.b);
807 s3c_fb_update_palette(sfb, win, regno, val);
813 pm_runtime_put_sync(sfb->dev);
814 return 1; /* unknown type */
817 pm_runtime_put_sync(sfb->dev);
822 * s3c_fb_blank() - blank or unblank the given window
823 * @blank_mode: The blank state from FB_BLANK_*
824 * @info: The framebuffer to blank.
826 * Framebuffer layer request to change the power state.
828 static int s3c_fb_blank(int blank_mode, struct fb_info *info)
830 struct s3c_fb_win *win = info->par;
831 struct s3c_fb *sfb = win->parent;
832 unsigned int index = win->index;
835 dev_dbg(sfb->dev, "blank mode %d\n", blank_mode);
837 pm_runtime_get_sync(sfb->dev);
839 wincon = readl(sfb->regs + sfb->variant.wincon + (index * 4));
841 switch (blank_mode) {
842 case FB_BLANK_POWERDOWN:
843 wincon &= ~WINCONx_ENWIN;
844 sfb->enabled &= ~(1 << index);
845 /* fall through to FB_BLANK_NORMAL */
847 case FB_BLANK_NORMAL:
848 /* disable the DMA and display 0x0 (black) */
849 shadow_protect_win(win, 1);
850 writel(WINxMAP_MAP | WINxMAP_MAP_COLOUR(0x0),
851 sfb->regs + sfb->variant.winmap + (index * 4));
852 shadow_protect_win(win, 0);
855 case FB_BLANK_UNBLANK:
856 shadow_protect_win(win, 1);
857 writel(0x0, sfb->regs + sfb->variant.winmap + (index * 4));
858 shadow_protect_win(win, 0);
859 wincon |= WINCONx_ENWIN;
860 sfb->enabled |= (1 << index);
863 case FB_BLANK_VSYNC_SUSPEND:
864 case FB_BLANK_HSYNC_SUSPEND:
866 pm_runtime_put_sync(sfb->dev);
870 shadow_protect_win(win, 1);
871 writel(wincon, sfb->regs + sfb->variant.wincon + (index * 4));
872 shadow_protect_win(win, 0);
874 /* Check the enabled state to see if we need to be running the
875 * main LCD interface, as if there are no active windows then
876 * it is highly likely that we also do not need to output
880 /* We could do something like the following code, but the current
881 * system of using framebuffer events means that we cannot make
882 * the distinction between just window 0 being inactive and all
883 * the windows being down.
885 * s3c_fb_enable(sfb, sfb->enabled ? 1 : 0);
888 /* we're stuck with this until we can do something about overriding
889 * the power control using the blanking event for a single fb.
891 if (index == sfb->pdata->default_win) {
892 shadow_protect_win(win, 1);
893 s3c_fb_enable(sfb, blank_mode != FB_BLANK_POWERDOWN ? 1 : 0);
894 shadow_protect_win(win, 0);
897 pm_runtime_put_sync(sfb->dev);
903 * s3c_fb_pan_display() - Pan the display.
905 * Note that the offsets can be written to the device at any time, as their
906 * values are latched at each vsync automatically. This also means that only
907 * the last call to this function will have any effect on next vsync, but
908 * there is no need to sleep waiting for it to prevent tearing.
910 * @var: The screen information to verify.
911 * @info: The framebuffer device.
913 static int s3c_fb_pan_display(struct fb_var_screeninfo *var,
914 struct fb_info *info)
916 struct s3c_fb_win *win = info->par;
917 struct s3c_fb *sfb = win->parent;
918 void __iomem *buf = sfb->regs + win->index * 8;
919 unsigned int start_boff, end_boff;
921 pm_runtime_get_sync(sfb->dev);
923 /* Offset in bytes to the start of the displayed area */
924 start_boff = var->yoffset * info->fix.line_length;
925 /* X offset depends on the current bpp */
926 if (info->var.bits_per_pixel >= 8) {
927 start_boff += var->xoffset * (info->var.bits_per_pixel >> 3);
929 switch (info->var.bits_per_pixel) {
931 start_boff += var->xoffset >> 1;
934 start_boff += var->xoffset >> 2;
937 start_boff += var->xoffset >> 3;
940 dev_err(sfb->dev, "invalid bpp\n");
941 pm_runtime_put_sync(sfb->dev);
945 /* Offset in bytes to the end of the displayed area */
946 end_boff = start_boff + info->var.yres * info->fix.line_length;
948 /* Temporarily turn off per-vsync update from shadow registers until
949 * both start and end addresses are updated to prevent corruption */
950 shadow_protect_win(win, 1);
952 writel(info->fix.smem_start + start_boff, buf + sfb->variant.buf_start);
953 writel(info->fix.smem_start + end_boff, buf + sfb->variant.buf_end);
955 shadow_protect_win(win, 0);
957 pm_runtime_put_sync(sfb->dev);
962 * s3c_fb_enable_irq() - enable framebuffer interrupts
963 * @sfb: main hardware state
965 static void s3c_fb_enable_irq(struct s3c_fb *sfb)
967 void __iomem *regs = sfb->regs;
970 if (!test_and_set_bit(S3C_FB_VSYNC_IRQ_EN, &sfb->irq_flags)) {
971 /* IRQ disabled, enable it */
972 irq_ctrl_reg = readl(regs + VIDINTCON0);
974 irq_ctrl_reg |= VIDINTCON0_INT_ENABLE;
975 irq_ctrl_reg |= VIDINTCON0_INT_FRAME;
977 irq_ctrl_reg &= ~VIDINTCON0_FRAMESEL0_MASK;
978 irq_ctrl_reg |= VIDINTCON0_FRAMESEL0_VSYNC;
979 irq_ctrl_reg &= ~VIDINTCON0_FRAMESEL1_MASK;
980 irq_ctrl_reg |= VIDINTCON0_FRAMESEL1_NONE;
982 writel(irq_ctrl_reg, regs + VIDINTCON0);
987 * s3c_fb_disable_irq() - disable framebuffer interrupts
988 * @sfb: main hardware state
990 static void s3c_fb_disable_irq(struct s3c_fb *sfb)
992 void __iomem *regs = sfb->regs;
995 if (test_and_clear_bit(S3C_FB_VSYNC_IRQ_EN, &sfb->irq_flags)) {
996 /* IRQ enabled, disable it */
997 irq_ctrl_reg = readl(regs + VIDINTCON0);
999 irq_ctrl_reg &= ~VIDINTCON0_INT_FRAME;
1000 irq_ctrl_reg &= ~VIDINTCON0_INT_ENABLE;
1002 writel(irq_ctrl_reg, regs + VIDINTCON0);
1006 static irqreturn_t s3c_fb_irq(int irq, void *dev_id)
1008 struct s3c_fb *sfb = dev_id;
1009 void __iomem *regs = sfb->regs;
1012 spin_lock(&sfb->slock);
1014 irq_sts_reg = readl(regs + VIDINTCON1);
1016 if (irq_sts_reg & VIDINTCON1_INT_FRAME) {
1018 /* VSYNC interrupt, accept it */
1019 writel(VIDINTCON1_INT_FRAME, regs + VIDINTCON1);
1021 sfb->vsync_info.count++;
1022 wake_up_interruptible(&sfb->vsync_info.wait);
1025 /* We only support waiting for VSYNC for now, so it's safe
1026 * to always disable irqs here.
1028 s3c_fb_disable_irq(sfb);
1030 spin_unlock(&sfb->slock);
1035 * s3c_fb_wait_for_vsync() - sleep until next VSYNC interrupt or timeout
1036 * @sfb: main hardware state
1037 * @crtc: head index.
1039 static int s3c_fb_wait_for_vsync(struct s3c_fb *sfb, u32 crtc)
1041 unsigned long count;
1047 pm_runtime_get_sync(sfb->dev);
1049 count = sfb->vsync_info.count;
1050 s3c_fb_enable_irq(sfb);
1051 ret = wait_event_interruptible_timeout(sfb->vsync_info.wait,
1052 count != sfb->vsync_info.count,
1053 msecs_to_jiffies(VSYNC_TIMEOUT_MSEC));
1055 pm_runtime_put_sync(sfb->dev);
1063 static int s3c_fb_ioctl(struct fb_info *info, unsigned int cmd,
1066 struct s3c_fb_win *win = info->par;
1067 struct s3c_fb *sfb = win->parent;
1072 case FBIO_WAITFORVSYNC:
1073 if (get_user(crtc, (u32 __user *)arg)) {
1078 ret = s3c_fb_wait_for_vsync(sfb, crtc);
1087 static struct fb_ops s3c_fb_ops = {
1088 .owner = THIS_MODULE,
1089 .fb_check_var = s3c_fb_check_var,
1090 .fb_set_par = s3c_fb_set_par,
1091 .fb_blank = s3c_fb_blank,
1092 .fb_setcolreg = s3c_fb_setcolreg,
1093 .fb_fillrect = cfb_fillrect,
1094 .fb_copyarea = cfb_copyarea,
1095 .fb_imageblit = cfb_imageblit,
1096 .fb_pan_display = s3c_fb_pan_display,
1097 .fb_ioctl = s3c_fb_ioctl,
1101 * s3c_fb_missing_pixclock() - calculates pixel clock
1102 * @mode: The video mode to change.
1104 * Calculate the pixel clock when none has been given through platform data.
1106 static void __devinit s3c_fb_missing_pixclock(struct fb_videomode *mode)
1108 u64 pixclk = 1000000000000ULL;
1111 div = mode->left_margin + mode->hsync_len + mode->right_margin +
1113 div *= mode->upper_margin + mode->vsync_len + mode->lower_margin +
1115 div *= mode->refresh ? : 60;
1117 do_div(pixclk, div);
1119 mode->pixclock = pixclk;
1123 * s3c_fb_alloc_memory() - allocate display memory for framebuffer window
1124 * @sfb: The base resources for the hardware.
1125 * @win: The window to initialise memory for.
1127 * Allocate memory for the given framebuffer.
1129 static int __devinit s3c_fb_alloc_memory(struct s3c_fb *sfb,
1130 struct s3c_fb_win *win)
1132 struct s3c_fb_pd_win *windata = win->windata;
1133 unsigned int real_size, virt_size, size;
1134 struct fb_info *fbi = win->fbinfo;
1137 dev_dbg(sfb->dev, "allocating memory for display\n");
1139 real_size = windata->win_mode.xres * windata->win_mode.yres;
1140 virt_size = windata->virtual_x * windata->virtual_y;
1142 dev_dbg(sfb->dev, "real_size=%u (%u.%u), virt_size=%u (%u.%u)\n",
1143 real_size, windata->win_mode.xres, windata->win_mode.yres,
1144 virt_size, windata->virtual_x, windata->virtual_y);
1146 size = (real_size > virt_size) ? real_size : virt_size;
1147 size *= (windata->max_bpp > 16) ? 32 : windata->max_bpp;
1150 fbi->fix.smem_len = size;
1151 size = PAGE_ALIGN(size);
1153 dev_dbg(sfb->dev, "want %u bytes for window\n", size);
1155 fbi->screen_base = dma_alloc_writecombine(sfb->dev, size,
1156 &map_dma, GFP_KERNEL);
1157 if (!fbi->screen_base)
1160 dev_dbg(sfb->dev, "mapped %x to %p\n",
1161 (unsigned int)map_dma, fbi->screen_base);
1163 memset(fbi->screen_base, 0x0, size);
1164 fbi->fix.smem_start = map_dma;
1170 * s3c_fb_free_memory() - free the display memory for the given window
1171 * @sfb: The base resources for the hardware.
1172 * @win: The window to free the display memory for.
1174 * Free the display memory allocated by s3c_fb_alloc_memory().
1176 static void s3c_fb_free_memory(struct s3c_fb *sfb, struct s3c_fb_win *win)
1178 struct fb_info *fbi = win->fbinfo;
1180 if (fbi->screen_base)
1181 dma_free_writecombine(sfb->dev, PAGE_ALIGN(fbi->fix.smem_len),
1182 fbi->screen_base, fbi->fix.smem_start);
1186 * s3c_fb_release_win() - release resources for a framebuffer window.
1187 * @win: The window to cleanup the resources for.
1189 * Release the resources that where claimed for the hardware window,
1190 * such as the framebuffer instance and any memory claimed for it.
1192 static void s3c_fb_release_win(struct s3c_fb *sfb, struct s3c_fb_win *win)
1197 if (sfb->variant.has_shadowcon) {
1198 data = readl(sfb->regs + SHADOWCON);
1199 data &= ~SHADOWCON_CHx_ENABLE(win->index);
1200 data &= ~SHADOWCON_CHx_LOCAL_ENABLE(win->index);
1201 writel(data, sfb->regs + SHADOWCON);
1203 unregister_framebuffer(win->fbinfo);
1204 if (win->fbinfo->cmap.len)
1205 fb_dealloc_cmap(&win->fbinfo->cmap);
1206 s3c_fb_free_memory(sfb, win);
1207 framebuffer_release(win->fbinfo);
1212 * s3c_fb_probe_win() - register an hardware window
1213 * @sfb: The base resources for the hardware
1214 * @variant: The variant information for this window.
1215 * @res: Pointer to where to place the resultant window.
1217 * Allocate and do the basic initialisation for one of the hardware's graphics
1220 static int __devinit s3c_fb_probe_win(struct s3c_fb *sfb, unsigned int win_no,
1221 struct s3c_fb_win_variant *variant,
1222 struct s3c_fb_win **res)
1224 struct fb_var_screeninfo *var;
1225 struct fb_videomode *initmode;
1226 struct s3c_fb_pd_win *windata;
1227 struct s3c_fb_win *win;
1228 struct fb_info *fbinfo;
1232 dev_dbg(sfb->dev, "probing window %d, variant %p\n", win_no, variant);
1234 init_waitqueue_head(&sfb->vsync_info.wait);
1236 palette_size = variant->palette_sz * 4;
1238 fbinfo = framebuffer_alloc(sizeof(struct s3c_fb_win) +
1239 palette_size * sizeof(u32), sfb->dev);
1241 dev_err(sfb->dev, "failed to allocate framebuffer\n");
1245 windata = sfb->pdata->win[win_no];
1246 initmode = &windata->win_mode;
1248 WARN_ON(windata->max_bpp == 0);
1249 WARN_ON(windata->win_mode.xres == 0);
1250 WARN_ON(windata->win_mode.yres == 0);
1255 win->variant = *variant;
1256 win->fbinfo = fbinfo;
1258 win->windata = windata;
1259 win->index = win_no;
1260 win->palette_buffer = (u32 *)(win + 1);
1262 ret = s3c_fb_alloc_memory(sfb, win);
1264 dev_err(sfb->dev, "failed to allocate display memory\n");
1268 /* setup the r/b/g positions for the window's palette */
1269 if (win->variant.palette_16bpp) {
1270 /* Set RGB 5:6:5 as default */
1271 win->palette.r.offset = 11;
1272 win->palette.r.length = 5;
1273 win->palette.g.offset = 5;
1274 win->palette.g.length = 6;
1275 win->palette.b.offset = 0;
1276 win->palette.b.length = 5;
1279 /* Set 8bpp or 8bpp and 1bit alpha */
1280 win->palette.r.offset = 16;
1281 win->palette.r.length = 8;
1282 win->palette.g.offset = 8;
1283 win->palette.g.length = 8;
1284 win->palette.b.offset = 0;
1285 win->palette.b.length = 8;
1288 /* setup the initial video mode from the window */
1289 fb_videomode_to_var(&fbinfo->var, initmode);
1291 fbinfo->fix.type = FB_TYPE_PACKED_PIXELS;
1292 fbinfo->fix.accel = FB_ACCEL_NONE;
1293 fbinfo->var.activate = FB_ACTIVATE_NOW;
1294 fbinfo->var.vmode = FB_VMODE_NONINTERLACED;
1295 fbinfo->var.bits_per_pixel = windata->default_bpp;
1296 fbinfo->fbops = &s3c_fb_ops;
1297 fbinfo->flags = FBINFO_FLAG_DEFAULT;
1298 fbinfo->pseudo_palette = &win->pseudo_palette;
1300 /* prepare to actually start the framebuffer */
1302 ret = s3c_fb_check_var(&fbinfo->var, fbinfo);
1304 dev_err(sfb->dev, "check_var failed on initial video params\n");
1308 /* create initial colour map */
1310 ret = fb_alloc_cmap(&fbinfo->cmap, win->variant.palette_sz, 1);
1312 fb_set_cmap(&fbinfo->cmap, fbinfo);
1314 dev_err(sfb->dev, "failed to allocate fb cmap\n");
1316 s3c_fb_set_par(fbinfo);
1318 dev_dbg(sfb->dev, "about to register framebuffer\n");
1320 /* run the check_var and set_par on our configuration. */
1322 ret = register_framebuffer(fbinfo);
1324 dev_err(sfb->dev, "failed to register framebuffer\n");
1328 dev_info(sfb->dev, "window %d: fb %s\n", win_no, fbinfo->fix.id);
1334 * s3c_fb_clear_win() - clear hardware window registers.
1335 * @sfb: The base resources for the hardware.
1336 * @win: The window to process.
1338 * Reset the specific window registers to a known state.
1340 static void s3c_fb_clear_win(struct s3c_fb *sfb, int win)
1342 void __iomem *regs = sfb->regs;
1345 writel(0, regs + sfb->variant.wincon + (win * 4));
1346 writel(0, regs + VIDOSD_A(win, sfb->variant));
1347 writel(0, regs + VIDOSD_B(win, sfb->variant));
1348 writel(0, regs + VIDOSD_C(win, sfb->variant));
1349 reg = readl(regs + SHADOWCON);
1350 writel(reg & ~SHADOWCON_WINx_PROTECT(win), regs + SHADOWCON);
1353 static int __devinit s3c_fb_probe(struct platform_device *pdev)
1355 const struct platform_device_id *platid;
1356 struct s3c_fb_driverdata *fbdrv;
1357 struct device *dev = &pdev->dev;
1358 struct s3c_fb_platdata *pd;
1360 struct resource *res;
1365 platid = platform_get_device_id(pdev);
1366 fbdrv = (struct s3c_fb_driverdata *)platid->driver_data;
1368 if (fbdrv->variant.nr_windows > S3C_FB_MAX_WIN) {
1369 dev_err(dev, "too many windows, cannot attach\n");
1373 pd = pdev->dev.platform_data;
1375 dev_err(dev, "no platform data specified\n");
1379 sfb = devm_kzalloc(dev, sizeof(struct s3c_fb), GFP_KERNEL);
1381 dev_err(dev, "no memory for framebuffers\n");
1385 dev_dbg(dev, "allocate new framebuffer %p\n", sfb);
1389 sfb->variant = fbdrv->variant;
1391 spin_lock_init(&sfb->slock);
1393 sfb->bus_clk = clk_get(dev, "lcd");
1394 if (IS_ERR(sfb->bus_clk)) {
1395 dev_err(dev, "failed to get bus clock\n");
1396 ret = PTR_ERR(sfb->bus_clk);
1400 clk_enable(sfb->bus_clk);
1402 if (!sfb->variant.has_clksel) {
1403 sfb->lcd_clk = clk_get(dev, "sclk_fimd");
1404 if (IS_ERR(sfb->lcd_clk)) {
1405 dev_err(dev, "failed to get lcd clock\n");
1406 ret = PTR_ERR(sfb->lcd_clk);
1410 clk_enable(sfb->lcd_clk);
1413 pm_runtime_enable(sfb->dev);
1415 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1417 dev_err(dev, "failed to find registers\n");
1422 sfb->regs = devm_request_and_ioremap(dev, res);
1424 dev_err(dev, "failed to map registers\n");
1429 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1431 dev_err(dev, "failed to acquire irq resource\n");
1435 sfb->irq_no = res->start;
1436 ret = request_irq(sfb->irq_no, s3c_fb_irq,
1439 dev_err(dev, "irq request failed\n");
1443 dev_dbg(dev, "got resources (regs %p), probing windows\n", sfb->regs);
1445 platform_set_drvdata(pdev, sfb);
1446 pm_runtime_get_sync(sfb->dev);
1448 /* setup gpio and output polarity controls */
1452 writel(pd->vidcon1, sfb->regs + VIDCON1);
1454 /* set video clock running at under-run */
1455 if (sfb->variant.has_fixvclk) {
1456 reg = readl(sfb->regs + VIDCON1);
1457 reg &= ~VIDCON1_VCLK_MASK;
1458 reg |= VIDCON1_VCLK_RUN;
1459 writel(reg, sfb->regs + VIDCON1);
1462 /* zero all windows before we do anything */
1464 for (win = 0; win < fbdrv->variant.nr_windows; win++)
1465 s3c_fb_clear_win(sfb, win);
1467 /* initialise colour key controls */
1468 for (win = 0; win < (fbdrv->variant.nr_windows - 1); win++) {
1469 void __iomem *regs = sfb->regs + sfb->variant.keycon;
1472 writel(0xffffff, regs + WKEYCON0);
1473 writel(0xffffff, regs + WKEYCON1);
1476 /* we have the register setup, start allocating framebuffers */
1478 for (win = 0; win < fbdrv->variant.nr_windows; win++) {
1482 if (!pd->win[win]->win_mode.pixclock)
1483 s3c_fb_missing_pixclock(&pd->win[win]->win_mode);
1485 ret = s3c_fb_probe_win(sfb, win, fbdrv->win[win],
1486 &sfb->windows[win]);
1488 dev_err(dev, "failed to create window %d\n", win);
1489 for (; win >= 0; win--)
1490 s3c_fb_release_win(sfb, sfb->windows[win]);
1491 goto err_pm_runtime;
1495 platform_set_drvdata(pdev, sfb);
1496 pm_runtime_put_sync(sfb->dev);
1501 pm_runtime_put_sync(sfb->dev);
1502 free_irq(sfb->irq_no, sfb);
1505 pm_runtime_disable(sfb->dev);
1507 if (!sfb->variant.has_clksel) {
1508 clk_disable(sfb->lcd_clk);
1509 clk_put(sfb->lcd_clk);
1513 clk_disable(sfb->bus_clk);
1514 clk_put(sfb->bus_clk);
1521 * s3c_fb_remove() - Cleanup on module finalisation
1522 * @pdev: The platform device we are bound to.
1524 * Shutdown and then release all the resources that the driver allocated
1525 * on initialisation.
1527 static int __devexit s3c_fb_remove(struct platform_device *pdev)
1529 struct s3c_fb *sfb = platform_get_drvdata(pdev);
1532 pm_runtime_get_sync(sfb->dev);
1534 for (win = 0; win < S3C_FB_MAX_WIN; win++)
1535 if (sfb->windows[win])
1536 s3c_fb_release_win(sfb, sfb->windows[win]);
1538 free_irq(sfb->irq_no, sfb);
1540 if (!sfb->variant.has_clksel) {
1541 clk_disable(sfb->lcd_clk);
1542 clk_put(sfb->lcd_clk);
1545 clk_disable(sfb->bus_clk);
1546 clk_put(sfb->bus_clk);
1548 pm_runtime_put_sync(sfb->dev);
1549 pm_runtime_disable(sfb->dev);
1554 #ifdef CONFIG_PM_SLEEP
1555 static int s3c_fb_suspend(struct device *dev)
1557 struct platform_device *pdev = to_platform_device(dev);
1558 struct s3c_fb *sfb = platform_get_drvdata(pdev);
1559 struct s3c_fb_win *win;
1562 for (win_no = S3C_FB_MAX_WIN - 1; win_no >= 0; win_no--) {
1563 win = sfb->windows[win_no];
1567 /* use the blank function to push into power-down */
1568 s3c_fb_blank(FB_BLANK_POWERDOWN, win->fbinfo);
1571 if (!sfb->variant.has_clksel)
1572 clk_disable(sfb->lcd_clk);
1574 clk_disable(sfb->bus_clk);
1578 static int s3c_fb_resume(struct device *dev)
1580 struct platform_device *pdev = to_platform_device(dev);
1581 struct s3c_fb *sfb = platform_get_drvdata(pdev);
1582 struct s3c_fb_platdata *pd = sfb->pdata;
1583 struct s3c_fb_win *win;
1587 clk_enable(sfb->bus_clk);
1589 if (!sfb->variant.has_clksel)
1590 clk_enable(sfb->lcd_clk);
1592 /* setup gpio and output polarity controls */
1594 writel(pd->vidcon1, sfb->regs + VIDCON1);
1596 /* set video clock running at under-run */
1597 if (sfb->variant.has_fixvclk) {
1598 reg = readl(sfb->regs + VIDCON1);
1599 reg &= ~VIDCON1_VCLK_MASK;
1600 reg |= VIDCON1_VCLK_RUN;
1601 writel(reg, sfb->regs + VIDCON1);
1604 /* zero all windows before we do anything */
1605 for (win_no = 0; win_no < sfb->variant.nr_windows; win_no++)
1606 s3c_fb_clear_win(sfb, win_no);
1608 for (win_no = 0; win_no < sfb->variant.nr_windows - 1; win_no++) {
1609 void __iomem *regs = sfb->regs + sfb->variant.keycon;
1610 win = sfb->windows[win_no];
1614 shadow_protect_win(win, 1);
1615 regs += (win_no * 8);
1616 writel(0xffffff, regs + WKEYCON0);
1617 writel(0xffffff, regs + WKEYCON1);
1618 shadow_protect_win(win, 0);
1621 /* restore framebuffers */
1622 for (win_no = 0; win_no < S3C_FB_MAX_WIN; win_no++) {
1623 win = sfb->windows[win_no];
1627 dev_dbg(&pdev->dev, "resuming window %d\n", win_no);
1628 s3c_fb_set_par(win->fbinfo);
1635 #ifdef CONFIG_PM_RUNTIME
1636 static int s3c_fb_runtime_suspend(struct device *dev)
1638 struct platform_device *pdev = to_platform_device(dev);
1639 struct s3c_fb *sfb = platform_get_drvdata(pdev);
1641 if (!sfb->variant.has_clksel)
1642 clk_disable(sfb->lcd_clk);
1644 clk_disable(sfb->bus_clk);
1649 static int s3c_fb_runtime_resume(struct device *dev)
1651 struct platform_device *pdev = to_platform_device(dev);
1652 struct s3c_fb *sfb = platform_get_drvdata(pdev);
1653 struct s3c_fb_platdata *pd = sfb->pdata;
1655 clk_enable(sfb->bus_clk);
1657 if (!sfb->variant.has_clksel)
1658 clk_enable(sfb->lcd_clk);
1660 /* setup gpio and output polarity controls */
1662 writel(pd->vidcon1, sfb->regs + VIDCON1);
1668 #define VALID_BPP124 (VALID_BPP(1) | VALID_BPP(2) | VALID_BPP(4))
1669 #define VALID_BPP1248 (VALID_BPP124 | VALID_BPP(8))
1671 static struct s3c_fb_win_variant s3c_fb_data_64xx_wins[] = {
1674 .osd_size_off = 0x8,
1676 .valid_bpp = (VALID_BPP1248 | VALID_BPP(16) |
1677 VALID_BPP(18) | VALID_BPP(24)),
1682 .osd_size_off = 0xc,
1685 .valid_bpp = (VALID_BPP1248 | VALID_BPP(16) |
1686 VALID_BPP(18) | VALID_BPP(19) |
1687 VALID_BPP(24) | VALID_BPP(25) |
1693 .osd_size_off = 0xc,
1697 .valid_bpp = (VALID_BPP1248 | VALID_BPP(16) |
1698 VALID_BPP(18) | VALID_BPP(19) |
1699 VALID_BPP(24) | VALID_BPP(25) |
1707 .valid_bpp = (VALID_BPP124 | VALID_BPP(16) |
1708 VALID_BPP(18) | VALID_BPP(19) |
1709 VALID_BPP(24) | VALID_BPP(25) |
1717 .valid_bpp = (VALID_BPP(1) | VALID_BPP(2) |
1718 VALID_BPP(16) | VALID_BPP(18) |
1719 VALID_BPP(19) | VALID_BPP(24) |
1720 VALID_BPP(25) | VALID_BPP(28)),
1724 static struct s3c_fb_win_variant s3c_fb_data_s5p_wins[] = {
1727 .osd_size_off = 0x8,
1729 .valid_bpp = (VALID_BPP1248 | VALID_BPP(13) |
1730 VALID_BPP(15) | VALID_BPP(16) |
1731 VALID_BPP(18) | VALID_BPP(19) |
1732 VALID_BPP(24) | VALID_BPP(25) |
1738 .osd_size_off = 0xc,
1741 .valid_bpp = (VALID_BPP1248 | VALID_BPP(13) |
1742 VALID_BPP(15) | VALID_BPP(16) |
1743 VALID_BPP(18) | VALID_BPP(19) |
1744 VALID_BPP(24) | VALID_BPP(25) |
1750 .osd_size_off = 0xc,
1753 .valid_bpp = (VALID_BPP1248 | VALID_BPP(13) |
1754 VALID_BPP(15) | VALID_BPP(16) |
1755 VALID_BPP(18) | VALID_BPP(19) |
1756 VALID_BPP(24) | VALID_BPP(25) |
1763 .valid_bpp = (VALID_BPP1248 | VALID_BPP(13) |
1764 VALID_BPP(15) | VALID_BPP(16) |
1765 VALID_BPP(18) | VALID_BPP(19) |
1766 VALID_BPP(24) | VALID_BPP(25) |
1773 .valid_bpp = (VALID_BPP1248 | VALID_BPP(13) |
1774 VALID_BPP(15) | VALID_BPP(16) |
1775 VALID_BPP(18) | VALID_BPP(19) |
1776 VALID_BPP(24) | VALID_BPP(25) |
1781 static struct s3c_fb_driverdata s3c_fb_data_64xx = {
1784 .vidtcon = VIDTCON0,
1785 .wincon = WINCON(0),
1786 .winmap = WINxMAP(0),
1790 .buf_start = VIDW_BUF_START(0),
1791 .buf_size = VIDW_BUF_SIZE(0),
1792 .buf_end = VIDW_BUF_END(0),
1805 .win[0] = &s3c_fb_data_64xx_wins[0],
1806 .win[1] = &s3c_fb_data_64xx_wins[1],
1807 .win[2] = &s3c_fb_data_64xx_wins[2],
1808 .win[3] = &s3c_fb_data_64xx_wins[3],
1809 .win[4] = &s3c_fb_data_64xx_wins[4],
1812 static struct s3c_fb_driverdata s3c_fb_data_s5pc100 = {
1815 .vidtcon = VIDTCON0,
1816 .wincon = WINCON(0),
1817 .winmap = WINxMAP(0),
1821 .buf_start = VIDW_BUF_START(0),
1822 .buf_size = VIDW_BUF_SIZE(0),
1823 .buf_end = VIDW_BUF_END(0),
1837 .win[0] = &s3c_fb_data_s5p_wins[0],
1838 .win[1] = &s3c_fb_data_s5p_wins[1],
1839 .win[2] = &s3c_fb_data_s5p_wins[2],
1840 .win[3] = &s3c_fb_data_s5p_wins[3],
1841 .win[4] = &s3c_fb_data_s5p_wins[4],
1844 static struct s3c_fb_driverdata s3c_fb_data_s5pv210 = {
1847 .vidtcon = VIDTCON0,
1848 .wincon = WINCON(0),
1849 .winmap = WINxMAP(0),
1853 .buf_start = VIDW_BUF_START(0),
1854 .buf_size = VIDW_BUF_SIZE(0),
1855 .buf_end = VIDW_BUF_END(0),
1870 .win[0] = &s3c_fb_data_s5p_wins[0],
1871 .win[1] = &s3c_fb_data_s5p_wins[1],
1872 .win[2] = &s3c_fb_data_s5p_wins[2],
1873 .win[3] = &s3c_fb_data_s5p_wins[3],
1874 .win[4] = &s3c_fb_data_s5p_wins[4],
1877 static struct s3c_fb_driverdata s3c_fb_data_exynos4 = {
1880 .vidtcon = VIDTCON0,
1881 .wincon = WINCON(0),
1882 .winmap = WINxMAP(0),
1886 .buf_start = VIDW_BUF_START(0),
1887 .buf_size = VIDW_BUF_SIZE(0),
1888 .buf_end = VIDW_BUF_END(0),
1902 .win[0] = &s3c_fb_data_s5p_wins[0],
1903 .win[1] = &s3c_fb_data_s5p_wins[1],
1904 .win[2] = &s3c_fb_data_s5p_wins[2],
1905 .win[3] = &s3c_fb_data_s5p_wins[3],
1906 .win[4] = &s3c_fb_data_s5p_wins[4],
1909 /* S3C2443/S3C2416 style hardware */
1910 static struct s3c_fb_driverdata s3c_fb_data_s3c2443 = {
1931 .win[0] = &(struct s3c_fb_win_variant) {
1933 .valid_bpp = VALID_BPP1248 | VALID_BPP(16) | VALID_BPP(24),
1935 .win[1] = &(struct s3c_fb_win_variant) {
1939 .valid_bpp = (VALID_BPP1248 | VALID_BPP(16) |
1940 VALID_BPP(18) | VALID_BPP(19) |
1941 VALID_BPP(24) | VALID_BPP(25) |
1946 static struct s3c_fb_driverdata s3c_fb_data_s5p64x0 = {
1949 .vidtcon = VIDTCON0,
1950 .wincon = WINCON(0),
1951 .winmap = WINxMAP(0),
1955 .buf_start = VIDW_BUF_START(0),
1956 .buf_size = VIDW_BUF_SIZE(0),
1957 .buf_end = VIDW_BUF_END(0),
1968 .win[0] = &s3c_fb_data_s5p_wins[0],
1969 .win[1] = &s3c_fb_data_s5p_wins[1],
1970 .win[2] = &s3c_fb_data_s5p_wins[2],
1973 static struct platform_device_id s3c_fb_driver_ids[] = {
1976 .driver_data = (unsigned long)&s3c_fb_data_64xx,
1978 .name = "s5pc100-fb",
1979 .driver_data = (unsigned long)&s3c_fb_data_s5pc100,
1981 .name = "s5pv210-fb",
1982 .driver_data = (unsigned long)&s3c_fb_data_s5pv210,
1984 .name = "exynos4-fb",
1985 .driver_data = (unsigned long)&s3c_fb_data_exynos4,
1987 .name = "s3c2443-fb",
1988 .driver_data = (unsigned long)&s3c_fb_data_s3c2443,
1990 .name = "s5p64x0-fb",
1991 .driver_data = (unsigned long)&s3c_fb_data_s5p64x0,
1995 MODULE_DEVICE_TABLE(platform, s3c_fb_driver_ids);
1997 static const struct dev_pm_ops s3cfb_pm_ops = {
1998 SET_SYSTEM_SLEEP_PM_OPS(s3c_fb_suspend, s3c_fb_resume)
1999 SET_RUNTIME_PM_OPS(s3c_fb_runtime_suspend, s3c_fb_runtime_resume,
2003 static struct platform_driver s3c_fb_driver = {
2004 .probe = s3c_fb_probe,
2005 .remove = __devexit_p(s3c_fb_remove),
2006 .id_table = s3c_fb_driver_ids,
2009 .owner = THIS_MODULE,
2010 .pm = &s3cfb_pm_ops,
2014 module_platform_driver(s3c_fb_driver);
2016 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
2017 MODULE_DESCRIPTION("Samsung S3C SoC Framebuffer driver");
2018 MODULE_LICENSE("GPL");
2019 MODULE_ALIAS("platform:s3c-fb");