2 * linux/drivers/video/s3fb.c -- Frame buffer device driver for S3 Trio/Virge
4 * Copyright (c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org>
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive for
10 * Code is based on David Boucher's viafb (http://davesdomain.org.uk/viafb/)
11 * which is based on the code of neofb.
14 #include <linux/version.h>
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/errno.h>
18 #include <linux/string.h>
20 #include <linux/tty.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
24 #include <linux/svga.h>
25 #include <linux/init.h>
26 #include <linux/pci.h>
27 #include <linux/console.h> /* Why should fb driver call console functions? because acquire_console_sem() */
28 #include <video/vga.h>
35 int chip, rev, mclk_freq;
37 struct vgastate state;
38 struct mutex open_lock;
39 unsigned int ref_count;
40 u32 pseudo_palette[16];
44 /* ------------------------------------------------------------------------- */
46 static const struct svga_fb_format s3fb_formats[] = {
47 { 0, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
48 FB_TYPE_TEXT, FB_AUX_TEXT_SVGA_STEP4, FB_VISUAL_PSEUDOCOLOR, 8, 16},
49 { 4, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
50 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 8, 16},
51 { 4, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 1,
52 FB_TYPE_INTERLEAVED_PLANES, 1, FB_VISUAL_PSEUDOCOLOR, 8, 16},
53 { 8, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
54 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 4, 8},
55 {16, {10, 5, 0}, {5, 5, 0}, {0, 5, 0}, {0, 0, 0}, 0,
56 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 4},
57 {16, {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0}, 0,
58 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 4},
59 {24, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
60 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 1, 2},
61 {32, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
62 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 1, 2},
67 static const struct svga_pll s3_pll = {3, 129, 3, 33, 0, 3,
68 35000, 240000, 14318};
70 static const int s3_memsizes[] = {4096, 0, 3072, 8192, 2048, 6144, 1024, 512};
72 static const char * const s3_names[] = {"S3 Unknown", "S3 Trio32", "S3 Trio64", "S3 Trio64V+",
73 "S3 Trio64UV+", "S3 Trio64V2/DX", "S3 Trio64V2/GX",
74 "S3 Plato/PX", "S3 Aurora64VP", "S3 Virge",
75 "S3 Virge/VX", "S3 Virge/DX", "S3 Virge/GX",
76 "S3 Virge/GX2", "S3 Virge/GX2P", "S3 Virge/GX2P"};
78 #define CHIP_UNKNOWN 0x00
79 #define CHIP_732_TRIO32 0x01
80 #define CHIP_764_TRIO64 0x02
81 #define CHIP_765_TRIO64VP 0x03
82 #define CHIP_767_TRIO64UVP 0x04
83 #define CHIP_775_TRIO64V2_DX 0x05
84 #define CHIP_785_TRIO64V2_GX 0x06
85 #define CHIP_551_PLATO_PX 0x07
86 #define CHIP_M65_AURORA64VP 0x08
87 #define CHIP_325_VIRGE 0x09
88 #define CHIP_988_VIRGE_VX 0x0A
89 #define CHIP_375_VIRGE_DX 0x0B
90 #define CHIP_385_VIRGE_GX 0x0C
91 #define CHIP_356_VIRGE_GX2 0x0D
92 #define CHIP_357_VIRGE_GX2P 0x0E
93 #define CHIP_359_VIRGE_GX2P 0x0F
95 #define CHIP_XXX_TRIO 0x80
96 #define CHIP_XXX_TRIO64V2_DXGX 0x81
97 #define CHIP_XXX_VIRGE_DXGX 0x82
99 #define CHIP_UNDECIDED_FLAG 0x80
100 #define CHIP_MASK 0xFF
102 /* CRT timing register sets */
104 static const struct vga_regset s3_h_total_regs[] = {{0x00, 0, 7}, {0x5D, 0, 0}, VGA_REGSET_END};
105 static const struct vga_regset s3_h_display_regs[] = {{0x01, 0, 7}, {0x5D, 1, 1}, VGA_REGSET_END};
106 static const struct vga_regset s3_h_blank_start_regs[] = {{0x02, 0, 7}, {0x5D, 2, 2}, VGA_REGSET_END};
107 static const struct vga_regset s3_h_blank_end_regs[] = {{0x03, 0, 4}, {0x05, 7, 7}, VGA_REGSET_END};
108 static const struct vga_regset s3_h_sync_start_regs[] = {{0x04, 0, 7}, {0x5D, 4, 4}, VGA_REGSET_END};
109 static const struct vga_regset s3_h_sync_end_regs[] = {{0x05, 0, 4}, VGA_REGSET_END};
111 static const struct vga_regset s3_v_total_regs[] = {{0x06, 0, 7}, {0x07, 0, 0}, {0x07, 5, 5}, {0x5E, 0, 0}, VGA_REGSET_END};
112 static const struct vga_regset s3_v_display_regs[] = {{0x12, 0, 7}, {0x07, 1, 1}, {0x07, 6, 6}, {0x5E, 1, 1}, VGA_REGSET_END};
113 static const struct vga_regset s3_v_blank_start_regs[] = {{0x15, 0, 7}, {0x07, 3, 3}, {0x09, 5, 5}, {0x5E, 2, 2}, VGA_REGSET_END};
114 static const struct vga_regset s3_v_blank_end_regs[] = {{0x16, 0, 7}, VGA_REGSET_END};
115 static const struct vga_regset s3_v_sync_start_regs[] = {{0x10, 0, 7}, {0x07, 2, 2}, {0x07, 7, 7}, {0x5E, 4, 4}, VGA_REGSET_END};
116 static const struct vga_regset s3_v_sync_end_regs[] = {{0x11, 0, 3}, VGA_REGSET_END};
118 static const struct vga_regset s3_line_compare_regs[] = {{0x18, 0, 7}, {0x07, 4, 4}, {0x09, 6, 6}, {0x5E, 6, 6}, VGA_REGSET_END};
119 static const struct vga_regset s3_start_address_regs[] = {{0x0d, 0, 7}, {0x0c, 0, 7}, {0x31, 4, 5}, {0x51, 0, 1}, VGA_REGSET_END};
120 static const struct vga_regset s3_offset_regs[] = {{0x13, 0, 7}, {0x51, 4, 5}, VGA_REGSET_END}; /* set 0x43 bit 2 to 0 */
122 static const struct svga_timing_regs s3_timing_regs = {
123 s3_h_total_regs, s3_h_display_regs, s3_h_blank_start_regs,
124 s3_h_blank_end_regs, s3_h_sync_start_regs, s3_h_sync_end_regs,
125 s3_v_total_regs, s3_v_display_regs, s3_v_blank_start_regs,
126 s3_v_blank_end_regs, s3_v_sync_start_regs, s3_v_sync_end_regs,
130 /* ------------------------------------------------------------------------- */
132 /* Module parameters */
135 static char *mode = "640x480-8@60";
141 static int fasttext = 1;
144 MODULE_AUTHOR("(c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org>");
145 MODULE_LICENSE("GPL");
146 MODULE_DESCRIPTION("fbdev driver for S3 Trio/Virge");
148 module_param(mode, charp, 0444);
149 MODULE_PARM_DESC(mode, "Default video mode ('640x480-8@60', etc)");
152 module_param(mtrr, int, 0444);
153 MODULE_PARM_DESC(mtrr, "Enable write-combining with MTRR (1=enable, 0=disable, default=1)");
156 module_param(fasttext, int, 0644);
157 MODULE_PARM_DESC(fasttext, "Enable S3 fast text mode (1=enable, 0=disable, default=1)");
160 /* ------------------------------------------------------------------------- */
162 /* Set font in S3 fast text mode */
164 static void s3fb_settile_fast(struct fb_info *info, struct fb_tilemap *map)
166 const u8 *font = map->data;
167 u8 __iomem *fb = (u8 __iomem *) info->screen_base;
170 if ((map->width != 8) || (map->height != 16) ||
171 (map->depth != 1) || (map->length != 256)) {
172 printk(KERN_ERR "fb%d: unsupported font parameters: width %d, height %d, depth %d, length %d\n",
173 info->node, map->width, map->height, map->depth, map->length);
178 for (i = 0; i < map->height; i++) {
179 for (c = 0; c < map->length; c++) {
180 fb_writeb(font[c * map->height + i], fb + c * 4);
186 static int s3fb_get_tilemax(struct fb_info *info)
191 static struct fb_tile_ops s3fb_tile_ops = {
192 .fb_settile = svga_settile,
193 .fb_tilecopy = svga_tilecopy,
194 .fb_tilefill = svga_tilefill,
195 .fb_tileblit = svga_tileblit,
196 .fb_tilecursor = svga_tilecursor,
197 .fb_get_tilemax = s3fb_get_tilemax,
200 static struct fb_tile_ops s3fb_fast_tile_ops = {
201 .fb_settile = s3fb_settile_fast,
202 .fb_tilecopy = svga_tilecopy,
203 .fb_tilefill = svga_tilefill,
204 .fb_tileblit = svga_tileblit,
205 .fb_tilecursor = svga_tilecursor,
206 .fb_get_tilemax = s3fb_get_tilemax,
210 /* ------------------------------------------------------------------------- */
212 /* image data is MSB-first, fb structure is MSB-first too */
213 static inline u32 expand_color(u32 c)
215 return ((c & 1) | ((c & 2) << 7) | ((c & 4) << 14) | ((c & 8) << 21)) * 0xFF;
218 /* s3fb_iplan_imageblit silently assumes that almost everything is 8-pixel aligned */
219 static void s3fb_iplan_imageblit(struct fb_info *info, const struct fb_image *image)
221 u32 fg = expand_color(image->fg_color);
222 u32 bg = expand_color(image->bg_color);
223 const u8 *src1, *src;
230 dst1 = info->screen_base + (image->dy * info->fix.line_length)
231 + ((image->dx / 8) * 4);
233 for (y = 0; y < image->height; y++) {
235 dst = (u32 __iomem *) dst1;
236 for (x = 0; x < image->width; x += 8) {
237 val = *(src++) * 0x01010101;
238 val = (val & fg) | (~val & bg);
239 fb_writel(val, dst++);
241 src1 += image->width / 8;
242 dst1 += info->fix.line_length;
247 /* s3fb_iplan_fillrect silently assumes that almost everything is 8-pixel aligned */
248 static void s3fb_iplan_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
250 u32 fg = expand_color(rect->color);
255 dst1 = info->screen_base + (rect->dy * info->fix.line_length)
256 + ((rect->dx / 8) * 4);
258 for (y = 0; y < rect->height; y++) {
259 dst = (u32 __iomem *) dst1;
260 for (x = 0; x < rect->width; x += 8) {
261 fb_writel(fg, dst++);
263 dst1 += info->fix.line_length;
268 /* image data is MSB-first, fb structure is high-nibble-in-low-byte-first */
269 static inline u32 expand_pixel(u32 c)
271 return (((c & 1) << 24) | ((c & 2) << 27) | ((c & 4) << 14) | ((c & 8) << 17) |
272 ((c & 16) << 4) | ((c & 32) << 7) | ((c & 64) >> 6) | ((c & 128) >> 3)) * 0xF;
275 /* s3fb_cfb4_imageblit silently assumes that almost everything is 8-pixel aligned */
276 static void s3fb_cfb4_imageblit(struct fb_info *info, const struct fb_image *image)
278 u32 fg = image->fg_color * 0x11111111;
279 u32 bg = image->bg_color * 0x11111111;
280 const u8 *src1, *src;
287 dst1 = info->screen_base + (image->dy * info->fix.line_length)
288 + ((image->dx / 8) * 4);
290 for (y = 0; y < image->height; y++) {
292 dst = (u32 __iomem *) dst1;
293 for (x = 0; x < image->width; x += 8) {
294 val = expand_pixel(*(src++));
295 val = (val & fg) | (~val & bg);
296 fb_writel(val, dst++);
298 src1 += image->width / 8;
299 dst1 += info->fix.line_length;
303 static void s3fb_imageblit(struct fb_info *info, const struct fb_image *image)
305 if ((info->var.bits_per_pixel == 4) && (image->depth == 1)
306 && ((image->width % 8) == 0) && ((image->dx % 8) == 0)) {
307 if (info->fix.type == FB_TYPE_INTERLEAVED_PLANES)
308 s3fb_iplan_imageblit(info, image);
310 s3fb_cfb4_imageblit(info, image);
312 cfb_imageblit(info, image);
315 static void s3fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
317 if ((info->var.bits_per_pixel == 4)
318 && ((rect->width % 8) == 0) && ((rect->dx % 8) == 0)
319 && (info->fix.type == FB_TYPE_INTERLEAVED_PLANES))
320 s3fb_iplan_fillrect(info, rect);
322 cfb_fillrect(info, rect);
327 /* ------------------------------------------------------------------------- */
330 static void s3_set_pixclock(struct fb_info *info, u32 pixclock)
336 rv = svga_compute_pll(&s3_pll, 1000000000 / pixclock, &m, &n, &r, info->node);
338 printk(KERN_ERR "fb%d: cannot set requested pixclock, keeping old value\n", info->node);
342 /* Set VGA misc register */
343 regval = vga_r(NULL, VGA_MIS_R);
344 vga_w(NULL, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD);
346 /* Set S3 clock registers */
347 vga_wseq(NULL, 0x12, ((n - 2) | (r << 5)));
348 vga_wseq(NULL, 0x13, m - 2);
352 /* Activate clock - write 0, 1, 0 to seq/15 bit 5 */
353 regval = vga_rseq (NULL, 0x15); /* | 0x80; */
354 vga_wseq(NULL, 0x15, regval & ~(1<<5));
355 vga_wseq(NULL, 0x15, regval | (1<<5));
356 vga_wseq(NULL, 0x15, regval & ~(1<<5));
360 /* Open framebuffer */
362 static int s3fb_open(struct fb_info *info, int user)
364 struct s3fb_info *par = info->par;
366 mutex_lock(&(par->open_lock));
367 if (par->ref_count == 0) {
368 memset(&(par->state), 0, sizeof(struct vgastate));
369 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP;
370 par->state.num_crtc = 0x70;
371 par->state.num_seq = 0x20;
372 save_vga(&(par->state));
376 mutex_unlock(&(par->open_lock));
381 /* Close framebuffer */
383 static int s3fb_release(struct fb_info *info, int user)
385 struct s3fb_info *par = info->par;
387 mutex_lock(&(par->open_lock));
388 if (par->ref_count == 0) {
389 mutex_unlock(&(par->open_lock));
393 if (par->ref_count == 1)
394 restore_vga(&(par->state));
397 mutex_unlock(&(par->open_lock));
402 /* Validate passed in var */
404 static int s3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
406 struct s3fb_info *par = info->par;
409 /* Find appropriate format */
410 rv = svga_match_format (s3fb_formats, var, NULL);
411 if ((rv < 0) || ((par->chip == CHIP_988_VIRGE_VX) ? (rv == 7) : (rv == 6)))
412 { /* 24bpp on VIRGE VX, 32bpp on others */
413 printk(KERN_ERR "fb%d: unsupported mode requested\n", info->node);
417 /* Do not allow to have real resoulution larger than virtual */
418 if (var->xres > var->xres_virtual)
419 var->xres_virtual = var->xres;
421 if (var->yres > var->yres_virtual)
422 var->yres_virtual = var->yres;
424 /* Round up xres_virtual to have proper alignment of lines */
425 step = s3fb_formats[rv].xresstep - 1;
426 var->xres_virtual = (var->xres_virtual+step) & ~step;
428 /* Check whether have enough memory */
429 mem = ((var->bits_per_pixel * var->xres_virtual) >> 3) * var->yres_virtual;
430 if (mem > info->screen_size)
432 printk(KERN_ERR "fb%d: not enough framebuffer memory (%d kB requested , %d kB available)\n",
433 info->node, mem >> 10, (unsigned int) (info->screen_size >> 10));
437 rv = svga_check_timings (&s3_timing_regs, var, info->node);
440 printk(KERN_ERR "fb%d: invalid timings requested\n", info->node);
447 /* Set video mode from par */
449 static int s3fb_set_par(struct fb_info *info)
451 struct s3fb_info *par = info->par;
452 u32 value, mode, hmul, offset_value, screen_size, multiplex;
453 u32 bpp = info->var.bits_per_pixel;
456 info->fix.ypanstep = 1;
457 info->fix.line_length = (info->var.xres_virtual * bpp) / 8;
459 info->flags &= ~FBINFO_MISC_TILEBLITTING;
460 info->tileops = NULL;
462 /* supports blit rectangles of any dimension */
463 info->pixmap.blit_x = ~(u32)0;
464 info->pixmap.blit_y = ~(u32)0;
465 offset_value = (info->var.xres_virtual * bpp) / 64;
466 screen_size = info->var.yres_virtual * info->fix.line_length;
468 info->fix.ypanstep = 16;
469 info->fix.line_length = 0;
471 info->flags |= FBINFO_MISC_TILEBLITTING;
472 info->tileops = fasttext ? &s3fb_fast_tile_ops : &s3fb_tile_ops;
473 /* supports 8x16 tiles only */
474 info->pixmap.blit_x = 1 << (8 - 1);
475 info->pixmap.blit_y = 1 << (16 - 1);
477 offset_value = info->var.xres_virtual / 16;
478 screen_size = (info->var.xres_virtual * info->var.yres_virtual) / 64;
481 info->var.xoffset = 0;
482 info->var.yoffset = 0;
483 info->var.activate = FB_ACTIVATE_NOW;
485 /* Unlock registers */
486 vga_wcrt(NULL, 0x38, 0x48);
487 vga_wcrt(NULL, 0x39, 0xA5);
488 vga_wseq(NULL, 0x08, 0x06);
489 svga_wcrt_mask(0x11, 0x00, 0x80);
491 /* Blank screen and turn off sync */
492 svga_wseq_mask(0x01, 0x20, 0x20);
493 svga_wcrt_mask(0x17, 0x00, 0x80);
495 /* Set default values */
496 svga_set_default_gfx_regs();
497 svga_set_default_atc_regs();
498 svga_set_default_seq_regs();
499 svga_set_default_crt_regs();
500 svga_wcrt_multi(s3_line_compare_regs, 0xFFFFFFFF);
501 svga_wcrt_multi(s3_start_address_regs, 0);
503 /* S3 specific initialization */
504 svga_wcrt_mask(0x58, 0x10, 0x10); /* enable linear framebuffer */
505 svga_wcrt_mask(0x31, 0x08, 0x08); /* enable sequencer access to framebuffer above 256 kB */
507 /* svga_wcrt_mask(0x33, 0x08, 0x08); */ /* DDR ? */
508 /* svga_wcrt_mask(0x43, 0x01, 0x01); */ /* DDR ? */
509 svga_wcrt_mask(0x33, 0x00, 0x08); /* no DDR ? */
510 svga_wcrt_mask(0x43, 0x00, 0x01); /* no DDR ? */
512 svga_wcrt_mask(0x5D, 0x00, 0x28); // Clear strange HSlen bits
514 /* svga_wcrt_mask(0x58, 0x03, 0x03); */
516 /* svga_wcrt_mask(0x53, 0x12, 0x13); */ /* enable MMIO */
517 /* svga_wcrt_mask(0x40, 0x08, 0x08); */ /* enable write buffer */
520 /* Set the offset register */
521 pr_debug("fb%d: offset register : %d\n", info->node, offset_value);
522 svga_wcrt_multi(s3_offset_regs, offset_value);
524 vga_wcrt(NULL, 0x54, 0x18); /* M parameter */
525 vga_wcrt(NULL, 0x60, 0xff); /* N parameter */
526 vga_wcrt(NULL, 0x61, 0xff); /* L parameter */
527 vga_wcrt(NULL, 0x62, 0xff); /* L parameter */
529 vga_wcrt(NULL, 0x3A, 0x35);
530 svga_wattr(0x33, 0x00);
532 if (info->var.vmode & FB_VMODE_DOUBLE)
533 svga_wcrt_mask(0x09, 0x80, 0x80);
535 svga_wcrt_mask(0x09, 0x00, 0x80);
537 if (info->var.vmode & FB_VMODE_INTERLACED)
538 svga_wcrt_mask(0x42, 0x20, 0x20);
540 svga_wcrt_mask(0x42, 0x00, 0x20);
542 /* Disable hardware graphics cursor */
543 svga_wcrt_mask(0x45, 0x00, 0x01);
544 /* Disable Streams engine */
545 svga_wcrt_mask(0x67, 0x00, 0x0C);
547 mode = svga_match_format(s3fb_formats, &(info->var), &(info->fix));
549 /* S3 virge DX hack */
550 if (par->chip == CHIP_375_VIRGE_DX) {
551 vga_wcrt(NULL, 0x86, 0x80);
552 vga_wcrt(NULL, 0x90, 0x00);
555 /* S3 virge VX hack */
556 if (par->chip == CHIP_988_VIRGE_VX) {
557 vga_wcrt(NULL, 0x50, 0x00);
558 vga_wcrt(NULL, 0x67, 0x50);
560 vga_wcrt(NULL, 0x63, (mode <= 2) ? 0x90 : 0x09);
561 vga_wcrt(NULL, 0x66, 0x90);
564 svga_wcrt_mask(0x31, 0x00, 0x40);
568 /* Set mode-specific register values */
571 pr_debug("fb%d: text mode\n", info->node);
572 svga_set_textmode_vga_regs();
574 /* Set additional registers like in 8-bit mode */
575 svga_wcrt_mask(0x50, 0x00, 0x30);
576 svga_wcrt_mask(0x67, 0x00, 0xF0);
578 /* Disable enhanced mode */
579 svga_wcrt_mask(0x3A, 0x00, 0x30);
582 pr_debug("fb%d: high speed text mode set\n", info->node);
583 svga_wcrt_mask(0x31, 0x40, 0x40);
587 pr_debug("fb%d: 4 bit pseudocolor\n", info->node);
588 vga_wgfx(NULL, VGA_GFX_MODE, 0x40);
590 /* Set additional registers like in 8-bit mode */
591 svga_wcrt_mask(0x50, 0x00, 0x30);
592 svga_wcrt_mask(0x67, 0x00, 0xF0);
594 /* disable enhanced mode */
595 svga_wcrt_mask(0x3A, 0x00, 0x30);
598 pr_debug("fb%d: 4 bit pseudocolor, planar\n", info->node);
600 /* Set additional registers like in 8-bit mode */
601 svga_wcrt_mask(0x50, 0x00, 0x30);
602 svga_wcrt_mask(0x67, 0x00, 0xF0);
604 /* disable enhanced mode */
605 svga_wcrt_mask(0x3A, 0x00, 0x30);
608 pr_debug("fb%d: 8 bit pseudocolor\n", info->node);
609 if (info->var.pixclock > 20000) {
610 svga_wcrt_mask(0x50, 0x00, 0x30);
611 svga_wcrt_mask(0x67, 0x00, 0xF0);
613 svga_wcrt_mask(0x50, 0x00, 0x30);
614 svga_wcrt_mask(0x67, 0x10, 0xF0);
619 pr_debug("fb%d: 5/5/5 truecolor\n", info->node);
620 if (par->chip == CHIP_988_VIRGE_VX) {
621 if (info->var.pixclock > 20000)
622 svga_wcrt_mask(0x67, 0x20, 0xF0);
624 svga_wcrt_mask(0x67, 0x30, 0xF0);
626 svga_wcrt_mask(0x50, 0x10, 0x30);
627 svga_wcrt_mask(0x67, 0x30, 0xF0);
632 pr_debug("fb%d: 5/6/5 truecolor\n", info->node);
633 if (par->chip == CHIP_988_VIRGE_VX) {
634 if (info->var.pixclock > 20000)
635 svga_wcrt_mask(0x67, 0x40, 0xF0);
637 svga_wcrt_mask(0x67, 0x50, 0xF0);
639 svga_wcrt_mask(0x50, 0x10, 0x30);
640 svga_wcrt_mask(0x67, 0x50, 0xF0);
646 pr_debug("fb%d: 8/8/8 truecolor\n", info->node);
647 svga_wcrt_mask(0x67, 0xD0, 0xF0);
650 pr_debug("fb%d: 8/8/8/8 truecolor\n", info->node);
651 svga_wcrt_mask(0x50, 0x30, 0x30);
652 svga_wcrt_mask(0x67, 0xD0, 0xF0);
655 printk(KERN_ERR "fb%d: unsupported mode - bug\n", info->node);
659 if (par->chip != CHIP_988_VIRGE_VX) {
660 svga_wseq_mask(0x15, multiplex ? 0x10 : 0x00, 0x10);
661 svga_wseq_mask(0x18, multiplex ? 0x80 : 0x00, 0x80);
664 s3_set_pixclock(info, info->var.pixclock);
665 svga_set_timings(&s3_timing_regs, &(info->var), hmul, 1,
666 (info->var.vmode & FB_VMODE_DOUBLE) ? 2 : 1,
667 (info->var.vmode & FB_VMODE_INTERLACED) ? 2 : 1,
670 /* Set interlaced mode start/end register */
671 value = info->var.xres + info->var.left_margin + info->var.right_margin + info->var.hsync_len;
672 value = ((value * hmul) / 8) - 5;
673 vga_wcrt(NULL, 0x3C, (value + 1) / 2);
675 memset_io(info->screen_base, 0x00, screen_size);
676 /* Device and screen back on */
677 svga_wcrt_mask(0x17, 0x80, 0x80);
678 svga_wseq_mask(0x01, 0x00, 0x20);
683 /* Set a colour register */
685 static int s3fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
686 u_int transp, struct fb_info *fb)
688 switch (fb->var.bits_per_pixel) {
694 if ((fb->var.bits_per_pixel == 4) &&
695 (fb->var.nonstd == 0)) {
696 outb(0xF0, VGA_PEL_MSK);
697 outb(regno*16, VGA_PEL_IW);
699 outb(0x0F, VGA_PEL_MSK);
700 outb(regno, VGA_PEL_IW);
702 outb(red >> 10, VGA_PEL_D);
703 outb(green >> 10, VGA_PEL_D);
704 outb(blue >> 10, VGA_PEL_D);
710 outb(0xFF, VGA_PEL_MSK);
711 outb(regno, VGA_PEL_IW);
712 outb(red >> 10, VGA_PEL_D);
713 outb(green >> 10, VGA_PEL_D);
714 outb(blue >> 10, VGA_PEL_D);
720 if (fb->var.green.length == 5)
721 ((u32*)fb->pseudo_palette)[regno] = ((red & 0xF800) >> 1) |
722 ((green & 0xF800) >> 6) | ((blue & 0xF800) >> 11);
723 else if (fb->var.green.length == 6)
724 ((u32*)fb->pseudo_palette)[regno] = (red & 0xF800) |
725 ((green & 0xFC00) >> 5) | ((blue & 0xF800) >> 11);
733 ((u32*)fb->pseudo_palette)[regno] = ((red & 0xFF00) << 8) |
734 (green & 0xFF00) | ((blue & 0xFF00) >> 8);
744 /* Set the display blanking state */
746 static int s3fb_blank(int blank_mode, struct fb_info *info)
748 switch (blank_mode) {
749 case FB_BLANK_UNBLANK:
750 pr_debug("fb%d: unblank\n", info->node);
751 svga_wcrt_mask(0x56, 0x00, 0x06);
752 svga_wseq_mask(0x01, 0x00, 0x20);
754 case FB_BLANK_NORMAL:
755 pr_debug("fb%d: blank\n", info->node);
756 svga_wcrt_mask(0x56, 0x00, 0x06);
757 svga_wseq_mask(0x01, 0x20, 0x20);
759 case FB_BLANK_HSYNC_SUSPEND:
760 pr_debug("fb%d: hsync\n", info->node);
761 svga_wcrt_mask(0x56, 0x02, 0x06);
762 svga_wseq_mask(0x01, 0x20, 0x20);
764 case FB_BLANK_VSYNC_SUSPEND:
765 pr_debug("fb%d: vsync\n", info->node);
766 svga_wcrt_mask(0x56, 0x04, 0x06);
767 svga_wseq_mask(0x01, 0x20, 0x20);
769 case FB_BLANK_POWERDOWN:
770 pr_debug("fb%d: sync down\n", info->node);
771 svga_wcrt_mask(0x56, 0x06, 0x06);
772 svga_wseq_mask(0x01, 0x20, 0x20);
780 /* Pan the display */
782 static int s3fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) {
786 /* Calculate the offset */
787 if (var->bits_per_pixel == 0) {
788 offset = (var->yoffset / 16) * (var->xres_virtual / 2) + (var->xoffset / 2);
789 offset = offset >> 2;
791 offset = (var->yoffset * info->fix.line_length) +
792 (var->xoffset * var->bits_per_pixel / 8);
793 offset = offset >> 2;
797 svga_wcrt_multi(s3_start_address_regs, offset);
802 /* ------------------------------------------------------------------------- */
804 /* Frame buffer operations */
806 static struct fb_ops s3fb_ops = {
807 .owner = THIS_MODULE,
808 .fb_open = s3fb_open,
809 .fb_release = s3fb_release,
810 .fb_check_var = s3fb_check_var,
811 .fb_set_par = s3fb_set_par,
812 .fb_setcolreg = s3fb_setcolreg,
813 .fb_blank = s3fb_blank,
814 .fb_pan_display = s3fb_pan_display,
815 .fb_fillrect = s3fb_fillrect,
816 .fb_copyarea = cfb_copyarea,
817 .fb_imageblit = s3fb_imageblit,
820 /* ------------------------------------------------------------------------- */
822 static int __devinit s3_identification(int chip)
824 if (chip == CHIP_XXX_TRIO) {
825 u8 cr30 = vga_rcrt(NULL, 0x30);
826 u8 cr2e = vga_rcrt(NULL, 0x2e);
827 u8 cr2f = vga_rcrt(NULL, 0x2f);
829 if ((cr30 == 0xE0) || (cr30 == 0xE1)) {
831 return CHIP_732_TRIO32;
834 return CHIP_764_TRIO64;
836 return CHIP_765_TRIO64VP;
841 if (chip == CHIP_XXX_TRIO64V2_DXGX) {
842 u8 cr6f = vga_rcrt(NULL, 0x6f);
845 return CHIP_775_TRIO64V2_DX;
847 return CHIP_785_TRIO64V2_GX;
850 if (chip == CHIP_XXX_VIRGE_DXGX) {
851 u8 cr6f = vga_rcrt(NULL, 0x6f);
854 return CHIP_375_VIRGE_DX;
856 return CHIP_385_VIRGE_GX;
865 static int __devinit s3_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
867 struct fb_info *info;
868 struct s3fb_info *par;
870 u8 regval, cr38, cr39;
872 /* Ignore secondary VGA device because there is no VGA arbitration */
873 if (! svga_primary_device(dev)) {
874 dev_info(&(dev->dev), "ignoring secondary device\n");
878 /* Allocate and fill driver data structure */
879 info = framebuffer_alloc(sizeof(struct s3fb_info), NULL);
881 dev_err(&(dev->dev), "cannot allocate memory\n");
886 mutex_init(&par->open_lock);
888 info->flags = FBINFO_PARTIAL_PAN_OK | FBINFO_HWACCEL_YPAN;
889 info->fbops = &s3fb_ops;
891 /* Prepare PCI device */
892 rc = pci_enable_device(dev);
894 dev_err(&(dev->dev), "cannot enable PCI device\n");
895 goto err_enable_device;
898 rc = pci_request_regions(dev, "s3fb");
900 dev_err(&(dev->dev), "cannot reserve framebuffer region\n");
901 goto err_request_regions;
905 info->fix.smem_start = pci_resource_start(dev, 0);
906 info->fix.smem_len = pci_resource_len(dev, 0);
908 /* Map physical IO memory address into kernel space */
909 info->screen_base = pci_iomap(dev, 0, 0);
910 if (! info->screen_base) {
912 dev_err(&(dev->dev), "iomap for framebuffer failed\n");
917 cr38 = vga_rcrt(NULL, 0x38);
918 cr39 = vga_rcrt(NULL, 0x39);
919 vga_wseq(NULL, 0x08, 0x06);
920 vga_wcrt(NULL, 0x38, 0x48);
921 vga_wcrt(NULL, 0x39, 0xA5);
923 /* Find how many physical memory there is on card */
924 /* 0x36 register is accessible even if other registers are locked */
925 regval = vga_rcrt(NULL, 0x36);
926 info->screen_size = s3_memsizes[regval >> 5] << 10;
927 info->fix.smem_len = info->screen_size;
929 par->chip = id->driver_data & CHIP_MASK;
930 par->rev = vga_rcrt(NULL, 0x2f);
931 if (par->chip & CHIP_UNDECIDED_FLAG)
932 par->chip = s3_identification(par->chip);
934 /* Find MCLK frequency */
935 regval = vga_rseq(NULL, 0x10);
936 par->mclk_freq = ((vga_rseq(NULL, 0x11) + 2) * 14318) / ((regval & 0x1F) + 2);
937 par->mclk_freq = par->mclk_freq >> (regval >> 5);
940 vga_wcrt(NULL, 0x38, cr38);
941 vga_wcrt(NULL, 0x39, cr39);
943 strcpy(info->fix.id, s3_names [par->chip]);
944 info->fix.mmio_start = 0;
945 info->fix.mmio_len = 0;
946 info->fix.type = FB_TYPE_PACKED_PIXELS;
947 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
948 info->fix.ypanstep = 0;
949 info->fix.accel = FB_ACCEL_NONE;
950 info->pseudo_palette = (void*) (par->pseudo_palette);
952 /* Prepare startup mode */
953 rc = fb_find_mode(&(info->var), info, mode, NULL, 0, NULL, 8);
954 if (! ((rc == 1) || (rc == 2))) {
956 dev_err(&(dev->dev), "mode %s not found\n", mode);
960 rc = fb_alloc_cmap(&info->cmap, 256, 0);
962 dev_err(&(dev->dev), "cannot allocate colormap\n");
966 rc = register_framebuffer(info);
968 dev_err(&(dev->dev), "cannot register framebuffer\n");
972 printk(KERN_INFO "fb%d: %s on %s, %d MB RAM, %d MHz MCLK\n", info->node, info->fix.id,
973 pci_name(dev), info->fix.smem_len >> 20, (par->mclk_freq + 500) / 1000);
975 if (par->chip == CHIP_UNKNOWN)
976 printk(KERN_INFO "fb%d: unknown chip, CR2D=%x, CR2E=%x, CRT2F=%x, CRT30=%x\n",
977 info->node, vga_rcrt(NULL, 0x2d), vga_rcrt(NULL, 0x2e),
978 vga_rcrt(NULL, 0x2f), vga_rcrt(NULL, 0x30));
980 /* Record a reference to the driver data */
981 pci_set_drvdata(dev, info);
986 par->mtrr_reg = mtrr_add(info->fix.smem_start, info->fix.smem_len, MTRR_TYPE_WRCOMB, 1);
994 fb_dealloc_cmap(&info->cmap);
997 pci_iounmap(dev, info->screen_base);
999 pci_release_regions(dev);
1000 err_request_regions:
1001 /* pci_disable_device(dev); */
1003 framebuffer_release(info);
1010 static void __devexit s3_pci_remove(struct pci_dev *dev)
1012 struct fb_info *info = pci_get_drvdata(dev);
1017 struct s3fb_info *par = info->par;
1019 if (par->mtrr_reg >= 0) {
1020 mtrr_del(par->mtrr_reg, 0, 0);
1025 unregister_framebuffer(info);
1026 fb_dealloc_cmap(&info->cmap);
1028 pci_iounmap(dev, info->screen_base);
1029 pci_release_regions(dev);
1030 /* pci_disable_device(dev); */
1032 pci_set_drvdata(dev, NULL);
1033 framebuffer_release(info);
1039 static int s3_pci_suspend(struct pci_dev* dev, pm_message_t state)
1041 struct fb_info *info = pci_get_drvdata(dev);
1042 struct s3fb_info *par = info->par;
1044 dev_info(&(dev->dev), "suspend\n");
1046 acquire_console_sem();
1047 mutex_lock(&(par->open_lock));
1049 if ((state.event == PM_EVENT_FREEZE) || (par->ref_count == 0)) {
1050 mutex_unlock(&(par->open_lock));
1051 release_console_sem();
1055 fb_set_suspend(info, 1);
1057 pci_save_state(dev);
1058 pci_disable_device(dev);
1059 pci_set_power_state(dev, pci_choose_state(dev, state));
1061 mutex_unlock(&(par->open_lock));
1062 release_console_sem();
1070 static int s3_pci_resume(struct pci_dev* dev)
1072 struct fb_info *info = pci_get_drvdata(dev);
1073 struct s3fb_info *par = info->par;
1076 dev_info(&(dev->dev), "resume\n");
1078 acquire_console_sem();
1079 mutex_lock(&(par->open_lock));
1081 if (par->ref_count == 0) {
1082 mutex_unlock(&(par->open_lock));
1083 release_console_sem();
1087 pci_set_power_state(dev, PCI_D0);
1088 pci_restore_state(dev);
1089 err = pci_enable_device(dev);
1091 mutex_unlock(&(par->open_lock));
1092 release_console_sem();
1093 dev_err(&(dev->dev), "error %d enabling device for resume\n", err);
1096 pci_set_master(dev);
1099 fb_set_suspend(info, 0);
1101 mutex_unlock(&(par->open_lock));
1102 release_console_sem();
1108 /* List of boards that we are trying to support */
1110 static struct pci_device_id s3_devices[] __devinitdata = {
1111 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8810), .driver_data = CHIP_XXX_TRIO},
1112 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8811), .driver_data = CHIP_XXX_TRIO},
1113 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8812), .driver_data = CHIP_M65_AURORA64VP},
1114 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8814), .driver_data = CHIP_767_TRIO64UVP},
1115 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8901), .driver_data = CHIP_XXX_TRIO64V2_DXGX},
1116 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8902), .driver_data = CHIP_551_PLATO_PX},
1118 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x5631), .driver_data = CHIP_325_VIRGE},
1119 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x883D), .driver_data = CHIP_988_VIRGE_VX},
1120 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A01), .driver_data = CHIP_XXX_VIRGE_DXGX},
1121 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A10), .driver_data = CHIP_356_VIRGE_GX2},
1122 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A11), .driver_data = CHIP_357_VIRGE_GX2P},
1123 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A12), .driver_data = CHIP_359_VIRGE_GX2P},
1125 {0, 0, 0, 0, 0, 0, 0}
1129 MODULE_DEVICE_TABLE(pci, s3_devices);
1131 static struct pci_driver s3fb_pci_driver = {
1133 .id_table = s3_devices,
1134 .probe = s3_pci_probe,
1135 .remove = __devexit_p(s3_pci_remove),
1136 .suspend = s3_pci_suspend,
1137 .resume = s3_pci_resume,
1140 /* Parse user speficied options */
1143 static int __init s3fb_setup(char *options)
1147 if (!options || !*options)
1150 while ((opt = strsep(&options, ",")) != NULL) {
1155 else if (!strncmp(opt, "mtrr:", 5))
1156 mtrr = simple_strtoul(opt + 5, NULL, 0);
1158 else if (!strncmp(opt, "fasttext:", 9))
1159 fasttext = simple_strtoul(opt + 9, NULL, 0);
1170 static void __exit s3fb_cleanup(void)
1172 pr_debug("s3fb: cleaning up\n");
1173 pci_unregister_driver(&s3fb_pci_driver);
1176 /* Driver Initialisation */
1178 static int __init s3fb_init(void)
1182 char *option = NULL;
1184 if (fb_get_options("s3fb", &option))
1189 pr_debug("s3fb: initializing\n");
1190 return pci_register_driver(&s3fb_pci_driver);
1193 /* ------------------------------------------------------------------------- */
1195 /* Modularization */
1197 module_init(s3fb_init);
1198 module_exit(s3fb_cleanup);