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[mv-sheeva.git] / drivers / video / sa1100fb.c
1 /*
2  *  linux/drivers/video/sa1100fb.c
3  *
4  *  Copyright (C) 1999 Eric A. Thomas
5  *   Based on acornfb.c Copyright (C) Russell King.
6  *
7  * This file is subject to the terms and conditions of the GNU General Public
8  * License.  See the file COPYING in the main directory of this archive for
9  * more details.
10  *
11  *              StrongARM 1100 LCD Controller Frame Buffer Driver
12  *
13  * Please direct your questions and comments on this driver to the following
14  * email address:
15  *
16  *      linux-arm-kernel@lists.arm.linux.org.uk
17  *
18  * Clean patches should be sent to the ARM Linux Patch System.  Please see the
19  * following web page for more information:
20  *
21  *      http://www.arm.linux.org.uk/developer/patches/info.shtml
22  *
23  * Thank you.
24  *
25  * Known problems:
26  *      - With the Neponset plugged into an Assabet, LCD powerdown
27  *        doesn't work (LCD stays powered up).  Therefore we shouldn't
28  *        blank the screen.
29  *      - We don't limit the CPU clock rate nor the mode selection
30  *        according to the available SDRAM bandwidth.
31  *
32  * Other notes:
33  *      - Linear grayscale palettes and the kernel.
34  *        Such code does not belong in the kernel.  The kernel frame buffer
35  *        drivers do not expect a linear colourmap, but a colourmap based on
36  *        the VT100 standard mapping.
37  *
38  *        If your _userspace_ requires a linear colourmap, then the setup of
39  *        such a colourmap belongs _in userspace_, not in the kernel.  Code
40  *        to set the colourmap correctly from user space has been sent to
41  *        David Neuer.  It's around 8 lines of C code, plus another 4 to
42  *        detect if we are using grayscale.
43  *
44  *      - The following must never be specified in a panel definition:
45  *           LCCR0_LtlEnd, LCCR3_PixClkDiv, LCCR3_VrtSnchL, LCCR3_HorSnchL
46  *
47  *      - The following should be specified:
48  *           either LCCR0_Color or LCCR0_Mono
49  *           either LCCR0_Sngl or LCCR0_Dual
50  *           either LCCR0_Act or LCCR0_Pas
51  *           either LCCR3_OutEnH or LCCD3_OutEnL
52  *           either LCCR3_PixRsEdg or LCCR3_PixFlEdg
53  *           either LCCR3_ACBsDiv or LCCR3_ACBsCntOff
54  *
55  * Code Status:
56  * 1999/04/01:
57  *      - Driver appears to be working for Brutus 320x200x8bpp mode.  Other
58  *        resolutions are working, but only the 8bpp mode is supported.
59  *        Changes need to be made to the palette encode and decode routines
60  *        to support 4 and 16 bpp modes.  
61  *        Driver is not designed to be a module.  The FrameBuffer is statically
62  *        allocated since dynamic allocation of a 300k buffer cannot be 
63  *        guaranteed. 
64  *
65  * 1999/06/17:
66  *      - FrameBuffer memory is now allocated at run-time when the
67  *        driver is initialized.    
68  *
69  * 2000/04/10: Nicolas Pitre <nico@cam.org>
70  *      - Big cleanup for dynamic selection of machine type at run time.
71  *
72  * 2000/07/19: Jamey Hicks <jamey@crl.dec.com>
73  *      - Support for Bitsy aka Compaq iPAQ H3600 added.
74  *
75  * 2000/08/07: Tak-Shing Chan <tchan.rd@idthk.com>
76  *             Jeff Sutherland <jsutherland@accelent.com>
77  *      - Resolved an issue caused by a change made to the Assabet's PLD 
78  *        earlier this year which broke the framebuffer driver for newer 
79  *        Phase 4 Assabets.  Some other parameters were changed to optimize
80  *        for the Sharp display.
81  *
82  * 2000/08/09: Kunihiko IMAI <imai@vasara.co.jp>
83  *      - XP860 support added
84  *
85  * 2000/08/19: Mark Huang <mhuang@livetoy.com>
86  *      - Allows standard options to be passed on the kernel command line
87  *        for most common passive displays.
88  *
89  * 2000/08/29:
90  *      - s/save_flags_cli/local_irq_save/
91  *      - remove unneeded extra save_flags_cli in sa1100fb_enable_lcd_controller
92  *
93  * 2000/10/10: Erik Mouw <J.A.K.Mouw@its.tudelft.nl>
94  *      - Updated LART stuff. Fixed some minor bugs.
95  *
96  * 2000/10/30: Murphy Chen <murphy@mail.dialogue.com.tw>
97  *      - Pangolin support added
98  *
99  * 2000/10/31: Roman Jordan <jor@hoeft-wessel.de>
100  *      - Huw Webpanel support added
101  *
102  * 2000/11/23: Eric Peng <ericpeng@coventive.com>
103  *      - Freebird add
104  *
105  * 2001/02/07: Jamey Hicks <jamey.hicks@compaq.com> 
106  *             Cliff Brake <cbrake@accelent.com>
107  *      - Added PM callback
108  *
109  * 2001/05/26: <rmk@arm.linux.org.uk>
110  *      - Fix 16bpp so that (a) we use the right colours rather than some
111  *        totally random colour depending on what was in page 0, and (b)
112  *        we don't de-reference a NULL pointer.
113  *      - remove duplicated implementation of consistent_alloc()
114  *      - convert dma address types to dma_addr_t
115  *      - remove unused 'montype' stuff
116  *      - remove redundant zero inits of init_var after the initial
117  *        memzero.
118  *      - remove allow_modeset (acornfb idea does not belong here)
119  *
120  * 2001/05/28: <rmk@arm.linux.org.uk>
121  *      - massive cleanup - move machine dependent data into structures
122  *      - I've left various #warnings in - if you see one, and know
123  *        the hardware concerned, please get in contact with me.
124  *
125  * 2001/05/31: <rmk@arm.linux.org.uk>
126  *      - Fix LCCR1 HSW value, fix all machine type specifications to
127  *        keep values in line.  (Please check your machine type specs)
128  *
129  * 2001/06/10: <rmk@arm.linux.org.uk>
130  *      - Fiddle with the LCD controller from task context only; mainly
131  *        so that we can run with interrupts on, and sleep.
132  *      - Convert #warnings into #errors.  No pain, no gain. ;)
133  *
134  * 2001/06/14: <rmk@arm.linux.org.uk>
135  *      - Make the palette BPS value for 12bpp come out correctly.
136  *      - Take notice of "greyscale" on any colour depth.
137  *      - Make truecolor visuals use the RGB channel encoding information.
138  *
139  * 2001/07/02: <rmk@arm.linux.org.uk>
140  *      - Fix colourmap problems.
141  *
142  * 2001/07/13: <abraham@2d3d.co.za>
143  *      - Added support for the ICP LCD-Kit01 on LART. This LCD is
144  *        manufactured by Prime View, model no V16C6448AB
145  *
146  * 2001/07/23: <rmk@arm.linux.org.uk>
147  *      - Hand merge version from handhelds.org CVS tree.  See patch
148  *        notes for 595/1 for more information.
149  *      - Drop 12bpp (it's 16bpp with different colour register mappings).
150  *      - This hardware can not do direct colour.  Therefore we don't
151  *        support it.
152  *
153  * 2001/07/27: <rmk@arm.linux.org.uk>
154  *      - Halve YRES on dual scan LCDs.
155  *
156  * 2001/08/22: <rmk@arm.linux.org.uk>
157  *      - Add b/w iPAQ pixclock value.
158  *
159  * 2001/10/12: <rmk@arm.linux.org.uk>
160  *      - Add patch 681/1 and clean up stork definitions.
161  */
162
163 #include <linux/module.h>
164 #include <linux/kernel.h>
165 #include <linux/sched.h>
166 #include <linux/errno.h>
167 #include <linux/string.h>
168 #include <linux/interrupt.h>
169 #include <linux/slab.h>
170 #include <linux/fb.h>
171 #include <linux/delay.h>
172 #include <linux/init.h>
173 #include <linux/ioport.h>
174 #include <linux/cpufreq.h>
175 #include <linux/platform_device.h>
176 #include <linux/dma-mapping.h>
177
178 #include <asm/hardware.h>
179 #include <asm/io.h>
180 #include <asm/mach-types.h>
181 #include <asm/arch/assabet.h>
182 #include <asm/arch/shannon.h>
183
184 /*
185  * debugging?
186  */
187 #define DEBUG 0
188 /*
189  * Complain if VAR is out of range.
190  */
191 #define DEBUG_VAR 1
192
193 #undef ASSABET_PAL_VIDEO
194
195 #include "sa1100fb.h"
196
197 extern void (*sa1100fb_backlight_power)(int on);
198 extern void (*sa1100fb_lcd_power)(int on);
199
200 /*
201  * IMHO this looks wrong.  In 8BPP, length should be 8.
202  */
203 static struct sa1100fb_rgb rgb_8 = {
204         .red    = { .offset = 0,  .length = 4, },
205         .green  = { .offset = 0,  .length = 4, },
206         .blue   = { .offset = 0,  .length = 4, },
207         .transp = { .offset = 0,  .length = 0, },
208 };
209
210 static struct sa1100fb_rgb def_rgb_16 = {
211         .red    = { .offset = 11, .length = 5, },
212         .green  = { .offset = 5,  .length = 6, },
213         .blue   = { .offset = 0,  .length = 5, },
214         .transp = { .offset = 0,  .length = 0, },
215 };
216
217 #ifdef CONFIG_SA1100_ASSABET
218 #ifndef ASSABET_PAL_VIDEO
219 /*
220  * The assabet uses a sharp LQ039Q2DS54 LCD module.  It is actually
221  * takes an RGB666 signal, but we provide it with an RGB565 signal
222  * instead (def_rgb_16).
223  */
224 static struct sa1100fb_mach_info lq039q2ds54_info __initdata = {
225         .pixclock       = 171521,       .bpp            = 16,
226         .xres           = 320,          .yres           = 240,
227
228         .hsync_len      = 5,            .vsync_len      = 1,
229         .left_margin    = 61,           .upper_margin   = 3,
230         .right_margin   = 9,            .lower_margin   = 0,
231
232         .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
233
234         .lccr0          = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
235         .lccr3          = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
236 };
237 #else
238 static struct sa1100fb_mach_info pal_info __initdata = {
239         .pixclock       = 67797,        .bpp            = 16,
240         .xres           = 640,          .yres           = 512,
241
242         .hsync_len      = 64,           .vsync_len      = 6,
243         .left_margin    = 125,          .upper_margin   = 70,
244         .right_margin   = 115,          .lower_margin   = 36,
245
246         .lccr0          = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
247         .lccr3          = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(512),
248 };
249 #endif
250 #endif
251
252 #ifdef CONFIG_SA1100_H3800
253 static struct sa1100fb_mach_info h3800_info __initdata = {
254         .pixclock       = 174757,       .bpp            = 16,
255         .xres           = 320,          .yres           = 240,
256
257         .hsync_len      = 3,            .vsync_len      = 3,
258         .left_margin    = 12,           .upper_margin   = 10,
259         .right_margin   = 17,           .lower_margin   = 1,
260
261         .cmap_static    = 1,
262
263         .lccr0          = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
264         .lccr3          = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
265 };
266 #endif
267
268 #ifdef CONFIG_SA1100_H3600
269 static struct sa1100fb_mach_info h3600_info __initdata = {
270         .pixclock       = 174757,       .bpp            = 16,
271         .xres           = 320,          .yres           = 240,
272
273         .hsync_len      = 3,            .vsync_len      = 3,
274         .left_margin    = 12,           .upper_margin   = 10,
275         .right_margin   = 17,           .lower_margin   = 1,
276
277         .cmap_static    = 1,
278
279         .lccr0          = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
280         .lccr3          = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
281 };
282
283 static struct sa1100fb_rgb h3600_rgb_16 = {
284         .red    = { .offset = 12, .length = 4, },
285         .green  = { .offset = 7,  .length = 4, },
286         .blue   = { .offset = 1,  .length = 4, },
287         .transp = { .offset = 0,  .length = 0, },
288 };
289 #endif
290
291 #ifdef CONFIG_SA1100_H3100
292 static struct sa1100fb_mach_info h3100_info __initdata = {
293         .pixclock       = 406977,       .bpp            = 4,
294         .xres           = 320,          .yres           = 240,
295
296         .hsync_len      = 26,           .vsync_len      = 41,
297         .left_margin    = 4,            .upper_margin   = 0,
298         .right_margin   = 4,            .lower_margin   = 0,
299
300         .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
301         .cmap_greyscale = 1,
302         .cmap_inverse   = 1,
303
304         .lccr0          = LCCR0_Mono | LCCR0_4PixMono | LCCR0_Sngl | LCCR0_Pas,
305         .lccr3          = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
306 };
307 #endif
308
309 #ifdef CONFIG_SA1100_COLLIE
310 static struct sa1100fb_mach_info collie_info __initdata = {
311         .pixclock       = 171521,       .bpp            = 16,
312         .xres           = 320,          .yres           = 240,
313
314         .hsync_len      = 5,            .vsync_len      = 1,
315         .left_margin    = 11,           .upper_margin   = 2,
316         .right_margin   = 30,           .lower_margin   = 0,
317
318         .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
319
320         .lccr0          = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
321         .lccr3          = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
322 };
323 #endif
324
325 #ifdef LART_GREY_LCD
326 static struct sa1100fb_mach_info lart_grey_info __initdata = {
327         .pixclock       = 150000,       .bpp            = 4,
328         .xres           = 320,          .yres           = 240,
329
330         .hsync_len      = 1,            .vsync_len      = 1,
331         .left_margin    = 4,            .upper_margin   = 0,
332         .right_margin   = 2,            .lower_margin   = 0,
333
334         .cmap_greyscale = 1,
335         .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
336
337         .lccr0          = LCCR0_Mono | LCCR0_Sngl | LCCR0_Pas | LCCR0_4PixMono,
338         .lccr3          = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(512),
339 };
340 #endif
341 #ifdef LART_COLOR_LCD
342 static struct sa1100fb_mach_info lart_color_info __initdata = {
343         .pixclock       = 150000,       .bpp            = 16,
344         .xres           = 320,          .yres           = 240,
345
346         .hsync_len      = 2,            .vsync_len      = 3,
347         .left_margin    = 69,           .upper_margin   = 14,
348         .right_margin   = 8,            .lower_margin   = 4,
349
350         .lccr0          = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
351         .lccr3          = LCCR3_OutEnH | LCCR3_PixFlEdg | LCCR3_ACBsDiv(512),
352 };
353 #endif
354 #ifdef LART_VIDEO_OUT
355 static struct sa1100fb_mach_info lart_video_info __initdata = {
356         .pixclock       = 39721,        .bpp            = 16,
357         .xres           = 640,          .yres           = 480,
358
359         .hsync_len      = 95,           .vsync_len      = 2,
360         .left_margin    = 40,           .upper_margin   = 32,
361         .right_margin   = 24,           .lower_margin   = 11,
362
363         .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
364
365         .lccr0          = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
366         .lccr3          = LCCR3_OutEnL | LCCR3_PixFlEdg | LCCR3_ACBsDiv(512),
367 };
368 #endif
369
370 #ifdef LART_KIT01_LCD
371 static struct sa1100fb_mach_info lart_kit01_info __initdata = {
372         .pixclock       = 63291,        .bpp            = 16,
373         .xres           = 640,          .yres           = 480,
374
375         .hsync_len      = 64,           .vsync_len      = 3,
376         .left_margin    = 122,          .upper_margin   = 45,
377         .right_margin   = 10,           .lower_margin   = 10,
378
379         .lccr0          = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
380         .lccr3          = LCCR3_OutEnH | LCCR3_PixFlEdg
381 };
382 #endif
383
384 #ifdef CONFIG_SA1100_SHANNON
385 static struct sa1100fb_mach_info shannon_info __initdata = {
386         .pixclock       = 152500,       .bpp            = 8,
387         .xres           = 640,          .yres           = 480,
388
389         .hsync_len      = 4,            .vsync_len      = 3,
390         .left_margin    = 2,            .upper_margin   = 0,
391         .right_margin   = 1,            .lower_margin   = 0,
392
393         .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
394
395         .lccr0          = LCCR0_Color | LCCR0_Dual | LCCR0_Pas,
396         .lccr3          = LCCR3_ACBsDiv(512),
397 };
398 #endif
399
400
401
402 static struct sa1100fb_mach_info * __init
403 sa1100fb_get_machine_info(struct sa1100fb_info *fbi)
404 {
405         struct sa1100fb_mach_info *inf = NULL;
406
407         /*
408          *            R        G       B       T
409          * default  {11,5}, { 5,6}, { 0,5}, { 0,0}
410          * h3600    {12,4}, { 7,4}, { 1,4}, { 0,0}
411          * freebird { 8,4}, { 4,4}, { 0,4}, {12,4}
412          */
413 #ifdef CONFIG_SA1100_ASSABET
414         if (machine_is_assabet()) {
415 #ifndef ASSABET_PAL_VIDEO
416                 inf = &lq039q2ds54_info;
417 #else
418                 inf = &pal_info;
419 #endif
420         }
421 #endif
422 #ifdef CONFIG_SA1100_H3100
423         if (machine_is_h3100()) {
424                 inf = &h3100_info;
425         }
426 #endif
427 #ifdef CONFIG_SA1100_H3600
428         if (machine_is_h3600()) {
429                 inf = &h3600_info;
430                 fbi->rgb[RGB_16] = &h3600_rgb_16;
431         }
432 #endif
433 #ifdef CONFIG_SA1100_H3800
434         if (machine_is_h3800()) {
435                 inf = &h3800_info;
436         }
437 #endif
438 #ifdef CONFIG_SA1100_COLLIE
439         if (machine_is_collie()) {
440                 inf = &collie_info;
441         }
442 #endif
443 #ifdef CONFIG_SA1100_LART
444         if (machine_is_lart()) {
445 #ifdef LART_GREY_LCD
446                 inf = &lart_grey_info;
447 #endif
448 #ifdef LART_COLOR_LCD
449                 inf = &lart_color_info;
450 #endif
451 #ifdef LART_VIDEO_OUT
452                 inf = &lart_video_info;
453 #endif
454 #ifdef LART_KIT01_LCD
455                 inf = &lart_kit01_info;
456 #endif
457         }
458 #endif
459 #ifdef CONFIG_SA1100_SHANNON
460         if (machine_is_shannon()) {
461                 inf = &shannon_info;
462         }
463 #endif
464         return inf;
465 }
466
467 static int sa1100fb_activate_var(struct fb_var_screeninfo *var, struct sa1100fb_info *);
468 static void set_ctrlr_state(struct sa1100fb_info *fbi, u_int state);
469
470 static inline void sa1100fb_schedule_work(struct sa1100fb_info *fbi, u_int state)
471 {
472         unsigned long flags;
473
474         local_irq_save(flags);
475         /*
476          * We need to handle two requests being made at the same time.
477          * There are two important cases:
478          *  1. When we are changing VT (C_REENABLE) while unblanking (C_ENABLE)
479          *     We must perform the unblanking, which will do our REENABLE for us.
480          *  2. When we are blanking, but immediately unblank before we have
481          *     blanked.  We do the "REENABLE" thing here as well, just to be sure.
482          */
483         if (fbi->task_state == C_ENABLE && state == C_REENABLE)
484                 state = (u_int) -1;
485         if (fbi->task_state == C_DISABLE && state == C_ENABLE)
486                 state = C_REENABLE;
487
488         if (state != (u_int)-1) {
489                 fbi->task_state = state;
490                 schedule_work(&fbi->task);
491         }
492         local_irq_restore(flags);
493 }
494
495 static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
496 {
497         chan &= 0xffff;
498         chan >>= 16 - bf->length;
499         return chan << bf->offset;
500 }
501
502 /*
503  * Convert bits-per-pixel to a hardware palette PBS value.
504  */
505 static inline u_int palette_pbs(struct fb_var_screeninfo *var)
506 {
507         int ret = 0;
508         switch (var->bits_per_pixel) {
509         case 4:  ret = 0 << 12; break;
510         case 8:  ret = 1 << 12; break;
511         case 16: ret = 2 << 12; break;
512         }
513         return ret;
514 }
515
516 static int
517 sa1100fb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
518                        u_int trans, struct fb_info *info)
519 {
520         struct sa1100fb_info *fbi = (struct sa1100fb_info *)info;
521         u_int val, ret = 1;
522
523         if (regno < fbi->palette_size) {
524                 val = ((red >> 4) & 0xf00);
525                 val |= ((green >> 8) & 0x0f0);
526                 val |= ((blue >> 12) & 0x00f);
527
528                 if (regno == 0)
529                         val |= palette_pbs(&fbi->fb.var);
530
531                 fbi->palette_cpu[regno] = val;
532                 ret = 0;
533         }
534         return ret;
535 }
536
537 static int
538 sa1100fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
539                    u_int trans, struct fb_info *info)
540 {
541         struct sa1100fb_info *fbi = (struct sa1100fb_info *)info;
542         unsigned int val;
543         int ret = 1;
544
545         /*
546          * If inverse mode was selected, invert all the colours
547          * rather than the register number.  The register number
548          * is what you poke into the framebuffer to produce the
549          * colour you requested.
550          */
551         if (fbi->cmap_inverse) {
552                 red   = 0xffff - red;
553                 green = 0xffff - green;
554                 blue  = 0xffff - blue;
555         }
556
557         /*
558          * If greyscale is true, then we convert the RGB value
559          * to greyscale no mater what visual we are using.
560          */
561         if (fbi->fb.var.grayscale)
562                 red = green = blue = (19595 * red + 38470 * green +
563                                         7471 * blue) >> 16;
564
565         switch (fbi->fb.fix.visual) {
566         case FB_VISUAL_TRUECOLOR:
567                 /*
568                  * 12 or 16-bit True Colour.  We encode the RGB value
569                  * according to the RGB bitfield information.
570                  */
571                 if (regno < 16) {
572                         u32 *pal = fbi->fb.pseudo_palette;
573
574                         val  = chan_to_field(red, &fbi->fb.var.red);
575                         val |= chan_to_field(green, &fbi->fb.var.green);
576                         val |= chan_to_field(blue, &fbi->fb.var.blue);
577
578                         pal[regno] = val;
579                         ret = 0;
580                 }
581                 break;
582
583         case FB_VISUAL_STATIC_PSEUDOCOLOR:
584         case FB_VISUAL_PSEUDOCOLOR:
585                 ret = sa1100fb_setpalettereg(regno, red, green, blue, trans, info);
586                 break;
587         }
588
589         return ret;
590 }
591
592 #ifdef CONFIG_CPU_FREQ
593 /*
594  *  sa1100fb_display_dma_period()
595  *    Calculate the minimum period (in picoseconds) between two DMA
596  *    requests for the LCD controller.  If we hit this, it means we're
597  *    doing nothing but LCD DMA.
598  */
599 static inline unsigned int sa1100fb_display_dma_period(struct fb_var_screeninfo *var)
600 {
601         /*
602          * Period = pixclock * bits_per_byte * bytes_per_transfer
603          *              / memory_bits_per_pixel;
604          */
605         return var->pixclock * 8 * 16 / var->bits_per_pixel;
606 }
607 #endif
608
609 /*
610  *  sa1100fb_check_var():
611  *    Round up in the following order: bits_per_pixel, xres,
612  *    yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
613  *    bitfields, horizontal timing, vertical timing.
614  */
615 static int
616 sa1100fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
617 {
618         struct sa1100fb_info *fbi = (struct sa1100fb_info *)info;
619         int rgbidx;
620
621         if (var->xres < MIN_XRES)
622                 var->xres = MIN_XRES;
623         if (var->yres < MIN_YRES)
624                 var->yres = MIN_YRES;
625         if (var->xres > fbi->max_xres)
626                 var->xres = fbi->max_xres;
627         if (var->yres > fbi->max_yres)
628                 var->yres = fbi->max_yres;
629         var->xres_virtual = max(var->xres_virtual, var->xres);
630         var->yres_virtual = max(var->yres_virtual, var->yres);
631
632         DPRINTK("var->bits_per_pixel=%d\n", var->bits_per_pixel);
633         switch (var->bits_per_pixel) {
634         case 4:
635                 rgbidx = RGB_8;
636                 break;
637         case 8:
638                 rgbidx = RGB_8;
639                 break;
640         case 16:
641                 rgbidx = RGB_16;
642                 break;
643         default:
644                 return -EINVAL;
645         }
646
647         /*
648          * Copy the RGB parameters for this display
649          * from the machine specific parameters.
650          */
651         var->red    = fbi->rgb[rgbidx]->red;
652         var->green  = fbi->rgb[rgbidx]->green;
653         var->blue   = fbi->rgb[rgbidx]->blue;
654         var->transp = fbi->rgb[rgbidx]->transp;
655
656         DPRINTK("RGBT length = %d:%d:%d:%d\n",
657                 var->red.length, var->green.length, var->blue.length,
658                 var->transp.length);
659
660         DPRINTK("RGBT offset = %d:%d:%d:%d\n",
661                 var->red.offset, var->green.offset, var->blue.offset,
662                 var->transp.offset);
663
664 #ifdef CONFIG_CPU_FREQ
665         printk(KERN_DEBUG "dma period = %d ps, clock = %d kHz\n",
666                 sa1100fb_display_dma_period(var),
667                 cpufreq_get(smp_processor_id()));
668 #endif
669
670         return 0;
671 }
672
673 static inline void sa1100fb_set_truecolor(u_int is_true_color)
674 {
675         if (machine_is_assabet()) {
676 #if 1           // phase 4 or newer Assabet's
677                 if (is_true_color)
678                         ASSABET_BCR_set(ASSABET_BCR_LCD_12RGB);
679                 else
680                         ASSABET_BCR_clear(ASSABET_BCR_LCD_12RGB);
681 #else
682                 // older Assabet's
683                 if (is_true_color)
684                         ASSABET_BCR_clear(ASSABET_BCR_LCD_12RGB);
685                 else
686                         ASSABET_BCR_set(ASSABET_BCR_LCD_12RGB);
687 #endif
688         }
689 }
690
691 /*
692  * sa1100fb_set_par():
693  *      Set the user defined part of the display for the specified console
694  */
695 static int sa1100fb_set_par(struct fb_info *info)
696 {
697         struct sa1100fb_info *fbi = (struct sa1100fb_info *)info;
698         struct fb_var_screeninfo *var = &info->var;
699         unsigned long palette_mem_size;
700
701         DPRINTK("set_par\n");
702
703         if (var->bits_per_pixel == 16)
704                 fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
705         else if (!fbi->cmap_static)
706                 fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
707         else {
708                 /*
709                  * Some people have weird ideas about wanting static
710                  * pseudocolor maps.  I suspect their user space
711                  * applications are broken.
712                  */
713                 fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
714         }
715
716         fbi->fb.fix.line_length = var->xres_virtual *
717                                   var->bits_per_pixel / 8;
718         fbi->palette_size = var->bits_per_pixel == 8 ? 256 : 16;
719
720         palette_mem_size = fbi->palette_size * sizeof(u16);
721
722         DPRINTK("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
723
724         fbi->palette_cpu = (u16 *)(fbi->map_cpu + PAGE_SIZE - palette_mem_size);
725         fbi->palette_dma = fbi->map_dma + PAGE_SIZE - palette_mem_size;
726
727         /*
728          * Set (any) board control register to handle new color depth
729          */
730         sa1100fb_set_truecolor(fbi->fb.fix.visual == FB_VISUAL_TRUECOLOR);
731         sa1100fb_activate_var(var, fbi);
732
733         return 0;
734 }
735
736 #if 0
737 static int
738 sa1100fb_set_cmap(struct fb_cmap *cmap, int kspc, int con,
739                   struct fb_info *info)
740 {
741         struct sa1100fb_info *fbi = (struct sa1100fb_info *)info;
742
743         /*
744          * Make sure the user isn't doing something stupid.
745          */
746         if (!kspc && (fbi->fb.var.bits_per_pixel == 16 || fbi->cmap_static))
747                 return -EINVAL;
748
749         return gen_set_cmap(cmap, kspc, con, info);
750 }
751 #endif
752
753 /*
754  * Formal definition of the VESA spec:
755  *  On
756  *      This refers to the state of the display when it is in full operation
757  *  Stand-By
758  *      This defines an optional operating state of minimal power reduction with
759  *      the shortest recovery time
760  *  Suspend
761  *      This refers to a level of power management in which substantial power
762  *      reduction is achieved by the display.  The display can have a longer 
763  *      recovery time from this state than from the Stand-by state
764  *  Off
765  *      This indicates that the display is consuming the lowest level of power
766  *      and is non-operational. Recovery from this state may optionally require
767  *      the user to manually power on the monitor
768  *
769  *  Now, the fbdev driver adds an additional state, (blank), where they
770  *  turn off the video (maybe by colormap tricks), but don't mess with the
771  *  video itself: think of it semantically between on and Stand-By.
772  *
773  *  So here's what we should do in our fbdev blank routine:
774  *
775  *      VESA_NO_BLANKING (mode 0)       Video on,  front/back light on
776  *      VESA_VSYNC_SUSPEND (mode 1)     Video on,  front/back light off
777  *      VESA_HSYNC_SUSPEND (mode 2)     Video on,  front/back light off
778  *      VESA_POWERDOWN (mode 3)         Video off, front/back light off
779  *
780  *  This will match the matrox implementation.
781  */
782 /*
783  * sa1100fb_blank():
784  *      Blank the display by setting all palette values to zero.  Note, the 
785  *      12 and 16 bpp modes don't really use the palette, so this will not
786  *      blank the display in all modes.  
787  */
788 static int sa1100fb_blank(int blank, struct fb_info *info)
789 {
790         struct sa1100fb_info *fbi = (struct sa1100fb_info *)info;
791         int i;
792
793         DPRINTK("sa1100fb_blank: blank=%d\n", blank);
794
795         switch (blank) {
796         case FB_BLANK_POWERDOWN:
797         case FB_BLANK_VSYNC_SUSPEND:
798         case FB_BLANK_HSYNC_SUSPEND:
799         case FB_BLANK_NORMAL:
800                 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
801                     fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
802                         for (i = 0; i < fbi->palette_size; i++)
803                                 sa1100fb_setpalettereg(i, 0, 0, 0, 0, info);
804                 sa1100fb_schedule_work(fbi, C_DISABLE);
805                 break;
806
807         case FB_BLANK_UNBLANK:
808                 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
809                     fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
810                         fb_set_cmap(&fbi->fb.cmap, info);
811                 sa1100fb_schedule_work(fbi, C_ENABLE);
812         }
813         return 0;
814 }
815
816 static int sa1100fb_mmap(struct fb_info *info,
817                          struct vm_area_struct *vma)
818 {
819         struct sa1100fb_info *fbi = (struct sa1100fb_info *)info;
820         unsigned long start, len, off = vma->vm_pgoff << PAGE_SHIFT;
821
822         if (off < info->fix.smem_len) {
823                 vma->vm_pgoff += 1; /* skip over the palette */
824                 return dma_mmap_writecombine(fbi->dev, vma, fbi->map_cpu,
825                                              fbi->map_dma, fbi->map_size);
826         }
827
828         start = info->fix.mmio_start;
829         len = PAGE_ALIGN((start & ~PAGE_MASK) + info->fix.mmio_len);
830
831         if ((vma->vm_end - vma->vm_start + off) > len)
832                 return -EINVAL;
833
834         off += start & PAGE_MASK;
835         vma->vm_pgoff = off >> PAGE_SHIFT;
836         vma->vm_flags |= VM_IO;
837         vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
838         return io_remap_pfn_range(vma, vma->vm_start, off >> PAGE_SHIFT,
839                                    vma->vm_end - vma->vm_start,
840                                    vma->vm_page_prot);
841 }
842
843 static struct fb_ops sa1100fb_ops = {
844         .owner          = THIS_MODULE,
845         .fb_check_var   = sa1100fb_check_var,
846         .fb_set_par     = sa1100fb_set_par,
847 //      .fb_set_cmap    = sa1100fb_set_cmap,
848         .fb_setcolreg   = sa1100fb_setcolreg,
849         .fb_fillrect    = cfb_fillrect,
850         .fb_copyarea    = cfb_copyarea,
851         .fb_imageblit   = cfb_imageblit,
852         .fb_blank       = sa1100fb_blank,
853         .fb_mmap        = sa1100fb_mmap,
854 };
855
856 /*
857  * Calculate the PCD value from the clock rate (in picoseconds).
858  * We take account of the PPCR clock setting.
859  */
860 static inline unsigned int get_pcd(unsigned int pixclock, unsigned int cpuclock)
861 {
862         unsigned int pcd = cpuclock / 100;
863
864         pcd *= pixclock;
865         pcd /= 10000000;
866
867         return pcd + 1; /* make up for integer math truncations */
868 }
869
870 /*
871  * sa1100fb_activate_var():
872  *      Configures LCD Controller based on entries in var parameter.  Settings are      
873  *      only written to the controller if changes were made.  
874  */
875 static int sa1100fb_activate_var(struct fb_var_screeninfo *var, struct sa1100fb_info *fbi)
876 {
877         struct sa1100fb_lcd_reg new_regs;
878         u_int half_screen_size, yres, pcd;
879         u_long flags;
880
881         DPRINTK("Configuring SA1100 LCD\n");
882
883         DPRINTK("var: xres=%d hslen=%d lm=%d rm=%d\n",
884                 var->xres, var->hsync_len,
885                 var->left_margin, var->right_margin);
886         DPRINTK("var: yres=%d vslen=%d um=%d bm=%d\n",
887                 var->yres, var->vsync_len,
888                 var->upper_margin, var->lower_margin);
889
890 #if DEBUG_VAR
891         if (var->xres < 16        || var->xres > 1024)
892                 printk(KERN_ERR "%s: invalid xres %d\n",
893                         fbi->fb.fix.id, var->xres);
894         if (var->hsync_len < 1    || var->hsync_len > 64)
895                 printk(KERN_ERR "%s: invalid hsync_len %d\n",
896                         fbi->fb.fix.id, var->hsync_len);
897         if (var->left_margin < 1  || var->left_margin > 255)
898                 printk(KERN_ERR "%s: invalid left_margin %d\n",
899                         fbi->fb.fix.id, var->left_margin);
900         if (var->right_margin < 1 || var->right_margin > 255)
901                 printk(KERN_ERR "%s: invalid right_margin %d\n",
902                         fbi->fb.fix.id, var->right_margin);
903         if (var->yres < 1         || var->yres > 1024)
904                 printk(KERN_ERR "%s: invalid yres %d\n",
905                         fbi->fb.fix.id, var->yres);
906         if (var->vsync_len < 1    || var->vsync_len > 64)
907                 printk(KERN_ERR "%s: invalid vsync_len %d\n",
908                         fbi->fb.fix.id, var->vsync_len);
909         if (var->upper_margin < 0 || var->upper_margin > 255)
910                 printk(KERN_ERR "%s: invalid upper_margin %d\n",
911                         fbi->fb.fix.id, var->upper_margin);
912         if (var->lower_margin < 0 || var->lower_margin > 255)
913                 printk(KERN_ERR "%s: invalid lower_margin %d\n",
914                         fbi->fb.fix.id, var->lower_margin);
915 #endif
916
917         new_regs.lccr0 = fbi->lccr0 |
918                 LCCR0_LEN | LCCR0_LDM | LCCR0_BAM |
919                 LCCR0_ERM | LCCR0_LtlEnd | LCCR0_DMADel(0);
920
921         new_regs.lccr1 =
922                 LCCR1_DisWdth(var->xres) +
923                 LCCR1_HorSnchWdth(var->hsync_len) +
924                 LCCR1_BegLnDel(var->left_margin) +
925                 LCCR1_EndLnDel(var->right_margin);
926
927         /*
928          * If we have a dual scan LCD, then we need to halve
929          * the YRES parameter.
930          */
931         yres = var->yres;
932         if (fbi->lccr0 & LCCR0_Dual)
933                 yres /= 2;
934
935         new_regs.lccr2 =
936                 LCCR2_DisHght(yres) +
937                 LCCR2_VrtSnchWdth(var->vsync_len) +
938                 LCCR2_BegFrmDel(var->upper_margin) +
939                 LCCR2_EndFrmDel(var->lower_margin);
940
941         pcd = get_pcd(var->pixclock, cpufreq_get(0));
942         new_regs.lccr3 = LCCR3_PixClkDiv(pcd) | fbi->lccr3 |
943                 (var->sync & FB_SYNC_HOR_HIGH_ACT ? LCCR3_HorSnchH : LCCR3_HorSnchL) |
944                 (var->sync & FB_SYNC_VERT_HIGH_ACT ? LCCR3_VrtSnchH : LCCR3_VrtSnchL);
945
946         DPRINTK("nlccr0 = 0x%08lx\n", new_regs.lccr0);
947         DPRINTK("nlccr1 = 0x%08lx\n", new_regs.lccr1);
948         DPRINTK("nlccr2 = 0x%08lx\n", new_regs.lccr2);
949         DPRINTK("nlccr3 = 0x%08lx\n", new_regs.lccr3);
950
951         half_screen_size = var->bits_per_pixel;
952         half_screen_size = half_screen_size * var->xres * var->yres / 16;
953
954         /* Update shadow copy atomically */
955         local_irq_save(flags);
956         fbi->dbar1 = fbi->palette_dma;
957         fbi->dbar2 = fbi->screen_dma + half_screen_size;
958
959         fbi->reg_lccr0 = new_regs.lccr0;
960         fbi->reg_lccr1 = new_regs.lccr1;
961         fbi->reg_lccr2 = new_regs.lccr2;
962         fbi->reg_lccr3 = new_regs.lccr3;
963         local_irq_restore(flags);
964
965         /*
966          * Only update the registers if the controller is enabled
967          * and something has changed.
968          */
969         if ((LCCR0 != fbi->reg_lccr0)       || (LCCR1 != fbi->reg_lccr1) ||
970             (LCCR2 != fbi->reg_lccr2)       || (LCCR3 != fbi->reg_lccr3) ||
971             (DBAR1 != fbi->dbar1) || (DBAR2 != fbi->dbar2))
972                 sa1100fb_schedule_work(fbi, C_REENABLE);
973
974         return 0;
975 }
976
977 /*
978  * NOTE!  The following functions are purely helpers for set_ctrlr_state.
979  * Do not call them directly; set_ctrlr_state does the correct serialisation
980  * to ensure that things happen in the right way 100% of time time.
981  *      -- rmk
982  */
983 static inline void __sa1100fb_backlight_power(struct sa1100fb_info *fbi, int on)
984 {
985         DPRINTK("backlight o%s\n", on ? "n" : "ff");
986
987         if (sa1100fb_backlight_power)
988                 sa1100fb_backlight_power(on);
989 }
990
991 static inline void __sa1100fb_lcd_power(struct sa1100fb_info *fbi, int on)
992 {
993         DPRINTK("LCD power o%s\n", on ? "n" : "ff");
994
995         if (sa1100fb_lcd_power)
996                 sa1100fb_lcd_power(on);
997 }
998
999 static void sa1100fb_setup_gpio(struct sa1100fb_info *fbi)
1000 {
1001         u_int mask = 0;
1002
1003         /*
1004          * Enable GPIO<9:2> for LCD use if:
1005          *  1. Active display, or
1006          *  2. Color Dual Passive display
1007          *
1008          * see table 11.8 on page 11-27 in the SA1100 manual
1009          *   -- Erik.
1010          *
1011          * SA1110 spec update nr. 25 says we can and should
1012          * clear LDD15 to 12 for 4 or 8bpp modes with active
1013          * panels.  
1014          */
1015         if ((fbi->reg_lccr0 & LCCR0_CMS) == LCCR0_Color &&
1016             (fbi->reg_lccr0 & (LCCR0_Dual|LCCR0_Act)) != 0) {
1017                 mask = GPIO_LDD11 | GPIO_LDD10 | GPIO_LDD9  | GPIO_LDD8;
1018
1019                 if (fbi->fb.var.bits_per_pixel > 8 ||
1020                     (fbi->reg_lccr0 & (LCCR0_Dual|LCCR0_Act)) == LCCR0_Dual)
1021                         mask |= GPIO_LDD15 | GPIO_LDD14 | GPIO_LDD13 | GPIO_LDD12;
1022
1023         }
1024
1025         if (mask) {
1026                 GPDR |= mask;
1027                 GAFR |= mask;
1028         }
1029 }
1030
1031 static void sa1100fb_enable_controller(struct sa1100fb_info *fbi)
1032 {
1033         DPRINTK("Enabling LCD controller\n");
1034
1035         /*
1036          * Make sure the mode bits are present in the first palette entry
1037          */
1038         fbi->palette_cpu[0] &= 0xcfff;
1039         fbi->palette_cpu[0] |= palette_pbs(&fbi->fb.var);
1040
1041         /* Sequence from 11.7.10 */
1042         LCCR3 = fbi->reg_lccr3;
1043         LCCR2 = fbi->reg_lccr2;
1044         LCCR1 = fbi->reg_lccr1;
1045         LCCR0 = fbi->reg_lccr0 & ~LCCR0_LEN;
1046         DBAR1 = fbi->dbar1;
1047         DBAR2 = fbi->dbar2;
1048         LCCR0 |= LCCR0_LEN;
1049
1050         if (machine_is_shannon()) {
1051                 GPDR |= SHANNON_GPIO_DISP_EN;
1052                 GPSR |= SHANNON_GPIO_DISP_EN;
1053         }
1054
1055         DPRINTK("DBAR1 = 0x%08x\n", DBAR1);
1056         DPRINTK("DBAR2 = 0x%08x\n", DBAR2);
1057         DPRINTK("LCCR0 = 0x%08x\n", LCCR0);
1058         DPRINTK("LCCR1 = 0x%08x\n", LCCR1);
1059         DPRINTK("LCCR2 = 0x%08x\n", LCCR2);
1060         DPRINTK("LCCR3 = 0x%08x\n", LCCR3);
1061 }
1062
1063 static void sa1100fb_disable_controller(struct sa1100fb_info *fbi)
1064 {
1065         DECLARE_WAITQUEUE(wait, current);
1066
1067         DPRINTK("Disabling LCD controller\n");
1068
1069         if (machine_is_shannon()) {
1070                 GPCR |= SHANNON_GPIO_DISP_EN;
1071         }       
1072
1073         set_current_state(TASK_UNINTERRUPTIBLE);
1074         add_wait_queue(&fbi->ctrlr_wait, &wait);
1075
1076         LCSR = 0xffffffff;      /* Clear LCD Status Register */
1077         LCCR0 &= ~LCCR0_LDM;    /* Enable LCD Disable Done Interrupt */
1078         LCCR0 &= ~LCCR0_LEN;    /* Disable LCD Controller */
1079
1080         schedule_timeout(20 * HZ / 1000);
1081         remove_wait_queue(&fbi->ctrlr_wait, &wait);
1082 }
1083
1084 /*
1085  *  sa1100fb_handle_irq: Handle 'LCD DONE' interrupts.
1086  */
1087 static irqreturn_t sa1100fb_handle_irq(int irq, void *dev_id)
1088 {
1089         struct sa1100fb_info *fbi = dev_id;
1090         unsigned int lcsr = LCSR;
1091
1092         if (lcsr & LCSR_LDD) {
1093                 LCCR0 |= LCCR0_LDM;
1094                 wake_up(&fbi->ctrlr_wait);
1095         }
1096
1097         LCSR = lcsr;
1098         return IRQ_HANDLED;
1099 }
1100
1101 /*
1102  * This function must be called from task context only, since it will
1103  * sleep when disabling the LCD controller, or if we get two contending
1104  * processes trying to alter state.
1105  */
1106 static void set_ctrlr_state(struct sa1100fb_info *fbi, u_int state)
1107 {
1108         u_int old_state;
1109
1110         down(&fbi->ctrlr_sem);
1111
1112         old_state = fbi->state;
1113
1114         /*
1115          * Hack around fbcon initialisation.
1116          */
1117         if (old_state == C_STARTUP && state == C_REENABLE)
1118                 state = C_ENABLE;
1119
1120         switch (state) {
1121         case C_DISABLE_CLKCHANGE:
1122                 /*
1123                  * Disable controller for clock change.  If the
1124                  * controller is already disabled, then do nothing.
1125                  */
1126                 if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
1127                         fbi->state = state;
1128                         sa1100fb_disable_controller(fbi);
1129                 }
1130                 break;
1131
1132         case C_DISABLE_PM:
1133         case C_DISABLE:
1134                 /*
1135                  * Disable controller
1136                  */
1137                 if (old_state != C_DISABLE) {
1138                         fbi->state = state;
1139
1140                         __sa1100fb_backlight_power(fbi, 0);
1141                         if (old_state != C_DISABLE_CLKCHANGE)
1142                                 sa1100fb_disable_controller(fbi);
1143                         __sa1100fb_lcd_power(fbi, 0);
1144                 }
1145                 break;
1146
1147         case C_ENABLE_CLKCHANGE:
1148                 /*
1149                  * Enable the controller after clock change.  Only
1150                  * do this if we were disabled for the clock change.
1151                  */
1152                 if (old_state == C_DISABLE_CLKCHANGE) {
1153                         fbi->state = C_ENABLE;
1154                         sa1100fb_enable_controller(fbi);
1155                 }
1156                 break;
1157
1158         case C_REENABLE:
1159                 /*
1160                  * Re-enable the controller only if it was already
1161                  * enabled.  This is so we reprogram the control
1162                  * registers.
1163                  */
1164                 if (old_state == C_ENABLE) {
1165                         sa1100fb_disable_controller(fbi);
1166                         sa1100fb_setup_gpio(fbi);
1167                         sa1100fb_enable_controller(fbi);
1168                 }
1169                 break;
1170
1171         case C_ENABLE_PM:
1172                 /*
1173                  * Re-enable the controller after PM.  This is not
1174                  * perfect - think about the case where we were doing
1175                  * a clock change, and we suspended half-way through.
1176                  */
1177                 if (old_state != C_DISABLE_PM)
1178                         break;
1179                 /* fall through */
1180
1181         case C_ENABLE:
1182                 /*
1183                  * Power up the LCD screen, enable controller, and
1184                  * turn on the backlight.
1185                  */
1186                 if (old_state != C_ENABLE) {
1187                         fbi->state = C_ENABLE;
1188                         sa1100fb_setup_gpio(fbi);
1189                         __sa1100fb_lcd_power(fbi, 1);
1190                         sa1100fb_enable_controller(fbi);
1191                         __sa1100fb_backlight_power(fbi, 1);
1192                 }
1193                 break;
1194         }
1195         up(&fbi->ctrlr_sem);
1196 }
1197
1198 /*
1199  * Our LCD controller task (which is called when we blank or unblank)
1200  * via keventd.
1201  */
1202 static void sa1100fb_task(struct work_struct *w)
1203 {
1204         struct sa1100fb_info *fbi = container_of(w, struct sa1100fb_info, task);
1205         u_int state = xchg(&fbi->task_state, -1);
1206
1207         set_ctrlr_state(fbi, state);
1208 }
1209
1210 #ifdef CONFIG_CPU_FREQ
1211 /*
1212  * Calculate the minimum DMA period over all displays that we own.
1213  * This, together with the SDRAM bandwidth defines the slowest CPU
1214  * frequency that can be selected.
1215  */
1216 static unsigned int sa1100fb_min_dma_period(struct sa1100fb_info *fbi)
1217 {
1218 #if 0
1219         unsigned int min_period = (unsigned int)-1;
1220         int i;
1221
1222         for (i = 0; i < MAX_NR_CONSOLES; i++) {
1223                 struct display *disp = &fb_display[i];
1224                 unsigned int period;
1225
1226                 /*
1227                  * Do we own this display?
1228                  */
1229                 if (disp->fb_info != &fbi->fb)
1230                         continue;
1231
1232                 /*
1233                  * Ok, calculate its DMA period
1234                  */
1235                 period = sa1100fb_display_dma_period(&disp->var);
1236                 if (period < min_period)
1237                         min_period = period;
1238         }
1239
1240         return min_period;
1241 #else
1242         /*
1243          * FIXME: we need to verify _all_ consoles.
1244          */
1245         return sa1100fb_display_dma_period(&fbi->fb.var);
1246 #endif
1247 }
1248
1249 /*
1250  * CPU clock speed change handler.  We need to adjust the LCD timing
1251  * parameters when the CPU clock is adjusted by the power management
1252  * subsystem.
1253  */
1254 static int
1255 sa1100fb_freq_transition(struct notifier_block *nb, unsigned long val,
1256                          void *data)
1257 {
1258         struct sa1100fb_info *fbi = TO_INF(nb, freq_transition);
1259         struct cpufreq_freqs *f = data;
1260         u_int pcd;
1261
1262         switch (val) {
1263         case CPUFREQ_PRECHANGE:
1264                 set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
1265                 break;
1266
1267         case CPUFREQ_POSTCHANGE:
1268                 pcd = get_pcd(fbi->fb.var.pixclock, f->new);
1269                 fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) | LCCR3_PixClkDiv(pcd);
1270                 set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
1271                 break;
1272         }
1273         return 0;
1274 }
1275
1276 static int
1277 sa1100fb_freq_policy(struct notifier_block *nb, unsigned long val,
1278                      void *data)
1279 {
1280         struct sa1100fb_info *fbi = TO_INF(nb, freq_policy);
1281         struct cpufreq_policy *policy = data;
1282
1283         switch (val) {
1284         case CPUFREQ_ADJUST:
1285         case CPUFREQ_INCOMPATIBLE:
1286                 printk(KERN_DEBUG "min dma period: %d ps, "
1287                         "new clock %d kHz\n", sa1100fb_min_dma_period(fbi),
1288                         policy->max);
1289                 /* todo: fill in min/max values */
1290                 break;
1291         case CPUFREQ_NOTIFY:
1292                 do {} while(0);
1293                 /* todo: panic if min/max values aren't fulfilled 
1294                  * [can't really happen unless there's a bug in the
1295                  * CPU policy verififcation process *
1296                  */
1297                 break;
1298         }
1299         return 0;
1300 }
1301 #endif
1302
1303 #ifdef CONFIG_PM
1304 /*
1305  * Power management hooks.  Note that we won't be called from IRQ context,
1306  * unlike the blank functions above, so we may sleep.
1307  */
1308 static int sa1100fb_suspend(struct platform_device *dev, pm_message_t state)
1309 {
1310         struct sa1100fb_info *fbi = platform_get_drvdata(dev);
1311
1312         set_ctrlr_state(fbi, C_DISABLE_PM);
1313         return 0;
1314 }
1315
1316 static int sa1100fb_resume(struct platform_device *dev)
1317 {
1318         struct sa1100fb_info *fbi = platform_get_drvdata(dev);
1319
1320         set_ctrlr_state(fbi, C_ENABLE_PM);
1321         return 0;
1322 }
1323 #else
1324 #define sa1100fb_suspend        NULL
1325 #define sa1100fb_resume         NULL
1326 #endif
1327
1328 /*
1329  * sa1100fb_map_video_memory():
1330  *      Allocates the DRAM memory for the frame buffer.  This buffer is  
1331  *      remapped into a non-cached, non-buffered, memory region to  
1332  *      allow palette and pixel writes to occur without flushing the 
1333  *      cache.  Once this area is remapped, all virtual memory
1334  *      access to the video memory should occur at the new region.
1335  */
1336 static int __init sa1100fb_map_video_memory(struct sa1100fb_info *fbi)
1337 {
1338         /*
1339          * We reserve one page for the palette, plus the size
1340          * of the framebuffer.
1341          */
1342         fbi->map_size = PAGE_ALIGN(fbi->fb.fix.smem_len + PAGE_SIZE);
1343         fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size,
1344                                               &fbi->map_dma, GFP_KERNEL);
1345
1346         if (fbi->map_cpu) {
1347                 fbi->fb.screen_base = fbi->map_cpu + PAGE_SIZE;
1348                 fbi->screen_dma = fbi->map_dma + PAGE_SIZE;
1349                 /*
1350                  * FIXME: this is actually the wrong thing to place in
1351                  * smem_start.  But fbdev suffers from the problem that
1352                  * it needs an API which doesn't exist (in this case,
1353                  * dma_writecombine_mmap)
1354                  */
1355                 fbi->fb.fix.smem_start = fbi->screen_dma;
1356         }
1357
1358         return fbi->map_cpu ? 0 : -ENOMEM;
1359 }
1360
1361 /* Fake monspecs to fill in fbinfo structure */
1362 static struct fb_monspecs monspecs __initdata = {
1363         .hfmin  = 30000,
1364         .hfmax  = 70000,
1365         .vfmin  = 50,
1366         .vfmax  = 65,
1367 };
1368
1369
1370 static struct sa1100fb_info * __init sa1100fb_init_fbinfo(struct device *dev)
1371 {
1372         struct sa1100fb_mach_info *inf;
1373         struct sa1100fb_info *fbi;
1374
1375         fbi = kmalloc(sizeof(struct sa1100fb_info) + sizeof(u32) * 16,
1376                       GFP_KERNEL);
1377         if (!fbi)
1378                 return NULL;
1379
1380         memset(fbi, 0, sizeof(struct sa1100fb_info));
1381         fbi->dev = dev;
1382
1383         strcpy(fbi->fb.fix.id, SA1100_NAME);
1384
1385         fbi->fb.fix.type        = FB_TYPE_PACKED_PIXELS;
1386         fbi->fb.fix.type_aux    = 0;
1387         fbi->fb.fix.xpanstep    = 0;
1388         fbi->fb.fix.ypanstep    = 0;
1389         fbi->fb.fix.ywrapstep   = 0;
1390         fbi->fb.fix.accel       = FB_ACCEL_NONE;
1391
1392         fbi->fb.var.nonstd      = 0;
1393         fbi->fb.var.activate    = FB_ACTIVATE_NOW;
1394         fbi->fb.var.height      = -1;
1395         fbi->fb.var.width       = -1;
1396         fbi->fb.var.accel_flags = 0;
1397         fbi->fb.var.vmode       = FB_VMODE_NONINTERLACED;
1398
1399         fbi->fb.fbops           = &sa1100fb_ops;
1400         fbi->fb.flags           = FBINFO_DEFAULT;
1401         fbi->fb.monspecs        = monspecs;
1402         fbi->fb.pseudo_palette  = (fbi + 1);
1403
1404         fbi->rgb[RGB_8]         = &rgb_8;
1405         fbi->rgb[RGB_16]        = &def_rgb_16;
1406
1407         inf = sa1100fb_get_machine_info(fbi);
1408
1409         /*
1410          * People just don't seem to get this.  We don't support
1411          * anything but correct entries now, so panic if someone
1412          * does something stupid.
1413          */
1414         if (inf->lccr3 & (LCCR3_VrtSnchL|LCCR3_HorSnchL|0xff) ||
1415             inf->pixclock == 0)
1416                 panic("sa1100fb error: invalid LCCR3 fields set or zero "
1417                         "pixclock.");
1418
1419         fbi->max_xres                   = inf->xres;
1420         fbi->fb.var.xres                = inf->xres;
1421         fbi->fb.var.xres_virtual        = inf->xres;
1422         fbi->max_yres                   = inf->yres;
1423         fbi->fb.var.yres                = inf->yres;
1424         fbi->fb.var.yres_virtual        = inf->yres;
1425         fbi->max_bpp                    = inf->bpp;
1426         fbi->fb.var.bits_per_pixel      = inf->bpp;
1427         fbi->fb.var.pixclock            = inf->pixclock;
1428         fbi->fb.var.hsync_len           = inf->hsync_len;
1429         fbi->fb.var.left_margin         = inf->left_margin;
1430         fbi->fb.var.right_margin        = inf->right_margin;
1431         fbi->fb.var.vsync_len           = inf->vsync_len;
1432         fbi->fb.var.upper_margin        = inf->upper_margin;
1433         fbi->fb.var.lower_margin        = inf->lower_margin;
1434         fbi->fb.var.sync                = inf->sync;
1435         fbi->fb.var.grayscale           = inf->cmap_greyscale;
1436         fbi->cmap_inverse               = inf->cmap_inverse;
1437         fbi->cmap_static                = inf->cmap_static;
1438         fbi->lccr0                      = inf->lccr0;
1439         fbi->lccr3                      = inf->lccr3;
1440         fbi->state                      = C_STARTUP;
1441         fbi->task_state                 = (u_char)-1;
1442         fbi->fb.fix.smem_len            = fbi->max_xres * fbi->max_yres *
1443                                           fbi->max_bpp / 8;
1444
1445         init_waitqueue_head(&fbi->ctrlr_wait);
1446         INIT_WORK(&fbi->task, sa1100fb_task);
1447         init_MUTEX(&fbi->ctrlr_sem);
1448
1449         return fbi;
1450 }
1451
1452 static int __init sa1100fb_probe(struct platform_device *pdev)
1453 {
1454         struct sa1100fb_info *fbi;
1455         int ret, irq;
1456
1457         irq = platform_get_irq(pdev, 0);
1458         if (irq < 0)
1459                 return -EINVAL;
1460
1461         if (!request_mem_region(0xb0100000, 0x10000, "LCD"))
1462                 return -EBUSY;
1463
1464         fbi = sa1100fb_init_fbinfo(&pdev->dev);
1465         ret = -ENOMEM;
1466         if (!fbi)
1467                 goto failed;
1468
1469         /* Initialize video memory */
1470         ret = sa1100fb_map_video_memory(fbi);
1471         if (ret)
1472                 goto failed;
1473
1474         ret = request_irq(irq, sa1100fb_handle_irq, IRQF_DISABLED,
1475                           "LCD", fbi);
1476         if (ret) {
1477                 printk(KERN_ERR "sa1100fb: request_irq failed: %d\n", ret);
1478                 goto failed;
1479         }
1480
1481 #ifdef ASSABET_PAL_VIDEO
1482         if (machine_is_assabet())
1483                 ASSABET_BCR_clear(ASSABET_BCR_LCD_ON);
1484 #endif
1485
1486         /*
1487          * This makes sure that our colour bitfield
1488          * descriptors are correctly initialised.
1489          */
1490         sa1100fb_check_var(&fbi->fb.var, &fbi->fb);
1491
1492         platform_set_drvdata(pdev, fbi);
1493
1494         ret = register_framebuffer(&fbi->fb);
1495         if (ret < 0)
1496                 goto err_free_irq;
1497
1498 #ifdef CONFIG_CPU_FREQ
1499         fbi->freq_transition.notifier_call = sa1100fb_freq_transition;
1500         fbi->freq_policy.notifier_call = sa1100fb_freq_policy;
1501         cpufreq_register_notifier(&fbi->freq_transition, CPUFREQ_TRANSITION_NOTIFIER);
1502         cpufreq_register_notifier(&fbi->freq_policy, CPUFREQ_POLICY_NOTIFIER);
1503 #endif
1504
1505         /* This driver cannot be unloaded at the moment */
1506         return 0;
1507
1508  err_free_irq:
1509         free_irq(irq, fbi);
1510  failed:
1511         platform_set_drvdata(pdev, NULL);
1512         kfree(fbi);
1513         release_mem_region(0xb0100000, 0x10000);
1514         return ret;
1515 }
1516
1517 static struct platform_driver sa1100fb_driver = {
1518         .probe          = sa1100fb_probe,
1519         .suspend        = sa1100fb_suspend,
1520         .resume         = sa1100fb_resume,
1521         .driver         = {
1522                 .name   = "sa11x0-fb",
1523         },
1524 };
1525
1526 int __init sa1100fb_init(void)
1527 {
1528         if (fb_get_options("sa1100fb", NULL))
1529                 return -ENODEV;
1530
1531         return platform_driver_register(&sa1100fb_driver);
1532 }
1533
1534 int __init sa1100fb_setup(char *options)
1535 {
1536 #if 0
1537         char *this_opt;
1538
1539         if (!options || !*options)
1540                 return 0;
1541
1542         while ((this_opt = strsep(&options, ",")) != NULL) {
1543
1544                 if (!strncmp(this_opt, "bpp:", 4))
1545                         current_par.max_bpp =
1546                             simple_strtoul(this_opt + 4, NULL, 0);
1547
1548                 if (!strncmp(this_opt, "lccr0:", 6))
1549                         lcd_shadow.lccr0 =
1550                             simple_strtoul(this_opt + 6, NULL, 0);
1551                 if (!strncmp(this_opt, "lccr1:", 6)) {
1552                         lcd_shadow.lccr1 =
1553                             simple_strtoul(this_opt + 6, NULL, 0);
1554                         current_par.max_xres =
1555                             (lcd_shadow.lccr1 & 0x3ff) + 16;
1556                 }
1557                 if (!strncmp(this_opt, "lccr2:", 6)) {
1558                         lcd_shadow.lccr2 =
1559                             simple_strtoul(this_opt + 6, NULL, 0);
1560                         current_par.max_yres =
1561                             (lcd_shadow.
1562                              lccr0 & LCCR0_SDS) ? ((lcd_shadow.
1563                                                     lccr2 & 0x3ff) +
1564                                                    1) *
1565                             2 : ((lcd_shadow.lccr2 & 0x3ff) + 1);
1566                 }
1567                 if (!strncmp(this_opt, "lccr3:", 6))
1568                         lcd_shadow.lccr3 =
1569                             simple_strtoul(this_opt + 6, NULL, 0);
1570         }
1571 #endif
1572         return 0;
1573 }
1574
1575 module_init(sa1100fb_init);
1576 MODULE_DESCRIPTION("StrongARM-1100/1110 framebuffer driver");
1577 MODULE_LICENSE("GPL");