2 * linux/drivers/video/sa1100fb.c
4 * Copyright (C) 1999 Eric A. Thomas
5 * Based on acornfb.c Copyright (C) Russell King.
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file COPYING in the main directory of this archive for
11 * StrongARM 1100 LCD Controller Frame Buffer Driver
13 * Please direct your questions and comments on this driver to the following
16 * linux-arm-kernel@lists.arm.linux.org.uk
18 * Clean patches should be sent to the ARM Linux Patch System. Please see the
19 * following web page for more information:
21 * http://www.arm.linux.org.uk/developer/patches/info.shtml
26 * - With the Neponset plugged into an Assabet, LCD powerdown
27 * doesn't work (LCD stays powered up). Therefore we shouldn't
29 * - We don't limit the CPU clock rate nor the mode selection
30 * according to the available SDRAM bandwidth.
33 * - Linear grayscale palettes and the kernel.
34 * Such code does not belong in the kernel. The kernel frame buffer
35 * drivers do not expect a linear colourmap, but a colourmap based on
36 * the VT100 standard mapping.
38 * If your _userspace_ requires a linear colourmap, then the setup of
39 * such a colourmap belongs _in userspace_, not in the kernel. Code
40 * to set the colourmap correctly from user space has been sent to
41 * David Neuer. It's around 8 lines of C code, plus another 4 to
42 * detect if we are using grayscale.
44 * - The following must never be specified in a panel definition:
45 * LCCR0_LtlEnd, LCCR3_PixClkDiv, LCCR3_VrtSnchL, LCCR3_HorSnchL
47 * - The following should be specified:
48 * either LCCR0_Color or LCCR0_Mono
49 * either LCCR0_Sngl or LCCR0_Dual
50 * either LCCR0_Act or LCCR0_Pas
51 * either LCCR3_OutEnH or LCCD3_OutEnL
52 * either LCCR3_PixRsEdg or LCCR3_PixFlEdg
53 * either LCCR3_ACBsDiv or LCCR3_ACBsCntOff
57 * - Driver appears to be working for Brutus 320x200x8bpp mode. Other
58 * resolutions are working, but only the 8bpp mode is supported.
59 * Changes need to be made to the palette encode and decode routines
60 * to support 4 and 16 bpp modes.
61 * Driver is not designed to be a module. The FrameBuffer is statically
62 * allocated since dynamic allocation of a 300k buffer cannot be
66 * - FrameBuffer memory is now allocated at run-time when the
67 * driver is initialized.
69 * 2000/04/10: Nicolas Pitre <nico@fluxnic.net>
70 * - Big cleanup for dynamic selection of machine type at run time.
72 * 2000/07/19: Jamey Hicks <jamey@crl.dec.com>
73 * - Support for Bitsy aka Compaq iPAQ H3600 added.
75 * 2000/08/07: Tak-Shing Chan <tchan.rd@idthk.com>
76 * Jeff Sutherland <jsutherland@accelent.com>
77 * - Resolved an issue caused by a change made to the Assabet's PLD
78 * earlier this year which broke the framebuffer driver for newer
79 * Phase 4 Assabets. Some other parameters were changed to optimize
80 * for the Sharp display.
82 * 2000/08/09: Kunihiko IMAI <imai@vasara.co.jp>
83 * - XP860 support added
85 * 2000/08/19: Mark Huang <mhuang@livetoy.com>
86 * - Allows standard options to be passed on the kernel command line
87 * for most common passive displays.
90 * - s/save_flags_cli/local_irq_save/
91 * - remove unneeded extra save_flags_cli in sa1100fb_enable_lcd_controller
93 * 2000/10/10: Erik Mouw <J.A.K.Mouw@its.tudelft.nl>
94 * - Updated LART stuff. Fixed some minor bugs.
96 * 2000/10/30: Murphy Chen <murphy@mail.dialogue.com.tw>
97 * - Pangolin support added
99 * 2000/10/31: Roman Jordan <jor@hoeft-wessel.de>
100 * - Huw Webpanel support added
102 * 2000/11/23: Eric Peng <ericpeng@coventive.com>
105 * 2001/02/07: Jamey Hicks <jamey.hicks@compaq.com>
106 * Cliff Brake <cbrake@accelent.com>
107 * - Added PM callback
109 * 2001/05/26: <rmk@arm.linux.org.uk>
110 * - Fix 16bpp so that (a) we use the right colours rather than some
111 * totally random colour depending on what was in page 0, and (b)
112 * we don't de-reference a NULL pointer.
113 * - remove duplicated implementation of consistent_alloc()
114 * - convert dma address types to dma_addr_t
115 * - remove unused 'montype' stuff
116 * - remove redundant zero inits of init_var after the initial
118 * - remove allow_modeset (acornfb idea does not belong here)
120 * 2001/05/28: <rmk@arm.linux.org.uk>
121 * - massive cleanup - move machine dependent data into structures
122 * - I've left various #warnings in - if you see one, and know
123 * the hardware concerned, please get in contact with me.
125 * 2001/05/31: <rmk@arm.linux.org.uk>
126 * - Fix LCCR1 HSW value, fix all machine type specifications to
127 * keep values in line. (Please check your machine type specs)
129 * 2001/06/10: <rmk@arm.linux.org.uk>
130 * - Fiddle with the LCD controller from task context only; mainly
131 * so that we can run with interrupts on, and sleep.
132 * - Convert #warnings into #errors. No pain, no gain. ;)
134 * 2001/06/14: <rmk@arm.linux.org.uk>
135 * - Make the palette BPS value for 12bpp come out correctly.
136 * - Take notice of "greyscale" on any colour depth.
137 * - Make truecolor visuals use the RGB channel encoding information.
139 * 2001/07/02: <rmk@arm.linux.org.uk>
140 * - Fix colourmap problems.
142 * 2001/07/13: <abraham@2d3d.co.za>
143 * - Added support for the ICP LCD-Kit01 on LART. This LCD is
144 * manufactured by Prime View, model no V16C6448AB
146 * 2001/07/23: <rmk@arm.linux.org.uk>
147 * - Hand merge version from handhelds.org CVS tree. See patch
148 * notes for 595/1 for more information.
149 * - Drop 12bpp (it's 16bpp with different colour register mappings).
150 * - This hardware can not do direct colour. Therefore we don't
153 * 2001/07/27: <rmk@arm.linux.org.uk>
154 * - Halve YRES on dual scan LCDs.
156 * 2001/08/22: <rmk@arm.linux.org.uk>
157 * - Add b/w iPAQ pixclock value.
159 * 2001/10/12: <rmk@arm.linux.org.uk>
160 * - Add patch 681/1 and clean up stork definitions.
163 #include <linux/module.h>
164 #include <linux/kernel.h>
165 #include <linux/sched.h>
166 #include <linux/errno.h>
167 #include <linux/string.h>
168 #include <linux/interrupt.h>
169 #include <linux/slab.h>
170 #include <linux/mm.h>
171 #include <linux/fb.h>
172 #include <linux/delay.h>
173 #include <linux/init.h>
174 #include <linux/ioport.h>
175 #include <linux/cpufreq.h>
176 #include <linux/platform_device.h>
177 #include <linux/dma-mapping.h>
178 #include <linux/mutex.h>
179 #include <linux/io.h>
181 #include <video/sa1100fb.h>
183 #include <mach/hardware.h>
184 #include <asm/mach-types.h>
185 #include <mach/shannon.h>
188 * Complain if VAR is out of range.
192 #include "sa1100fb.h"
194 static const struct sa1100fb_rgb rgb_4 = {
195 .red = { .offset = 0, .length = 4, },
196 .green = { .offset = 0, .length = 4, },
197 .blue = { .offset = 0, .length = 4, },
198 .transp = { .offset = 0, .length = 0, },
201 static const struct sa1100fb_rgb rgb_8 = {
202 .red = { .offset = 0, .length = 8, },
203 .green = { .offset = 0, .length = 8, },
204 .blue = { .offset = 0, .length = 8, },
205 .transp = { .offset = 0, .length = 0, },
208 static const struct sa1100fb_rgb def_rgb_16 = {
209 .red = { .offset = 11, .length = 5, },
210 .green = { .offset = 5, .length = 6, },
211 .blue = { .offset = 0, .length = 5, },
212 .transp = { .offset = 0, .length = 0, },
217 static int sa1100fb_activate_var(struct fb_var_screeninfo *var, struct sa1100fb_info *);
218 static void set_ctrlr_state(struct sa1100fb_info *fbi, u_int state);
220 static inline void sa1100fb_schedule_work(struct sa1100fb_info *fbi, u_int state)
224 local_irq_save(flags);
226 * We need to handle two requests being made at the same time.
227 * There are two important cases:
228 * 1. When we are changing VT (C_REENABLE) while unblanking (C_ENABLE)
229 * We must perform the unblanking, which will do our REENABLE for us.
230 * 2. When we are blanking, but immediately unblank before we have
231 * blanked. We do the "REENABLE" thing here as well, just to be sure.
233 if (fbi->task_state == C_ENABLE && state == C_REENABLE)
235 if (fbi->task_state == C_DISABLE && state == C_ENABLE)
238 if (state != (u_int)-1) {
239 fbi->task_state = state;
240 schedule_work(&fbi->task);
242 local_irq_restore(flags);
245 static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
248 chan >>= 16 - bf->length;
249 return chan << bf->offset;
253 * Convert bits-per-pixel to a hardware palette PBS value.
255 static inline u_int palette_pbs(struct fb_var_screeninfo *var)
258 switch (var->bits_per_pixel) {
259 case 4: ret = 0 << 12; break;
260 case 8: ret = 1 << 12; break;
261 case 16: ret = 2 << 12; break;
267 sa1100fb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
268 u_int trans, struct fb_info *info)
270 struct sa1100fb_info *fbi = (struct sa1100fb_info *)info;
273 if (regno < fbi->palette_size) {
274 val = ((red >> 4) & 0xf00);
275 val |= ((green >> 8) & 0x0f0);
276 val |= ((blue >> 12) & 0x00f);
279 val |= palette_pbs(&fbi->fb.var);
281 fbi->palette_cpu[regno] = val;
288 sa1100fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
289 u_int trans, struct fb_info *info)
291 struct sa1100fb_info *fbi = (struct sa1100fb_info *)info;
296 * If inverse mode was selected, invert all the colours
297 * rather than the register number. The register number
298 * is what you poke into the framebuffer to produce the
299 * colour you requested.
301 if (fbi->inf->cmap_inverse) {
303 green = 0xffff - green;
304 blue = 0xffff - blue;
308 * If greyscale is true, then we convert the RGB value
309 * to greyscale no mater what visual we are using.
311 if (fbi->fb.var.grayscale)
312 red = green = blue = (19595 * red + 38470 * green +
315 switch (fbi->fb.fix.visual) {
316 case FB_VISUAL_TRUECOLOR:
318 * 12 or 16-bit True Colour. We encode the RGB value
319 * according to the RGB bitfield information.
322 u32 *pal = fbi->fb.pseudo_palette;
324 val = chan_to_field(red, &fbi->fb.var.red);
325 val |= chan_to_field(green, &fbi->fb.var.green);
326 val |= chan_to_field(blue, &fbi->fb.var.blue);
333 case FB_VISUAL_STATIC_PSEUDOCOLOR:
334 case FB_VISUAL_PSEUDOCOLOR:
335 ret = sa1100fb_setpalettereg(regno, red, green, blue, trans, info);
342 #ifdef CONFIG_CPU_FREQ
344 * sa1100fb_display_dma_period()
345 * Calculate the minimum period (in picoseconds) between two DMA
346 * requests for the LCD controller. If we hit this, it means we're
347 * doing nothing but LCD DMA.
349 static inline unsigned int sa1100fb_display_dma_period(struct fb_var_screeninfo *var)
352 * Period = pixclock * bits_per_byte * bytes_per_transfer
353 * / memory_bits_per_pixel;
355 return var->pixclock * 8 * 16 / var->bits_per_pixel;
360 * sa1100fb_check_var():
361 * Round up in the following order: bits_per_pixel, xres,
362 * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
363 * bitfields, horizontal timing, vertical timing.
366 sa1100fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
368 struct sa1100fb_info *fbi = (struct sa1100fb_info *)info;
371 if (var->xres < MIN_XRES)
372 var->xres = MIN_XRES;
373 if (var->yres < MIN_YRES)
374 var->yres = MIN_YRES;
375 if (var->xres > fbi->inf->xres)
376 var->xres = fbi->inf->xres;
377 if (var->yres > fbi->inf->yres)
378 var->yres = fbi->inf->yres;
379 var->xres_virtual = max(var->xres_virtual, var->xres);
380 var->yres_virtual = max(var->yres_virtual, var->yres);
382 dev_dbg(fbi->dev, "var->bits_per_pixel=%d\n", var->bits_per_pixel);
383 switch (var->bits_per_pixel) {
398 * Copy the RGB parameters for this display
399 * from the machine specific parameters.
401 var->red = fbi->rgb[rgbidx]->red;
402 var->green = fbi->rgb[rgbidx]->green;
403 var->blue = fbi->rgb[rgbidx]->blue;
404 var->transp = fbi->rgb[rgbidx]->transp;
406 dev_dbg(fbi->dev, "RGBT length = %d:%d:%d:%d\n",
407 var->red.length, var->green.length, var->blue.length,
410 dev_dbg(fbi->dev, "RGBT offset = %d:%d:%d:%d\n",
411 var->red.offset, var->green.offset, var->blue.offset,
414 #ifdef CONFIG_CPU_FREQ
415 dev_dbg(fbi->dev, "dma period = %d ps, clock = %d kHz\n",
416 sa1100fb_display_dma_period(var),
417 cpufreq_get(smp_processor_id()));
423 static void sa1100fb_set_visual(struct sa1100fb_info *fbi, u32 visual)
425 if (fbi->inf->set_visual)
426 fbi->inf->set_visual(visual);
430 * sa1100fb_set_par():
431 * Set the user defined part of the display for the specified console
433 static int sa1100fb_set_par(struct fb_info *info)
435 struct sa1100fb_info *fbi = (struct sa1100fb_info *)info;
436 struct fb_var_screeninfo *var = &info->var;
437 unsigned long palette_mem_size;
439 dev_dbg(fbi->dev, "set_par\n");
441 if (var->bits_per_pixel == 16)
442 fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
443 else if (!fbi->inf->cmap_static)
444 fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
447 * Some people have weird ideas about wanting static
448 * pseudocolor maps. I suspect their user space
449 * applications are broken.
451 fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
454 fbi->fb.fix.line_length = var->xres_virtual *
455 var->bits_per_pixel / 8;
456 fbi->palette_size = var->bits_per_pixel == 8 ? 256 : 16;
458 palette_mem_size = fbi->palette_size * sizeof(u16);
460 dev_dbg(fbi->dev, "palette_mem_size = 0x%08lx\n", palette_mem_size);
462 fbi->palette_cpu = (u16 *)(fbi->map_cpu + PAGE_SIZE - palette_mem_size);
463 fbi->palette_dma = fbi->map_dma + PAGE_SIZE - palette_mem_size;
466 * Set (any) board control register to handle new color depth
468 sa1100fb_set_visual(fbi, fbi->fb.fix.visual);
469 sa1100fb_activate_var(var, fbi);
476 sa1100fb_set_cmap(struct fb_cmap *cmap, int kspc, int con,
477 struct fb_info *info)
479 struct sa1100fb_info *fbi = (struct sa1100fb_info *)info;
482 * Make sure the user isn't doing something stupid.
484 if (!kspc && (fbi->fb.var.bits_per_pixel == 16 || fbi->inf->cmap_static))
487 return gen_set_cmap(cmap, kspc, con, info);
492 * Formal definition of the VESA spec:
494 * This refers to the state of the display when it is in full operation
496 * This defines an optional operating state of minimal power reduction with
497 * the shortest recovery time
499 * This refers to a level of power management in which substantial power
500 * reduction is achieved by the display. The display can have a longer
501 * recovery time from this state than from the Stand-by state
503 * This indicates that the display is consuming the lowest level of power
504 * and is non-operational. Recovery from this state may optionally require
505 * the user to manually power on the monitor
507 * Now, the fbdev driver adds an additional state, (blank), where they
508 * turn off the video (maybe by colormap tricks), but don't mess with the
509 * video itself: think of it semantically between on and Stand-By.
511 * So here's what we should do in our fbdev blank routine:
513 * VESA_NO_BLANKING (mode 0) Video on, front/back light on
514 * VESA_VSYNC_SUSPEND (mode 1) Video on, front/back light off
515 * VESA_HSYNC_SUSPEND (mode 2) Video on, front/back light off
516 * VESA_POWERDOWN (mode 3) Video off, front/back light off
518 * This will match the matrox implementation.
522 * Blank the display by setting all palette values to zero. Note, the
523 * 12 and 16 bpp modes don't really use the palette, so this will not
524 * blank the display in all modes.
526 static int sa1100fb_blank(int blank, struct fb_info *info)
528 struct sa1100fb_info *fbi = (struct sa1100fb_info *)info;
531 dev_dbg(fbi->dev, "sa1100fb_blank: blank=%d\n", blank);
534 case FB_BLANK_POWERDOWN:
535 case FB_BLANK_VSYNC_SUSPEND:
536 case FB_BLANK_HSYNC_SUSPEND:
537 case FB_BLANK_NORMAL:
538 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
539 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
540 for (i = 0; i < fbi->palette_size; i++)
541 sa1100fb_setpalettereg(i, 0, 0, 0, 0, info);
542 sa1100fb_schedule_work(fbi, C_DISABLE);
545 case FB_BLANK_UNBLANK:
546 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
547 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
548 fb_set_cmap(&fbi->fb.cmap, info);
549 sa1100fb_schedule_work(fbi, C_ENABLE);
554 static int sa1100fb_mmap(struct fb_info *info,
555 struct vm_area_struct *vma)
557 struct sa1100fb_info *fbi = (struct sa1100fb_info *)info;
558 unsigned long start, len, off = vma->vm_pgoff << PAGE_SHIFT;
560 if (off < info->fix.smem_len) {
561 vma->vm_pgoff += 1; /* skip over the palette */
562 return dma_mmap_writecombine(fbi->dev, vma, fbi->map_cpu,
563 fbi->map_dma, fbi->map_size);
566 start = info->fix.mmio_start;
567 len = PAGE_ALIGN((start & ~PAGE_MASK) + info->fix.mmio_len);
569 if ((vma->vm_end - vma->vm_start + off) > len)
572 off += start & PAGE_MASK;
573 vma->vm_pgoff = off >> PAGE_SHIFT;
574 vma->vm_flags |= VM_IO;
575 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
576 return io_remap_pfn_range(vma, vma->vm_start, off >> PAGE_SHIFT,
577 vma->vm_end - vma->vm_start,
581 static struct fb_ops sa1100fb_ops = {
582 .owner = THIS_MODULE,
583 .fb_check_var = sa1100fb_check_var,
584 .fb_set_par = sa1100fb_set_par,
585 // .fb_set_cmap = sa1100fb_set_cmap,
586 .fb_setcolreg = sa1100fb_setcolreg,
587 .fb_fillrect = cfb_fillrect,
588 .fb_copyarea = cfb_copyarea,
589 .fb_imageblit = cfb_imageblit,
590 .fb_blank = sa1100fb_blank,
591 .fb_mmap = sa1100fb_mmap,
595 * Calculate the PCD value from the clock rate (in picoseconds).
596 * We take account of the PPCR clock setting.
598 static inline unsigned int get_pcd(unsigned int pixclock, unsigned int cpuclock)
600 unsigned int pcd = cpuclock / 100;
605 return pcd + 1; /* make up for integer math truncations */
609 * sa1100fb_activate_var():
610 * Configures LCD Controller based on entries in var parameter. Settings are
611 * only written to the controller if changes were made.
613 static int sa1100fb_activate_var(struct fb_var_screeninfo *var, struct sa1100fb_info *fbi)
615 struct sa1100fb_lcd_reg new_regs;
616 u_int half_screen_size, yres, pcd;
619 dev_dbg(fbi->dev, "Configuring SA1100 LCD\n");
621 dev_dbg(fbi->dev, "var: xres=%d hslen=%d lm=%d rm=%d\n",
622 var->xres, var->hsync_len,
623 var->left_margin, var->right_margin);
624 dev_dbg(fbi->dev, "var: yres=%d vslen=%d um=%d bm=%d\n",
625 var->yres, var->vsync_len,
626 var->upper_margin, var->lower_margin);
629 if (var->xres < 16 || var->xres > 1024)
630 dev_err(fbi->dev, "%s: invalid xres %d\n",
631 fbi->fb.fix.id, var->xres);
632 if (var->hsync_len < 1 || var->hsync_len > 64)
633 dev_err(fbi->dev, "%s: invalid hsync_len %d\n",
634 fbi->fb.fix.id, var->hsync_len);
635 if (var->left_margin < 1 || var->left_margin > 255)
636 dev_err(fbi->dev, "%s: invalid left_margin %d\n",
637 fbi->fb.fix.id, var->left_margin);
638 if (var->right_margin < 1 || var->right_margin > 255)
639 dev_err(fbi->dev, "%s: invalid right_margin %d\n",
640 fbi->fb.fix.id, var->right_margin);
641 if (var->yres < 1 || var->yres > 1024)
642 dev_err(fbi->dev, "%s: invalid yres %d\n",
643 fbi->fb.fix.id, var->yres);
644 if (var->vsync_len < 1 || var->vsync_len > 64)
645 dev_err(fbi->dev, "%s: invalid vsync_len %d\n",
646 fbi->fb.fix.id, var->vsync_len);
647 if (var->upper_margin < 0 || var->upper_margin > 255)
648 dev_err(fbi->dev, "%s: invalid upper_margin %d\n",
649 fbi->fb.fix.id, var->upper_margin);
650 if (var->lower_margin < 0 || var->lower_margin > 255)
651 dev_err(fbi->dev, "%s: invalid lower_margin %d\n",
652 fbi->fb.fix.id, var->lower_margin);
655 new_regs.lccr0 = fbi->inf->lccr0 |
656 LCCR0_LEN | LCCR0_LDM | LCCR0_BAM |
657 LCCR0_ERM | LCCR0_LtlEnd | LCCR0_DMADel(0);
660 LCCR1_DisWdth(var->xres) +
661 LCCR1_HorSnchWdth(var->hsync_len) +
662 LCCR1_BegLnDel(var->left_margin) +
663 LCCR1_EndLnDel(var->right_margin);
666 * If we have a dual scan LCD, then we need to halve
667 * the YRES parameter.
670 if (fbi->inf->lccr0 & LCCR0_Dual)
674 LCCR2_DisHght(yres) +
675 LCCR2_VrtSnchWdth(var->vsync_len) +
676 LCCR2_BegFrmDel(var->upper_margin) +
677 LCCR2_EndFrmDel(var->lower_margin);
679 pcd = get_pcd(var->pixclock, cpufreq_get(0));
680 new_regs.lccr3 = LCCR3_PixClkDiv(pcd) | fbi->inf->lccr3 |
681 (var->sync & FB_SYNC_HOR_HIGH_ACT ? LCCR3_HorSnchH : LCCR3_HorSnchL) |
682 (var->sync & FB_SYNC_VERT_HIGH_ACT ? LCCR3_VrtSnchH : LCCR3_VrtSnchL);
684 dev_dbg(fbi->dev, "nlccr0 = 0x%08lx\n", new_regs.lccr0);
685 dev_dbg(fbi->dev, "nlccr1 = 0x%08lx\n", new_regs.lccr1);
686 dev_dbg(fbi->dev, "nlccr2 = 0x%08lx\n", new_regs.lccr2);
687 dev_dbg(fbi->dev, "nlccr3 = 0x%08lx\n", new_regs.lccr3);
689 half_screen_size = var->bits_per_pixel;
690 half_screen_size = half_screen_size * var->xres * var->yres / 16;
692 /* Update shadow copy atomically */
693 local_irq_save(flags);
694 fbi->dbar1 = fbi->palette_dma;
695 fbi->dbar2 = fbi->screen_dma + half_screen_size;
697 fbi->reg_lccr0 = new_regs.lccr0;
698 fbi->reg_lccr1 = new_regs.lccr1;
699 fbi->reg_lccr2 = new_regs.lccr2;
700 fbi->reg_lccr3 = new_regs.lccr3;
701 local_irq_restore(flags);
704 * Only update the registers if the controller is enabled
705 * and something has changed.
707 if ((LCCR0 != fbi->reg_lccr0) || (LCCR1 != fbi->reg_lccr1) ||
708 (LCCR2 != fbi->reg_lccr2) || (LCCR3 != fbi->reg_lccr3) ||
709 (DBAR1 != fbi->dbar1) || (DBAR2 != fbi->dbar2))
710 sa1100fb_schedule_work(fbi, C_REENABLE);
716 * NOTE! The following functions are purely helpers for set_ctrlr_state.
717 * Do not call them directly; set_ctrlr_state does the correct serialisation
718 * to ensure that things happen in the right way 100% of time time.
721 static inline void __sa1100fb_backlight_power(struct sa1100fb_info *fbi, int on)
723 dev_dbg(fbi->dev, "backlight o%s\n", on ? "n" : "ff");
725 if (fbi->inf->backlight_power)
726 fbi->inf->backlight_power(on);
729 static inline void __sa1100fb_lcd_power(struct sa1100fb_info *fbi, int on)
731 dev_dbg(fbi->dev, "LCD power o%s\n", on ? "n" : "ff");
733 if (fbi->inf->lcd_power)
734 fbi->inf->lcd_power(on);
737 static void sa1100fb_setup_gpio(struct sa1100fb_info *fbi)
742 * Enable GPIO<9:2> for LCD use if:
743 * 1. Active display, or
744 * 2. Color Dual Passive display
746 * see table 11.8 on page 11-27 in the SA1100 manual
749 * SA1110 spec update nr. 25 says we can and should
750 * clear LDD15 to 12 for 4 or 8bpp modes with active
753 if ((fbi->reg_lccr0 & LCCR0_CMS) == LCCR0_Color &&
754 (fbi->reg_lccr0 & (LCCR0_Dual|LCCR0_Act)) != 0) {
755 mask = GPIO_LDD11 | GPIO_LDD10 | GPIO_LDD9 | GPIO_LDD8;
757 if (fbi->fb.var.bits_per_pixel > 8 ||
758 (fbi->reg_lccr0 & (LCCR0_Dual|LCCR0_Act)) == LCCR0_Dual)
759 mask |= GPIO_LDD15 | GPIO_LDD14 | GPIO_LDD13 | GPIO_LDD12;
769 static void sa1100fb_enable_controller(struct sa1100fb_info *fbi)
771 dev_dbg(fbi->dev, "Enabling LCD controller\n");
774 * Make sure the mode bits are present in the first palette entry
776 fbi->palette_cpu[0] &= 0xcfff;
777 fbi->palette_cpu[0] |= palette_pbs(&fbi->fb.var);
779 /* Sequence from 11.7.10 */
780 LCCR3 = fbi->reg_lccr3;
781 LCCR2 = fbi->reg_lccr2;
782 LCCR1 = fbi->reg_lccr1;
783 LCCR0 = fbi->reg_lccr0 & ~LCCR0_LEN;
788 if (machine_is_shannon()) {
789 GPDR |= SHANNON_GPIO_DISP_EN;
790 GPSR |= SHANNON_GPIO_DISP_EN;
793 dev_dbg(fbi->dev, "DBAR1 = 0x%08lx\n", DBAR1);
794 dev_dbg(fbi->dev, "DBAR2 = 0x%08lx\n", DBAR2);
795 dev_dbg(fbi->dev, "LCCR0 = 0x%08lx\n", LCCR0);
796 dev_dbg(fbi->dev, "LCCR1 = 0x%08lx\n", LCCR1);
797 dev_dbg(fbi->dev, "LCCR2 = 0x%08lx\n", LCCR2);
798 dev_dbg(fbi->dev, "LCCR3 = 0x%08lx\n", LCCR3);
801 static void sa1100fb_disable_controller(struct sa1100fb_info *fbi)
803 DECLARE_WAITQUEUE(wait, current);
805 dev_dbg(fbi->dev, "Disabling LCD controller\n");
807 if (machine_is_shannon()) {
808 GPCR |= SHANNON_GPIO_DISP_EN;
811 set_current_state(TASK_UNINTERRUPTIBLE);
812 add_wait_queue(&fbi->ctrlr_wait, &wait);
814 LCSR = 0xffffffff; /* Clear LCD Status Register */
815 LCCR0 &= ~LCCR0_LDM; /* Enable LCD Disable Done Interrupt */
816 LCCR0 &= ~LCCR0_LEN; /* Disable LCD Controller */
818 schedule_timeout(20 * HZ / 1000);
819 remove_wait_queue(&fbi->ctrlr_wait, &wait);
823 * sa1100fb_handle_irq: Handle 'LCD DONE' interrupts.
825 static irqreturn_t sa1100fb_handle_irq(int irq, void *dev_id)
827 struct sa1100fb_info *fbi = dev_id;
828 unsigned int lcsr = LCSR;
830 if (lcsr & LCSR_LDD) {
832 wake_up(&fbi->ctrlr_wait);
840 * This function must be called from task context only, since it will
841 * sleep when disabling the LCD controller, or if we get two contending
842 * processes trying to alter state.
844 static void set_ctrlr_state(struct sa1100fb_info *fbi, u_int state)
848 mutex_lock(&fbi->ctrlr_lock);
850 old_state = fbi->state;
853 * Hack around fbcon initialisation.
855 if (old_state == C_STARTUP && state == C_REENABLE)
859 case C_DISABLE_CLKCHANGE:
861 * Disable controller for clock change. If the
862 * controller is already disabled, then do nothing.
864 if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
866 sa1100fb_disable_controller(fbi);
875 if (old_state != C_DISABLE) {
878 __sa1100fb_backlight_power(fbi, 0);
879 if (old_state != C_DISABLE_CLKCHANGE)
880 sa1100fb_disable_controller(fbi);
881 __sa1100fb_lcd_power(fbi, 0);
885 case C_ENABLE_CLKCHANGE:
887 * Enable the controller after clock change. Only
888 * do this if we were disabled for the clock change.
890 if (old_state == C_DISABLE_CLKCHANGE) {
891 fbi->state = C_ENABLE;
892 sa1100fb_enable_controller(fbi);
898 * Re-enable the controller only if it was already
899 * enabled. This is so we reprogram the control
902 if (old_state == C_ENABLE) {
903 sa1100fb_disable_controller(fbi);
904 sa1100fb_setup_gpio(fbi);
905 sa1100fb_enable_controller(fbi);
911 * Re-enable the controller after PM. This is not
912 * perfect - think about the case where we were doing
913 * a clock change, and we suspended half-way through.
915 if (old_state != C_DISABLE_PM)
921 * Power up the LCD screen, enable controller, and
922 * turn on the backlight.
924 if (old_state != C_ENABLE) {
925 fbi->state = C_ENABLE;
926 sa1100fb_setup_gpio(fbi);
927 __sa1100fb_lcd_power(fbi, 1);
928 sa1100fb_enable_controller(fbi);
929 __sa1100fb_backlight_power(fbi, 1);
933 mutex_unlock(&fbi->ctrlr_lock);
937 * Our LCD controller task (which is called when we blank or unblank)
940 static void sa1100fb_task(struct work_struct *w)
942 struct sa1100fb_info *fbi = container_of(w, struct sa1100fb_info, task);
943 u_int state = xchg(&fbi->task_state, -1);
945 set_ctrlr_state(fbi, state);
948 #ifdef CONFIG_CPU_FREQ
950 * Calculate the minimum DMA period over all displays that we own.
951 * This, together with the SDRAM bandwidth defines the slowest CPU
952 * frequency that can be selected.
954 static unsigned int sa1100fb_min_dma_period(struct sa1100fb_info *fbi)
957 unsigned int min_period = (unsigned int)-1;
960 for (i = 0; i < MAX_NR_CONSOLES; i++) {
961 struct display *disp = &fb_display[i];
965 * Do we own this display?
967 if (disp->fb_info != &fbi->fb)
971 * Ok, calculate its DMA period
973 period = sa1100fb_display_dma_period(&disp->var);
974 if (period < min_period)
981 * FIXME: we need to verify _all_ consoles.
983 return sa1100fb_display_dma_period(&fbi->fb.var);
988 * CPU clock speed change handler. We need to adjust the LCD timing
989 * parameters when the CPU clock is adjusted by the power management
993 sa1100fb_freq_transition(struct notifier_block *nb, unsigned long val,
996 struct sa1100fb_info *fbi = TO_INF(nb, freq_transition);
997 struct cpufreq_freqs *f = data;
1001 case CPUFREQ_PRECHANGE:
1002 set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
1005 case CPUFREQ_POSTCHANGE:
1006 pcd = get_pcd(fbi->fb.var.pixclock, f->new);
1007 fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) | LCCR3_PixClkDiv(pcd);
1008 set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
1015 sa1100fb_freq_policy(struct notifier_block *nb, unsigned long val,
1018 struct sa1100fb_info *fbi = TO_INF(nb, freq_policy);
1019 struct cpufreq_policy *policy = data;
1022 case CPUFREQ_ADJUST:
1023 case CPUFREQ_INCOMPATIBLE:
1024 dev_dbg(fbi->dev, "min dma period: %d ps, "
1025 "new clock %d kHz\n", sa1100fb_min_dma_period(fbi),
1027 /* todo: fill in min/max values */
1029 case CPUFREQ_NOTIFY:
1031 /* todo: panic if min/max values aren't fulfilled
1032 * [can't really happen unless there's a bug in the
1033 * CPU policy verififcation process *
1043 * Power management hooks. Note that we won't be called from IRQ context,
1044 * unlike the blank functions above, so we may sleep.
1046 static int sa1100fb_suspend(struct platform_device *dev, pm_message_t state)
1048 struct sa1100fb_info *fbi = platform_get_drvdata(dev);
1050 set_ctrlr_state(fbi, C_DISABLE_PM);
1054 static int sa1100fb_resume(struct platform_device *dev)
1056 struct sa1100fb_info *fbi = platform_get_drvdata(dev);
1058 set_ctrlr_state(fbi, C_ENABLE_PM);
1062 #define sa1100fb_suspend NULL
1063 #define sa1100fb_resume NULL
1067 * sa1100fb_map_video_memory():
1068 * Allocates the DRAM memory for the frame buffer. This buffer is
1069 * remapped into a non-cached, non-buffered, memory region to
1070 * allow palette and pixel writes to occur without flushing the
1071 * cache. Once this area is remapped, all virtual memory
1072 * access to the video memory should occur at the new region.
1074 static int __devinit sa1100fb_map_video_memory(struct sa1100fb_info *fbi)
1077 * We reserve one page for the palette, plus the size
1078 * of the framebuffer.
1080 fbi->map_size = PAGE_ALIGN(fbi->fb.fix.smem_len + PAGE_SIZE);
1081 fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size,
1082 &fbi->map_dma, GFP_KERNEL);
1085 fbi->fb.screen_base = fbi->map_cpu + PAGE_SIZE;
1086 fbi->screen_dma = fbi->map_dma + PAGE_SIZE;
1088 * FIXME: this is actually the wrong thing to place in
1089 * smem_start. But fbdev suffers from the problem that
1090 * it needs an API which doesn't exist (in this case,
1091 * dma_writecombine_mmap)
1093 fbi->fb.fix.smem_start = fbi->screen_dma;
1096 return fbi->map_cpu ? 0 : -ENOMEM;
1099 /* Fake monspecs to fill in fbinfo structure */
1100 static struct fb_monspecs monspecs __devinitdata = {
1108 static struct sa1100fb_info * __devinit sa1100fb_init_fbinfo(struct device *dev)
1110 struct sa1100fb_mach_info *inf = dev->platform_data;
1111 struct sa1100fb_info *fbi;
1114 fbi = kmalloc(sizeof(struct sa1100fb_info) + sizeof(u32) * 16,
1119 memset(fbi, 0, sizeof(struct sa1100fb_info));
1122 strcpy(fbi->fb.fix.id, SA1100_NAME);
1124 fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS;
1125 fbi->fb.fix.type_aux = 0;
1126 fbi->fb.fix.xpanstep = 0;
1127 fbi->fb.fix.ypanstep = 0;
1128 fbi->fb.fix.ywrapstep = 0;
1129 fbi->fb.fix.accel = FB_ACCEL_NONE;
1131 fbi->fb.var.nonstd = 0;
1132 fbi->fb.var.activate = FB_ACTIVATE_NOW;
1133 fbi->fb.var.height = -1;
1134 fbi->fb.var.width = -1;
1135 fbi->fb.var.accel_flags = 0;
1136 fbi->fb.var.vmode = FB_VMODE_NONINTERLACED;
1138 fbi->fb.fbops = &sa1100fb_ops;
1139 fbi->fb.flags = FBINFO_DEFAULT;
1140 fbi->fb.monspecs = monspecs;
1141 fbi->fb.pseudo_palette = (fbi + 1);
1143 fbi->rgb[RGB_4] = &rgb_4;
1144 fbi->rgb[RGB_8] = &rgb_8;
1145 fbi->rgb[RGB_16] = &def_rgb_16;
1148 * People just don't seem to get this. We don't support
1149 * anything but correct entries now, so panic if someone
1150 * does something stupid.
1152 if (inf->lccr3 & (LCCR3_VrtSnchL|LCCR3_HorSnchL|0xff) ||
1154 panic("sa1100fb error: invalid LCCR3 fields set or zero "
1157 fbi->fb.var.xres = inf->xres;
1158 fbi->fb.var.xres_virtual = inf->xres;
1159 fbi->fb.var.yres = inf->yres;
1160 fbi->fb.var.yres_virtual = inf->yres;
1161 fbi->fb.var.bits_per_pixel = inf->bpp;
1162 fbi->fb.var.pixclock = inf->pixclock;
1163 fbi->fb.var.hsync_len = inf->hsync_len;
1164 fbi->fb.var.left_margin = inf->left_margin;
1165 fbi->fb.var.right_margin = inf->right_margin;
1166 fbi->fb.var.vsync_len = inf->vsync_len;
1167 fbi->fb.var.upper_margin = inf->upper_margin;
1168 fbi->fb.var.lower_margin = inf->lower_margin;
1169 fbi->fb.var.sync = inf->sync;
1170 fbi->fb.var.grayscale = inf->cmap_greyscale;
1171 fbi->state = C_STARTUP;
1172 fbi->task_state = (u_char)-1;
1173 fbi->fb.fix.smem_len = inf->xres * inf->yres *
1177 /* Copy the RGB bitfield overrides */
1178 for (i = 0; i < NR_RGB; i++)
1180 fbi->rgb[i] = inf->rgb[i];
1182 init_waitqueue_head(&fbi->ctrlr_wait);
1183 INIT_WORK(&fbi->task, sa1100fb_task);
1184 mutex_init(&fbi->ctrlr_lock);
1189 static int __devinit sa1100fb_probe(struct platform_device *pdev)
1191 struct sa1100fb_info *fbi;
1194 if (!pdev->dev.platform_data) {
1195 dev_err(&pdev->dev, "no platform LCD data\n");
1199 irq = platform_get_irq(pdev, 0);
1203 if (!request_mem_region(0xb0100000, 0x10000, "LCD"))
1206 fbi = sa1100fb_init_fbinfo(&pdev->dev);
1211 /* Initialize video memory */
1212 ret = sa1100fb_map_video_memory(fbi);
1216 ret = request_irq(irq, sa1100fb_handle_irq, 0, "LCD", fbi);
1218 dev_err(&pdev->dev, "request_irq failed: %d\n", ret);
1223 * This makes sure that our colour bitfield
1224 * descriptors are correctly initialised.
1226 sa1100fb_check_var(&fbi->fb.var, &fbi->fb);
1228 platform_set_drvdata(pdev, fbi);
1230 ret = register_framebuffer(&fbi->fb);
1234 #ifdef CONFIG_CPU_FREQ
1235 fbi->freq_transition.notifier_call = sa1100fb_freq_transition;
1236 fbi->freq_policy.notifier_call = sa1100fb_freq_policy;
1237 cpufreq_register_notifier(&fbi->freq_transition, CPUFREQ_TRANSITION_NOTIFIER);
1238 cpufreq_register_notifier(&fbi->freq_policy, CPUFREQ_POLICY_NOTIFIER);
1241 /* This driver cannot be unloaded at the moment */
1247 platform_set_drvdata(pdev, NULL);
1249 release_mem_region(0xb0100000, 0x10000);
1253 static struct platform_driver sa1100fb_driver = {
1254 .probe = sa1100fb_probe,
1255 .suspend = sa1100fb_suspend,
1256 .resume = sa1100fb_resume,
1258 .name = "sa11x0-fb",
1259 .owner = THIS_MODULE,
1263 int __init sa1100fb_init(void)
1265 if (fb_get_options("sa1100fb", NULL))
1268 return platform_driver_register(&sa1100fb_driver);
1271 int __init sa1100fb_setup(char *options)
1276 if (!options || !*options)
1279 while ((this_opt = strsep(&options, ",")) != NULL) {
1281 if (!strncmp(this_opt, "bpp:", 4))
1282 current_par.max_bpp =
1283 simple_strtoul(this_opt + 4, NULL, 0);
1285 if (!strncmp(this_opt, "lccr0:", 6))
1287 simple_strtoul(this_opt + 6, NULL, 0);
1288 if (!strncmp(this_opt, "lccr1:", 6)) {
1290 simple_strtoul(this_opt + 6, NULL, 0);
1291 current_par.max_xres =
1292 (lcd_shadow.lccr1 & 0x3ff) + 16;
1294 if (!strncmp(this_opt, "lccr2:", 6)) {
1296 simple_strtoul(this_opt + 6, NULL, 0);
1297 current_par.max_yres =
1299 lccr0 & LCCR0_SDS) ? ((lcd_shadow.
1302 2 : ((lcd_shadow.lccr2 & 0x3ff) + 1);
1304 if (!strncmp(this_opt, "lccr3:", 6))
1306 simple_strtoul(this_opt + 6, NULL, 0);
1312 module_init(sa1100fb_init);
1313 MODULE_DESCRIPTION("StrongARM-1100/1110 framebuffer driver");
1314 MODULE_LICENSE("GPL");