2 * linux/drivers/video/savagefb.c -- S3 Savage Framebuffer Driver
4 * Copyright (c) 2001-2002 Denis Oliver Kropp <dok@directfb.org>
5 * Sven Neumann <neo@directfb.org>
8 * Card specific code is based on XFree86's savage driver.
9 * Framebuffer framework code is based on code of cyber2000fb and tdfxfb.
11 * This file is subject to the terms and conditions of the GNU General
12 * Public License. See the file COPYING in the main directory of this
13 * archive for more details.
16 * - hardware accelerated clear and move
19 * - wait for vertical retrace before writing to cr67
20 * at the beginning of savagefb_set_par
21 * - use synchronization registers cr23 and cr26
25 * - don't return alpha bits for 32bit format
28 * - added WaitIdle functions for all Savage types
29 * - do WaitIdle before mode switching
33 * - first working version
37 * - clock validations in decode_var
40 * - white margin on bootup
44 #include <linux/module.h>
45 #include <linux/kernel.h>
46 #include <linux/errno.h>
47 #include <linux/string.h>
49 #include <linux/slab.h>
50 #include <linux/delay.h>
52 #include <linux/pci.h>
53 #include <linux/init.h>
54 #include <linux/console.h>
58 #include <asm/pgtable.h>
59 #include <asm/system.h>
68 #define SAVAGEFB_VERSION "0.4.0_2.6"
70 /* --------------------------------------------------------------------- */
73 static char *mode_option __devinitdata = NULL;
77 MODULE_AUTHOR("(c) 2001-2002 Denis Oliver Kropp <dok@directfb.org>");
78 MODULE_LICENSE("GPL");
79 MODULE_DESCRIPTION("FBDev driver for S3 Savage PCI/AGP Chips");
84 /* --------------------------------------------------------------------- */
86 static void vgaHWSeqReset(struct savagefb_par *par, int start)
89 VGAwSEQ(0x00, 0x01, par); /* Synchronous Reset */
91 VGAwSEQ(0x00, 0x03, par); /* End Reset */
94 static void vgaHWProtect(struct savagefb_par *par, int on)
100 * Turn off screen and disable sequencer.
102 tmp = VGArSEQ(0x01, par);
104 vgaHWSeqReset(par, 1); /* start synchronous reset */
105 VGAwSEQ(0x01, tmp | 0x20, par);/* disable the display */
107 VGAenablePalette(par);
110 * Reenable sequencer, then turn on screen.
113 tmp = VGArSEQ(0x01, par);
115 VGAwSEQ(0x01, tmp & ~0x20, par);/* reenable display */
116 vgaHWSeqReset(par, 0); /* clear synchronous reset */
118 VGAdisablePalette(par);
122 static void vgaHWRestore(struct savagefb_par *par, struct savage_reg *reg)
126 VGAwMISC(reg->MiscOutReg, par);
128 for (i = 1; i < 5; i++)
129 VGAwSEQ(i, reg->Sequencer[i], par);
131 /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 or
133 VGAwCR(17, reg->CRTC[17] & ~0x80, par);
135 for (i = 0; i < 25; i++)
136 VGAwCR(i, reg->CRTC[i], par);
138 for (i = 0; i < 9; i++)
139 VGAwGR(i, reg->Graphics[i], par);
141 VGAenablePalette(par);
143 for (i = 0; i < 21; i++)
144 VGAwATTR(i, reg->Attribute[i], par);
146 VGAdisablePalette(par);
149 static void vgaHWInit(struct fb_var_screeninfo *var,
150 struct savagefb_par *par,
151 struct xtimings *timings,
152 struct savage_reg *reg)
154 reg->MiscOutReg = 0x23;
156 if (!(timings->sync & FB_SYNC_HOR_HIGH_ACT))
157 reg->MiscOutReg |= 0x40;
159 if (!(timings->sync & FB_SYNC_VERT_HIGH_ACT))
160 reg->MiscOutReg |= 0x80;
165 reg->Sequencer[0x00] = 0x00;
166 reg->Sequencer[0x01] = 0x01;
167 reg->Sequencer[0x02] = 0x0F;
168 reg->Sequencer[0x03] = 0x00; /* Font select */
169 reg->Sequencer[0x04] = 0x0E; /* Misc */
174 reg->CRTC[0x00] = (timings->HTotal >> 3) - 5;
175 reg->CRTC[0x01] = (timings->HDisplay >> 3) - 1;
176 reg->CRTC[0x02] = (timings->HSyncStart >> 3) - 1;
177 reg->CRTC[0x03] = (((timings->HSyncEnd >> 3) - 1) & 0x1f) | 0x80;
178 reg->CRTC[0x04] = (timings->HSyncStart >> 3);
179 reg->CRTC[0x05] = ((((timings->HSyncEnd >> 3) - 1) & 0x20) << 2) |
180 (((timings->HSyncEnd >> 3)) & 0x1f);
181 reg->CRTC[0x06] = (timings->VTotal - 2) & 0xFF;
182 reg->CRTC[0x07] = (((timings->VTotal - 2) & 0x100) >> 8) |
183 (((timings->VDisplay - 1) & 0x100) >> 7) |
184 ((timings->VSyncStart & 0x100) >> 6) |
185 (((timings->VSyncStart - 1) & 0x100) >> 5) |
187 (((timings->VTotal - 2) & 0x200) >> 4) |
188 (((timings->VDisplay - 1) & 0x200) >> 3) |
189 ((timings->VSyncStart & 0x200) >> 2);
190 reg->CRTC[0x08] = 0x00;
191 reg->CRTC[0x09] = (((timings->VSyncStart - 1) & 0x200) >> 4) | 0x40;
193 if (timings->dblscan)
194 reg->CRTC[0x09] |= 0x80;
196 reg->CRTC[0x0a] = 0x00;
197 reg->CRTC[0x0b] = 0x00;
198 reg->CRTC[0x0c] = 0x00;
199 reg->CRTC[0x0d] = 0x00;
200 reg->CRTC[0x0e] = 0x00;
201 reg->CRTC[0x0f] = 0x00;
202 reg->CRTC[0x10] = timings->VSyncStart & 0xff;
203 reg->CRTC[0x11] = (timings->VSyncEnd & 0x0f) | 0x20;
204 reg->CRTC[0x12] = (timings->VDisplay - 1) & 0xff;
205 reg->CRTC[0x13] = var->xres_virtual >> 4;
206 reg->CRTC[0x14] = 0x00;
207 reg->CRTC[0x15] = (timings->VSyncStart - 1) & 0xff;
208 reg->CRTC[0x16] = (timings->VSyncEnd - 1) & 0xff;
209 reg->CRTC[0x17] = 0xc3;
210 reg->CRTC[0x18] = 0xff;
213 * are these unnecessary?
214 * vgaHWHBlankKGA(mode, regp, 0, KGA_FIX_OVERSCAN|KGA_ENABLE_ON_ZERO);
215 * vgaHWVBlankKGA(mode, regp, 0, KGA_FIX_OVERSCAN|KGA_ENABLE_ON_ZERO);
219 * Graphics Display Controller
221 reg->Graphics[0x00] = 0x00;
222 reg->Graphics[0x01] = 0x00;
223 reg->Graphics[0x02] = 0x00;
224 reg->Graphics[0x03] = 0x00;
225 reg->Graphics[0x04] = 0x00;
226 reg->Graphics[0x05] = 0x40;
227 reg->Graphics[0x06] = 0x05; /* only map 64k VGA memory !!!! */
228 reg->Graphics[0x07] = 0x0F;
229 reg->Graphics[0x08] = 0xFF;
232 reg->Attribute[0x00] = 0x00; /* standard colormap translation */
233 reg->Attribute[0x01] = 0x01;
234 reg->Attribute[0x02] = 0x02;
235 reg->Attribute[0x03] = 0x03;
236 reg->Attribute[0x04] = 0x04;
237 reg->Attribute[0x05] = 0x05;
238 reg->Attribute[0x06] = 0x06;
239 reg->Attribute[0x07] = 0x07;
240 reg->Attribute[0x08] = 0x08;
241 reg->Attribute[0x09] = 0x09;
242 reg->Attribute[0x0a] = 0x0A;
243 reg->Attribute[0x0b] = 0x0B;
244 reg->Attribute[0x0c] = 0x0C;
245 reg->Attribute[0x0d] = 0x0D;
246 reg->Attribute[0x0e] = 0x0E;
247 reg->Attribute[0x0f] = 0x0F;
248 reg->Attribute[0x10] = 0x41;
249 reg->Attribute[0x11] = 0xFF;
250 reg->Attribute[0x12] = 0x0F;
251 reg->Attribute[0x13] = 0x00;
252 reg->Attribute[0x14] = 0x00;
255 /* -------------------- Hardware specific routines ------------------------- */
258 * Hardware Acceleration for SavageFB
261 /* Wait for fifo space */
263 savage3D_waitfifo(struct savagefb_par *par, int space)
265 int slots = MAXFIFO - space;
267 while ((savage_in32(0x48C00, par) & 0x0000ffff) > slots);
271 savage4_waitfifo(struct savagefb_par *par, int space)
273 int slots = MAXFIFO - space;
275 while ((savage_in32(0x48C60, par) & 0x001fffff) > slots);
279 savage2000_waitfifo(struct savagefb_par *par, int space)
281 int slots = MAXFIFO - space;
283 while ((savage_in32(0x48C60, par) & 0x0000ffff) > slots);
286 /* Wait for idle accelerator */
288 savage3D_waitidle(struct savagefb_par *par)
290 while ((savage_in32(0x48C00, par) & 0x0008ffff) != 0x80000);
294 savage4_waitidle(struct savagefb_par *par)
296 while ((savage_in32(0x48C60, par) & 0x00a00000) != 0x00a00000);
300 savage2000_waitidle(struct savagefb_par *par)
302 while ((savage_in32(0x48C60, par) & 0x009fffff));
305 #ifdef CONFIG_FB_SAVAGE_ACCEL
307 SavageSetup2DEngine(struct savagefb_par *par)
309 unsigned long GlobalBitmapDescriptor;
311 GlobalBitmapDescriptor = 1 | 8 | BCI_BD_BW_DISABLE;
312 BCI_BD_SET_BPP(GlobalBitmapDescriptor, par->depth);
313 BCI_BD_SET_STRIDE(GlobalBitmapDescriptor, par->vwidth);
319 savage_out32(0x48C18, savage_in32(0x48C18, par) & 0x3FF0, par);
320 /* Setup BCI command overflow buffer */
321 savage_out32(0x48C14,
322 (par->cob_offset >> 11) | (par->cob_index << 29),
324 /* Program shadow status update. */
325 savage_out32(0x48C10, 0x78207220, par);
326 savage_out32(0x48C0C, 0, par);
327 /* Enable BCI and command overflow buffer */
328 savage_out32(0x48C18, savage_in32(0x48C18, par) | 0x0C, par);
333 case S3_PROSAVAGEDDR:
336 savage_out32(0x48C18, savage_in32(0x48C18, par) & 0x3FF0, par);
337 /* Program shadow status update */
338 savage_out32(0x48C10, 0x00700040, par);
339 savage_out32(0x48C0C, 0, par);
340 /* Enable BCI without the COB */
341 savage_out32(0x48C18, savage_in32(0x48C18, par) | 0x08, par);
345 savage_out32(0x48C18, 0, par);
346 /* Setup BCI command overflow buffer */
347 savage_out32(0x48C18,
348 (par->cob_offset >> 7) | (par->cob_index),
350 /* Disable shadow status update */
351 savage_out32(0x48A30, 0, par);
352 /* Enable BCI and command overflow buffer */
353 savage_out32(0x48C18, savage_in32(0x48C18, par) | 0x00280000,
359 /* Turn on 16-bit register access. */
360 vga_out8(0x3d4, 0x31, par);
361 vga_out8(0x3d5, 0x0c, par);
363 /* Set stride to use GBD. */
364 vga_out8(0x3d4, 0x50, par);
365 vga_out8(0x3d5, vga_in8(0x3d5, par) | 0xC1, par);
367 /* Enable 2D engine. */
368 vga_out8(0x3d4, 0x40, par);
369 vga_out8(0x3d5, 0x01, par);
371 savage_out32(MONO_PAT_0, ~0, par);
372 savage_out32(MONO_PAT_1, ~0, par);
374 /* Setup plane masks */
375 savage_out32(0x8128, ~0, par); /* enable all write planes */
376 savage_out32(0x812C, ~0, par); /* enable all read planes */
377 savage_out16(0x8134, 0x27, par);
378 savage_out16(0x8136, 0x07, par);
380 /* Now set the GBD */
382 par->SavageWaitFifo(par, 4);
384 BCI_SEND(BCI_CMD_SETREG | (1 << 16) | BCI_GBD1);
386 BCI_SEND(BCI_CMD_SETREG | (1 << 16) | BCI_GBD2);
387 BCI_SEND(GlobalBitmapDescriptor);
390 * I don't know why, sending this twice fixes the initial black screen,
391 * prevents X from crashing at least in Toshiba laptops with SavageIX.
395 par->SavageWaitFifo(par, 4);
397 BCI_SEND(BCI_CMD_SETREG | (1 << 16) | BCI_GBD1);
399 BCI_SEND(BCI_CMD_SETREG | (1 << 16) | BCI_GBD2);
400 BCI_SEND(GlobalBitmapDescriptor);
403 static void savagefb_set_clip(struct fb_info *info)
405 struct savagefb_par *par = info->par;
408 cmd = BCI_CMD_NOP | BCI_CMD_CLIP_NEW;
410 par->SavageWaitFifo(par,3);
412 BCI_SEND(BCI_CLIP_TL(0, 0));
413 BCI_SEND(BCI_CLIP_BR(0xfff, 0xfff));
416 static void SavageSetup2DEngine(struct savagefb_par *par) {}
420 static void SavageCalcClock(long freq, int min_m, int min_n1, int max_n1,
421 int min_n2, int max_n2, long freq_min,
422 long freq_max, unsigned int *mdiv,
423 unsigned int *ndiv, unsigned int *r)
425 long diff, best_diff;
427 unsigned char n1, n2, best_n1=16+2, best_n2=2, best_m=125+2;
429 if (freq < freq_min / (1 << max_n2)) {
430 printk(KERN_ERR "invalid frequency %ld Khz\n", freq);
431 freq = freq_min / (1 << max_n2);
433 if (freq > freq_max / (1 << min_n2)) {
434 printk(KERN_ERR "invalid frequency %ld Khz\n", freq);
435 freq = freq_max / (1 << min_n2);
438 /* work out suitable timings */
441 for (n2=min_n2; n2<=max_n2; n2++) {
442 for (n1=min_n1+2; n1<=max_n1+2; n1++) {
443 m = (freq * n1 * (1 << n2) + HALF_BASE_FREQ) /
445 if (m < min_m+2 || m > 127+2)
447 if ((m * BASE_FREQ >= freq_min * n1) &&
448 (m * BASE_FREQ <= freq_max * n1)) {
449 diff = freq * (1 << n2) * n1 - BASE_FREQ * m;
452 if (diff < best_diff) {
467 static int common_calc_clock(long freq, int min_m, int min_n1, int max_n1,
468 int min_n2, int max_n2, long freq_min,
469 long freq_max, unsigned char *mdiv,
472 long diff, best_diff;
474 unsigned char n1, n2;
475 unsigned char best_n1 = 16+2, best_n2 = 2, best_m = 125+2;
479 for (n2 = min_n2; n2 <= max_n2; n2++) {
480 for (n1 = min_n1+2; n1 <= max_n1+2; n1++) {
481 m = (freq * n1 * (1 << n2) + HALF_BASE_FREQ) /
483 if (m < min_m + 2 || m > 127+2)
485 if ((m * BASE_FREQ >= freq_min * n1) &&
486 (m * BASE_FREQ <= freq_max * n1)) {
487 diff = freq * (1 << n2) * n1 - BASE_FREQ * m;
490 if (diff < best_diff) {
501 *ndiv = (best_n1 - 2) | (best_n2 << 6);
503 *ndiv = (best_n1 - 2) | (best_n2 << 5);
510 #ifdef SAVAGEFB_DEBUG
511 /* This function is used to debug, it prints out the contents of s3 regs */
513 static void SavagePrintRegs(struct savagefb_par *par)
516 int vgaCRIndex = 0x3d4;
517 int vgaCRReg = 0x3d5;
519 printk(KERN_DEBUG "SR x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE "
522 for (i = 0; i < 0x70; i++) {
524 printk(KERN_DEBUG "\nSR%xx ", i >> 4);
525 vga_out8(0x3c4, i, par);
526 printk(KERN_DEBUG " %02x", vga_in8(0x3c5, par));
529 printk(KERN_DEBUG "\n\nCR x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC "
532 for (i = 0; i < 0xB7; i++) {
534 printk(KERN_DEBUG "\nCR%xx ", i >> 4);
535 vga_out8(vgaCRIndex, i, par);
536 printk(KERN_DEBUG " %02x", vga_in8(vgaCRReg, par));
539 printk(KERN_DEBUG "\n\n");
543 /* --------------------------------------------------------------------- */
545 static void savage_get_default_par(struct savagefb_par *par, struct savage_reg *reg)
547 unsigned char cr3a, cr53, cr66;
549 vga_out16(0x3d4, 0x4838, par);
550 vga_out16(0x3d4, 0xa039, par);
551 vga_out16(0x3c4, 0x0608, par);
553 vga_out8(0x3d4, 0x66, par);
554 cr66 = vga_in8(0x3d5, par);
555 vga_out8(0x3d5, cr66 | 0x80, par);
556 vga_out8(0x3d4, 0x3a, par);
557 cr3a = vga_in8(0x3d5, par);
558 vga_out8(0x3d5, cr3a | 0x80, par);
559 vga_out8(0x3d4, 0x53, par);
560 cr53 = vga_in8(0x3d5, par);
561 vga_out8(0x3d5, cr53 & 0x7f, par);
563 vga_out8(0x3d4, 0x66, par);
564 vga_out8(0x3d5, cr66, par);
565 vga_out8(0x3d4, 0x3a, par);
566 vga_out8(0x3d5, cr3a, par);
568 vga_out8(0x3d4, 0x66, par);
569 vga_out8(0x3d5, cr66, par);
570 vga_out8(0x3d4, 0x3a, par);
571 vga_out8(0x3d5, cr3a, par);
573 /* unlock extended seq regs */
574 vga_out8(0x3c4, 0x08, par);
575 reg->SR08 = vga_in8(0x3c5, par);
576 vga_out8(0x3c5, 0x06, par);
578 /* now save all the extended regs we need */
579 vga_out8(0x3d4, 0x31, par);
580 reg->CR31 = vga_in8(0x3d5, par);
581 vga_out8(0x3d4, 0x32, par);
582 reg->CR32 = vga_in8(0x3d5, par);
583 vga_out8(0x3d4, 0x34, par);
584 reg->CR34 = vga_in8(0x3d5, par);
585 vga_out8(0x3d4, 0x36, par);
586 reg->CR36 = vga_in8(0x3d5, par);
587 vga_out8(0x3d4, 0x3a, par);
588 reg->CR3A = vga_in8(0x3d5, par);
589 vga_out8(0x3d4, 0x40, par);
590 reg->CR40 = vga_in8(0x3d5, par);
591 vga_out8(0x3d4, 0x42, par);
592 reg->CR42 = vga_in8(0x3d5, par);
593 vga_out8(0x3d4, 0x45, par);
594 reg->CR45 = vga_in8(0x3d5, par);
595 vga_out8(0x3d4, 0x50, par);
596 reg->CR50 = vga_in8(0x3d5, par);
597 vga_out8(0x3d4, 0x51, par);
598 reg->CR51 = vga_in8(0x3d5, par);
599 vga_out8(0x3d4, 0x53, par);
600 reg->CR53 = vga_in8(0x3d5, par);
601 vga_out8(0x3d4, 0x58, par);
602 reg->CR58 = vga_in8(0x3d5, par);
603 vga_out8(0x3d4, 0x60, par);
604 reg->CR60 = vga_in8(0x3d5, par);
605 vga_out8(0x3d4, 0x66, par);
606 reg->CR66 = vga_in8(0x3d5, par);
607 vga_out8(0x3d4, 0x67, par);
608 reg->CR67 = vga_in8(0x3d5, par);
609 vga_out8(0x3d4, 0x68, par);
610 reg->CR68 = vga_in8(0x3d5, par);
611 vga_out8(0x3d4, 0x69, par);
612 reg->CR69 = vga_in8(0x3d5, par);
613 vga_out8(0x3d4, 0x6f, par);
614 reg->CR6F = vga_in8(0x3d5, par);
616 vga_out8(0x3d4, 0x33, par);
617 reg->CR33 = vga_in8(0x3d5, par);
618 vga_out8(0x3d4, 0x86, par);
619 reg->CR86 = vga_in8(0x3d5, par);
620 vga_out8(0x3d4, 0x88, par);
621 reg->CR88 = vga_in8(0x3d5, par);
622 vga_out8(0x3d4, 0x90, par);
623 reg->CR90 = vga_in8(0x3d5, par);
624 vga_out8(0x3d4, 0x91, par);
625 reg->CR91 = vga_in8(0x3d5, par);
626 vga_out8(0x3d4, 0xb0, par);
627 reg->CRB0 = vga_in8(0x3d5, par) | 0x80;
629 /* extended mode timing regs */
630 vga_out8(0x3d4, 0x3b, par);
631 reg->CR3B = vga_in8(0x3d5, par);
632 vga_out8(0x3d4, 0x3c, par);
633 reg->CR3C = vga_in8(0x3d5, par);
634 vga_out8(0x3d4, 0x43, par);
635 reg->CR43 = vga_in8(0x3d5, par);
636 vga_out8(0x3d4, 0x5d, par);
637 reg->CR5D = vga_in8(0x3d5, par);
638 vga_out8(0x3d4, 0x5e, par);
639 reg->CR5E = vga_in8(0x3d5, par);
640 vga_out8(0x3d4, 0x65, par);
641 reg->CR65 = vga_in8(0x3d5, par);
643 /* save seq extended regs for DCLK PLL programming */
644 vga_out8(0x3c4, 0x0e, par);
645 reg->SR0E = vga_in8(0x3c5, par);
646 vga_out8(0x3c4, 0x0f, par);
647 reg->SR0F = vga_in8(0x3c5, par);
648 vga_out8(0x3c4, 0x10, par);
649 reg->SR10 = vga_in8(0x3c5, par);
650 vga_out8(0x3c4, 0x11, par);
651 reg->SR11 = vga_in8(0x3c5, par);
652 vga_out8(0x3c4, 0x12, par);
653 reg->SR12 = vga_in8(0x3c5, par);
654 vga_out8(0x3c4, 0x13, par);
655 reg->SR13 = vga_in8(0x3c5, par);
656 vga_out8(0x3c4, 0x29, par);
657 reg->SR29 = vga_in8(0x3c5, par);
659 vga_out8(0x3c4, 0x15, par);
660 reg->SR15 = vga_in8(0x3c5, par);
661 vga_out8(0x3c4, 0x30, par);
662 reg->SR30 = vga_in8(0x3c5, par);
663 vga_out8(0x3c4, 0x18, par);
664 reg->SR18 = vga_in8(0x3c5, par);
666 /* Save flat panel expansion regsters. */
667 if (par->chip == S3_SAVAGE_MX) {
670 for (i = 0; i < 8; i++) {
671 vga_out8(0x3c4, 0x54+i, par);
672 reg->SR54[i] = vga_in8(0x3c5, par);
676 vga_out8(0x3d4, 0x66, par);
677 cr66 = vga_in8(0x3d5, par);
678 vga_out8(0x3d5, cr66 | 0x80, par);
679 vga_out8(0x3d4, 0x3a, par);
680 cr3a = vga_in8(0x3d5, par);
681 vga_out8(0x3d5, cr3a | 0x80, par);
683 /* now save MIU regs */
684 if (par->chip != S3_SAVAGE_MX) {
685 reg->MMPR0 = savage_in32(FIFO_CONTROL_REG, par);
686 reg->MMPR1 = savage_in32(MIU_CONTROL_REG, par);
687 reg->MMPR2 = savage_in32(STREAMS_TIMEOUT_REG, par);
688 reg->MMPR3 = savage_in32(MISC_TIMEOUT_REG, par);
691 vga_out8(0x3d4, 0x3a, par);
692 vga_out8(0x3d5, cr3a, par);
693 vga_out8(0x3d4, 0x66, par);
694 vga_out8(0x3d5, cr66, par);
697 static void savage_set_default_par(struct savagefb_par *par,
698 struct savage_reg *reg)
700 unsigned char cr3a, cr53, cr66;
702 vga_out16(0x3d4, 0x4838, par);
703 vga_out16(0x3d4, 0xa039, par);
704 vga_out16(0x3c4, 0x0608, par);
706 vga_out8(0x3d4, 0x66, par);
707 cr66 = vga_in8(0x3d5, par);
708 vga_out8(0x3d5, cr66 | 0x80, par);
709 vga_out8(0x3d4, 0x3a, par);
710 cr3a = vga_in8(0x3d5, par);
711 vga_out8(0x3d5, cr3a | 0x80, par);
712 vga_out8(0x3d4, 0x53, par);
713 cr53 = vga_in8(0x3d5, par);
714 vga_out8(0x3d5, cr53 & 0x7f, par);
716 vga_out8(0x3d4, 0x66, par);
717 vga_out8(0x3d5, cr66, par);
718 vga_out8(0x3d4, 0x3a, par);
719 vga_out8(0x3d5, cr3a, par);
721 vga_out8(0x3d4, 0x66, par);
722 vga_out8(0x3d5, cr66, par);
723 vga_out8(0x3d4, 0x3a, par);
724 vga_out8(0x3d5, cr3a, par);
726 /* unlock extended seq regs */
727 vga_out8(0x3c4, 0x08, par);
728 vga_out8(0x3c5, reg->SR08, par);
729 vga_out8(0x3c5, 0x06, par);
731 /* now restore all the extended regs we need */
732 vga_out8(0x3d4, 0x31, par);
733 vga_out8(0x3d5, reg->CR31, par);
734 vga_out8(0x3d4, 0x32, par);
735 vga_out8(0x3d5, reg->CR32, par);
736 vga_out8(0x3d4, 0x34, par);
737 vga_out8(0x3d5, reg->CR34, par);
738 vga_out8(0x3d4, 0x36, par);
739 vga_out8(0x3d5,reg->CR36, par);
740 vga_out8(0x3d4, 0x3a, par);
741 vga_out8(0x3d5, reg->CR3A, par);
742 vga_out8(0x3d4, 0x40, par);
743 vga_out8(0x3d5, reg->CR40, par);
744 vga_out8(0x3d4, 0x42, par);
745 vga_out8(0x3d5, reg->CR42, par);
746 vga_out8(0x3d4, 0x45, par);
747 vga_out8(0x3d5, reg->CR45, par);
748 vga_out8(0x3d4, 0x50, par);
749 vga_out8(0x3d5, reg->CR50, par);
750 vga_out8(0x3d4, 0x51, par);
751 vga_out8(0x3d5, reg->CR51, par);
752 vga_out8(0x3d4, 0x53, par);
753 vga_out8(0x3d5, reg->CR53, par);
754 vga_out8(0x3d4, 0x58, par);
755 vga_out8(0x3d5, reg->CR58, par);
756 vga_out8(0x3d4, 0x60, par);
757 vga_out8(0x3d5, reg->CR60, par);
758 vga_out8(0x3d4, 0x66, par);
759 vga_out8(0x3d5, reg->CR66, par);
760 vga_out8(0x3d4, 0x67, par);
761 vga_out8(0x3d5, reg->CR67, par);
762 vga_out8(0x3d4, 0x68, par);
763 vga_out8(0x3d5, reg->CR68, par);
764 vga_out8(0x3d4, 0x69, par);
765 vga_out8(0x3d5, reg->CR69, par);
766 vga_out8(0x3d4, 0x6f, par);
767 vga_out8(0x3d5, reg->CR6F, par);
769 vga_out8(0x3d4, 0x33, par);
770 vga_out8(0x3d5, reg->CR33, par);
771 vga_out8(0x3d4, 0x86, par);
772 vga_out8(0x3d5, reg->CR86, par);
773 vga_out8(0x3d4, 0x88, par);
774 vga_out8(0x3d5, reg->CR88, par);
775 vga_out8(0x3d4, 0x90, par);
776 vga_out8(0x3d5, reg->CR90, par);
777 vga_out8(0x3d4, 0x91, par);
778 vga_out8(0x3d5, reg->CR91, par);
779 vga_out8(0x3d4, 0xb0, par);
780 vga_out8(0x3d5, reg->CRB0, par);
782 /* extended mode timing regs */
783 vga_out8(0x3d4, 0x3b, par);
784 vga_out8(0x3d5, reg->CR3B, par);
785 vga_out8(0x3d4, 0x3c, par);
786 vga_out8(0x3d5, reg->CR3C, par);
787 vga_out8(0x3d4, 0x43, par);
788 vga_out8(0x3d5, reg->CR43, par);
789 vga_out8(0x3d4, 0x5d, par);
790 vga_out8(0x3d5, reg->CR5D, par);
791 vga_out8(0x3d4, 0x5e, par);
792 vga_out8(0x3d5, reg->CR5E, par);
793 vga_out8(0x3d4, 0x65, par);
794 vga_out8(0x3d5, reg->CR65, par);
796 /* save seq extended regs for DCLK PLL programming */
797 vga_out8(0x3c4, 0x0e, par);
798 vga_out8(0x3c5, reg->SR0E, par);
799 vga_out8(0x3c4, 0x0f, par);
800 vga_out8(0x3c5, reg->SR0F, par);
801 vga_out8(0x3c4, 0x10, par);
802 vga_out8(0x3c5, reg->SR10, par);
803 vga_out8(0x3c4, 0x11, par);
804 vga_out8(0x3c5, reg->SR11, par);
805 vga_out8(0x3c4, 0x12, par);
806 vga_out8(0x3c5, reg->SR12, par);
807 vga_out8(0x3c4, 0x13, par);
808 vga_out8(0x3c5, reg->SR13, par);
809 vga_out8(0x3c4, 0x29, par);
810 vga_out8(0x3c5, reg->SR29, par);
812 vga_out8(0x3c4, 0x15, par);
813 vga_out8(0x3c5, reg->SR15, par);
814 vga_out8(0x3c4, 0x30, par);
815 vga_out8(0x3c5, reg->SR30, par);
816 vga_out8(0x3c4, 0x18, par);
817 vga_out8(0x3c5, reg->SR18, par);
819 /* Save flat panel expansion regsters. */
820 if (par->chip == S3_SAVAGE_MX) {
823 for (i = 0; i < 8; i++) {
824 vga_out8(0x3c4, 0x54+i, par);
825 vga_out8(0x3c5, reg->SR54[i], par);
829 vga_out8(0x3d4, 0x66, par);
830 cr66 = vga_in8(0x3d5, par);
831 vga_out8(0x3d5, cr66 | 0x80, par);
832 vga_out8(0x3d4, 0x3a, par);
833 cr3a = vga_in8(0x3d5, par);
834 vga_out8(0x3d5, cr3a | 0x80, par);
836 /* now save MIU regs */
837 if (par->chip != S3_SAVAGE_MX) {
838 savage_out32(FIFO_CONTROL_REG, reg->MMPR0, par);
839 savage_out32(MIU_CONTROL_REG, reg->MMPR1, par);
840 savage_out32(STREAMS_TIMEOUT_REG, reg->MMPR2, par);
841 savage_out32(MISC_TIMEOUT_REG, reg->MMPR3, par);
844 vga_out8(0x3d4, 0x3a, par);
845 vga_out8(0x3d5, cr3a, par);
846 vga_out8(0x3d4, 0x66, par);
847 vga_out8(0x3d5, cr66, par);
850 static void savage_update_var(struct fb_var_screeninfo *var,
851 const struct fb_videomode *modedb)
853 var->xres = var->xres_virtual = modedb->xres;
854 var->yres = modedb->yres;
855 if (var->yres_virtual < var->yres)
856 var->yres_virtual = var->yres;
857 var->xoffset = var->yoffset = 0;
858 var->pixclock = modedb->pixclock;
859 var->left_margin = modedb->left_margin;
860 var->right_margin = modedb->right_margin;
861 var->upper_margin = modedb->upper_margin;
862 var->lower_margin = modedb->lower_margin;
863 var->hsync_len = modedb->hsync_len;
864 var->vsync_len = modedb->vsync_len;
865 var->sync = modedb->sync;
866 var->vmode = modedb->vmode;
869 static int savagefb_check_var(struct fb_var_screeninfo *var,
870 struct fb_info *info)
872 struct savagefb_par *par = info->par;
873 int memlen, vramlen, mode_valid = 0;
875 DBG("savagefb_check_var");
877 var->transp.offset = 0;
878 var->transp.length = 0;
879 switch (var->bits_per_pixel) {
881 var->red.offset = var->green.offset =
882 var->blue.offset = 0;
883 var->red.length = var->green.length =
884 var->blue.length = var->bits_per_pixel;
887 var->red.offset = 11;
889 var->green.offset = 5;
890 var->green.length = 6;
891 var->blue.offset = 0;
892 var->blue.length = 5;
895 var->transp.offset = 24;
896 var->transp.length = 8;
897 var->red.offset = 16;
899 var->green.offset = 8;
900 var->green.length = 8;
901 var->blue.offset = 0;
902 var->blue.length = 8;
909 if (!info->monspecs.hfmax || !info->monspecs.vfmax ||
910 !info->monspecs.dclkmax || !fb_validate_mode(var, info))
913 /* calculate modeline if supported by monitor */
914 if (!mode_valid && info->monspecs.gtf) {
915 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
920 const struct fb_videomode *mode;
922 mode = fb_find_best_mode(var, &info->modelist);
924 savage_update_var(var, mode);
929 if (!mode_valid && info->monspecs.modedb_len)
932 /* Is the mode larger than the LCD panel? */
933 if (par->SavagePanelWidth &&
934 (var->xres > par->SavagePanelWidth ||
935 var->yres > par->SavagePanelHeight)) {
936 printk(KERN_INFO "Mode (%dx%d) larger than the LCD panel "
937 "(%dx%d)\n", var->xres, var->yres,
938 par->SavagePanelWidth,
939 par->SavagePanelHeight);
943 if (var->yres_virtual < var->yres)
944 var->yres_virtual = var->yres;
945 if (var->xres_virtual < var->xres)
946 var->xres_virtual = var->xres;
948 vramlen = info->fix.smem_len;
950 memlen = var->xres_virtual * var->bits_per_pixel *
951 var->yres_virtual / 8;
952 if (memlen > vramlen) {
953 var->yres_virtual = vramlen * 8 /
954 (var->xres_virtual * var->bits_per_pixel);
955 memlen = var->xres_virtual * var->bits_per_pixel *
956 var->yres_virtual / 8;
959 /* we must round yres/xres down, we already rounded y/xres_virtual up
960 if it was possible. We should return -EINVAL, but I disagree */
961 if (var->yres_virtual < var->yres)
962 var->yres = var->yres_virtual;
963 if (var->xres_virtual < var->xres)
964 var->xres = var->xres_virtual;
965 if (var->xoffset + var->xres > var->xres_virtual)
966 var->xoffset = var->xres_virtual - var->xres;
967 if (var->yoffset + var->yres > var->yres_virtual)
968 var->yoffset = var->yres_virtual - var->yres;
974 static int savagefb_decode_var(struct fb_var_screeninfo *var,
975 struct savagefb_par *par,
976 struct savage_reg *reg)
978 struct xtimings timings;
979 int width, dclk, i, j; /*, refresh; */
980 unsigned int m, n, r;
981 unsigned char tmp = 0;
982 unsigned int pixclock = var->pixclock;
984 DBG("savagefb_decode_var");
986 memset(&timings, 0, sizeof(timings));
988 if (!pixclock) pixclock = 10000; /* 10ns = 100MHz */
989 timings.Clock = 1000000000 / pixclock;
990 if (timings.Clock < 1) timings.Clock = 1;
991 timings.dblscan = var->vmode & FB_VMODE_DOUBLE;
992 timings.interlaced = var->vmode & FB_VMODE_INTERLACED;
993 timings.HDisplay = var->xres;
994 timings.HSyncStart = timings.HDisplay + var->right_margin;
995 timings.HSyncEnd = timings.HSyncStart + var->hsync_len;
996 timings.HTotal = timings.HSyncEnd + var->left_margin;
997 timings.VDisplay = var->yres;
998 timings.VSyncStart = timings.VDisplay + var->lower_margin;
999 timings.VSyncEnd = timings.VSyncStart + var->vsync_len;
1000 timings.VTotal = timings.VSyncEnd + var->upper_margin;
1001 timings.sync = var->sync;
1004 par->depth = var->bits_per_pixel;
1005 par->vwidth = var->xres_virtual;
1007 if (var->bits_per_pixel == 16 && par->chip == S3_SAVAGE3D) {
1008 timings.HDisplay *= 2;
1009 timings.HSyncStart *= 2;
1010 timings.HSyncEnd *= 2;
1011 timings.HTotal *= 2;
1015 * This will allocate the datastructure and initialize all of the
1016 * generic VGA registers.
1018 vgaHWInit(var, par, &timings, reg);
1020 /* We need to set CR67 whether or not we use the BIOS. */
1022 dclk = timings.Clock;
1025 switch(var->bits_per_pixel) {
1027 if ((par->chip == S3_SAVAGE2000) && (dclk >= 230000))
1028 reg->CR67 = 0x10; /* 8bpp, 2 pixels/clock */
1030 reg->CR67 = 0x00; /* 8bpp, 1 pixel/clock */
1033 if (S3_SAVAGE_MOBILE_SERIES(par->chip) ||
1034 ((par->chip == S3_SAVAGE2000) && (dclk >= 230000)))
1035 reg->CR67 = 0x30; /* 15bpp, 2 pixel/clock */
1037 reg->CR67 = 0x20; /* 15bpp, 1 pixels/clock */
1040 if (S3_SAVAGE_MOBILE_SERIES(par->chip) ||
1041 ((par->chip == S3_SAVAGE2000) && (dclk >= 230000)))
1042 reg->CR67 = 0x50; /* 16bpp, 2 pixel/clock */
1044 reg->CR67 = 0x40; /* 16bpp, 1 pixels/clock */
1055 * Either BIOS use is disabled, or we failed to find a suitable
1056 * match. Fall back to traditional register-crunching.
1059 vga_out8(0x3d4, 0x3a, par);
1060 tmp = vga_in8(0x3d5, par);
1061 if (1 /*FIXME:psav->pci_burst*/)
1062 reg->CR3A = (tmp & 0x7f) | 0x15;
1064 reg->CR3A = tmp | 0x95;
1070 vga_out8(0x3d4, 0x58, par);
1071 reg->CR58 = vga_in8(0x3d5, par) & 0x80;
1074 reg->SR15 = 0x03 | 0x80;
1076 reg->CR43 = reg->CR45 = reg->CR65 = 0x00;
1078 vga_out8(0x3d4, 0x40, par);
1079 reg->CR40 = vga_in8(0x3d5, par) & ~0x01;
1081 reg->MMPR0 = 0x010400;
1083 reg->MMPR2 = 0x0808;
1084 reg->MMPR3 = 0x08080810;
1086 SavageCalcClock(dclk, 1, 1, 127, 0, 4, 180000, 360000, &m, &n, &r);
1087 /* m = 107; n = 4; r = 2; */
1089 if (par->MCLK <= 0) {
1093 common_calc_clock(par->MCLK, 1, 1, 31, 0, 3, 135000, 270000,
1094 ®->SR11, ®->SR10);
1095 /* reg->SR10 = 80; // MCLK == 286000 */
1096 /* reg->SR11 = 125; */
1099 reg->SR12 = (r << 6) | (n & 0x3f);
1100 reg->SR13 = m & 0xff;
1101 reg->SR29 = (r & 4) | (m & 0x100) >> 5 | (n & 0x40) >> 2;
1103 if (var->bits_per_pixel < 24)
1104 reg->MMPR0 -= 0x8000;
1106 reg->MMPR0 -= 0x4000;
1108 if (timings.interlaced)
1113 reg->CR34 = 0x10; /* display fifo */
1115 i = ((((timings.HTotal >> 3) - 5) & 0x100) >> 8) |
1116 ((((timings.HDisplay >> 3) - 1) & 0x100) >> 7) |
1117 ((((timings.HSyncStart >> 3) - 1) & 0x100) >> 6) |
1118 ((timings.HSyncStart & 0x800) >> 7);
1120 if ((timings.HSyncEnd >> 3) - (timings.HSyncStart >> 3) > 64)
1122 if ((timings.HSyncEnd >> 3) - (timings.HSyncStart >> 3) > 32)
1125 j = (reg->CRTC[0] + ((i & 0x01) << 8) +
1126 reg->CRTC[4] + ((i & 0x10) << 4) + 1) / 2;
1128 if (j - (reg->CRTC[4] + ((i & 0x10) << 4)) < 4) {
1129 if (reg->CRTC[4] + ((i & 0x10) << 4) + 4 <=
1130 reg->CRTC[0] + ((i & 0x01) << 8))
1131 j = reg->CRTC[4] + ((i & 0x10) << 4) + 4;
1133 j = reg->CRTC[0] + ((i & 0x01) << 8) + 1;
1136 reg->CR3B = j & 0xff;
1137 i |= (j & 0x100) >> 2;
1138 reg->CR3C = (reg->CRTC[0] + ((i & 0x01) << 8)) / 2;
1140 reg->CR5E = (((timings.VTotal - 2) & 0x400) >> 10) |
1141 (((timings.VDisplay - 1) & 0x400) >> 9) |
1142 (((timings.VSyncStart) & 0x400) >> 8) |
1143 (((timings.VSyncStart) & 0x400) >> 6) | 0x40;
1144 width = (var->xres_virtual * ((var->bits_per_pixel+7) / 8)) >> 3;
1145 reg->CR91 = reg->CRTC[19] = 0xff & width;
1146 reg->CR51 = (0x300 & width) >> 4;
1147 reg->CR90 = 0x80 | (width >> 8);
1148 reg->MiscOutReg |= 0x0c;
1150 /* Set frame buffer description. */
1152 if (var->bits_per_pixel <= 8)
1154 else if (var->bits_per_pixel <= 16)
1159 if (var->xres_virtual <= 640)
1161 else if (var->xres_virtual == 800)
1163 else if (var->xres_virtual == 1024)
1165 else if (var->xres_virtual == 1152)
1167 else if (var->xres_virtual == 1280)
1169 else if (var->xres_virtual == 1600)
1172 reg->CR50 |= 0xc1; /* Use GBD */
1174 if (par->chip == S3_SAVAGE2000)
1179 reg->CRTC[0x17] = 0xeb;
1183 vga_out8(0x3d4, 0x36, par);
1184 reg->CR36 = vga_in8(0x3d5, par);
1185 vga_out8(0x3d4, 0x68, par);
1186 reg->CR68 = vga_in8(0x3d5, par);
1188 vga_out8(0x3d4, 0x6f, par);
1189 reg->CR6F = vga_in8(0x3d5, par);
1190 vga_out8(0x3d4, 0x86, par);
1191 reg->CR86 = vga_in8(0x3d5, par);
1192 vga_out8(0x3d4, 0x88, par);
1193 reg->CR88 = vga_in8(0x3d5, par) | 0x08;
1194 vga_out8(0x3d4, 0xb0, par);
1195 reg->CRB0 = vga_in8(0x3d5, par) | 0x80;
1200 /* --------------------------------------------------------------------- */
1203 * Set a single color register. Return != 0 for invalid regno.
1205 static int savagefb_setcolreg(unsigned regno,
1210 struct fb_info *info)
1212 struct savagefb_par *par = info->par;
1214 if (regno >= NR_PALETTE)
1217 par->palette[regno].red = red;
1218 par->palette[regno].green = green;
1219 par->palette[regno].blue = blue;
1220 par->palette[regno].transp = transp;
1222 switch (info->var.bits_per_pixel) {
1224 vga_out8(0x3c8, regno, par);
1226 vga_out8(0x3c9, red >> 10, par);
1227 vga_out8(0x3c9, green >> 10, par);
1228 vga_out8(0x3c9, blue >> 10, par);
1233 ((u32 *)info->pseudo_palette)[regno] =
1235 ((green & 0xfc00) >> 5) |
1236 ((blue & 0xf800) >> 11);
1241 ((u32 *)info->pseudo_palette)[regno] =
1242 ((red & 0xff00) << 8) |
1243 ((green & 0xff00) ) |
1244 ((blue & 0xff00) >> 8);
1248 ((u32 *)info->pseudo_palette)[regno] =
1249 ((transp & 0xff00) << 16) |
1250 ((red & 0xff00) << 8) |
1251 ((green & 0xff00) ) |
1252 ((blue & 0xff00) >> 8);
1262 static void savagefb_set_par_int(struct savagefb_par *par, struct savage_reg *reg)
1264 unsigned char tmp, cr3a, cr66, cr67;
1266 DBG("savagefb_set_par_int");
1268 par->SavageWaitIdle(par);
1270 vga_out8(0x3c2, 0x23, par);
1272 vga_out16(0x3d4, 0x4838, par);
1273 vga_out16(0x3d4, 0xa539, par);
1274 vga_out16(0x3c4, 0x0608, par);
1276 vgaHWProtect(par, 1);
1279 * Some Savage/MX and /IX systems go nuts when trying to exit the
1280 * server after WindowMaker has displayed a gradient background. I
1281 * haven't been able to find what causes it, but a non-destructive
1282 * switch to mode 3 here seems to eliminate the issue.
1285 VerticalRetraceWait(par);
1286 vga_out8(0x3d4, 0x67, par);
1287 cr67 = vga_in8(0x3d5, par);
1288 vga_out8(0x3d5, cr67/*par->CR67*/ & ~0x0c, par); /* no STREAMS yet */
1290 vga_out8(0x3d4, 0x23, par);
1291 vga_out8(0x3d5, 0x00, par);
1292 vga_out8(0x3d4, 0x26, par);
1293 vga_out8(0x3d5, 0x00, par);
1295 /* restore extended regs */
1296 vga_out8(0x3d4, 0x66, par);
1297 vga_out8(0x3d5, reg->CR66, par);
1298 vga_out8(0x3d4, 0x3a, par);
1299 vga_out8(0x3d5, reg->CR3A, par);
1300 vga_out8(0x3d4, 0x31, par);
1301 vga_out8(0x3d5, reg->CR31, par);
1302 vga_out8(0x3d4, 0x32, par);
1303 vga_out8(0x3d5, reg->CR32, par);
1304 vga_out8(0x3d4, 0x58, par);
1305 vga_out8(0x3d5, reg->CR58, par);
1306 vga_out8(0x3d4, 0x53, par);
1307 vga_out8(0x3d5, reg->CR53 & 0x7f, par);
1309 vga_out16(0x3c4, 0x0608, par);
1311 /* Restore DCLK registers. */
1313 vga_out8(0x3c4, 0x0e, par);
1314 vga_out8(0x3c5, reg->SR0E, par);
1315 vga_out8(0x3c4, 0x0f, par);
1316 vga_out8(0x3c5, reg->SR0F, par);
1317 vga_out8(0x3c4, 0x29, par);
1318 vga_out8(0x3c5, reg->SR29, par);
1319 vga_out8(0x3c4, 0x15, par);
1320 vga_out8(0x3c5, reg->SR15, par);
1322 /* Restore flat panel expansion regsters. */
1323 if (par->chip == S3_SAVAGE_MX) {
1326 for (i = 0; i < 8; i++) {
1327 vga_out8(0x3c4, 0x54+i, par);
1328 vga_out8(0x3c5, reg->SR54[i], par);
1332 vgaHWRestore (par, reg);
1334 /* extended mode timing registers */
1335 vga_out8(0x3d4, 0x53, par);
1336 vga_out8(0x3d5, reg->CR53, par);
1337 vga_out8(0x3d4, 0x5d, par);
1338 vga_out8(0x3d5, reg->CR5D, par);
1339 vga_out8(0x3d4, 0x5e, par);
1340 vga_out8(0x3d5, reg->CR5E, par);
1341 vga_out8(0x3d4, 0x3b, par);
1342 vga_out8(0x3d5, reg->CR3B, par);
1343 vga_out8(0x3d4, 0x3c, par);
1344 vga_out8(0x3d5, reg->CR3C, par);
1345 vga_out8(0x3d4, 0x43, par);
1346 vga_out8(0x3d5, reg->CR43, par);
1347 vga_out8(0x3d4, 0x65, par);
1348 vga_out8(0x3d5, reg->CR65, par);
1350 /* restore the desired video mode with cr67 */
1351 vga_out8(0x3d4, 0x67, par);
1352 /* following part not present in X11 driver */
1353 cr67 = vga_in8(0x3d5, par) & 0xf;
1354 vga_out8(0x3d5, 0x50 | cr67, par);
1356 vga_out8(0x3d4, 0x67, par);
1358 vga_out8(0x3d5, reg->CR67 & ~0x0c, par);
1360 /* other mode timing and extended regs */
1361 vga_out8(0x3d4, 0x34, par);
1362 vga_out8(0x3d5, reg->CR34, par);
1363 vga_out8(0x3d4, 0x40, par);
1364 vga_out8(0x3d5, reg->CR40, par);
1365 vga_out8(0x3d4, 0x42, par);
1366 vga_out8(0x3d5, reg->CR42, par);
1367 vga_out8(0x3d4, 0x45, par);
1368 vga_out8(0x3d5, reg->CR45, par);
1369 vga_out8(0x3d4, 0x50, par);
1370 vga_out8(0x3d5, reg->CR50, par);
1371 vga_out8(0x3d4, 0x51, par);
1372 vga_out8(0x3d5, reg->CR51, par);
1374 /* memory timings */
1375 vga_out8(0x3d4, 0x36, par);
1376 vga_out8(0x3d5, reg->CR36, par);
1377 vga_out8(0x3d4, 0x60, par);
1378 vga_out8(0x3d5, reg->CR60, par);
1379 vga_out8(0x3d4, 0x68, par);
1380 vga_out8(0x3d5, reg->CR68, par);
1381 vga_out8(0x3d4, 0x69, par);
1382 vga_out8(0x3d5, reg->CR69, par);
1383 vga_out8(0x3d4, 0x6f, par);
1384 vga_out8(0x3d5, reg->CR6F, par);
1386 vga_out8(0x3d4, 0x33, par);
1387 vga_out8(0x3d5, reg->CR33, par);
1388 vga_out8(0x3d4, 0x86, par);
1389 vga_out8(0x3d5, reg->CR86, par);
1390 vga_out8(0x3d4, 0x88, par);
1391 vga_out8(0x3d5, reg->CR88, par);
1392 vga_out8(0x3d4, 0x90, par);
1393 vga_out8(0x3d5, reg->CR90, par);
1394 vga_out8(0x3d4, 0x91, par);
1395 vga_out8(0x3d5, reg->CR91, par);
1397 if (par->chip == S3_SAVAGE4) {
1398 vga_out8(0x3d4, 0xb0, par);
1399 vga_out8(0x3d5, reg->CRB0, par);
1402 vga_out8(0x3d4, 0x32, par);
1403 vga_out8(0x3d5, reg->CR32, par);
1405 /* unlock extended seq regs */
1406 vga_out8(0x3c4, 0x08, par);
1407 vga_out8(0x3c5, 0x06, par);
1409 /* Restore extended sequencer regs for MCLK. SR10 == 255 indicates
1410 * that we should leave the default SR10 and SR11 values there.
1412 if (reg->SR10 != 255) {
1413 vga_out8(0x3c4, 0x10, par);
1414 vga_out8(0x3c5, reg->SR10, par);
1415 vga_out8(0x3c4, 0x11, par);
1416 vga_out8(0x3c5, reg->SR11, par);
1419 /* restore extended seq regs for dclk */
1420 vga_out8(0x3c4, 0x0e, par);
1421 vga_out8(0x3c5, reg->SR0E, par);
1422 vga_out8(0x3c4, 0x0f, par);
1423 vga_out8(0x3c5, reg->SR0F, par);
1424 vga_out8(0x3c4, 0x12, par);
1425 vga_out8(0x3c5, reg->SR12, par);
1426 vga_out8(0x3c4, 0x13, par);
1427 vga_out8(0x3c5, reg->SR13, par);
1428 vga_out8(0x3c4, 0x29, par);
1429 vga_out8(0x3c5, reg->SR29, par);
1430 vga_out8(0x3c4, 0x18, par);
1431 vga_out8(0x3c5, reg->SR18, par);
1433 /* load new m, n pll values for dclk & mclk */
1434 vga_out8(0x3c4, 0x15, par);
1435 tmp = vga_in8(0x3c5, par) & ~0x21;
1437 vga_out8(0x3c5, tmp | 0x03, par);
1438 vga_out8(0x3c5, tmp | 0x23, par);
1439 vga_out8(0x3c5, tmp | 0x03, par);
1440 vga_out8(0x3c5, reg->SR15, par);
1443 vga_out8(0x3c4, 0x30, par);
1444 vga_out8(0x3c5, reg->SR30, par);
1445 vga_out8(0x3c4, 0x08, par);
1446 vga_out8(0x3c5, reg->SR08, par);
1448 /* now write out cr67 in full, possibly starting STREAMS */
1449 VerticalRetraceWait(par);
1450 vga_out8(0x3d4, 0x67, par);
1451 vga_out8(0x3d5, reg->CR67, par);
1453 vga_out8(0x3d4, 0x66, par);
1454 cr66 = vga_in8(0x3d5, par);
1455 vga_out8(0x3d5, cr66 | 0x80, par);
1456 vga_out8(0x3d4, 0x3a, par);
1457 cr3a = vga_in8(0x3d5, par);
1458 vga_out8(0x3d5, cr3a | 0x80, par);
1460 if (par->chip != S3_SAVAGE_MX) {
1461 VerticalRetraceWait(par);
1462 savage_out32(FIFO_CONTROL_REG, reg->MMPR0, par);
1463 par->SavageWaitIdle(par);
1464 savage_out32(MIU_CONTROL_REG, reg->MMPR1, par);
1465 par->SavageWaitIdle(par);
1466 savage_out32(STREAMS_TIMEOUT_REG, reg->MMPR2, par);
1467 par->SavageWaitIdle(par);
1468 savage_out32(MISC_TIMEOUT_REG, reg->MMPR3, par);
1471 vga_out8(0x3d4, 0x66, par);
1472 vga_out8(0x3d5, cr66, par);
1473 vga_out8(0x3d4, 0x3a, par);
1474 vga_out8(0x3d5, cr3a, par);
1476 SavageSetup2DEngine(par);
1477 vgaHWProtect(par, 0);
1480 static void savagefb_update_start(struct savagefb_par *par,
1481 struct fb_var_screeninfo *var)
1485 base = ((var->yoffset * var->xres_virtual + (var->xoffset & ~1))
1486 * ((var->bits_per_pixel+7) / 8)) >> 2;
1488 /* now program the start address registers */
1489 vga_out16(0x3d4, (base & 0x00ff00) | 0x0c, par);
1490 vga_out16(0x3d4, ((base & 0x00ff) << 8) | 0x0d, par);
1491 vga_out8(0x3d4, 0x69, par);
1492 vga_out8(0x3d5, (base & 0x7f0000) >> 16, par);
1496 static void savagefb_set_fix(struct fb_info *info)
1498 info->fix.line_length = info->var.xres_virtual *
1499 info->var.bits_per_pixel / 8;
1501 if (info->var.bits_per_pixel == 8) {
1502 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
1503 info->fix.xpanstep = 4;
1505 info->fix.visual = FB_VISUAL_TRUECOLOR;
1506 info->fix.xpanstep = 2;
1511 static int savagefb_set_par(struct fb_info *info)
1513 struct savagefb_par *par = info->par;
1514 struct fb_var_screeninfo *var = &info->var;
1517 DBG("savagefb_set_par");
1518 err = savagefb_decode_var(var, par, &par->state);
1522 if (par->dacSpeedBpp <= 0) {
1523 if (var->bits_per_pixel > 24)
1524 par->dacSpeedBpp = par->clock[3];
1525 else if (var->bits_per_pixel >= 24)
1526 par->dacSpeedBpp = par->clock[2];
1527 else if ((var->bits_per_pixel > 8) && (var->bits_per_pixel < 24))
1528 par->dacSpeedBpp = par->clock[1];
1529 else if (var->bits_per_pixel <= 8)
1530 par->dacSpeedBpp = par->clock[0];
1533 /* Set ramdac limits */
1534 par->maxClock = par->dacSpeedBpp;
1535 par->minClock = 10000;
1537 savagefb_set_par_int(par, &par->state);
1538 fb_set_cmap(&info->cmap, info);
1539 savagefb_set_fix(info);
1540 savagefb_set_clip(info);
1542 SavagePrintRegs(par);
1547 * Pan or Wrap the Display
1549 static int savagefb_pan_display(struct fb_var_screeninfo *var,
1550 struct fb_info *info)
1552 struct savagefb_par *par = info->par;
1554 savagefb_update_start(par, var);
1558 static int savagefb_blank(int blank, struct fb_info *info)
1560 struct savagefb_par *par = info->par;
1561 u8 sr8 = 0, srd = 0;
1563 if (par->display_type == DISP_CRT) {
1564 vga_out8(0x3c4, 0x08, par);
1565 sr8 = vga_in8(0x3c5, par);
1567 vga_out8(0x3c5, sr8, par);
1568 vga_out8(0x3c4, 0x0d, par);
1569 srd = vga_in8(0x3c5, par);
1573 case FB_BLANK_UNBLANK:
1574 case FB_BLANK_NORMAL:
1576 case FB_BLANK_VSYNC_SUSPEND:
1579 case FB_BLANK_HSYNC_SUSPEND:
1582 case FB_BLANK_POWERDOWN:
1587 vga_out8(0x3c4, 0x0d, par);
1588 vga_out8(0x3c5, srd, par);
1591 if (par->display_type == DISP_LCD ||
1592 par->display_type == DISP_DFP) {
1594 case FB_BLANK_UNBLANK:
1595 case FB_BLANK_NORMAL:
1596 vga_out8(0x3c4, 0x31, par); /* SR31 bit 4 - FP enable */
1597 vga_out8(0x3c5, vga_in8(0x3c5, par) | 0x10, par);
1599 case FB_BLANK_VSYNC_SUSPEND:
1600 case FB_BLANK_HSYNC_SUSPEND:
1601 case FB_BLANK_POWERDOWN:
1602 vga_out8(0x3c4, 0x31, par); /* SR31 bit 4 - FP enable */
1603 vga_out8(0x3c5, vga_in8(0x3c5, par) & ~0x10, par);
1608 return (blank == FB_BLANK_NORMAL) ? 1 : 0;
1611 static int savagefb_open(struct fb_info *info, int user)
1613 struct savagefb_par *par = info->par;
1615 mutex_lock(&par->open_lock);
1617 if (!par->open_count) {
1618 memset(&par->vgastate, 0, sizeof(par->vgastate));
1619 par->vgastate.flags = VGA_SAVE_CMAP | VGA_SAVE_FONTS |
1621 par->vgastate.vgabase = par->mmio.vbase + 0x8000;
1622 save_vga(&par->vgastate);
1623 savage_get_default_par(par, &par->initial);
1627 mutex_unlock(&par->open_lock);
1631 static int savagefb_release(struct fb_info *info, int user)
1633 struct savagefb_par *par = info->par;
1635 mutex_lock(&par->open_lock);
1637 if (par->open_count == 1) {
1638 savage_set_default_par(par, &par->initial);
1639 restore_vga(&par->vgastate);
1643 mutex_unlock(&par->open_lock);
1647 static struct fb_ops savagefb_ops = {
1648 .owner = THIS_MODULE,
1649 .fb_open = savagefb_open,
1650 .fb_release = savagefb_release,
1651 .fb_check_var = savagefb_check_var,
1652 .fb_set_par = savagefb_set_par,
1653 .fb_setcolreg = savagefb_setcolreg,
1654 .fb_pan_display = savagefb_pan_display,
1655 .fb_blank = savagefb_blank,
1656 #if defined(CONFIG_FB_SAVAGE_ACCEL)
1657 .fb_fillrect = savagefb_fillrect,
1658 .fb_copyarea = savagefb_copyarea,
1659 .fb_imageblit = savagefb_imageblit,
1660 .fb_sync = savagefb_sync,
1662 .fb_fillrect = cfb_fillrect,
1663 .fb_copyarea = cfb_copyarea,
1664 .fb_imageblit = cfb_imageblit,
1668 /* --------------------------------------------------------------------- */
1670 static struct fb_var_screeninfo __devinitdata savagefb_var800x600x8 = {
1671 .accel_flags = FB_ACCELF_TEXT,
1674 .xres_virtual = 800,
1675 .yres_virtual = 600,
1676 .bits_per_pixel = 8,
1684 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
1685 .vmode = FB_VMODE_NONINTERLACED
1688 static void savage_enable_mmio(struct savagefb_par *par)
1692 DBG("savage_enable_mmio\n");
1694 val = vga_in8(0x3c3, par);
1695 vga_out8(0x3c3, val | 0x01, par);
1696 val = vga_in8(0x3cc, par);
1697 vga_out8(0x3c2, val | 0x01, par);
1699 if (par->chip >= S3_SAVAGE4) {
1700 vga_out8(0x3d4, 0x40, par);
1701 val = vga_in8(0x3d5, par);
1702 vga_out8(0x3d5, val | 1, par);
1707 static void savage_disable_mmio(struct savagefb_par *par)
1711 DBG("savage_disable_mmio\n");
1713 if (par->chip >= S3_SAVAGE4) {
1714 vga_out8(0x3d4, 0x40, par);
1715 val = vga_in8(0x3d5, par);
1716 vga_out8(0x3d5, val | 1, par);
1721 static int __devinit savage_map_mmio(struct fb_info *info)
1723 struct savagefb_par *par = info->par;
1724 DBG("savage_map_mmio");
1726 if (S3_SAVAGE3D_SERIES(par->chip))
1727 par->mmio.pbase = pci_resource_start(par->pcidev, 0) +
1728 SAVAGE_NEWMMIO_REGBASE_S3;
1730 par->mmio.pbase = pci_resource_start(par->pcidev, 0) +
1731 SAVAGE_NEWMMIO_REGBASE_S4;
1733 par->mmio.len = SAVAGE_NEWMMIO_REGSIZE;
1735 par->mmio.vbase = ioremap(par->mmio.pbase, par->mmio.len);
1736 if (!par->mmio.vbase) {
1737 printk("savagefb: unable to map memory mapped IO\n");
1740 printk(KERN_INFO "savagefb: mapped io at %p\n",
1743 info->fix.mmio_start = par->mmio.pbase;
1744 info->fix.mmio_len = par->mmio.len;
1746 par->bci_base = (u32 __iomem *)(par->mmio.vbase + BCI_BUFFER_OFFSET);
1749 savage_enable_mmio(par);
1754 static void savage_unmap_mmio(struct fb_info *info)
1756 struct savagefb_par *par = info->par;
1757 DBG("savage_unmap_mmio");
1759 savage_disable_mmio(par);
1761 if (par->mmio.vbase) {
1762 iounmap(par->mmio.vbase);
1763 par->mmio.vbase = NULL;
1767 static int __devinit savage_map_video(struct fb_info *info,
1770 struct savagefb_par *par = info->par;
1773 DBG("savage_map_video");
1775 if (S3_SAVAGE3D_SERIES(par->chip))
1780 par->video.pbase = pci_resource_start(par->pcidev, resource);
1781 par->video.len = video_len;
1782 par->video.vbase = ioremap(par->video.pbase, par->video.len);
1784 if (!par->video.vbase) {
1785 printk("savagefb: unable to map screen memory\n");
1788 printk(KERN_INFO "savagefb: mapped framebuffer at %p, "
1789 "pbase == %x\n", par->video.vbase, par->video.pbase);
1791 info->fix.smem_start = par->video.pbase;
1792 info->fix.smem_len = par->video.len - par->cob_size;
1793 info->screen_base = par->video.vbase;
1796 par->video.mtrr = mtrr_add(par->video.pbase, video_len,
1797 MTRR_TYPE_WRCOMB, 1);
1800 /* Clear framebuffer, it's all white in memory after boot */
1801 memset_io(par->video.vbase, 0, par->video.len);
1806 static void savage_unmap_video(struct fb_info *info)
1808 struct savagefb_par *par = info->par;
1810 DBG("savage_unmap_video");
1812 if (par->video.vbase) {
1814 mtrr_del(par->video.mtrr, par->video.pbase, par->video.len);
1817 iounmap(par->video.vbase);
1818 par->video.vbase = NULL;
1819 info->screen_base = NULL;
1823 static int savage_init_hw(struct savagefb_par *par)
1825 unsigned char config1, m, n, n1, n2, sr8, cr3f, cr66 = 0, tmp;
1827 static unsigned char RamSavage3D[] = { 8, 4, 4, 2 };
1828 static unsigned char RamSavage4[] = { 2, 4, 8, 12, 16, 32, 64, 32 };
1829 static unsigned char RamSavageMX[] = { 2, 8, 4, 16, 8, 16, 4, 16 };
1830 static unsigned char RamSavageNB[] = { 0, 2, 4, 8, 16, 32, 2, 2 };
1831 int videoRam, videoRambytes, dvi;
1833 DBG("savage_init_hw");
1835 /* unprotect CRTC[0-7] */
1836 vga_out8(0x3d4, 0x11, par);
1837 tmp = vga_in8(0x3d5, par);
1838 vga_out8(0x3d5, tmp & 0x7f, par);
1840 /* unlock extended regs */
1841 vga_out16(0x3d4, 0x4838, par);
1842 vga_out16(0x3d4, 0xa039, par);
1843 vga_out16(0x3c4, 0x0608, par);
1845 vga_out8(0x3d4, 0x40, par);
1846 tmp = vga_in8(0x3d5, par);
1847 vga_out8(0x3d5, tmp & ~0x01, par);
1849 /* unlock sys regs */
1850 vga_out8(0x3d4, 0x38, par);
1851 vga_out8(0x3d5, 0x48, par);
1853 /* Unlock system registers. */
1854 vga_out16(0x3d4, 0x4838, par);
1856 /* Next go on to detect amount of installed ram */
1858 vga_out8(0x3d4, 0x36, par); /* for register CR36 (CONFG_REG1), */
1859 config1 = vga_in8(0x3d5, par); /* get amount of vram installed */
1861 /* Compute the amount of video memory and offscreen memory. */
1863 switch (par->chip) {
1865 videoRam = RamSavage3D[(config1 & 0xC0) >> 6 ] * 1024;
1870 * The Savage4 has one ugly special case to consider. On
1871 * systems with 4 banks of 2Mx32 SDRAM, the BIOS says 4MB
1872 * when it really means 8MB. Why do it the same when you
1873 * can do it different...
1875 vga_out8(0x3d4, 0x68, par); /* memory control 1 */
1876 if ((vga_in8(0x3d5, par) & 0xC0) == (0x01 << 6))
1882 videoRam = RamSavage4[(config1 & 0xE0) >> 5] * 1024;
1886 case S3_SUPERSAVAGE:
1887 videoRam = RamSavageMX[(config1 & 0x0E) >> 1] * 1024;
1891 case S3_PROSAVAGEDDR:
1893 videoRam = RamSavageNB[(config1 & 0xE0) >> 5] * 1024;
1897 /* How did we get here? */
1902 videoRambytes = videoRam * 1024;
1904 printk(KERN_INFO "savagefb: probed videoram: %dk\n", videoRam);
1906 /* reset graphics engine to avoid memory corruption */
1907 vga_out8(0x3d4, 0x66, par);
1908 cr66 = vga_in8(0x3d5, par);
1909 vga_out8(0x3d5, cr66 | 0x02, par);
1912 vga_out8(0x3d4, 0x66, par);
1913 vga_out8(0x3d5, cr66 & ~0x02, par); /* clear reset flag */
1918 * reset memory interface, 3D engine, AGP master, PCI master,
1919 * master engine unit, motion compensation/LPB
1921 vga_out8(0x3d4, 0x3f, par);
1922 cr3f = vga_in8(0x3d5, par);
1923 vga_out8(0x3d5, cr3f | 0x08, par);
1926 vga_out8(0x3d4, 0x3f, par);
1927 vga_out8(0x3d5, cr3f & ~0x08, par); /* clear reset flags */
1930 /* Savage ramdac speeds */
1932 par->clock[0] = 250000;
1933 par->clock[1] = 250000;
1934 par->clock[2] = 220000;
1935 par->clock[3] = 220000;
1937 /* detect current mclk */
1938 vga_out8(0x3c4, 0x08, par);
1939 sr8 = vga_in8(0x3c5, par);
1940 vga_out8(0x3c5, 0x06, par);
1941 vga_out8(0x3c4, 0x10, par);
1942 n = vga_in8(0x3c5, par);
1943 vga_out8(0x3c4, 0x11, par);
1944 m = vga_in8(0x3c5, par);
1945 vga_out8(0x3c4, 0x08, par);
1946 vga_out8(0x3c5, sr8, par);
1949 n2 = (n >> 5) & 0x03;
1950 par->MCLK = ((1431818 * (m+2)) / (n1+2) / (1 << n2) + 50) / 100;
1951 printk(KERN_INFO "savagefb: Detected current MCLK value of %d kHz\n",
1954 /* check for DVI/flat panel */
1957 if (par->chip == S3_SAVAGE4) {
1958 unsigned char sr30 = 0x00;
1960 vga_out8(0x3c4, 0x30, par);
1962 vga_out8(0x3c5, vga_in8(0x3c5, par) & ~0x02, par);
1963 sr30 = vga_in8(0x3c5, par);
1964 if (sr30 & 0x02 /*0x04 */) {
1966 printk("savagefb: Digital Flat Panel Detected\n");
1970 if ((S3_SAVAGE_MOBILE_SERIES(par->chip) ||
1971 S3_MOBILE_TWISTER_SERIES(par->chip)) && !par->crtonly)
1972 par->display_type = DISP_LCD;
1973 else if (dvi || (par->chip == S3_SAVAGE4 && par->dvi))
1974 par->display_type = DISP_DFP;
1976 par->display_type = DISP_CRT;
1978 /* Check LCD panel parrmation */
1980 if (par->display_type == DISP_LCD) {
1981 unsigned char cr6b = VGArCR(0x6b, par);
1983 int panelX = (VGArSEQ(0x61, par) +
1984 ((VGArSEQ(0x66, par) & 0x02) << 7) + 1) * 8;
1985 int panelY = (VGArSEQ(0x69, par) +
1986 ((VGArSEQ(0x6e, par) & 0x70) << 4) + 1);
1988 char * sTechnology = "Unknown";
1990 /* OK, I admit it. I don't know how to limit the max dot clock
1991 * for LCD panels of various sizes. I thought I copied the
1992 * formula from the BIOS, but many users have parrmed me of
1995 * Instead, I'll abandon any attempt to automatically limit the
1996 * clock, and add an LCDClock option to XF86Config. Some day,
1997 * I should come back to this.
2000 enum ACTIVE_DISPLAYS { /* These are the bits in CR6B */
2008 if ((VGArSEQ(0x39, par) & 0x03) == 0) {
2009 sTechnology = "TFT";
2010 } else if ((VGArSEQ(0x30, par) & 0x01) == 0) {
2011 sTechnology = "DSTN";
2013 sTechnology = "STN";
2016 printk(KERN_INFO "savagefb: %dx%d %s LCD panel detected %s\n",
2017 panelX, panelY, sTechnology,
2018 cr6b & ActiveLCD ? "and active" : "but not active");
2020 if (cr6b & ActiveLCD) {
2022 * If the LCD is active and panel expansion is enabled,
2023 * we probably want to kill the HW cursor.
2026 printk(KERN_INFO "savagefb: Limiting video mode to "
2027 "%dx%d\n", panelX, panelY);
2029 par->SavagePanelWidth = panelX;
2030 par->SavagePanelHeight = panelY;
2033 par->display_type = DISP_CRT;
2036 savage_get_default_par(par, &par->state);
2037 par->save = par->state;
2039 if (S3_SAVAGE4_SERIES(par->chip)) {
2041 * The Savage4 and ProSavage have COB coherency bugs which
2042 * render the buffer useless. We disable it.
2045 par->cob_size = 0x8000 << par->cob_index;
2046 par->cob_offset = videoRambytes;
2048 /* We use 128kB for the COB on all chips. */
2051 par->cob_size = 0x400 << par->cob_index;
2052 par->cob_offset = videoRambytes - par->cob_size;
2055 return videoRambytes;
2058 static int __devinit savage_init_fb_info(struct fb_info *info,
2059 struct pci_dev *dev,
2060 const struct pci_device_id *id)
2062 struct savagefb_par *par = info->par;
2067 info->fix.type = FB_TYPE_PACKED_PIXELS;
2068 info->fix.type_aux = 0;
2069 info->fix.ypanstep = 1;
2070 info->fix.ywrapstep = 0;
2071 info->fix.accel = id->driver_data;
2073 switch (info->fix.accel) {
2074 case FB_ACCEL_SUPERSAVAGE:
2075 par->chip = S3_SUPERSAVAGE;
2076 snprintf(info->fix.id, 16, "SuperSavage");
2078 case FB_ACCEL_SAVAGE4:
2079 par->chip = S3_SAVAGE4;
2080 snprintf(info->fix.id, 16, "Savage4");
2082 case FB_ACCEL_SAVAGE3D:
2083 par->chip = S3_SAVAGE3D;
2084 snprintf(info->fix.id, 16, "Savage3D");
2086 case FB_ACCEL_SAVAGE3D_MV:
2087 par->chip = S3_SAVAGE3D;
2088 snprintf(info->fix.id, 16, "Savage3D-MV");
2090 case FB_ACCEL_SAVAGE2000:
2091 par->chip = S3_SAVAGE2000;
2092 snprintf(info->fix.id, 16, "Savage2000");
2094 case FB_ACCEL_SAVAGE_MX_MV:
2095 par->chip = S3_SAVAGE_MX;
2096 snprintf(info->fix.id, 16, "Savage/MX-MV");
2098 case FB_ACCEL_SAVAGE_MX:
2099 par->chip = S3_SAVAGE_MX;
2100 snprintf(info->fix.id, 16, "Savage/MX");
2102 case FB_ACCEL_SAVAGE_IX_MV:
2103 par->chip = S3_SAVAGE_MX;
2104 snprintf(info->fix.id, 16, "Savage/IX-MV");
2106 case FB_ACCEL_SAVAGE_IX:
2107 par->chip = S3_SAVAGE_MX;
2108 snprintf(info->fix.id, 16, "Savage/IX");
2110 case FB_ACCEL_PROSAVAGE_PM:
2111 par->chip = S3_PROSAVAGE;
2112 snprintf(info->fix.id, 16, "ProSavagePM");
2114 case FB_ACCEL_PROSAVAGE_KM:
2115 par->chip = S3_PROSAVAGE;
2116 snprintf(info->fix.id, 16, "ProSavageKM");
2118 case FB_ACCEL_S3TWISTER_P:
2119 par->chip = S3_TWISTER;
2120 snprintf(info->fix.id, 16, "TwisterP");
2122 case FB_ACCEL_S3TWISTER_K:
2123 par->chip = S3_TWISTER;
2124 snprintf(info->fix.id, 16, "TwisterK");
2126 case FB_ACCEL_PROSAVAGE_DDR:
2127 par->chip = S3_PROSAVAGEDDR;
2128 snprintf(info->fix.id, 16, "ProSavageDDR");
2130 case FB_ACCEL_PROSAVAGE_DDRK:
2131 par->chip = S3_PROSAVAGEDDR;
2132 snprintf(info->fix.id, 16, "ProSavage8");
2136 if (S3_SAVAGE3D_SERIES(par->chip)) {
2137 par->SavageWaitIdle = savage3D_waitidle;
2138 par->SavageWaitFifo = savage3D_waitfifo;
2139 } else if (S3_SAVAGE4_SERIES(par->chip) ||
2140 S3_SUPERSAVAGE == par->chip) {
2141 par->SavageWaitIdle = savage4_waitidle;
2142 par->SavageWaitFifo = savage4_waitfifo;
2144 par->SavageWaitIdle = savage2000_waitidle;
2145 par->SavageWaitFifo = savage2000_waitfifo;
2148 info->var.nonstd = 0;
2149 info->var.activate = FB_ACTIVATE_NOW;
2150 info->var.width = -1;
2151 info->var.height = -1;
2152 info->var.accel_flags = 0;
2154 info->fbops = &savagefb_ops;
2155 info->flags = FBINFO_DEFAULT |
2156 FBINFO_HWACCEL_YPAN |
2157 FBINFO_HWACCEL_XPAN;
2159 info->pseudo_palette = par->pseudo_palette;
2161 #if defined(CONFIG_FB_SAVAGE_ACCEL)
2162 /* FIFO size + padding for commands */
2163 info->pixmap.addr = kcalloc(8, 1024, GFP_KERNEL);
2166 if (info->pixmap.addr) {
2167 info->pixmap.size = 8*1024;
2168 info->pixmap.scan_align = 4;
2169 info->pixmap.buf_align = 4;
2170 info->pixmap.access_align = 32;
2172 err = fb_alloc_cmap(&info->cmap, NR_PALETTE, 0);
2174 info->flags |= FBINFO_HWACCEL_COPYAREA |
2175 FBINFO_HWACCEL_FILLRECT |
2176 FBINFO_HWACCEL_IMAGEBLIT;
2182 /* --------------------------------------------------------------------- */
2184 static int __devinit savagefb_probe(struct pci_dev* dev,
2185 const struct pci_device_id* id)
2187 struct fb_info *info;
2188 struct savagefb_par *par;
2189 u_int h_sync, v_sync;
2193 DBG("savagefb_probe");
2195 info = framebuffer_alloc(sizeof(struct savagefb_par), &dev->dev);
2199 mutex_init(&par->open_lock);
2200 err = pci_enable_device(dev);
2204 if ((err = pci_request_regions(dev, "savagefb"))) {
2205 printk(KERN_ERR "cannot request PCI regions\n");
2211 if ((err = savage_init_fb_info(info, dev, id)))
2214 err = savage_map_mmio(info);
2218 video_len = savage_init_hw(par);
2219 /* FIXME: can't be negative */
2220 if (video_len < 0) {
2225 err = savage_map_video(info, video_len);
2229 INIT_LIST_HEAD(&info->modelist);
2230 #if defined(CONFIG_FB_SAVAGE_I2C)
2231 savagefb_create_i2c_busses(info);
2232 savagefb_probe_i2c_connector(info, &par->edid);
2233 fb_edid_to_monspecs(par->edid, &info->monspecs);
2235 fb_videomode_to_modelist(info->monspecs.modedb,
2236 info->monspecs.modedb_len,
2239 info->var = savagefb_var800x600x8;
2242 fb_find_mode(&info->var, info, mode_option,
2243 info->monspecs.modedb, info->monspecs.modedb_len,
2245 } else if (info->monspecs.modedb != NULL) {
2246 const struct fb_videomode *mode;
2248 mode = fb_find_best_display(&info->monspecs, &info->modelist);
2249 savage_update_var(&info->var, mode);
2252 /* maximize virtual vertical length */
2253 lpitch = info->var.xres_virtual*((info->var.bits_per_pixel + 7) >> 3);
2254 info->var.yres_virtual = info->fix.smem_len/lpitch;
2256 if (info->var.yres_virtual < info->var.yres)
2259 #if defined(CONFIG_FB_SAVAGE_ACCEL)
2261 * The clipping coordinates are masked with 0xFFF, so limit our
2262 * virtual resolutions to these sizes.
2264 if (info->var.yres_virtual > 0x1000)
2265 info->var.yres_virtual = 0x1000;
2267 if (info->var.xres_virtual > 0x1000)
2268 info->var.xres_virtual = 0x1000;
2270 savagefb_check_var(&info->var, info);
2271 savagefb_set_fix(info);
2274 * Calculate the hsync and vsync frequencies. Note that
2275 * we split the 1e12 constant up so that we can preserve
2276 * the precision and fit the results into 32-bit registers.
2277 * (1953125000 * 512 = 1e12)
2279 h_sync = 1953125000 / info->var.pixclock;
2280 h_sync = h_sync * 512 / (info->var.xres + info->var.left_margin +
2281 info->var.right_margin +
2282 info->var.hsync_len);
2283 v_sync = h_sync / (info->var.yres + info->var.upper_margin +
2284 info->var.lower_margin + info->var.vsync_len);
2286 printk(KERN_INFO "savagefb v" SAVAGEFB_VERSION ": "
2287 "%dkB VRAM, using %dx%d, %d.%03dkHz, %dHz\n",
2288 info->fix.smem_len >> 10,
2289 info->var.xres, info->var.yres,
2290 h_sync / 1000, h_sync % 1000, v_sync);
2293 fb_destroy_modedb(info->monspecs.modedb);
2294 info->monspecs.modedb = NULL;
2296 err = register_framebuffer(info);
2300 printk(KERN_INFO "fb: S3 %s frame buffer device\n",
2306 pci_set_drvdata(dev, info);
2311 #ifdef CONFIG_FB_SAVAGE_I2C
2312 savagefb_delete_i2c_busses(info);
2314 fb_alloc_cmap(&info->cmap, 0, 0);
2315 savage_unmap_video(info);
2317 savage_unmap_mmio(info);
2319 kfree(info->pixmap.addr);
2321 pci_release_regions(dev);
2323 framebuffer_release(info);
2328 static void __devexit savagefb_remove(struct pci_dev *dev)
2330 struct fb_info *info = pci_get_drvdata(dev);
2332 DBG("savagefb_remove");
2336 * If unregister_framebuffer fails, then
2337 * we will be leaving hooks that could cause
2338 * oopsen laying around.
2340 if (unregister_framebuffer(info))
2341 printk(KERN_WARNING "savagefb: danger danger! "
2342 "Oopsen imminent!\n");
2344 #ifdef CONFIG_FB_SAVAGE_I2C
2345 savagefb_delete_i2c_busses(info);
2347 fb_alloc_cmap(&info->cmap, 0, 0);
2348 savage_unmap_video(info);
2349 savage_unmap_mmio(info);
2350 kfree(info->pixmap.addr);
2351 pci_release_regions(dev);
2352 framebuffer_release(info);
2355 * Ensure that the driver data is no longer
2358 pci_set_drvdata(dev, NULL);
2362 static int savagefb_suspend(struct pci_dev *dev, pm_message_t mesg)
2364 struct fb_info *info = pci_get_drvdata(dev);
2365 struct savagefb_par *par = info->par;
2367 DBG("savagefb_suspend");
2369 if (mesg.event == PM_EVENT_PRETHAW)
2370 mesg.event = PM_EVENT_FREEZE;
2371 par->pm_state = mesg.event;
2372 dev->dev.power.power_state = mesg;
2375 * For PM_EVENT_FREEZE, do not power down so the console
2376 * can remain active.
2378 if (mesg.event == PM_EVENT_FREEZE)
2382 fb_set_suspend(info, 1);
2384 if (info->fbops->fb_sync)
2385 info->fbops->fb_sync(info);
2387 savagefb_blank(FB_BLANK_POWERDOWN, info);
2388 savage_set_default_par(par, &par->save);
2389 savage_disable_mmio(par);
2390 pci_save_state(dev);
2391 pci_disable_device(dev);
2392 pci_set_power_state(dev, pci_choose_state(dev, mesg));
2398 static int savagefb_resume(struct pci_dev* dev)
2400 struct fb_info *info = pci_get_drvdata(dev);
2401 struct savagefb_par *par = info->par;
2402 int cur_state = par->pm_state;
2404 DBG("savage_resume");
2406 par->pm_state = PM_EVENT_ON;
2409 * The adapter was not powered down coming back from a
2412 if (cur_state == PM_EVENT_FREEZE) {
2413 pci_set_power_state(dev, PCI_D0);
2419 pci_set_power_state(dev, PCI_D0);
2420 pci_restore_state(dev);
2422 if (pci_enable_device(dev))
2425 pci_set_master(dev);
2426 savage_enable_mmio(par);
2427 savage_init_hw(par);
2428 savagefb_set_par(info);
2429 fb_set_suspend(info, 0);
2430 savagefb_blank(FB_BLANK_UNBLANK, info);
2437 static struct pci_device_id savagefb_devices[] __devinitdata = {
2438 {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_MX128,
2439 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2441 {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_MX64,
2442 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2444 {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_MX64C,
2445 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2447 {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IX128SDR,
2448 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2450 {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IX128DDR,
2451 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2453 {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IX64SDR,
2454 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2456 {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IX64DDR,
2457 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2459 {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IXCSDR,
2460 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2462 {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IXCDDR,
2463 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2465 {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE4,
2466 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE4},
2468 {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE3D,
2469 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE3D},
2471 {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE3D_MV,
2472 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE3D_MV},
2474 {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE2000,
2475 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE2000},
2477 {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE_MX_MV,
2478 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE_MX_MV},
2480 {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE_MX,
2481 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE_MX},
2483 {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE_IX_MV,
2484 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE_IX_MV},
2486 {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE_IX,
2487 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE_IX},
2489 {PCI_VENDOR_ID_S3, PCI_CHIP_PROSAVAGE_PM,
2490 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_PROSAVAGE_PM},
2492 {PCI_VENDOR_ID_S3, PCI_CHIP_PROSAVAGE_KM,
2493 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_PROSAVAGE_KM},
2495 {PCI_VENDOR_ID_S3, PCI_CHIP_S3TWISTER_P,
2496 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_S3TWISTER_P},
2498 {PCI_VENDOR_ID_S3, PCI_CHIP_S3TWISTER_K,
2499 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_S3TWISTER_K},
2501 {PCI_VENDOR_ID_S3, PCI_CHIP_PROSAVAGE_DDR,
2502 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_PROSAVAGE_DDR},
2504 {PCI_VENDOR_ID_S3, PCI_CHIP_PROSAVAGE_DDRK,
2505 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_PROSAVAGE_DDRK},
2507 {0, 0, 0, 0, 0, 0, 0}
2510 MODULE_DEVICE_TABLE(pci, savagefb_devices);
2512 static struct pci_driver savagefb_driver = {
2514 .id_table = savagefb_devices,
2515 .probe = savagefb_probe,
2516 .suspend = savagefb_suspend,
2517 .resume = savagefb_resume,
2518 .remove = __devexit_p(savagefb_remove)
2521 /* **************************** exit-time only **************************** */
2523 static void __exit savage_done(void)
2526 pci_unregister_driver(&savagefb_driver);
2530 /* ************************* init in-kernel code ************************** */
2532 static int __init savagefb_setup(char *options)
2537 if (!options || !*options)
2540 while ((this_opt = strsep(&options, ",")) != NULL) {
2541 mode_option = this_opt;
2543 #endif /* !MODULE */
2547 static int __init savagefb_init(void)
2551 DBG("savagefb_init");
2553 if (fb_get_options("savagefb", &option))
2556 savagefb_setup(option);
2557 return pci_register_driver(&savagefb_driver);
2561 module_init(savagefb_init);
2562 module_exit(savage_done);
2564 module_param(mode_option, charp, 0);
2565 MODULE_PARM_DESC(mode_option, "Specify initial video mode");