drivers/video/sh_mobile_hdmi.c

   1 /*
   2  * SH-Mobile High-Definition Multimedia Interface (HDMI) driver
   3  * for SLISHDMI13T and SLIPHDMIT IP cores
   4  *
   5  * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/console.h>
  14 #include <linux/delay.h>
  15 #include <linux/err.h>
  16 #include <linux/init.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/slab.h>
  23 #include <linux/types.h>
  24 #include <linux/workqueue.h>
  25 #include <sound/soc.h>
  26 #include <sound/soc-dapm.h>
  27 #include <sound/initval.h>
  28
  29 #include <video/sh_mobile_hdmi.h>
  30 #include <video/sh_mobile_lcdc.h>
  31
  32 #include "sh_mobile_lcdcfb.h"
  33
  34 #define HDMI_SYSTEM_CTRL                        0x00 /* System control */
  35 #define HDMI_L_R_DATA_SWAP_CTRL_RPKT            0x01 /* L/R data swap control,
  36                                                         bits 19..16 of 20-bit N for Audio Clock Regeneration packet */
  37 #define HDMI_20_BIT_N_FOR_AUDIO_RPKT_15_8       0x02 /* bits 15..8 of 20-bit N for Audio Clock Regeneration packet */
  38 #define HDMI_20_BIT_N_FOR_AUDIO_RPKT_7_0        0x03 /* bits 7..0 of 20-bit N for Audio Clock Regeneration packet */
  39 #define HDMI_SPDIF_AUDIO_SAMP_FREQ_CTS          0x04 /* SPDIF audio sampling frequency,
  40                                                         bits 19..16 of Internal CTS */
  41 #define HDMI_INTERNAL_CTS_15_8                  0x05 /* bits 15..8 of Internal CTS */
  42 #define HDMI_INTERNAL_CTS_7_0                   0x06 /* bits 7..0 of Internal CTS */
  43 #define HDMI_EXTERNAL_CTS_19_16                 0x07 /* External CTS */
  44 #define HDMI_EXTERNAL_CTS_15_8                  0x08 /* External CTS */
  45 #define HDMI_EXTERNAL_CTS_7_0                   0x09 /* External CTS */
  46 #define HDMI_AUDIO_SETTING_1                    0x0A /* Audio setting.1 */
  47 #define HDMI_AUDIO_SETTING_2                    0x0B /* Audio setting.2 */
  48 #define HDMI_I2S_AUDIO_SET                      0x0C /* I2S audio setting */
  49 #define HDMI_DSD_AUDIO_SET                      0x0D /* DSD audio setting */
  50 #define HDMI_DEBUG_MONITOR_1                    0x0E /* Debug monitor.1 */
  51 #define HDMI_DEBUG_MONITOR_2                    0x0F /* Debug monitor.2 */
  52 #define HDMI_I2S_INPUT_PIN_SWAP                 0x10 /* I2S input pin swap */
  53 #define HDMI_AUDIO_STATUS_BITS_SETTING_1        0x11 /* Audio status bits setting.1 */
  54 #define HDMI_AUDIO_STATUS_BITS_SETTING_2        0x12 /* Audio status bits setting.2 */
  55 #define HDMI_CATEGORY_CODE                      0x13 /* Category code */
  56 #define HDMI_SOURCE_NUM_AUDIO_WORD_LEN          0x14 /* Source number/Audio word length */
  57 #define HDMI_AUDIO_VIDEO_SETTING_1              0x15 /* Audio/Video setting.1 */
  58 #define HDMI_VIDEO_SETTING_1                    0x16 /* Video setting.1 */
  59 #define HDMI_DEEP_COLOR_MODES                   0x17 /* Deep Color Modes */
  60
  61 /* 12 16- and 10-bit Color space conversion parameters: 0x18..0x2f */
  62 #define HDMI_COLOR_SPACE_CONVERSION_PARAMETERS  0x18
  63
  64 #define HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS      0x30 /* External video parameter settings */
  65 #define HDMI_EXTERNAL_H_TOTAL_7_0               0x31 /* External horizontal total (LSB) */
  66 #define HDMI_EXTERNAL_H_TOTAL_11_8              0x32 /* External horizontal total (MSB) */
  67 #define HDMI_EXTERNAL_H_BLANK_7_0               0x33 /* External horizontal blank (LSB) */
  68 #define HDMI_EXTERNAL_H_BLANK_9_8               0x34 /* External horizontal blank (MSB) */
  69 #define HDMI_EXTERNAL_H_DELAY_7_0               0x35 /* External horizontal delay (LSB) */
  70 #define HDMI_EXTERNAL_H_DELAY_9_8               0x36 /* External horizontal delay (MSB) */
  71 #define HDMI_EXTERNAL_H_DURATION_7_0            0x37 /* External horizontal duration (LSB) */
  72 #define HDMI_EXTERNAL_H_DURATION_9_8            0x38 /* External horizontal duration (MSB) */
  73 #define HDMI_EXTERNAL_V_TOTAL_7_0               0x39 /* External vertical total (LSB) */
  74 #define HDMI_EXTERNAL_V_TOTAL_9_8               0x3A /* External vertical total (MSB) */
  75 #define HDMI_AUDIO_VIDEO_SETTING_2              0x3B /* Audio/Video setting.2 */
  76 #define HDMI_EXTERNAL_V_BLANK                   0x3D /* External vertical blank */
  77 #define HDMI_EXTERNAL_V_DELAY                   0x3E /* External vertical delay */
  78 #define HDMI_EXTERNAL_V_DURATION                0x3F /* External vertical duration */
  79 #define HDMI_CTRL_PKT_MANUAL_SEND_CONTROL       0x40 /* Control packet manual send control */
  80 #define HDMI_CTRL_PKT_AUTO_SEND                 0x41 /* Control packet auto send with VSYNC control */
  81 #define HDMI_AUTO_CHECKSUM_OPTION               0x42 /* Auto checksum option */
  82 #define HDMI_VIDEO_SETTING_2                    0x45 /* Video setting.2 */
  83 #define HDMI_OUTPUT_OPTION                      0x46 /* Output option */
  84 #define HDMI_SLIPHDMIT_PARAM_OPTION             0x51 /* SLIPHDMIT parameter option */
  85 #define HDMI_HSYNC_PMENT_AT_EMB_7_0             0x52 /* HSYNC placement at embedded sync (LSB) */
  86 #define HDMI_HSYNC_PMENT_AT_EMB_15_8            0x53 /* HSYNC placement at embedded sync (MSB) */
  87 #define HDMI_VSYNC_PMENT_AT_EMB_7_0             0x54 /* VSYNC placement at embedded sync (LSB) */
  88 #define HDMI_VSYNC_PMENT_AT_EMB_14_8            0x55 /* VSYNC placement at embedded sync (MSB) */
  89 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_1         0x56 /* SLIPHDMIT parameter settings.1 */
  90 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_2         0x57 /* SLIPHDMIT parameter settings.2 */
  91 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_3         0x58 /* SLIPHDMIT parameter settings.3 */
  92 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_5         0x59 /* SLIPHDMIT parameter settings.5 */
  93 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_6         0x5A /* SLIPHDMIT parameter settings.6 */
  94 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_7         0x5B /* SLIPHDMIT parameter settings.7 */
  95 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_8         0x5C /* SLIPHDMIT parameter settings.8 */
  96 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_9         0x5D /* SLIPHDMIT parameter settings.9 */
  97 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_10        0x5E /* SLIPHDMIT parameter settings.10 */
  98 #define HDMI_CTRL_PKT_BUF_INDEX                 0x5F /* Control packet buffer index */
  99 #define HDMI_CTRL_PKT_BUF_ACCESS_HB0            0x60 /* Control packet data buffer access window - HB0 */
 100 #define HDMI_CTRL_PKT_BUF_ACCESS_HB1            0x61 /* Control packet data buffer access window - HB1 */
 101 #define HDMI_CTRL_PKT_BUF_ACCESS_HB2            0x62 /* Control packet data buffer access window - HB2 */
 102 #define HDMI_CTRL_PKT_BUF_ACCESS_PB0            0x63 /* Control packet data buffer access window - PB0 */
 103 #define HDMI_CTRL_PKT_BUF_ACCESS_PB1            0x64 /* Control packet data buffer access window - PB1 */
 104 #define HDMI_CTRL_PKT_BUF_ACCESS_PB2            0x65 /* Control packet data buffer access window - PB2 */
 105 #define HDMI_CTRL_PKT_BUF_ACCESS_PB3            0x66 /* Control packet data buffer access window - PB3 */
 106 #define HDMI_CTRL_PKT_BUF_ACCESS_PB4            0x67 /* Control packet data buffer access window - PB4 */
 107 #define HDMI_CTRL_PKT_BUF_ACCESS_PB5            0x68 /* Control packet data buffer access window - PB5 */
 108 #define HDMI_CTRL_PKT_BUF_ACCESS_PB6            0x69 /* Control packet data buffer access window - PB6 */
 109 #define HDMI_CTRL_PKT_BUF_ACCESS_PB7            0x6A /* Control packet data buffer access window - PB7 */
 110 #define HDMI_CTRL_PKT_BUF_ACCESS_PB8            0x6B /* Control packet data buffer access window - PB8 */
 111 #define HDMI_CTRL_PKT_BUF_ACCESS_PB9            0x6C /* Control packet data buffer access window - PB9 */
 112 #define HDMI_CTRL_PKT_BUF_ACCESS_PB10           0x6D /* Control packet data buffer access window - PB10 */
 113 #define HDMI_CTRL_PKT_BUF_ACCESS_PB11           0x6E /* Control packet data buffer access window - PB11 */
 114 #define HDMI_CTRL_PKT_BUF_ACCESS_PB12           0x6F /* Control packet data buffer access window - PB12 */
 115 #define HDMI_CTRL_PKT_BUF_ACCESS_PB13           0x70 /* Control packet data buffer access window - PB13 */
 116 #define HDMI_CTRL_PKT_BUF_ACCESS_PB14           0x71 /* Control packet data buffer access window - PB14 */
 117 #define HDMI_CTRL_PKT_BUF_ACCESS_PB15           0x72 /* Control packet data buffer access window - PB15 */
 118 #define HDMI_CTRL_PKT_BUF_ACCESS_PB16           0x73 /* Control packet data buffer access window - PB16 */
 119 #define HDMI_CTRL_PKT_BUF_ACCESS_PB17           0x74 /* Control packet data buffer access window - PB17 */
 120 #define HDMI_CTRL_PKT_BUF_ACCESS_PB18           0x75 /* Control packet data buffer access window - PB18 */
 121 #define HDMI_CTRL_PKT_BUF_ACCESS_PB19           0x76 /* Control packet data buffer access window - PB19 */
 122 #define HDMI_CTRL_PKT_BUF_ACCESS_PB20           0x77 /* Control packet data buffer access window - PB20 */
 123 #define HDMI_CTRL_PKT_BUF_ACCESS_PB21           0x78 /* Control packet data buffer access window - PB21 */
 124 #define HDMI_CTRL_PKT_BUF_ACCESS_PB22           0x79 /* Control packet data buffer access window - PB22 */
 125 #define HDMI_CTRL_PKT_BUF_ACCESS_PB23           0x7A /* Control packet data buffer access window - PB23 */
 126 #define HDMI_CTRL_PKT_BUF_ACCESS_PB24           0x7B /* Control packet data buffer access window - PB24 */
 127 #define HDMI_CTRL_PKT_BUF_ACCESS_PB25           0x7C /* Control packet data buffer access window - PB25 */
 128 #define HDMI_CTRL_PKT_BUF_ACCESS_PB26           0x7D /* Control packet data buffer access window - PB26 */
 129 #define HDMI_CTRL_PKT_BUF_ACCESS_PB27           0x7E /* Control packet data buffer access window - PB27 */
 130 #define HDMI_EDID_KSV_FIFO_ACCESS_WINDOW        0x80 /* EDID/KSV FIFO access window */
 131 #define HDMI_DDC_BUS_ACCESS_FREQ_CTRL_7_0       0x81 /* DDC bus access frequency control (LSB) */
 132 #define HDMI_DDC_BUS_ACCESS_FREQ_CTRL_15_8      0x82 /* DDC bus access frequency control (MSB) */
 133 #define HDMI_INTERRUPT_MASK_1                   0x92 /* Interrupt mask.1 */
 134 #define HDMI_INTERRUPT_MASK_2                   0x93 /* Interrupt mask.2 */
 135 #define HDMI_INTERRUPT_STATUS_1                 0x94 /* Interrupt status.1 */
 136 #define HDMI_INTERRUPT_STATUS_2                 0x95 /* Interrupt status.2 */
 137 #define HDMI_INTERRUPT_MASK_3                   0x96 /* Interrupt mask.3 */
 138 #define HDMI_INTERRUPT_MASK_4                   0x97 /* Interrupt mask.4 */
 139 #define HDMI_INTERRUPT_STATUS_3                 0x98 /* Interrupt status.3 */
 140 #define HDMI_INTERRUPT_STATUS_4                 0x99 /* Interrupt status.4 */
 141 #define HDMI_SOFTWARE_HDCP_CONTROL_1            0x9A /* Software HDCP control.1 */
 142 #define HDMI_FRAME_COUNTER                      0x9C /* Frame counter */
 143 #define HDMI_FRAME_COUNTER_FOR_RI_CHECK         0x9D /* Frame counter for Ri check */
 144 #define HDMI_HDCP_CONTROL                       0xAF /* HDCP control */
 145 #define HDMI_RI_FRAME_COUNT_REGISTER            0xB2 /* Ri frame count register */
 146 #define HDMI_DDC_BUS_CONTROL                    0xB7 /* DDC bus control */
 147 #define HDMI_HDCP_STATUS                        0xB8 /* HDCP status */
 148 #define HDMI_SHA0                               0xB9 /* sha0 */
 149 #define HDMI_SHA1                               0xBA /* sha1 */
 150 #define HDMI_SHA2                               0xBB /* sha2 */
 151 #define HDMI_SHA3                               0xBC /* sha3 */
 152 #define HDMI_SHA4                               0xBD /* sha4 */
 153 #define HDMI_BCAPS_READ                         0xBE /* BCAPS read / debug */
 154 #define HDMI_AKSV_BKSV_7_0_MONITOR              0xBF /* AKSV/BKSV[7:0] monitor */
 155 #define HDMI_AKSV_BKSV_15_8_MONITOR             0xC0 /* AKSV/BKSV[15:8] monitor */
 156 #define HDMI_AKSV_BKSV_23_16_MONITOR            0xC1 /* AKSV/BKSV[23:16] monitor */
 157 #define HDMI_AKSV_BKSV_31_24_MONITOR            0xC2 /* AKSV/BKSV[31:24] monitor */
 158 #define HDMI_AKSV_BKSV_39_32_MONITOR            0xC3 /* AKSV/BKSV[39:32] monitor */
 159 #define HDMI_EDID_SEGMENT_POINTER               0xC4 /* EDID segment pointer */
 160 #define HDMI_EDID_WORD_ADDRESS                  0xC5 /* EDID word address */
 161 #define HDMI_EDID_DATA_FIFO_ADDRESS             0xC6 /* EDID data FIFO address */
 162 #define HDMI_NUM_OF_HDMI_DEVICES                0xC7 /* Number of HDMI devices */
 163 #define HDMI_HDCP_ERROR_CODE                    0xC8 /* HDCP error code */
 164 #define HDMI_100MS_TIMER_SET                    0xC9 /* 100ms timer setting */
 165 #define HDMI_5SEC_TIMER_SET                     0xCA /* 5sec timer setting */
 166 #define HDMI_RI_READ_COUNT                      0xCB /* Ri read count */
 167 #define HDMI_AN_SEED                            0xCC /* An seed */
 168 #define HDMI_MAX_NUM_OF_RCIVRS_ALLOWED          0xCD /* Maximum number of receivers allowed */
 169 #define HDMI_HDCP_MEMORY_ACCESS_CONTROL_1       0xCE /* HDCP memory access control.1 */
 170 #define HDMI_HDCP_MEMORY_ACCESS_CONTROL_2       0xCF /* HDCP memory access control.2 */
 171 #define HDMI_HDCP_CONTROL_2                     0xD0 /* HDCP Control 2 */
 172 #define HDMI_HDCP_KEY_MEMORY_CONTROL            0xD2 /* HDCP Key Memory Control */
 173 #define HDMI_COLOR_SPACE_CONV_CONFIG_1          0xD3 /* Color space conversion configuration.1 */
 174 #define HDMI_VIDEO_SETTING_3                    0xD4 /* Video setting.3 */
 175 #define HDMI_RI_7_0                             0xD5 /* Ri[7:0] */
 176 #define HDMI_RI_15_8                            0xD6 /* Ri[15:8] */
 177 #define HDMI_PJ                                 0xD7 /* Pj */
 178 #define HDMI_SHA_RD                             0xD8 /* sha_rd */
 179 #define HDMI_RI_7_0_SAVED                       0xD9 /* Ri[7:0] saved */
 180 #define HDMI_RI_15_8_SAVED                      0xDA /* Ri[15:8] saved */
 181 #define HDMI_PJ_SAVED                           0xDB /* Pj saved */
 182 #define HDMI_NUM_OF_DEVICES                     0xDC /* Number of devices */
 183 #define HDMI_HOT_PLUG_MSENS_STATUS              0xDF /* Hot plug/MSENS status */
 184 #define HDMI_BCAPS_WRITE                        0xE0 /* bcaps */
 185 #define HDMI_BSTAT_7_0                          0xE1 /* bstat[7:0] */
 186 #define HDMI_BSTAT_15_8                         0xE2 /* bstat[15:8] */
 187 #define HDMI_BKSV_7_0                           0xE3 /* bksv[7:0] */
 188 #define HDMI_BKSV_15_8                          0xE4 /* bksv[15:8] */
 189 #define HDMI_BKSV_23_16                         0xE5 /* bksv[23:16] */
 190 #define HDMI_BKSV_31_24                         0xE6 /* bksv[31:24] */
 191 #define HDMI_BKSV_39_32                         0xE7 /* bksv[39:32] */
 192 #define HDMI_AN_7_0                             0xE8 /* An[7:0] */
 193 #define HDMI_AN_15_8                            0xE9 /* An [15:8] */
 194 #define HDMI_AN_23_16                           0xEA /* An [23:16] */
 195 #define HDMI_AN_31_24                           0xEB /* An [31:24] */
 196 #define HDMI_AN_39_32                           0xEC /* An [39:32] */
 197 #define HDMI_AN_47_40                           0xED /* An [47:40] */
 198 #define HDMI_AN_55_48                           0xEE /* An [55:48] */
 199 #define HDMI_AN_63_56                           0xEF /* An [63:56] */
 200 #define HDMI_PRODUCT_ID                         0xF0 /* Product ID */
 201 #define HDMI_REVISION_ID                        0xF1 /* Revision ID */
 202 #define HDMI_TEST_MODE                          0xFE /* Test mode */
 203
 204 enum hotplug_state {
 205         HDMI_HOTPLUG_DISCONNECTED,
 206         HDMI_HOTPLUG_CONNECTED,
 207         HDMI_HOTPLUG_EDID_DONE,
 208 };
 209
 210 struct sh_hdmi {
 211         void __iomem *base;
 212         enum hotplug_state hp_state;    /* hot-plug status */
 213         u8 preprogrammed_vic;           /* use a pre-programmed VIC or
 214                                            the external mode */
 215         u8 edid_block_addr;
 216         u8 edid_segment_nr;
 217         u8 edid_blocks;
 218         struct clk *hdmi_clk;
 219         struct device *dev;
 220         struct fb_info *info;
 221         struct mutex mutex;             /* Protect the info pointer */
 222         struct delayed_work edid_work;
 223         struct fb_var_screeninfo var;
 224         struct fb_monspecs monspec;
 225         struct notifier_block notifier;
 226 };
 227
 228 #define notifier_to_hdmi(n)     container_of(n, struct sh_hdmi, notifier)
 229
 230 static void hdmi_write(struct sh_hdmi *hdmi, u8 data, u8 reg)
 231 {
 232         iowrite8(data, hdmi->base + reg);
 233 }
 234
 235 static u8 hdmi_read(struct sh_hdmi *hdmi, u8 reg)
 236 {
 237         return ioread8(hdmi->base + reg);
 238 }
 239
 240 /*
 241  *      HDMI sound
 242  */
 243 static unsigned int sh_hdmi_snd_read(struct snd_soc_codec *codec,
 244                                      unsigned int reg)
 245 {
 246         struct sh_hdmi *hdmi = snd_soc_codec_get_drvdata(codec);
 247
 248         return hdmi_read(hdmi, reg);
 249 }
 250
 251 static int sh_hdmi_snd_write(struct snd_soc_codec *codec,
 252                              unsigned int reg,
 253                              unsigned int value)
 254 {
 255         struct sh_hdmi *hdmi = snd_soc_codec_get_drvdata(codec);
 256
 257         hdmi_write(hdmi, value, reg);
 258         return 0;
 259 }
 260
 261 static struct snd_soc_dai_driver sh_hdmi_dai = {
 262         .name = "sh_mobile_hdmi-hifi",
 263         .playback = {
 264                 .stream_name = "Playback",
 265                 .channels_min = 2,
 266                 .channels_max = 8,
 267                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100  |
 268                          SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200  |
 269                          SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
 270                          SNDRV_PCM_RATE_192000,
 271                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 272         },
 273 };
 274
 275 static int sh_hdmi_snd_probe(struct snd_soc_codec *codec)
 276 {
 277         dev_info(codec->dev, "SH Mobile HDMI Audio Codec");
 278
 279         return 0;
 280 }
 281
 282 static struct snd_soc_codec_driver soc_codec_dev_sh_hdmi = {
 283         .probe          = sh_hdmi_snd_probe,
 284         .read           = sh_hdmi_snd_read,
 285         .write          = sh_hdmi_snd_write,
 286 };
 287
 288 /*
 289  *      HDMI video
 290  */
 291
 292 /* External video parameter settings */
 293 static void sh_hdmi_external_video_param(struct sh_hdmi *hdmi)
 294 {
 295         struct fb_var_screeninfo *var = &hdmi->var;
 296         u16 htotal, hblank, hdelay, vtotal, vblank, vdelay, voffset;
 297         u8 sync = 0;
 298
 299         htotal = var->xres + var->right_margin + var->left_margin + var->hsync_len;
 300
 301         hdelay = var->hsync_len + var->left_margin;
 302         hblank = var->right_margin + hdelay;
 303
 304         /*
 305          * Vertical timing looks a bit different in Figure 18,
 306          * but let's try the same first by setting offset = 0
 307          */
 308         vtotal = var->yres + var->upper_margin + var->lower_margin + var->vsync_len;
 309
 310         vdelay = var->vsync_len + var->upper_margin;
 311         vblank = var->lower_margin + vdelay;
 312         voffset = min(var->upper_margin / 2, 6U);
 313
 314         /*
 315          * [3]: VSYNC polarity: Positive
 316          * [2]: HSYNC polarity: Positive
 317          * [1]: Interlace/Progressive: Progressive
 318          * [0]: External video settings enable: used.
 319          */
 320         if (var->sync & FB_SYNC_HOR_HIGH_ACT)
 321                 sync |= 4;
 322         if (var->sync & FB_SYNC_VERT_HIGH_ACT)
 323                 sync |= 8;
 324
 325         dev_dbg(hdmi->dev, "H: %u, %u, %u, %u; V: %u, %u, %u, %u; sync 0x%x\n",
 326                 htotal, hblank, hdelay, var->hsync_len,
 327                 vtotal, vblank, vdelay, var->vsync_len, sync);
 328
 329         hdmi_write(hdmi, sync | (voffset << 4), HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS);
 330
 331         hdmi_write(hdmi, htotal, HDMI_EXTERNAL_H_TOTAL_7_0);
 332         hdmi_write(hdmi, htotal >> 8, HDMI_EXTERNAL_H_TOTAL_11_8);
 333
 334         hdmi_write(hdmi, hblank, HDMI_EXTERNAL_H_BLANK_7_0);
 335         hdmi_write(hdmi, hblank >> 8, HDMI_EXTERNAL_H_BLANK_9_8);
 336
 337         hdmi_write(hdmi, hdelay, HDMI_EXTERNAL_H_DELAY_7_0);
 338         hdmi_write(hdmi, hdelay >> 8, HDMI_EXTERNAL_H_DELAY_9_8);
 339
 340         hdmi_write(hdmi, var->hsync_len, HDMI_EXTERNAL_H_DURATION_7_0);
 341         hdmi_write(hdmi, var->hsync_len >> 8, HDMI_EXTERNAL_H_DURATION_9_8);
 342
 343         hdmi_write(hdmi, vtotal, HDMI_EXTERNAL_V_TOTAL_7_0);
 344         hdmi_write(hdmi, vtotal >> 8, HDMI_EXTERNAL_V_TOTAL_9_8);
 345
 346         hdmi_write(hdmi, vblank, HDMI_EXTERNAL_V_BLANK);
 347
 348         hdmi_write(hdmi, vdelay, HDMI_EXTERNAL_V_DELAY);
 349
 350         hdmi_write(hdmi, var->vsync_len, HDMI_EXTERNAL_V_DURATION);
 351
 352         /* Set bit 0 of HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS here for external mode */
 353         if (!hdmi->preprogrammed_vic)
 354                 hdmi_write(hdmi, sync | 1 | (voffset << 4),
 355                            HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS);
 356 }
 357
 358 /**
 359  * sh_hdmi_video_config()
 360  */
 361 static void sh_hdmi_video_config(struct sh_hdmi *hdmi)
 362 {
 363         /*
 364          * [7:4]: Audio sampling frequency: 48kHz
 365          * [3:1]: Input video format: RGB and YCbCr 4:4:4 (Y on Green)
 366          * [0]: Internal/External DE select: internal
 367          */
 368         hdmi_write(hdmi, 0x20, HDMI_AUDIO_VIDEO_SETTING_1);
 369
 370         /*
 371          * [7:6]: Video output format: RGB 4:4:4
 372          * [5:4]: Input video data width: 8 bit
 373          * [3:1]: EAV/SAV location: channel 1
 374          * [0]: Video input color space: RGB
 375          */
 376         hdmi_write(hdmi, 0x34, HDMI_VIDEO_SETTING_1);
 377
 378         /*
 379          * [7:6]: Together with bit [6] of HDMI_AUDIO_VIDEO_SETTING_2, which is
 380          * left at 0 by default, this configures 24bpp and sets the Color Depth
 381          * (CD) field in the General Control Packet
 382          */
 383         hdmi_write(hdmi, 0x20, HDMI_DEEP_COLOR_MODES);
 384 }
 385
 386 /**
 387  * sh_hdmi_audio_config()
 388  */
 389 static void sh_hdmi_audio_config(struct sh_hdmi *hdmi)
 390 {
 391         u8 data;
 392         struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
 393
 394         /*
 395          * [7:4] L/R data swap control
 396          * [3:0] appropriate N[19:16]
 397          */
 398         hdmi_write(hdmi, 0x00, HDMI_L_R_DATA_SWAP_CTRL_RPKT);
 399         /* appropriate N[15:8] */
 400         hdmi_write(hdmi, 0x18, HDMI_20_BIT_N_FOR_AUDIO_RPKT_15_8);
 401         /* appropriate N[7:0] */
 402         hdmi_write(hdmi, 0x00, HDMI_20_BIT_N_FOR_AUDIO_RPKT_7_0);
 403
 404         /* [7:4] 48 kHz SPDIF not used */
 405         hdmi_write(hdmi, 0x20, HDMI_SPDIF_AUDIO_SAMP_FREQ_CTS);
 406
 407         /*
 408          * [6:5] set required down sampling rate if required
 409          * [4:3] set required audio source
 410          */
 411         switch (pdata->flags & HDMI_SND_SRC_MASK) {
 412         default:
 413                 /* fall through */
 414         case HDMI_SND_SRC_I2S:
 415                 data = 0x0 << 3;
 416                 break;
 417         case HDMI_SND_SRC_SPDIF:
 418                 data = 0x1 << 3;
 419                 break;
 420         case HDMI_SND_SRC_DSD:
 421                 data = 0x2 << 3;
 422                 break;
 423         case HDMI_SND_SRC_HBR:
 424                 data = 0x3 << 3;
 425                 break;
 426         }
 427         hdmi_write(hdmi, data, HDMI_AUDIO_SETTING_1);
 428
 429         /* [3:0] set sending channel number for channel status */
 430         hdmi_write(hdmi, 0x40, HDMI_AUDIO_SETTING_2);
 431
 432         /*
 433          * [5:2] set valid I2S source input pin
 434          * [1:0] set input I2S source mode
 435          */
 436         hdmi_write(hdmi, 0x04, HDMI_I2S_AUDIO_SET);
 437
 438         /* [7:4] set valid DSD source input pin */
 439         hdmi_write(hdmi, 0x00, HDMI_DSD_AUDIO_SET);
 440
 441         /* [7:0] set appropriate I2S input pin swap settings if required */
 442         hdmi_write(hdmi, 0x00, HDMI_I2S_INPUT_PIN_SWAP);
 443
 444         /*
 445          * [7] set validity bit for channel status
 446          * [3:0] set original sample frequency for channel status
 447          */
 448         hdmi_write(hdmi, 0x00, HDMI_AUDIO_STATUS_BITS_SETTING_1);
 449
 450         /*
 451          * [7] set value for channel status
 452          * [6] set value for channel status
 453          * [5] set copyright bit for channel status
 454          * [4:2] set additional information for channel status
 455          * [1:0] set clock accuracy for channel status
 456          */
 457         hdmi_write(hdmi, 0x00, HDMI_AUDIO_STATUS_BITS_SETTING_2);
 458
 459         /* [7:0] set category code for channel status */
 460         hdmi_write(hdmi, 0x00, HDMI_CATEGORY_CODE);
 461
 462         /*
 463          * [7:4] set source number for channel status
 464          * [3:0] set word length for channel status
 465          */
 466         hdmi_write(hdmi, 0x00, HDMI_SOURCE_NUM_AUDIO_WORD_LEN);
 467
 468         /* [7:4] set sample frequency for channel status */
 469         hdmi_write(hdmi, 0x20, HDMI_AUDIO_VIDEO_SETTING_1);
 470 }
 471
 472 /**
 473  * sh_hdmi_phy_config() - configure the HDMI PHY for the used video mode
 474  */
 475 static void sh_hdmi_phy_config(struct sh_hdmi *hdmi)
 476 {
 477         if (hdmi->var.pixclock < 10000) {
 478                 /* for 1080p8bit 148MHz */
 479                 hdmi_write(hdmi, 0x1d, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
 480                 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
 481                 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
 482                 hdmi_write(hdmi, 0x4c, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
 483                 hdmi_write(hdmi, 0x1e, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
 484                 hdmi_write(hdmi, 0x48, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
 485                 hdmi_write(hdmi, 0x0e, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
 486                 hdmi_write(hdmi, 0x25, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
 487                 hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
 488         } else if (hdmi->var.pixclock < 30000) {
 489                 /* 720p, 8bit, 74.25MHz. Might need to be adjusted for other formats */
 490                 /*
 491                  * [1:0]        Speed_A
 492                  * [3:2]        Speed_B
 493                  * [4]          PLLA_Bypass
 494                  * [6]          DRV_TEST_EN
 495                  * [7]          DRV_TEST_IN
 496                  */
 497                 hdmi_write(hdmi, 0x0f, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
 498                 /* PLLB_CONFIG[17], PLLA_CONFIG[17] - not in PHY datasheet */
 499                 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
 500                 /*
 501                  * [2:0]        BGR_I_OFFSET
 502                  * [6:4]        BGR_V_OFFSET
 503                  */
 504                 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
 505                 /* PLLA_CONFIG[7:0]: VCO gain, VCO offset, LPF resistance[0] */
 506                 hdmi_write(hdmi, 0x44, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
 507                 /*
 508                  * PLLA_CONFIG[15:8]: regulator voltage[0], CP current,
 509                  * LPF capacitance, LPF resistance[1]
 510                  */
 511                 hdmi_write(hdmi, 0x32, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
 512                 /* PLLB_CONFIG[7:0]: LPF resistance[0], VCO offset, VCO gain */
 513                 hdmi_write(hdmi, 0x4A, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
 514                 /*
 515                  * PLLB_CONFIG[15:8]: regulator voltage[0], CP current,
 516                  * LPF capacitance, LPF resistance[1]
 517                  */
 518                 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
 519                 /* DRV_CONFIG, PE_CONFIG */
 520                 hdmi_write(hdmi, 0x25, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
 521                 /*
 522                  * [2:0]        AMON_SEL (4 == LPF voltage)
 523                  * [4]          PLLA_CONFIG[16]
 524                  * [5]          PLLB_CONFIG[16]
 525                  */
 526                 hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
 527         } else {
 528                 /* for 480p8bit 27MHz */
 529                 hdmi_write(hdmi, 0x19, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
 530                 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
 531                 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
 532                 hdmi_write(hdmi, 0x44, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
 533                 hdmi_write(hdmi, 0x32, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
 534                 hdmi_write(hdmi, 0x48, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
 535                 hdmi_write(hdmi, 0x0F, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
 536                 hdmi_write(hdmi, 0x20, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
 537                 hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
 538         }
 539 }
 540
 541 /**
 542  * sh_hdmi_avi_infoframe_setup() - Auxiliary Video Information InfoFrame CONTROL PACKET
 543  */
 544 static void sh_hdmi_avi_infoframe_setup(struct sh_hdmi *hdmi)
 545 {
 546         u8 vic;
 547
 548         /* AVI InfoFrame */
 549         hdmi_write(hdmi, 0x06, HDMI_CTRL_PKT_BUF_INDEX);
 550
 551         /* Packet Type = 0x82 */
 552         hdmi_write(hdmi, 0x82, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
 553
 554         /* Version = 0x02 */
 555         hdmi_write(hdmi, 0x02, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
 556
 557         /* Length = 13 (0x0D) */
 558         hdmi_write(hdmi, 0x0D, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
 559
 560         /* N. A. Checksum */
 561         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0);
 562
 563         /*
 564          * Y = RGB
 565          * A0 = No Data
 566          * B = Bar Data not valid
 567          * S = No Data
 568          */
 569         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB1);
 570
 571         /*
 572          * [7:6] C = Colorimetry: no data
 573          * [5:4] M = 2: 16:9, 1: 4:3 Picture Aspect Ratio
 574          * [3:0] R = 8: Active Frame Aspect Ratio: same as picture aspect ratio
 575          */
 576         hdmi_write(hdmi, 0x28, HDMI_CTRL_PKT_BUF_ACCESS_PB2);
 577
 578         /*
 579          * ITC = No Data
 580          * EC = xvYCC601
 581          * Q = Default (depends on video format)
 582          * SC = No Known non_uniform Scaling
 583          */
 584         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB3);
 585
 586         /*
 587          * VIC should be ignored if external config is used, so, we could just use 0,
 588          * but play safe and use a valid value in any case just in case
 589          */
 590         if (hdmi->preprogrammed_vic)
 591                 vic = hdmi->preprogrammed_vic;
 592         else
 593                 vic = 4;
 594         hdmi_write(hdmi, vic, HDMI_CTRL_PKT_BUF_ACCESS_PB4);
 595
 596         /* PR = No Repetition */
 597         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB5);
 598
 599         /* Line Number of End of Top Bar (lower 8 bits) */
 600         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB6);
 601
 602         /* Line Number of End of Top Bar (upper 8 bits) */
 603         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB7);
 604
 605         /* Line Number of Start of Bottom Bar (lower 8 bits) */
 606         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB8);
 607
 608         /* Line Number of Start of Bottom Bar (upper 8 bits) */
 609         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB9);
 610
 611         /* Pixel Number of End of Left Bar (lower 8 bits) */
 612         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB10);
 613
 614         /* Pixel Number of End of Left Bar (upper 8 bits) */
 615         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB11);
 616
 617         /* Pixel Number of Start of Right Bar (lower 8 bits) */
 618         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB12);
 619
 620         /* Pixel Number of Start of Right Bar (upper 8 bits) */
 621         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB13);
 622 }
 623
 624 /**
 625  * sh_hdmi_audio_infoframe_setup() - Audio InfoFrame of CONTROL PACKET
 626  */
 627 static void sh_hdmi_audio_infoframe_setup(struct sh_hdmi *hdmi)
 628 {
 629         /* Audio InfoFrame */
 630         hdmi_write(hdmi, 0x08, HDMI_CTRL_PKT_BUF_INDEX);
 631
 632         /* Packet Type = 0x84 */
 633         hdmi_write(hdmi, 0x84, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
 634
 635         /* Version Number = 0x01 */
 636         hdmi_write(hdmi, 0x01, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
 637
 638         /* 0 Length = 10 (0x0A) */
 639         hdmi_write(hdmi, 0x0A, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
 640
 641         /* n. a. Checksum */
 642         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0);
 643
 644         /* Audio Channel Count = Refer to Stream Header */
 645         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB1);
 646
 647         /* Refer to Stream Header */
 648         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB2);
 649
 650         /* Format depends on coding type (i.e. CT0...CT3) */
 651         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB3);
 652
 653         /* Speaker Channel Allocation = Front Right + Front Left */
 654         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB4);
 655
 656         /* Level Shift Value = 0 dB, Down - mix is permitted or no information */
 657         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB5);
 658
 659         /* Reserved (0) */
 660         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB6);
 661         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB7);
 662         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB8);
 663         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB9);
 664         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB10);
 665 }
 666
 667 /**
 668  * sh_hdmi_configure() - Initialise HDMI for output
 669  */
 670 static void sh_hdmi_configure(struct sh_hdmi *hdmi)
 671 {
 672         /* Configure video format */
 673         sh_hdmi_video_config(hdmi);
 674
 675         /* Configure audio format */
 676         sh_hdmi_audio_config(hdmi);
 677
 678         /* Configure PHY */
 679         sh_hdmi_phy_config(hdmi);
 680
 681         /* Auxiliary Video Information (AVI) InfoFrame */
 682         sh_hdmi_avi_infoframe_setup(hdmi);
 683
 684         /* Audio InfoFrame */
 685         sh_hdmi_audio_infoframe_setup(hdmi);
 686
 687         /*
 688          * Control packet auto send with VSYNC control: auto send
 689          * General control, Gamut metadata, ISRC, and ACP packets
 690          */
 691         hdmi_write(hdmi, 0x8E, HDMI_CTRL_PKT_AUTO_SEND);
 692
 693         /* FIXME */
 694         msleep(10);
 695
 696         /* PS mode b->d, reset PLLA and PLLB */
 697         hdmi_write(hdmi, 0x4C, HDMI_SYSTEM_CTRL);
 698
 699         udelay(10);
 700
 701         hdmi_write(hdmi, 0x40, HDMI_SYSTEM_CTRL);
 702 }
 703
 704 static unsigned long sh_hdmi_rate_error(struct sh_hdmi *hdmi,
 705                 const struct fb_videomode *mode,
 706                 unsigned long *hdmi_rate, unsigned long *parent_rate)
 707 {
 708         unsigned long target = PICOS2KHZ(mode->pixclock) * 1000, rate_error;
 709         struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
 710
 711         *hdmi_rate = clk_round_rate(hdmi->hdmi_clk, target);
 712         if ((long)*hdmi_rate < 0)
 713                 *hdmi_rate = clk_get_rate(hdmi->hdmi_clk);
 714
 715         rate_error = (long)*hdmi_rate > 0 ? abs(*hdmi_rate - target) : ULONG_MAX;
 716         if (rate_error && pdata->clk_optimize_parent)
 717                 rate_error = pdata->clk_optimize_parent(target, hdmi_rate, parent_rate);
 718         else if (clk_get_parent(hdmi->hdmi_clk))
 719                 *parent_rate = clk_get_rate(clk_get_parent(hdmi->hdmi_clk));
 720
 721         dev_dbg(hdmi->dev, "%u-%u-%u-%u x %u-%u-%u-%u\n",
 722                 mode->left_margin, mode->xres,
 723                 mode->right_margin, mode->hsync_len,
 724                 mode->upper_margin, mode->yres,
 725                 mode->lower_margin, mode->vsync_len);
 726
 727         dev_dbg(hdmi->dev, "\t@%lu(+/-%lu)Hz, e=%lu / 1000, r=%uHz, p=%luHz\n", target,
 728                 rate_error, rate_error ? 10000 / (10 * target / rate_error) : 0,
 729                 mode->refresh, *parent_rate);
 730
 731         return rate_error;
 732 }
 733
 734 static int sh_hdmi_read_edid(struct sh_hdmi *hdmi, unsigned long *hdmi_rate,
 735                              unsigned long *parent_rate)
 736 {
 737         struct fb_var_screeninfo tmpvar;
 738         struct fb_var_screeninfo *var = &tmpvar;
 739         const struct fb_videomode *mode, *found = NULL;
 740         struct fb_info *info = hdmi->info;
 741         struct fb_modelist *modelist = NULL;
 742         unsigned int f_width = 0, f_height = 0, f_refresh = 0;
 743         unsigned long found_rate_error = ULONG_MAX; /* silly compiler... */
 744         bool scanning = false, preferred_bad = false;
 745         u8 edid[128];
 746         char *forced;
 747         int i;
 748
 749         /* Read EDID */
 750         dev_dbg(hdmi->dev, "Read back EDID code:");
 751         for (i = 0; i < 128; i++) {
 752                 edid[i] = hdmi_read(hdmi, HDMI_EDID_KSV_FIFO_ACCESS_WINDOW);
 753 #ifdef DEBUG
 754                 if ((i % 16) == 0) {
 755                         printk(KERN_CONT "\n");
 756                         printk(KERN_DEBUG "%02X | %02X", i, edid[i]);
 757                 } else {
 758                         printk(KERN_CONT " %02X", edid[i]);
 759                 }
 760 #endif
 761         }
 762 #ifdef DEBUG
 763         printk(KERN_CONT "\n");
 764 #endif
 765
 766         if (!hdmi->edid_blocks) {
 767                 fb_edid_to_monspecs(edid, &hdmi->monspec);
 768                 hdmi->edid_blocks = edid[126] + 1;
 769
 770                 dev_dbg(hdmi->dev, "%d main modes, %d extension blocks\n",
 771                         hdmi->monspec.modedb_len, hdmi->edid_blocks - 1);
 772         } else {
 773                 dev_dbg(hdmi->dev, "Extension %u detected, DTD start %u\n",
 774                         edid[0], edid[2]);
 775                 fb_edid_add_monspecs(edid, &hdmi->monspec);
 776         }
 777
 778         if (hdmi->edid_blocks > hdmi->edid_segment_nr * 2 +
 779             (hdmi->edid_block_addr >> 7) + 1) {
 780                 /* More blocks to read */
 781                 if (hdmi->edid_block_addr) {
 782                         hdmi->edid_block_addr = 0;
 783                         hdmi->edid_segment_nr++;
 784                 } else {
 785                         hdmi->edid_block_addr = 0x80;
 786                 }
 787                 /* Set EDID word address  */
 788                 hdmi_write(hdmi, hdmi->edid_block_addr, HDMI_EDID_WORD_ADDRESS);
 789                 /* Enable EDID interrupt */
 790                 hdmi_write(hdmi, 0xC6, HDMI_INTERRUPT_MASK_1);
 791                 /* Set EDID segment pointer - starts reading EDID */
 792                 hdmi_write(hdmi, hdmi->edid_segment_nr, HDMI_EDID_SEGMENT_POINTER);
 793                 return -EAGAIN;
 794         }
 795
 796         /* All E-EDID blocks ready */
 797         dev_dbg(hdmi->dev, "%d main and extended modes\n", hdmi->monspec.modedb_len);
 798
 799         fb_get_options("sh_mobile_lcdc", &forced);
 800         if (forced && *forced) {
 801                 /* Only primitive parsing so far */
 802                 i = sscanf(forced, "%ux%u@%u",
 803                            &f_width, &f_height, &f_refresh);
 804                 if (i < 2) {
 805                         f_width = 0;
 806                         f_height = 0;
 807                 } else {
 808                         /* The user wants us to use the EDID data */
 809                         scanning = true;
 810                 }
 811                 dev_dbg(hdmi->dev, "Forced mode %ux%u@%uHz\n",
 812                         f_width, f_height, f_refresh);
 813         }
 814
 815         /* Walk monitor modes to find the best or the exact match */
 816         for (i = 0, mode = hdmi->monspec.modedb;
 817              i < hdmi->monspec.modedb_len && scanning;
 818              i++, mode++) {
 819                 unsigned long rate_error;
 820
 821                 if (!f_width && !f_height) {
 822                         /*
 823                          * A parameter string "video=sh_mobile_lcdc:0x0" means
 824                          * use the preferred EDID mode. If it is rejected by
 825                          * .fb_check_var(), keep looking, until an acceptable
 826                          * one is found.
 827                          */
 828                         if ((mode->flag & FB_MODE_IS_FIRST) || preferred_bad)
 829                                 scanning = false;
 830                         else
 831                                 continue;
 832                 } else if (f_width != mode->xres || f_height != mode->yres) {
 833                         /* No interest in unmatching modes */
 834                         continue;
 835                 }
 836
 837                 rate_error = sh_hdmi_rate_error(hdmi, mode, hdmi_rate, parent_rate);
 838
 839                 if (scanning) {
 840                         if (f_refresh == mode->refresh || (!f_refresh && !rate_error))
 841                                 /*
 842                                  * Exact match if either the refresh rate
 843                                  * matches or it hasn't been specified and we've
 844                                  * found a mode, for which we can configure the
 845                                  * clock precisely
 846                                  */
 847                                 scanning = false;
 848                         else if (found && found_rate_error <= rate_error)
 849                                 /*
 850                                  * We otherwise search for the closest matching
 851                                  * clock rate - either if no refresh rate has
 852                                  * been specified or we cannot find an exactly
 853                                  * matching one
 854                                  */
 855                                 continue;
 856                 }
 857
 858                 /* Check if supported: sufficient fb memory, supported clock-rate */
 859                 fb_videomode_to_var(var, mode);
 860
 861                 var->bits_per_pixel = info->var.bits_per_pixel;
 862
 863                 if (info && info->fbops->fb_check_var &&
 864                     info->fbops->fb_check_var(var, info)) {
 865                         scanning = true;
 866                         preferred_bad = true;
 867                         continue;
 868                 }
 869
 870                 found = mode;
 871                 found_rate_error = rate_error;
 872         }
 873
 874         hdmi->var.width = hdmi->monspec.max_x * 10;
 875         hdmi->var.height = hdmi->monspec.max_y * 10;
 876
 877         /*
 878          * TODO 1: if no ->info is present, postpone running the config until
 879          * after ->info first gets registered.
 880          * TODO 2: consider registering the HDMI platform device from the LCDC
 881          * driver, and passing ->info with HDMI platform data.
 882          */
 883         if (info && !found) {
 884                 modelist = info->modelist.next &&
 885                         !list_empty(&info->modelist) ?
 886                         list_entry(info->modelist.next,
 887                                    struct fb_modelist, list) :
 888                         NULL;
 889
 890                 if (modelist) {
 891                         found = &modelist->mode;
 892                         found_rate_error = sh_hdmi_rate_error(hdmi, found, hdmi_rate, parent_rate);
 893                 }
 894         }
 895
 896         /* No cookie today */
 897         if (!found)
 898                 return -ENXIO;
 899
 900         if (found->xres == 640 && found->yres == 480 && found->refresh == 60)
 901                 hdmi->preprogrammed_vic = 1;
 902         else if (found->xres == 720 && found->yres == 480 && found->refresh == 60)
 903                 hdmi->preprogrammed_vic = 2;
 904         else if (found->xres == 720 && found->yres == 576 && found->refresh == 50)
 905                 hdmi->preprogrammed_vic = 17;
 906         else if (found->xres == 1280 && found->yres == 720 && found->refresh == 60)
 907                 hdmi->preprogrammed_vic = 4;
 908         else if (found->xres == 1920 && found->yres == 1080 && found->refresh == 24)
 909                 hdmi->preprogrammed_vic = 32;
 910         else if (found->xres == 1920 && found->yres == 1080 && found->refresh == 50)
 911                 hdmi->preprogrammed_vic = 31;
 912         else if (found->xres == 1920 && found->yres == 1080 && found->refresh == 60)
 913                 hdmi->preprogrammed_vic = 16;
 914         else
 915                 hdmi->preprogrammed_vic = 0;
 916
 917         dev_dbg(hdmi->dev, "Using %s %s mode %ux%u@%uHz (%luHz), clock error %luHz\n",
 918                 modelist ? "default" : "EDID", hdmi->preprogrammed_vic ? "VIC" : "external",
 919                 found->xres, found->yres, found->refresh,
 920                 PICOS2KHZ(found->pixclock) * 1000, found_rate_error);
 921
 922         fb_videomode_to_var(&hdmi->var, found);
 923         sh_hdmi_external_video_param(hdmi);
 924
 925         return 0;
 926 }
 927
 928 static irqreturn_t sh_hdmi_hotplug(int irq, void *dev_id)
 929 {
 930         struct sh_hdmi *hdmi = dev_id;
 931         u8 status1, status2, mask1, mask2;
 932
 933         /* mode_b and PLLA and PLLB reset */
 934         hdmi_write(hdmi, 0x2C, HDMI_SYSTEM_CTRL);
 935
 936         /* How long shall reset be held? */
 937         udelay(10);
 938
 939         /* mode_b and PLLA and PLLB reset release */
 940         hdmi_write(hdmi, 0x20, HDMI_SYSTEM_CTRL);
 941
 942         status1 = hdmi_read(hdmi, HDMI_INTERRUPT_STATUS_1);
 943         status2 = hdmi_read(hdmi, HDMI_INTERRUPT_STATUS_2);
 944
 945         mask1 = hdmi_read(hdmi, HDMI_INTERRUPT_MASK_1);
 946         mask2 = hdmi_read(hdmi, HDMI_INTERRUPT_MASK_2);
 947
 948         /* Correct would be to ack only set bits, but the datasheet requires 0xff */
 949         hdmi_write(hdmi, 0xFF, HDMI_INTERRUPT_STATUS_1);
 950         hdmi_write(hdmi, 0xFF, HDMI_INTERRUPT_STATUS_2);
 951
 952         if (printk_ratelimit())
 953                 dev_dbg(hdmi->dev, "IRQ #%d: Status #1: 0x%x & 0x%x, #2: 0x%x & 0x%x\n",
 954                         irq, status1, mask1, status2, mask2);
 955
 956         if (!((status1 & mask1) | (status2 & mask2))) {
 957                 return IRQ_NONE;
 958         } else if (status1 & 0xc0) {
 959                 u8 msens;
 960
 961                 /* Datasheet specifies 10ms... */
 962                 udelay(500);
 963
 964                 msens = hdmi_read(hdmi, HDMI_HOT_PLUG_MSENS_STATUS);
 965                 dev_dbg(hdmi->dev, "MSENS 0x%x\n", msens);
 966                 /* Check, if hot plug & MSENS pin status are both high */
 967                 if ((msens & 0xC0) == 0xC0) {
 968                         /* Display plug in */
 969                         hdmi->edid_segment_nr = 0;
 970                         hdmi->edid_block_addr = 0;
 971                         hdmi->edid_blocks = 0;
 972                         hdmi->hp_state = HDMI_HOTPLUG_CONNECTED;
 973
 974                         /* Set EDID word address  */
 975                         hdmi_write(hdmi, 0x00, HDMI_EDID_WORD_ADDRESS);
 976                         /* Enable EDID interrupt */
 977                         hdmi_write(hdmi, 0xC6, HDMI_INTERRUPT_MASK_1);
 978                         /* Set EDID segment pointer - starts reading EDID */
 979                         hdmi_write(hdmi, 0x00, HDMI_EDID_SEGMENT_POINTER);
 980                 } else if (!(status1 & 0x80)) {
 981                         /* Display unplug, beware multiple interrupts */
 982                         if (hdmi->hp_state != HDMI_HOTPLUG_DISCONNECTED) {
 983                                 hdmi->hp_state = HDMI_HOTPLUG_DISCONNECTED;
 984                                 schedule_delayed_work(&hdmi->edid_work, 0);
 985                         }
 986                         /* display_off will switch back to mode_a */
 987                 }
 988         } else if (status1 & 2) {
 989                 /* EDID error interrupt: retry */
 990                 /* Set EDID word address  */
 991                 hdmi_write(hdmi, hdmi->edid_block_addr, HDMI_EDID_WORD_ADDRESS);
 992                 /* Set EDID segment pointer */
 993                 hdmi_write(hdmi, hdmi->edid_segment_nr, HDMI_EDID_SEGMENT_POINTER);
 994         } else if (status1 & 4) {
 995                 /* Disable EDID interrupt */
 996                 hdmi_write(hdmi, 0xC0, HDMI_INTERRUPT_MASK_1);
 997                 schedule_delayed_work(&hdmi->edid_work, msecs_to_jiffies(10));
 998         }
 999
1000         return IRQ_HANDLED;
1001 }
1002
1003 /* locking:     called with info->lock held, or before register_framebuffer() */
1004 static void sh_hdmi_display_on(void *arg, struct fb_info *info)
1005 {
1006         /*
1007          * info is guaranteed to be valid, when we are called, because our
1008          * FB_EVENT_FB_UNBIND notify is also called with info->lock held
1009          */
1010         struct sh_hdmi *hdmi = arg;
1011         struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
1012         struct sh_mobile_lcdc_chan *ch = info->par;
1013
1014         dev_dbg(hdmi->dev, "%s(%p): state %x\n", __func__,
1015                 pdata->lcd_dev, info->state);
1016
1017         /* No need to lock */
1018         hdmi->info = info;
1019
1020         /*
1021          * hp_state can be set to
1022          * HDMI_HOTPLUG_DISCONNECTED:   on monitor unplug
1023          * HDMI_HOTPLUG_CONNECTED:      on monitor plug-in
1024          * HDMI_HOTPLUG_EDID_DONE:      on EDID read completion
1025          */
1026         switch (hdmi->hp_state) {
1027         case HDMI_HOTPLUG_EDID_DONE:
1028                 /* PS mode d->e. All functions are active */
1029                 hdmi_write(hdmi, 0x80, HDMI_SYSTEM_CTRL);
1030                 dev_dbg(hdmi->dev, "HDMI running\n");
1031                 break;
1032         case HDMI_HOTPLUG_DISCONNECTED:
1033                 info->state = FBINFO_STATE_SUSPENDED;
1034         default:
1035                 hdmi->var = ch->display_var;
1036         }
1037 }
1038
1039 /* locking: called with info->lock held */
1040 static void sh_hdmi_display_off(void *arg)
1041 {
1042         struct sh_hdmi *hdmi = arg;
1043         struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
1044
1045         dev_dbg(hdmi->dev, "%s(%p)\n", __func__, pdata->lcd_dev);
1046         /* PS mode e->a */
1047         hdmi_write(hdmi, 0x10, HDMI_SYSTEM_CTRL);
1048 }
1049
1050 static bool sh_hdmi_must_reconfigure(struct sh_hdmi *hdmi)
1051 {
1052         struct fb_info *info = hdmi->info;
1053         struct sh_mobile_lcdc_chan *ch = info->par;
1054         struct fb_var_screeninfo *new_var = &hdmi->var, *old_var = &ch->display_var;
1055         struct fb_videomode mode1, mode2;
1056
1057         fb_var_to_videomode(&mode1, old_var);
1058         fb_var_to_videomode(&mode2, new_var);
1059
1060         dev_dbg(info->dev, "Old %ux%u, new %ux%u\n",
1061                 mode1.xres, mode1.yres, mode2.xres, mode2.yres);
1062
1063         if (fb_mode_is_equal(&mode1, &mode2)) {
1064                 /* It can be a different monitor with an equal video-mode */
1065                 old_var->width = new_var->width;
1066                 old_var->height = new_var->height;
1067                 return false;
1068         }
1069
1070         dev_dbg(info->dev, "Switching %u -> %u lines\n",
1071                 mode1.yres, mode2.yres);
1072         *old_var = *new_var;
1073
1074         return true;
1075 }
1076
1077 /**
1078  * sh_hdmi_clk_configure() - set HDMI clock frequency and enable the clock
1079  * @hdmi:               driver context
1080  * @hdmi_rate:          HDMI clock frequency in Hz
1081  * @parent_rate:        if != 0 - set parent clock rate for optimal precision
1082  * return:              configured positive rate if successful
1083  *                      0 if couldn't set the rate, but managed to enable the
1084  *                      clock, negative error, if couldn't enable the clock
1085  */
1086 static long sh_hdmi_clk_configure(struct sh_hdmi *hdmi, unsigned long hdmi_rate,
1087                                   unsigned long parent_rate)
1088 {
1089         int ret;
1090
1091         if (parent_rate && clk_get_parent(hdmi->hdmi_clk)) {
1092                 ret = clk_set_rate(clk_get_parent(hdmi->hdmi_clk), parent_rate);
1093                 if (ret < 0) {
1094                         dev_warn(hdmi->dev, "Cannot set parent rate %ld: %d\n", parent_rate, ret);
1095                         hdmi_rate = clk_round_rate(hdmi->hdmi_clk, hdmi_rate);
1096                 } else {
1097                         dev_dbg(hdmi->dev, "HDMI set parent frequency %lu\n", parent_rate);
1098                 }
1099         }
1100
1101         ret = clk_set_rate(hdmi->hdmi_clk, hdmi_rate);
1102         if (ret < 0) {
1103                 dev_warn(hdmi->dev, "Cannot set rate %ld: %d\n", hdmi_rate, ret);
1104                 hdmi_rate = 0;
1105         } else {
1106                 dev_dbg(hdmi->dev, "HDMI set frequency %lu\n", hdmi_rate);
1107         }
1108
1109         return hdmi_rate;
1110 }
1111
1112 /* Hotplug interrupt occurred, read EDID */
1113 static void sh_hdmi_edid_work_fn(struct work_struct *work)
1114 {
1115         struct sh_hdmi *hdmi = container_of(work, struct sh_hdmi, edid_work.work);
1116         struct fb_info *info;
1117         struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
1118         struct sh_mobile_lcdc_chan *ch;
1119         int ret;
1120
1121         dev_dbg(hdmi->dev, "%s(%p): begin, hotplug status %d\n", __func__,
1122                 pdata->lcd_dev, hdmi->hp_state);
1123
1124         if (!pdata->lcd_dev)
1125                 return;
1126
1127         mutex_lock(&hdmi->mutex);
1128
1129         info = hdmi->info;
1130
1131         if (hdmi->hp_state == HDMI_HOTPLUG_CONNECTED) {
1132                 unsigned long parent_rate = 0, hdmi_rate;
1133
1134                 ret = sh_hdmi_read_edid(hdmi, &hdmi_rate, &parent_rate);
1135                 if (ret < 0)
1136                         goto out;
1137
1138                 hdmi->hp_state = HDMI_HOTPLUG_EDID_DONE;
1139
1140                 /* Reconfigure the clock */
1141                 ret = sh_hdmi_clk_configure(hdmi, hdmi_rate, parent_rate);
1142                 if (ret < 0)
1143                         goto out;
1144
1145                 msleep(10);
1146                 sh_hdmi_configure(hdmi);
1147                 /* Switched to another (d) power-save mode */
1148                 msleep(10);
1149
1150                 if (!info)
1151                         goto out;
1152
1153                 ch = info->par;
1154
1155                 if (lock_fb_info(info)) {
1156                         console_lock();
1157
1158                         /* HDMI plug in */
1159                         if (!sh_hdmi_must_reconfigure(hdmi) &&
1160                             info->state == FBINFO_STATE_RUNNING) {
1161                                 /*
1162                                  * First activation with the default monitor - just turn
1163                                  * on, if we run a resume here, the logo disappears
1164                                  */
1165                                 info->var.width = hdmi->var.width;
1166                                 info->var.height = hdmi->var.height;
1167                                 sh_hdmi_display_on(hdmi, info);
1168                         } else {
1169                                 /* New monitor or have to wake up */
1170                                 fb_set_suspend(info, 0);
1171                         }
1172
1173                         console_unlock();
1174                         unlock_fb_info(info);
1175                 }
1176         } else {
1177                 ret = 0;
1178                 if (!info)
1179                         goto out;
1180
1181                 hdmi->monspec.modedb_len = 0;
1182                 fb_destroy_modedb(hdmi->monspec.modedb);
1183                 hdmi->monspec.modedb = NULL;
1184
1185                 if (lock_fb_info(info)) {
1186                         console_lock();
1187
1188                         /* HDMI disconnect */
1189                         fb_set_suspend(info, 1);
1190
1191                         console_unlock();
1192                         unlock_fb_info(info);
1193                 }
1194         }
1195
1196 out:
1197         if (ret < 0 && ret != -EAGAIN)
1198                 hdmi->hp_state = HDMI_HOTPLUG_DISCONNECTED;
1199         mutex_unlock(&hdmi->mutex);
1200
1201         dev_dbg(hdmi->dev, "%s(%p): end\n", __func__, pdata->lcd_dev);
1202 }
1203
1204 static int sh_hdmi_notify(struct notifier_block *nb,
1205                           unsigned long action, void *data)
1206 {
1207         struct fb_event *event = data;
1208         struct fb_info *info = event->info;
1209         struct sh_hdmi *hdmi = notifier_to_hdmi(nb);
1210
1211         if (hdmi->info != info)
1212                 return NOTIFY_DONE;
1213
1214         switch(action) {
1215         case FB_EVENT_FB_REGISTERED:
1216                 /* Unneeded, activation taken care by sh_hdmi_display_on() */
1217                 break;
1218         case FB_EVENT_FB_UNREGISTERED:
1219                 /*
1220                  * We are called from unregister_framebuffer() with the
1221                  * info->lock held. This is bad for us, because we can race with
1222                  * the scheduled work, which has to call fb_set_suspend(), which
1223                  * takes info->lock internally, so, sh_hdmi_edid_work_fn()
1224                  * cannot take and hold info->lock for the whole function
1225                  * duration. Using an additional lock creates a classical AB-BA
1226                  * lock up. Therefore, we have to release the info->lock
1227                  * temporarily, synchronise with the work queue and re-acquire
1228                  * the info->lock.
1229                  */
1230                 unlock_fb_info(info);
1231                 mutex_lock(&hdmi->mutex);
1232                 hdmi->info = NULL;
1233                 mutex_unlock(&hdmi->mutex);
1234                 lock_fb_info(info);
1235                 return NOTIFY_OK;
1236         }
1237         return NOTIFY_DONE;
1238 }
1239
1240 static int __init sh_hdmi_probe(struct platform_device *pdev)
1241 {
1242         struct sh_mobile_hdmi_info *pdata = pdev->dev.platform_data;
1243         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1244         struct sh_mobile_lcdc_board_cfg *board_cfg;
1245         int irq = platform_get_irq(pdev, 0), ret;
1246         struct sh_hdmi *hdmi;
1247         long rate;
1248
1249         if (!res || !pdata || irq < 0)
1250                 return -ENODEV;
1251
1252         hdmi = kzalloc(sizeof(*hdmi), GFP_KERNEL);
1253         if (!hdmi) {
1254                 dev_err(&pdev->dev, "Cannot allocate device data\n");
1255                 return -ENOMEM;
1256         }
1257
1258         mutex_init(&hdmi->mutex);
1259
1260         hdmi->dev = &pdev->dev;
1261
1262         hdmi->hdmi_clk = clk_get(&pdev->dev, "ick");
1263         if (IS_ERR(hdmi->hdmi_clk)) {
1264                 ret = PTR_ERR(hdmi->hdmi_clk);
1265                 dev_err(&pdev->dev, "Unable to get clock: %d\n", ret);
1266                 goto egetclk;
1267         }
1268
1269         /* An arbitrary relaxed pixclock just to get things started: from standard 480p */
1270         rate = clk_round_rate(hdmi->hdmi_clk, PICOS2KHZ(37037));
1271         if (rate > 0)
1272                 rate = sh_hdmi_clk_configure(hdmi, rate, 0);
1273
1274         if (rate < 0) {
1275                 ret = rate;
1276                 goto erate;
1277         }
1278
1279         ret = clk_enable(hdmi->hdmi_clk);
1280         if (ret < 0) {
1281                 dev_err(hdmi->dev, "Cannot enable clock: %d\n", ret);
1282                 goto erate;
1283         }
1284
1285         dev_dbg(&pdev->dev, "Enabled HDMI clock at %luHz\n", rate);
1286
1287         if (!request_mem_region(res->start, resource_size(res), dev_name(&pdev->dev))) {
1288                 dev_err(&pdev->dev, "HDMI register region already claimed\n");
1289                 ret = -EBUSY;
1290                 goto ereqreg;
1291         }
1292
1293         hdmi->base = ioremap(res->start, resource_size(res));
1294         if (!hdmi->base) {
1295                 dev_err(&pdev->dev, "HDMI register region already claimed\n");
1296                 ret = -ENOMEM;
1297                 goto emap;
1298         }
1299
1300         platform_set_drvdata(pdev, hdmi);
1301
1302         /* Set up LCDC callbacks */
1303         board_cfg = &pdata->lcd_chan->board_cfg;
1304         board_cfg->owner = THIS_MODULE;
1305         board_cfg->board_data = hdmi;
1306         board_cfg->display_on = sh_hdmi_display_on;
1307         board_cfg->display_off = sh_hdmi_display_off;
1308
1309         INIT_DELAYED_WORK(&hdmi->edid_work, sh_hdmi_edid_work_fn);
1310
1311         pm_runtime_enable(&pdev->dev);
1312         pm_runtime_get_sync(&pdev->dev);
1313
1314         /* Product and revision IDs are 0 in sh-mobile version */
1315         dev_info(&pdev->dev, "Detected HDMI controller 0x%x:0x%x\n",
1316                  hdmi_read(hdmi, HDMI_PRODUCT_ID), hdmi_read(hdmi, HDMI_REVISION_ID));
1317
1318         ret = request_irq(irq, sh_hdmi_hotplug, 0,
1319                           dev_name(&pdev->dev), hdmi);
1320         if (ret < 0) {
1321                 dev_err(&pdev->dev, "Unable to request irq: %d\n", ret);
1322                 goto ereqirq;
1323         }
1324
1325         ret = snd_soc_register_codec(&pdev->dev,
1326                         &soc_codec_dev_sh_hdmi, &sh_hdmi_dai, 1);
1327         if (ret < 0) {
1328                 dev_err(&pdev->dev, "codec registration failed\n");
1329                 goto ecodec;
1330         }
1331
1332         hdmi->notifier.notifier_call = sh_hdmi_notify;
1333         fb_register_client(&hdmi->notifier);
1334
1335         return 0;
1336
1337 ecodec:
1338         free_irq(irq, hdmi);
1339 ereqirq:
1340         pm_runtime_put(&pdev->dev);
1341         pm_runtime_disable(&pdev->dev);
1342         iounmap(hdmi->base);
1343 emap:
1344         release_mem_region(res->start, resource_size(res));
1345 ereqreg:
1346         clk_disable(hdmi->hdmi_clk);
1347 erate:
1348         clk_put(hdmi->hdmi_clk);
1349 egetclk:
1350         mutex_destroy(&hdmi->mutex);
1351         kfree(hdmi);
1352
1353         return ret;
1354 }
1355
1356 static int __exit sh_hdmi_remove(struct platform_device *pdev)
1357 {
1358         struct sh_mobile_hdmi_info *pdata = pdev->dev.platform_data;
1359         struct sh_hdmi *hdmi = platform_get_drvdata(pdev);
1360         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1361         struct sh_mobile_lcdc_board_cfg *board_cfg = &pdata->lcd_chan->board_cfg;
1362         int irq = platform_get_irq(pdev, 0);
1363
1364         snd_soc_unregister_codec(&pdev->dev);
1365
1366         fb_unregister_client(&hdmi->notifier);
1367
1368         board_cfg->display_on = NULL;
1369         board_cfg->display_off = NULL;
1370         board_cfg->board_data = NULL;
1371         board_cfg->owner = NULL;
1372
1373         /* No new work will be scheduled, wait for running ISR */
1374         free_irq(irq, hdmi);
1375         /* Wait for already scheduled work */
1376         cancel_delayed_work_sync(&hdmi->edid_work);
1377         pm_runtime_put(&pdev->dev);
1378         pm_runtime_disable(&pdev->dev);
1379         clk_disable(hdmi->hdmi_clk);
1380         clk_put(hdmi->hdmi_clk);
1381         iounmap(hdmi->base);
1382         release_mem_region(res->start, resource_size(res));
1383         mutex_destroy(&hdmi->mutex);
1384         kfree(hdmi);
1385
1386         return 0;
1387 }
1388
1389 static struct platform_driver sh_hdmi_driver = {
1390         .remove         = __exit_p(sh_hdmi_remove),
1391         .driver = {
1392                 .name   = "sh-mobile-hdmi",
1393         },
1394 };
1395
1396 static int __init sh_hdmi_init(void)
1397 {
1398         return platform_driver_probe(&sh_hdmi_driver, sh_hdmi_probe);
1399 }
1400 module_init(sh_hdmi_init);
1401
1402 static void __exit sh_hdmi_exit(void)
1403 {
1404         platform_driver_unregister(&sh_hdmi_driver);
1405 }
1406 module_exit(sh_hdmi_exit);
1407
1408 MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
1409 MODULE_DESCRIPTION("SuperH / ARM-shmobile HDMI driver");
1410 MODULE_LICENSE("GPL v2");