drivers/video/sh_mobile_hdmi.c

   1 /*
   2  * SH-Mobile High-Definition Multimedia Interface (HDMI) driver
   3  * for SLISHDMI13T and SLIPHDMIT IP cores
   4  *
   5  * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/console.h>
  14 #include <linux/delay.h>
  15 #include <linux/err.h>
  16 #include <linux/init.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/slab.h>
  23 #include <linux/types.h>
  24 #include <linux/workqueue.h>
  25 #include <sound/soc.h>
  26 #include <sound/soc-dapm.h>
  27 #include <sound/initval.h>
  28
  29 #include <video/sh_mobile_hdmi.h>
  30 #include <video/sh_mobile_lcdc.h>
  31
  32 #include "sh_mobile_lcdcfb.h"
  33
  34 #define HDMI_SYSTEM_CTRL                        0x00 /* System control */
  35 #define HDMI_L_R_DATA_SWAP_CTRL_RPKT            0x01 /* L/R data swap control,
  36                                                         bits 19..16 of 20-bit N for Audio Clock Regeneration packet */
  37 #define HDMI_20_BIT_N_FOR_AUDIO_RPKT_15_8       0x02 /* bits 15..8 of 20-bit N for Audio Clock Regeneration packet */
  38 #define HDMI_20_BIT_N_FOR_AUDIO_RPKT_7_0        0x03 /* bits 7..0 of 20-bit N for Audio Clock Regeneration packet */
  39 #define HDMI_SPDIF_AUDIO_SAMP_FREQ_CTS          0x04 /* SPDIF audio sampling frequency,
  40                                                         bits 19..16 of Internal CTS */
  41 #define HDMI_INTERNAL_CTS_15_8                  0x05 /* bits 15..8 of Internal CTS */
  42 #define HDMI_INTERNAL_CTS_7_0                   0x06 /* bits 7..0 of Internal CTS */
  43 #define HDMI_EXTERNAL_CTS_19_16                 0x07 /* External CTS */
  44 #define HDMI_EXTERNAL_CTS_15_8                  0x08 /* External CTS */
  45 #define HDMI_EXTERNAL_CTS_7_0                   0x09 /* External CTS */
  46 #define HDMI_AUDIO_SETTING_1                    0x0A /* Audio setting.1 */
  47 #define HDMI_AUDIO_SETTING_2                    0x0B /* Audio setting.2 */
  48 #define HDMI_I2S_AUDIO_SET                      0x0C /* I2S audio setting */
  49 #define HDMI_DSD_AUDIO_SET                      0x0D /* DSD audio setting */
  50 #define HDMI_DEBUG_MONITOR_1                    0x0E /* Debug monitor.1 */
  51 #define HDMI_DEBUG_MONITOR_2                    0x0F /* Debug monitor.2 */
  52 #define HDMI_I2S_INPUT_PIN_SWAP                 0x10 /* I2S input pin swap */
  53 #define HDMI_AUDIO_STATUS_BITS_SETTING_1        0x11 /* Audio status bits setting.1 */
  54 #define HDMI_AUDIO_STATUS_BITS_SETTING_2        0x12 /* Audio status bits setting.2 */
  55 #define HDMI_CATEGORY_CODE                      0x13 /* Category code */
  56 #define HDMI_SOURCE_NUM_AUDIO_WORD_LEN          0x14 /* Source number/Audio word length */
  57 #define HDMI_AUDIO_VIDEO_SETTING_1              0x15 /* Audio/Video setting.1 */
  58 #define HDMI_VIDEO_SETTING_1                    0x16 /* Video setting.1 */
  59 #define HDMI_DEEP_COLOR_MODES                   0x17 /* Deep Color Modes */
  60
  61 /* 12 16- and 10-bit Color space conversion parameters: 0x18..0x2f */
  62 #define HDMI_COLOR_SPACE_CONVERSION_PARAMETERS  0x18
  63
  64 #define HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS      0x30 /* External video parameter settings */
  65 #define HDMI_EXTERNAL_H_TOTAL_7_0               0x31 /* External horizontal total (LSB) */
  66 #define HDMI_EXTERNAL_H_TOTAL_11_8              0x32 /* External horizontal total (MSB) */
  67 #define HDMI_EXTERNAL_H_BLANK_7_0               0x33 /* External horizontal blank (LSB) */
  68 #define HDMI_EXTERNAL_H_BLANK_9_8               0x34 /* External horizontal blank (MSB) */
  69 #define HDMI_EXTERNAL_H_DELAY_7_0               0x35 /* External horizontal delay (LSB) */
  70 #define HDMI_EXTERNAL_H_DELAY_9_8               0x36 /* External horizontal delay (MSB) */
  71 #define HDMI_EXTERNAL_H_DURATION_7_0            0x37 /* External horizontal duration (LSB) */
  72 #define HDMI_EXTERNAL_H_DURATION_9_8            0x38 /* External horizontal duration (MSB) */
  73 #define HDMI_EXTERNAL_V_TOTAL_7_0               0x39 /* External vertical total (LSB) */
  74 #define HDMI_EXTERNAL_V_TOTAL_9_8               0x3A /* External vertical total (MSB) */
  75 #define HDMI_AUDIO_VIDEO_SETTING_2              0x3B /* Audio/Video setting.2 */
  76 #define HDMI_EXTERNAL_V_BLANK                   0x3D /* External vertical blank */
  77 #define HDMI_EXTERNAL_V_DELAY                   0x3E /* External vertical delay */
  78 #define HDMI_EXTERNAL_V_DURATION                0x3F /* External vertical duration */
  79 #define HDMI_CTRL_PKT_MANUAL_SEND_CONTROL       0x40 /* Control packet manual send control */
  80 #define HDMI_CTRL_PKT_AUTO_SEND                 0x41 /* Control packet auto send with VSYNC control */
  81 #define HDMI_AUTO_CHECKSUM_OPTION               0x42 /* Auto checksum option */
  82 #define HDMI_VIDEO_SETTING_2                    0x45 /* Video setting.2 */
  83 #define HDMI_OUTPUT_OPTION                      0x46 /* Output option */
  84 #define HDMI_SLIPHDMIT_PARAM_OPTION             0x51 /* SLIPHDMIT parameter option */
  85 #define HDMI_HSYNC_PMENT_AT_EMB_7_0             0x52 /* HSYNC placement at embedded sync (LSB) */
  86 #define HDMI_HSYNC_PMENT_AT_EMB_15_8            0x53 /* HSYNC placement at embedded sync (MSB) */
  87 #define HDMI_VSYNC_PMENT_AT_EMB_7_0             0x54 /* VSYNC placement at embedded sync (LSB) */
  88 #define HDMI_VSYNC_PMENT_AT_EMB_14_8            0x55 /* VSYNC placement at embedded sync (MSB) */
  89 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_1         0x56 /* SLIPHDMIT parameter settings.1 */
  90 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_2         0x57 /* SLIPHDMIT parameter settings.2 */
  91 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_3         0x58 /* SLIPHDMIT parameter settings.3 */
  92 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_5         0x59 /* SLIPHDMIT parameter settings.5 */
  93 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_6         0x5A /* SLIPHDMIT parameter settings.6 */
  94 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_7         0x5B /* SLIPHDMIT parameter settings.7 */
  95 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_8         0x5C /* SLIPHDMIT parameter settings.8 */
  96 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_9         0x5D /* SLIPHDMIT parameter settings.9 */
  97 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_10        0x5E /* SLIPHDMIT parameter settings.10 */
  98 #define HDMI_CTRL_PKT_BUF_INDEX                 0x5F /* Control packet buffer index */
  99 #define HDMI_CTRL_PKT_BUF_ACCESS_HB0            0x60 /* Control packet data buffer access window - HB0 */
 100 #define HDMI_CTRL_PKT_BUF_ACCESS_HB1            0x61 /* Control packet data buffer access window - HB1 */
 101 #define HDMI_CTRL_PKT_BUF_ACCESS_HB2            0x62 /* Control packet data buffer access window - HB2 */
 102 #define HDMI_CTRL_PKT_BUF_ACCESS_PB0            0x63 /* Control packet data buffer access window - PB0 */
 103 #define HDMI_CTRL_PKT_BUF_ACCESS_PB1            0x64 /* Control packet data buffer access window - PB1 */
 104 #define HDMI_CTRL_PKT_BUF_ACCESS_PB2            0x65 /* Control packet data buffer access window - PB2 */
 105 #define HDMI_CTRL_PKT_BUF_ACCESS_PB3            0x66 /* Control packet data buffer access window - PB3 */
 106 #define HDMI_CTRL_PKT_BUF_ACCESS_PB4            0x67 /* Control packet data buffer access window - PB4 */
 107 #define HDMI_CTRL_PKT_BUF_ACCESS_PB5            0x68 /* Control packet data buffer access window - PB5 */
 108 #define HDMI_CTRL_PKT_BUF_ACCESS_PB6            0x69 /* Control packet data buffer access window - PB6 */
 109 #define HDMI_CTRL_PKT_BUF_ACCESS_PB7            0x6A /* Control packet data buffer access window - PB7 */
 110 #define HDMI_CTRL_PKT_BUF_ACCESS_PB8            0x6B /* Control packet data buffer access window - PB8 */
 111 #define HDMI_CTRL_PKT_BUF_ACCESS_PB9            0x6C /* Control packet data buffer access window - PB9 */
 112 #define HDMI_CTRL_PKT_BUF_ACCESS_PB10           0x6D /* Control packet data buffer access window - PB10 */
 113 #define HDMI_CTRL_PKT_BUF_ACCESS_PB11           0x6E /* Control packet data buffer access window - PB11 */
 114 #define HDMI_CTRL_PKT_BUF_ACCESS_PB12           0x6F /* Control packet data buffer access window - PB12 */
 115 #define HDMI_CTRL_PKT_BUF_ACCESS_PB13           0x70 /* Control packet data buffer access window - PB13 */
 116 #define HDMI_CTRL_PKT_BUF_ACCESS_PB14           0x71 /* Control packet data buffer access window - PB14 */
 117 #define HDMI_CTRL_PKT_BUF_ACCESS_PB15           0x72 /* Control packet data buffer access window - PB15 */
 118 #define HDMI_CTRL_PKT_BUF_ACCESS_PB16           0x73 /* Control packet data buffer access window - PB16 */
 119 #define HDMI_CTRL_PKT_BUF_ACCESS_PB17           0x74 /* Control packet data buffer access window - PB17 */
 120 #define HDMI_CTRL_PKT_BUF_ACCESS_PB18           0x75 /* Control packet data buffer access window - PB18 */
 121 #define HDMI_CTRL_PKT_BUF_ACCESS_PB19           0x76 /* Control packet data buffer access window - PB19 */
 122 #define HDMI_CTRL_PKT_BUF_ACCESS_PB20           0x77 /* Control packet data buffer access window - PB20 */
 123 #define HDMI_CTRL_PKT_BUF_ACCESS_PB21           0x78 /* Control packet data buffer access window - PB21 */
 124 #define HDMI_CTRL_PKT_BUF_ACCESS_PB22           0x79 /* Control packet data buffer access window - PB22 */
 125 #define HDMI_CTRL_PKT_BUF_ACCESS_PB23           0x7A /* Control packet data buffer access window - PB23 */
 126 #define HDMI_CTRL_PKT_BUF_ACCESS_PB24           0x7B /* Control packet data buffer access window - PB24 */
 127 #define HDMI_CTRL_PKT_BUF_ACCESS_PB25           0x7C /* Control packet data buffer access window - PB25 */
 128 #define HDMI_CTRL_PKT_BUF_ACCESS_PB26           0x7D /* Control packet data buffer access window - PB26 */
 129 #define HDMI_CTRL_PKT_BUF_ACCESS_PB27           0x7E /* Control packet data buffer access window - PB27 */
 130 #define HDMI_EDID_KSV_FIFO_ACCESS_WINDOW        0x80 /* EDID/KSV FIFO access window */
 131 #define HDMI_DDC_BUS_ACCESS_FREQ_CTRL_7_0       0x81 /* DDC bus access frequency control (LSB) */
 132 #define HDMI_DDC_BUS_ACCESS_FREQ_CTRL_15_8      0x82 /* DDC bus access frequency control (MSB) */
 133 #define HDMI_INTERRUPT_MASK_1                   0x92 /* Interrupt mask.1 */
 134 #define HDMI_INTERRUPT_MASK_2                   0x93 /* Interrupt mask.2 */
 135 #define HDMI_INTERRUPT_STATUS_1                 0x94 /* Interrupt status.1 */
 136 #define HDMI_INTERRUPT_STATUS_2                 0x95 /* Interrupt status.2 */
 137 #define HDMI_INTERRUPT_MASK_3                   0x96 /* Interrupt mask.3 */
 138 #define HDMI_INTERRUPT_MASK_4                   0x97 /* Interrupt mask.4 */
 139 #define HDMI_INTERRUPT_STATUS_3                 0x98 /* Interrupt status.3 */
 140 #define HDMI_INTERRUPT_STATUS_4                 0x99 /* Interrupt status.4 */
 141 #define HDMI_SOFTWARE_HDCP_CONTROL_1            0x9A /* Software HDCP control.1 */
 142 #define HDMI_FRAME_COUNTER                      0x9C /* Frame counter */
 143 #define HDMI_FRAME_COUNTER_FOR_RI_CHECK         0x9D /* Frame counter for Ri check */
 144 #define HDMI_HDCP_CONTROL                       0xAF /* HDCP control */
 145 #define HDMI_RI_FRAME_COUNT_REGISTER            0xB2 /* Ri frame count register */
 146 #define HDMI_DDC_BUS_CONTROL                    0xB7 /* DDC bus control */
 147 #define HDMI_HDCP_STATUS                        0xB8 /* HDCP status */
 148 #define HDMI_SHA0                               0xB9 /* sha0 */
 149 #define HDMI_SHA1                               0xBA /* sha1 */
 150 #define HDMI_SHA2                               0xBB /* sha2 */
 151 #define HDMI_SHA3                               0xBC /* sha3 */
 152 #define HDMI_SHA4                               0xBD /* sha4 */
 153 #define HDMI_BCAPS_READ                         0xBE /* BCAPS read / debug */
 154 #define HDMI_AKSV_BKSV_7_0_MONITOR              0xBF /* AKSV/BKSV[7:0] monitor */
 155 #define HDMI_AKSV_BKSV_15_8_MONITOR             0xC0 /* AKSV/BKSV[15:8] monitor */
 156 #define HDMI_AKSV_BKSV_23_16_MONITOR            0xC1 /* AKSV/BKSV[23:16] monitor */
 157 #define HDMI_AKSV_BKSV_31_24_MONITOR            0xC2 /* AKSV/BKSV[31:24] monitor */
 158 #define HDMI_AKSV_BKSV_39_32_MONITOR            0xC3 /* AKSV/BKSV[39:32] monitor */
 159 #define HDMI_EDID_SEGMENT_POINTER               0xC4 /* EDID segment pointer */
 160 #define HDMI_EDID_WORD_ADDRESS                  0xC5 /* EDID word address */
 161 #define HDMI_EDID_DATA_FIFO_ADDRESS             0xC6 /* EDID data FIFO address */
 162 #define HDMI_NUM_OF_HDMI_DEVICES                0xC7 /* Number of HDMI devices */
 163 #define HDMI_HDCP_ERROR_CODE                    0xC8 /* HDCP error code */
 164 #define HDMI_100MS_TIMER_SET                    0xC9 /* 100ms timer setting */
 165 #define HDMI_5SEC_TIMER_SET                     0xCA /* 5sec timer setting */
 166 #define HDMI_RI_READ_COUNT                      0xCB /* Ri read count */
 167 #define HDMI_AN_SEED                            0xCC /* An seed */
 168 #define HDMI_MAX_NUM_OF_RCIVRS_ALLOWED          0xCD /* Maximum number of receivers allowed */
 169 #define HDMI_HDCP_MEMORY_ACCESS_CONTROL_1       0xCE /* HDCP memory access control.1 */
 170 #define HDMI_HDCP_MEMORY_ACCESS_CONTROL_2       0xCF /* HDCP memory access control.2 */
 171 #define HDMI_HDCP_CONTROL_2                     0xD0 /* HDCP Control 2 */
 172 #define HDMI_HDCP_KEY_MEMORY_CONTROL            0xD2 /* HDCP Key Memory Control */
 173 #define HDMI_COLOR_SPACE_CONV_CONFIG_1          0xD3 /* Color space conversion configuration.1 */
 174 #define HDMI_VIDEO_SETTING_3                    0xD4 /* Video setting.3 */
 175 #define HDMI_RI_7_0                             0xD5 /* Ri[7:0] */
 176 #define HDMI_RI_15_8                            0xD6 /* Ri[15:8] */
 177 #define HDMI_PJ                                 0xD7 /* Pj */
 178 #define HDMI_SHA_RD                             0xD8 /* sha_rd */
 179 #define HDMI_RI_7_0_SAVED                       0xD9 /* Ri[7:0] saved */
 180 #define HDMI_RI_15_8_SAVED                      0xDA /* Ri[15:8] saved */
 181 #define HDMI_PJ_SAVED                           0xDB /* Pj saved */
 182 #define HDMI_NUM_OF_DEVICES                     0xDC /* Number of devices */
 183 #define HDMI_HOT_PLUG_MSENS_STATUS              0xDF /* Hot plug/MSENS status */
 184 #define HDMI_BCAPS_WRITE                        0xE0 /* bcaps */
 185 #define HDMI_BSTAT_7_0                          0xE1 /* bstat[7:0] */
 186 #define HDMI_BSTAT_15_8                         0xE2 /* bstat[15:8] */
 187 #define HDMI_BKSV_7_0                           0xE3 /* bksv[7:0] */
 188 #define HDMI_BKSV_15_8                          0xE4 /* bksv[15:8] */
 189 #define HDMI_BKSV_23_16                         0xE5 /* bksv[23:16] */
 190 #define HDMI_BKSV_31_24                         0xE6 /* bksv[31:24] */
 191 #define HDMI_BKSV_39_32                         0xE7 /* bksv[39:32] */
 192 #define HDMI_AN_7_0                             0xE8 /* An[7:0] */
 193 #define HDMI_AN_15_8                            0xE9 /* An [15:8] */
 194 #define HDMI_AN_23_16                           0xEA /* An [23:16] */
 195 #define HDMI_AN_31_24                           0xEB /* An [31:24] */
 196 #define HDMI_AN_39_32                           0xEC /* An [39:32] */
 197 #define HDMI_AN_47_40                           0xED /* An [47:40] */
 198 #define HDMI_AN_55_48                           0xEE /* An [55:48] */
 199 #define HDMI_AN_63_56                           0xEF /* An [63:56] */
 200 #define HDMI_PRODUCT_ID                         0xF0 /* Product ID */
 201 #define HDMI_REVISION_ID                        0xF1 /* Revision ID */
 202 #define HDMI_TEST_MODE                          0xFE /* Test mode */
 203
 204 enum hotplug_state {
 205         HDMI_HOTPLUG_DISCONNECTED,
 206         HDMI_HOTPLUG_CONNECTED,
 207         HDMI_HOTPLUG_EDID_DONE,
 208 };
 209
 210 struct sh_hdmi {
 211         struct sh_mobile_lcdc_entity entity;
 212
 213         void __iomem *base;
 214         enum hotplug_state hp_state;    /* hot-plug status */
 215         u8 preprogrammed_vic;           /* use a pre-programmed VIC or
 216                                            the external mode */
 217         u8 edid_block_addr;
 218         u8 edid_segment_nr;
 219         u8 edid_blocks;
 220         struct clk *hdmi_clk;
 221         struct device *dev;
 222         struct delayed_work edid_work;
 223         struct fb_videomode mode;
 224         struct fb_monspecs monspec;
 225
 226         /* register access functions */
 227         void (*write)(struct sh_hdmi *hdmi, u8 data, u8 reg);
 228         u8 (*read)(struct sh_hdmi *hdmi, u8 reg);
 229 };
 230
 231 #define entity_to_sh_hdmi(e)    container_of(e, struct sh_hdmi, entity)
 232
 233 static void __hdmi_write8(struct sh_hdmi *hdmi, u8 data, u8 reg)
 234 {
 235         iowrite8(data, hdmi->base + reg);
 236 }
 237
 238 static u8 __hdmi_read8(struct sh_hdmi *hdmi, u8 reg)
 239 {
 240         return ioread8(hdmi->base + reg);
 241 }
 242
 243 static void __hdmi_write32(struct sh_hdmi *hdmi, u8 data, u8 reg)
 244 {
 245         iowrite32((u32)data, hdmi->base + (reg * 4));
 246         udelay(100);
 247 }
 248
 249 static u8 __hdmi_read32(struct sh_hdmi *hdmi, u8 reg)
 250 {
 251         return (u8)ioread32(hdmi->base + (reg * 4));
 252 }
 253
 254 static void hdmi_write(struct sh_hdmi *hdmi, u8 data, u8 reg)
 255 {
 256         hdmi->write(hdmi, data, reg);
 257 }
 258
 259 static u8 hdmi_read(struct sh_hdmi *hdmi, u8 reg)
 260 {
 261         return hdmi->read(hdmi, reg);
 262 }
 263
 264 static void hdmi_bit_set(struct sh_hdmi *hdmi, u8 mask, u8 data, u8 reg)
 265 {
 266         u8 val = hdmi_read(hdmi, reg);
 267
 268         val &= ~mask;
 269         val |= (data & mask);
 270
 271         hdmi_write(hdmi, val, reg);
 272 }
 273
 274 /*
 275  *      HDMI sound
 276  */
 277 static unsigned int sh_hdmi_snd_read(struct snd_soc_codec *codec,
 278                                      unsigned int reg)
 279 {
 280         struct sh_hdmi *hdmi = snd_soc_codec_get_drvdata(codec);
 281
 282         return hdmi_read(hdmi, reg);
 283 }
 284
 285 static int sh_hdmi_snd_write(struct snd_soc_codec *codec,
 286                              unsigned int reg,
 287                              unsigned int value)
 288 {
 289         struct sh_hdmi *hdmi = snd_soc_codec_get_drvdata(codec);
 290
 291         hdmi_write(hdmi, value, reg);
 292         return 0;
 293 }
 294
 295 static struct snd_soc_dai_driver sh_hdmi_dai = {
 296         .name = "sh_mobile_hdmi-hifi",
 297         .playback = {
 298                 .stream_name = "Playback",
 299                 .channels_min = 2,
 300                 .channels_max = 8,
 301                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100  |
 302                          SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200  |
 303                          SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
 304                          SNDRV_PCM_RATE_192000,
 305                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 306         },
 307 };
 308
 309 static int sh_hdmi_snd_probe(struct snd_soc_codec *codec)
 310 {
 311         dev_info(codec->dev, "SH Mobile HDMI Audio Codec");
 312
 313         return 0;
 314 }
 315
 316 static struct snd_soc_codec_driver soc_codec_dev_sh_hdmi = {
 317         .probe          = sh_hdmi_snd_probe,
 318         .read           = sh_hdmi_snd_read,
 319         .write          = sh_hdmi_snd_write,
 320 };
 321
 322 /*
 323  *      HDMI video
 324  */
 325
 326 /* External video parameter settings */
 327 static void sh_hdmi_external_video_param(struct sh_hdmi *hdmi)
 328 {
 329         struct fb_videomode *mode = &hdmi->mode;
 330         u16 htotal, hblank, hdelay, vtotal, vblank, vdelay, voffset;
 331         u8 sync = 0;
 332
 333         htotal = mode->xres + mode->right_margin + mode->left_margin
 334                + mode->hsync_len;
 335         hdelay = mode->hsync_len + mode->left_margin;
 336         hblank = mode->right_margin + hdelay;
 337
 338         /*
 339          * Vertical timing looks a bit different in Figure 18,
 340          * but let's try the same first by setting offset = 0
 341          */
 342         vtotal = mode->yres + mode->upper_margin + mode->lower_margin
 343                + mode->vsync_len;
 344         vdelay = mode->vsync_len + mode->upper_margin;
 345         vblank = mode->lower_margin + vdelay;
 346         voffset = min(mode->upper_margin / 2, 6U);
 347
 348         /*
 349          * [3]: VSYNC polarity: Positive
 350          * [2]: HSYNC polarity: Positive
 351          * [1]: Interlace/Progressive: Progressive
 352          * [0]: External video settings enable: used.
 353          */
 354         if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
 355                 sync |= 4;
 356         if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
 357                 sync |= 8;
 358
 359         dev_dbg(hdmi->dev, "H: %u, %u, %u, %u; V: %u, %u, %u, %u; sync 0x%x\n",
 360                 htotal, hblank, hdelay, mode->hsync_len,
 361                 vtotal, vblank, vdelay, mode->vsync_len, sync);
 362
 363         hdmi_write(hdmi, sync | (voffset << 4), HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS);
 364
 365         hdmi_write(hdmi, htotal, HDMI_EXTERNAL_H_TOTAL_7_0);
 366         hdmi_write(hdmi, htotal >> 8, HDMI_EXTERNAL_H_TOTAL_11_8);
 367
 368         hdmi_write(hdmi, hblank, HDMI_EXTERNAL_H_BLANK_7_0);
 369         hdmi_write(hdmi, hblank >> 8, HDMI_EXTERNAL_H_BLANK_9_8);
 370
 371         hdmi_write(hdmi, hdelay, HDMI_EXTERNAL_H_DELAY_7_0);
 372         hdmi_write(hdmi, hdelay >> 8, HDMI_EXTERNAL_H_DELAY_9_8);
 373
 374         hdmi_write(hdmi, mode->hsync_len, HDMI_EXTERNAL_H_DURATION_7_0);
 375         hdmi_write(hdmi, mode->hsync_len >> 8, HDMI_EXTERNAL_H_DURATION_9_8);
 376
 377         hdmi_write(hdmi, vtotal, HDMI_EXTERNAL_V_TOTAL_7_0);
 378         hdmi_write(hdmi, vtotal >> 8, HDMI_EXTERNAL_V_TOTAL_9_8);
 379
 380         hdmi_write(hdmi, vblank, HDMI_EXTERNAL_V_BLANK);
 381
 382         hdmi_write(hdmi, vdelay, HDMI_EXTERNAL_V_DELAY);
 383
 384         hdmi_write(hdmi, mode->vsync_len, HDMI_EXTERNAL_V_DURATION);
 385
 386         /* Set bit 0 of HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS here for external mode */
 387         if (!hdmi->preprogrammed_vic)
 388                 hdmi_write(hdmi, sync | 1 | (voffset << 4),
 389                            HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS);
 390 }
 391
 392 /**
 393  * sh_hdmi_video_config()
 394  */
 395 static void sh_hdmi_video_config(struct sh_hdmi *hdmi)
 396 {
 397         /*
 398          * [7:4]: Audio sampling frequency: 48kHz
 399          * [3:1]: Input video format: RGB and YCbCr 4:4:4 (Y on Green)
 400          * [0]: Internal/External DE select: internal
 401          */
 402         hdmi_write(hdmi, 0x20, HDMI_AUDIO_VIDEO_SETTING_1);
 403
 404         /*
 405          * [7:6]: Video output format: RGB 4:4:4
 406          * [5:4]: Input video data width: 8 bit
 407          * [3:1]: EAV/SAV location: channel 1
 408          * [0]: Video input color space: RGB
 409          */
 410         hdmi_write(hdmi, 0x34, HDMI_VIDEO_SETTING_1);
 411
 412         /*
 413          * [7:6]: Together with bit [6] of HDMI_AUDIO_VIDEO_SETTING_2, which is
 414          * left at 0 by default, this configures 24bpp and sets the Color Depth
 415          * (CD) field in the General Control Packet
 416          */
 417         hdmi_write(hdmi, 0x20, HDMI_DEEP_COLOR_MODES);
 418 }
 419
 420 /**
 421  * sh_hdmi_audio_config()
 422  */
 423 static void sh_hdmi_audio_config(struct sh_hdmi *hdmi)
 424 {
 425         u8 data;
 426         struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
 427
 428         /*
 429          * [7:4] L/R data swap control
 430          * [3:0] appropriate N[19:16]
 431          */
 432         hdmi_write(hdmi, 0x00, HDMI_L_R_DATA_SWAP_CTRL_RPKT);
 433         /* appropriate N[15:8] */
 434         hdmi_write(hdmi, 0x18, HDMI_20_BIT_N_FOR_AUDIO_RPKT_15_8);
 435         /* appropriate N[7:0] */
 436         hdmi_write(hdmi, 0x00, HDMI_20_BIT_N_FOR_AUDIO_RPKT_7_0);
 437
 438         /* [7:4] 48 kHz SPDIF not used */
 439         hdmi_write(hdmi, 0x20, HDMI_SPDIF_AUDIO_SAMP_FREQ_CTS);
 440
 441         /*
 442          * [6:5] set required down sampling rate if required
 443          * [4:3] set required audio source
 444          */
 445         switch (pdata->flags & HDMI_SND_SRC_MASK) {
 446         default:
 447                 /* fall through */
 448         case HDMI_SND_SRC_I2S:
 449                 data = 0x0 << 3;
 450                 break;
 451         case HDMI_SND_SRC_SPDIF:
 452                 data = 0x1 << 3;
 453                 break;
 454         case HDMI_SND_SRC_DSD:
 455                 data = 0x2 << 3;
 456                 break;
 457         case HDMI_SND_SRC_HBR:
 458                 data = 0x3 << 3;
 459                 break;
 460         }
 461         hdmi_write(hdmi, data, HDMI_AUDIO_SETTING_1);
 462
 463         /* [3:0] set sending channel number for channel status */
 464         hdmi_write(hdmi, 0x40, HDMI_AUDIO_SETTING_2);
 465
 466         /*
 467          * [5:2] set valid I2S source input pin
 468          * [1:0] set input I2S source mode
 469          */
 470         hdmi_write(hdmi, 0x04, HDMI_I2S_AUDIO_SET);
 471
 472         /* [7:4] set valid DSD source input pin */
 473         hdmi_write(hdmi, 0x00, HDMI_DSD_AUDIO_SET);
 474
 475         /* [7:0] set appropriate I2S input pin swap settings if required */
 476         hdmi_write(hdmi, 0x00, HDMI_I2S_INPUT_PIN_SWAP);
 477
 478         /*
 479          * [7] set validity bit for channel status
 480          * [3:0] set original sample frequency for channel status
 481          */
 482         hdmi_write(hdmi, 0x00, HDMI_AUDIO_STATUS_BITS_SETTING_1);
 483
 484         /*
 485          * [7] set value for channel status
 486          * [6] set value for channel status
 487          * [5] set copyright bit for channel status
 488          * [4:2] set additional information for channel status
 489          * [1:0] set clock accuracy for channel status
 490          */
 491         hdmi_write(hdmi, 0x00, HDMI_AUDIO_STATUS_BITS_SETTING_2);
 492
 493         /* [7:0] set category code for channel status */
 494         hdmi_write(hdmi, 0x00, HDMI_CATEGORY_CODE);
 495
 496         /*
 497          * [7:4] set source number for channel status
 498          * [3:0] set word length for channel status
 499          */
 500         hdmi_write(hdmi, 0x00, HDMI_SOURCE_NUM_AUDIO_WORD_LEN);
 501
 502         /* [7:4] set sample frequency for channel status */
 503         hdmi_write(hdmi, 0x20, HDMI_AUDIO_VIDEO_SETTING_1);
 504 }
 505
 506 /**
 507  * sh_hdmi_phy_config() - configure the HDMI PHY for the used video mode
 508  */
 509 static void sh_hdmi_phy_config(struct sh_hdmi *hdmi)
 510 {
 511         if (hdmi->mode.pixclock < 10000) {
 512                 /* for 1080p8bit 148MHz */
 513                 hdmi_write(hdmi, 0x1d, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
 514                 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
 515                 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
 516                 hdmi_write(hdmi, 0x4c, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
 517                 hdmi_write(hdmi, 0x1e, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
 518                 hdmi_write(hdmi, 0x48, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
 519                 hdmi_write(hdmi, 0x0e, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
 520                 hdmi_write(hdmi, 0x25, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
 521                 hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
 522         } else if (hdmi->mode.pixclock < 30000) {
 523                 /* 720p, 8bit, 74.25MHz. Might need to be adjusted for other formats */
 524                 /*
 525                  * [1:0]        Speed_A
 526                  * [3:2]        Speed_B
 527                  * [4]          PLLA_Bypass
 528                  * [6]          DRV_TEST_EN
 529                  * [7]          DRV_TEST_IN
 530                  */
 531                 hdmi_write(hdmi, 0x0f, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
 532                 /* PLLB_CONFIG[17], PLLA_CONFIG[17] - not in PHY datasheet */
 533                 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
 534                 /*
 535                  * [2:0]        BGR_I_OFFSET
 536                  * [6:4]        BGR_V_OFFSET
 537                  */
 538                 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
 539                 /* PLLA_CONFIG[7:0]: VCO gain, VCO offset, LPF resistance[0] */
 540                 hdmi_write(hdmi, 0x44, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
 541                 /*
 542                  * PLLA_CONFIG[15:8]: regulator voltage[0], CP current,
 543                  * LPF capacitance, LPF resistance[1]
 544                  */
 545                 hdmi_write(hdmi, 0x32, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
 546                 /* PLLB_CONFIG[7:0]: LPF resistance[0], VCO offset, VCO gain */
 547                 hdmi_write(hdmi, 0x4A, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
 548                 /*
 549                  * PLLB_CONFIG[15:8]: regulator voltage[0], CP current,
 550                  * LPF capacitance, LPF resistance[1]
 551                  */
 552                 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
 553                 /* DRV_CONFIG, PE_CONFIG */
 554                 hdmi_write(hdmi, 0x25, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
 555                 /*
 556                  * [2:0]        AMON_SEL (4 == LPF voltage)
 557                  * [4]          PLLA_CONFIG[16]
 558                  * [5]          PLLB_CONFIG[16]
 559                  */
 560                 hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
 561         } else {
 562                 /* for 480p8bit 27MHz */
 563                 hdmi_write(hdmi, 0x19, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
 564                 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
 565                 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
 566                 hdmi_write(hdmi, 0x44, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
 567                 hdmi_write(hdmi, 0x32, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
 568                 hdmi_write(hdmi, 0x48, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
 569                 hdmi_write(hdmi, 0x0F, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
 570                 hdmi_write(hdmi, 0x20, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
 571                 hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
 572         }
 573 }
 574
 575 /**
 576  * sh_hdmi_avi_infoframe_setup() - Auxiliary Video Information InfoFrame CONTROL PACKET
 577  */
 578 static void sh_hdmi_avi_infoframe_setup(struct sh_hdmi *hdmi)
 579 {
 580         u8 vic;
 581
 582         /* AVI InfoFrame */
 583         hdmi_write(hdmi, 0x06, HDMI_CTRL_PKT_BUF_INDEX);
 584
 585         /* Packet Type = 0x82 */
 586         hdmi_write(hdmi, 0x82, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
 587
 588         /* Version = 0x02 */
 589         hdmi_write(hdmi, 0x02, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
 590
 591         /* Length = 13 (0x0D) */
 592         hdmi_write(hdmi, 0x0D, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
 593
 594         /* N. A. Checksum */
 595         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0);
 596
 597         /*
 598          * Y = RGB
 599          * A0 = No Data
 600          * B = Bar Data not valid
 601          * S = No Data
 602          */
 603         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB1);
 604
 605         /*
 606          * [7:6] C = Colorimetry: no data
 607          * [5:4] M = 2: 16:9, 1: 4:3 Picture Aspect Ratio
 608          * [3:0] R = 8: Active Frame Aspect Ratio: same as picture aspect ratio
 609          */
 610         hdmi_write(hdmi, 0x28, HDMI_CTRL_PKT_BUF_ACCESS_PB2);
 611
 612         /*
 613          * ITC = No Data
 614          * EC = xvYCC601
 615          * Q = Default (depends on video format)
 616          * SC = No Known non_uniform Scaling
 617          */
 618         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB3);
 619
 620         /*
 621          * VIC should be ignored if external config is used, so, we could just use 0,
 622          * but play safe and use a valid value in any case just in case
 623          */
 624         if (hdmi->preprogrammed_vic)
 625                 vic = hdmi->preprogrammed_vic;
 626         else
 627                 vic = 4;
 628         hdmi_write(hdmi, vic, HDMI_CTRL_PKT_BUF_ACCESS_PB4);
 629
 630         /* PR = No Repetition */
 631         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB5);
 632
 633         /* Line Number of End of Top Bar (lower 8 bits) */
 634         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB6);
 635
 636         /* Line Number of End of Top Bar (upper 8 bits) */
 637         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB7);
 638
 639         /* Line Number of Start of Bottom Bar (lower 8 bits) */
 640         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB8);
 641
 642         /* Line Number of Start of Bottom Bar (upper 8 bits) */
 643         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB9);
 644
 645         /* Pixel Number of End of Left Bar (lower 8 bits) */
 646         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB10);
 647
 648         /* Pixel Number of End of Left Bar (upper 8 bits) */
 649         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB11);
 650
 651         /* Pixel Number of Start of Right Bar (lower 8 bits) */
 652         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB12);
 653
 654         /* Pixel Number of Start of Right Bar (upper 8 bits) */
 655         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB13);
 656 }
 657
 658 /**
 659  * sh_hdmi_audio_infoframe_setup() - Audio InfoFrame of CONTROL PACKET
 660  */
 661 static void sh_hdmi_audio_infoframe_setup(struct sh_hdmi *hdmi)
 662 {
 663         /* Audio InfoFrame */
 664         hdmi_write(hdmi, 0x08, HDMI_CTRL_PKT_BUF_INDEX);
 665
 666         /* Packet Type = 0x84 */
 667         hdmi_write(hdmi, 0x84, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
 668
 669         /* Version Number = 0x01 */
 670         hdmi_write(hdmi, 0x01, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
 671
 672         /* 0 Length = 10 (0x0A) */
 673         hdmi_write(hdmi, 0x0A, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
 674
 675         /* n. a. Checksum */
 676         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0);
 677
 678         /* Audio Channel Count = Refer to Stream Header */
 679         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB1);
 680
 681         /* Refer to Stream Header */
 682         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB2);
 683
 684         /* Format depends on coding type (i.e. CT0...CT3) */
 685         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB3);
 686
 687         /* Speaker Channel Allocation = Front Right + Front Left */
 688         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB4);
 689
 690         /* Level Shift Value = 0 dB, Down - mix is permitted or no information */
 691         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB5);
 692
 693         /* Reserved (0) */
 694         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB6);
 695         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB7);
 696         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB8);
 697         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB9);
 698         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB10);
 699 }
 700
 701 /**
 702  * sh_hdmi_configure() - Initialise HDMI for output
 703  */
 704 static void sh_hdmi_configure(struct sh_hdmi *hdmi)
 705 {
 706         /* Configure video format */
 707         sh_hdmi_video_config(hdmi);
 708
 709         /* Configure audio format */
 710         sh_hdmi_audio_config(hdmi);
 711
 712         /* Configure PHY */
 713         sh_hdmi_phy_config(hdmi);
 714
 715         /* Auxiliary Video Information (AVI) InfoFrame */
 716         sh_hdmi_avi_infoframe_setup(hdmi);
 717
 718         /* Audio InfoFrame */
 719         sh_hdmi_audio_infoframe_setup(hdmi);
 720
 721         /*
 722          * Control packet auto send with VSYNC control: auto send
 723          * General control, Gamut metadata, ISRC, and ACP packets
 724          */
 725         hdmi_write(hdmi, 0x8E, HDMI_CTRL_PKT_AUTO_SEND);
 726
 727         /* FIXME */
 728         msleep(10);
 729
 730         /* PS mode b->d, reset PLLA and PLLB */
 731         hdmi_bit_set(hdmi, 0xFC, 0x4C, HDMI_SYSTEM_CTRL);
 732
 733         udelay(10);
 734
 735         hdmi_bit_set(hdmi, 0xFC, 0x40, HDMI_SYSTEM_CTRL);
 736 }
 737
 738 static unsigned long sh_hdmi_rate_error(struct sh_hdmi *hdmi,
 739                 const struct fb_videomode *mode,
 740                 unsigned long *hdmi_rate, unsigned long *parent_rate)
 741 {
 742         unsigned long target = PICOS2KHZ(mode->pixclock) * 1000, rate_error;
 743         struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
 744
 745         *hdmi_rate = clk_round_rate(hdmi->hdmi_clk, target);
 746         if ((long)*hdmi_rate < 0)
 747                 *hdmi_rate = clk_get_rate(hdmi->hdmi_clk);
 748
 749         rate_error = (long)*hdmi_rate > 0 ? abs(*hdmi_rate - target) : ULONG_MAX;
 750         if (rate_error && pdata->clk_optimize_parent)
 751                 rate_error = pdata->clk_optimize_parent(target, hdmi_rate, parent_rate);
 752         else if (clk_get_parent(hdmi->hdmi_clk))
 753                 *parent_rate = clk_get_rate(clk_get_parent(hdmi->hdmi_clk));
 754
 755         dev_dbg(hdmi->dev, "%u-%u-%u-%u x %u-%u-%u-%u\n",
 756                 mode->left_margin, mode->xres,
 757                 mode->right_margin, mode->hsync_len,
 758                 mode->upper_margin, mode->yres,
 759                 mode->lower_margin, mode->vsync_len);
 760
 761         dev_dbg(hdmi->dev, "\t@%lu(+/-%lu)Hz, e=%lu / 1000, r=%uHz, p=%luHz\n", target,
 762                 rate_error, rate_error ? 10000 / (10 * target / rate_error) : 0,
 763                 mode->refresh, *parent_rate);
 764
 765         return rate_error;
 766 }
 767
 768 static int sh_hdmi_read_edid(struct sh_hdmi *hdmi, unsigned long *hdmi_rate,
 769                              unsigned long *parent_rate)
 770 {
 771         struct sh_mobile_lcdc_chan *ch = hdmi->entity.lcdc;
 772         const struct fb_videomode *mode, *found = NULL;
 773         unsigned int f_width = 0, f_height = 0, f_refresh = 0;
 774         unsigned long found_rate_error = ULONG_MAX; /* silly compiler... */
 775         bool scanning = false, preferred_bad = false;
 776         bool use_edid_mode = false;
 777         u8 edid[128];
 778         char *forced;
 779         int i;
 780
 781         /* Read EDID */
 782         dev_dbg(hdmi->dev, "Read back EDID code:");
 783         for (i = 0; i < 128; i++) {
 784                 edid[i] = hdmi_read(hdmi, HDMI_EDID_KSV_FIFO_ACCESS_WINDOW);
 785 #ifdef DEBUG
 786                 if ((i % 16) == 0) {
 787                         printk(KERN_CONT "\n");
 788                         printk(KERN_DEBUG "%02X | %02X", i, edid[i]);
 789                 } else {
 790                         printk(KERN_CONT " %02X", edid[i]);
 791                 }
 792 #endif
 793         }
 794 #ifdef DEBUG
 795         printk(KERN_CONT "\n");
 796 #endif
 797
 798         if (!hdmi->edid_blocks) {
 799                 fb_edid_to_monspecs(edid, &hdmi->monspec);
 800                 hdmi->edid_blocks = edid[126] + 1;
 801
 802                 dev_dbg(hdmi->dev, "%d main modes, %d extension blocks\n",
 803                         hdmi->monspec.modedb_len, hdmi->edid_blocks - 1);
 804         } else {
 805                 dev_dbg(hdmi->dev, "Extension %u detected, DTD start %u\n",
 806                         edid[0], edid[2]);
 807                 fb_edid_add_monspecs(edid, &hdmi->monspec);
 808         }
 809
 810         if (hdmi->edid_blocks > hdmi->edid_segment_nr * 2 +
 811             (hdmi->edid_block_addr >> 7) + 1) {
 812                 /* More blocks to read */
 813                 if (hdmi->edid_block_addr) {
 814                         hdmi->edid_block_addr = 0;
 815                         hdmi->edid_segment_nr++;
 816                 } else {
 817                         hdmi->edid_block_addr = 0x80;
 818                 }
 819                 /* Set EDID word address  */
 820                 hdmi_write(hdmi, hdmi->edid_block_addr, HDMI_EDID_WORD_ADDRESS);
 821                 /* Enable EDID interrupt */
 822                 hdmi_write(hdmi, 0xC6, HDMI_INTERRUPT_MASK_1);
 823                 /* Set EDID segment pointer - starts reading EDID */
 824                 hdmi_write(hdmi, hdmi->edid_segment_nr, HDMI_EDID_SEGMENT_POINTER);
 825                 return -EAGAIN;
 826         }
 827
 828         /* All E-EDID blocks ready */
 829         dev_dbg(hdmi->dev, "%d main and extended modes\n", hdmi->monspec.modedb_len);
 830
 831         fb_get_options("sh_mobile_lcdc", &forced);
 832         if (forced && *forced) {
 833                 /* Only primitive parsing so far */
 834                 i = sscanf(forced, "%ux%u@%u",
 835                            &f_width, &f_height, &f_refresh);
 836                 if (i < 2) {
 837                         f_width = 0;
 838                         f_height = 0;
 839                 } else {
 840                         /* The user wants us to use the EDID data */
 841                         scanning = true;
 842                 }
 843                 dev_dbg(hdmi->dev, "Forced mode %ux%u@%uHz\n",
 844                         f_width, f_height, f_refresh);
 845         }
 846
 847         /* Walk monitor modes to find the best or the exact match */
 848         for (i = 0, mode = hdmi->monspec.modedb;
 849              i < hdmi->monspec.modedb_len && scanning;
 850              i++, mode++) {
 851                 unsigned long rate_error;
 852
 853                 if (!f_width && !f_height) {
 854                         /*
 855                          * A parameter string "video=sh_mobile_lcdc:0x0" means
 856                          * use the preferred EDID mode. If it is rejected by
 857                          * .fb_check_var(), keep looking, until an acceptable
 858                          * one is found.
 859                          */
 860                         if ((mode->flag & FB_MODE_IS_FIRST) || preferred_bad)
 861                                 scanning = false;
 862                         else
 863                                 continue;
 864                 } else if (f_width != mode->xres || f_height != mode->yres) {
 865                         /* No interest in unmatching modes */
 866                         continue;
 867                 }
 868
 869                 rate_error = sh_hdmi_rate_error(hdmi, mode, hdmi_rate, parent_rate);
 870
 871                 if (scanning) {
 872                         if (f_refresh == mode->refresh || (!f_refresh && !rate_error))
 873                                 /*
 874                                  * Exact match if either the refresh rate
 875                                  * matches or it hasn't been specified and we've
 876                                  * found a mode, for which we can configure the
 877                                  * clock precisely
 878                                  */
 879                                 scanning = false;
 880                         else if (found && found_rate_error <= rate_error)
 881                                 /*
 882                                  * We otherwise search for the closest matching
 883                                  * clock rate - either if no refresh rate has
 884                                  * been specified or we cannot find an exactly
 885                                  * matching one
 886                                  */
 887                                 continue;
 888                 }
 889
 890                 /* Check if supported: sufficient fb memory, supported clock-rate */
 891                 if (ch && ch->notify &&
 892                     ch->notify(ch, SH_MOBILE_LCDC_EVENT_DISPLAY_MODE, mode,
 893                                NULL)) {
 894                         scanning = true;
 895                         preferred_bad = true;
 896                         continue;
 897                 }
 898
 899                 found = mode;
 900                 found_rate_error = rate_error;
 901                 use_edid_mode = true;
 902         }
 903
 904         /*
 905          * TODO 1: if no default mode is present, postpone running the config
 906          * until after the LCDC channel is initialized.
 907          * TODO 2: consider registering the HDMI platform device from the LCDC
 908          * driver.
 909          */
 910         if (!found && hdmi->entity.def_mode.xres != 0) {
 911                 found = &hdmi->entity.def_mode;
 912                 found_rate_error = sh_hdmi_rate_error(hdmi, found, hdmi_rate,
 913                                                       parent_rate);
 914         }
 915
 916         /* No cookie today */
 917         if (!found)
 918                 return -ENXIO;
 919
 920         if (found->xres == 640 && found->yres == 480 && found->refresh == 60)
 921                 hdmi->preprogrammed_vic = 1;
 922         else if (found->xres == 720 && found->yres == 480 && found->refresh == 60)
 923                 hdmi->preprogrammed_vic = 2;
 924         else if (found->xres == 720 && found->yres == 576 && found->refresh == 50)
 925                 hdmi->preprogrammed_vic = 17;
 926         else if (found->xres == 1280 && found->yres == 720 && found->refresh == 60)
 927                 hdmi->preprogrammed_vic = 4;
 928         else if (found->xres == 1920 && found->yres == 1080 && found->refresh == 24)
 929                 hdmi->preprogrammed_vic = 32;
 930         else if (found->xres == 1920 && found->yres == 1080 && found->refresh == 50)
 931                 hdmi->preprogrammed_vic = 31;
 932         else if (found->xres == 1920 && found->yres == 1080 && found->refresh == 60)
 933                 hdmi->preprogrammed_vic = 16;
 934         else
 935                 hdmi->preprogrammed_vic = 0;
 936
 937         dev_dbg(hdmi->dev, "Using %s %s mode %ux%u@%uHz (%luHz), "
 938                 "clock error %luHz\n", use_edid_mode ? "EDID" : "default",
 939                 hdmi->preprogrammed_vic ? "VIC" : "external", found->xres,
 940                 found->yres, found->refresh, PICOS2KHZ(found->pixclock) * 1000,
 941                 found_rate_error);
 942
 943         hdmi->mode = *found;
 944         sh_hdmi_external_video_param(hdmi);
 945
 946         return 0;
 947 }
 948
 949 static irqreturn_t sh_hdmi_hotplug(int irq, void *dev_id)
 950 {
 951         struct sh_hdmi *hdmi = dev_id;
 952         u8 status1, status2, mask1, mask2;
 953
 954         /* mode_b and PLLA and PLLB reset */
 955         hdmi_bit_set(hdmi, 0xFC, 0x2C, HDMI_SYSTEM_CTRL);
 956
 957         /* How long shall reset be held? */
 958         udelay(10);
 959
 960         /* mode_b and PLLA and PLLB reset release */
 961         hdmi_bit_set(hdmi, 0xFC, 0x20, HDMI_SYSTEM_CTRL);
 962
 963         status1 = hdmi_read(hdmi, HDMI_INTERRUPT_STATUS_1);
 964         status2 = hdmi_read(hdmi, HDMI_INTERRUPT_STATUS_2);
 965
 966         mask1 = hdmi_read(hdmi, HDMI_INTERRUPT_MASK_1);
 967         mask2 = hdmi_read(hdmi, HDMI_INTERRUPT_MASK_2);
 968
 969         /* Correct would be to ack only set bits, but the datasheet requires 0xff */
 970         hdmi_write(hdmi, 0xFF, HDMI_INTERRUPT_STATUS_1);
 971         hdmi_write(hdmi, 0xFF, HDMI_INTERRUPT_STATUS_2);
 972
 973         if (printk_ratelimit())
 974                 dev_dbg(hdmi->dev, "IRQ #%d: Status #1: 0x%x & 0x%x, #2: 0x%x & 0x%x\n",
 975                         irq, status1, mask1, status2, mask2);
 976
 977         if (!((status1 & mask1) | (status2 & mask2))) {
 978                 return IRQ_NONE;
 979         } else if (status1 & 0xc0) {
 980                 u8 msens;
 981
 982                 /* Datasheet specifies 10ms... */
 983                 udelay(500);
 984
 985                 msens = hdmi_read(hdmi, HDMI_HOT_PLUG_MSENS_STATUS);
 986                 dev_dbg(hdmi->dev, "MSENS 0x%x\n", msens);
 987                 /* Check, if hot plug & MSENS pin status are both high */
 988                 if ((msens & 0xC0) == 0xC0) {
 989                         /* Display plug in */
 990                         hdmi->edid_segment_nr = 0;
 991                         hdmi->edid_block_addr = 0;
 992                         hdmi->edid_blocks = 0;
 993                         hdmi->hp_state = HDMI_HOTPLUG_CONNECTED;
 994
 995                         /* Set EDID word address  */
 996                         hdmi_write(hdmi, 0x00, HDMI_EDID_WORD_ADDRESS);
 997                         /* Enable EDID interrupt */
 998                         hdmi_write(hdmi, 0xC6, HDMI_INTERRUPT_MASK_1);
 999                         /* Set EDID segment pointer - starts reading EDID */
1000                         hdmi_write(hdmi, 0x00, HDMI_EDID_SEGMENT_POINTER);
1001                 } else if (!(status1 & 0x80)) {
1002                         /* Display unplug, beware multiple interrupts */
1003                         if (hdmi->hp_state != HDMI_HOTPLUG_DISCONNECTED) {
1004                                 hdmi->hp_state = HDMI_HOTPLUG_DISCONNECTED;
1005                                 schedule_delayed_work(&hdmi->edid_work, 0);
1006                         }
1007                         /* display_off will switch back to mode_a */
1008                 }
1009         } else if (status1 & 2) {
1010                 /* EDID error interrupt: retry */
1011                 /* Set EDID word address  */
1012                 hdmi_write(hdmi, hdmi->edid_block_addr, HDMI_EDID_WORD_ADDRESS);
1013                 /* Set EDID segment pointer */
1014                 hdmi_write(hdmi, hdmi->edid_segment_nr, HDMI_EDID_SEGMENT_POINTER);
1015         } else if (status1 & 4) {
1016                 /* Disable EDID interrupt */
1017                 hdmi_write(hdmi, 0xC0, HDMI_INTERRUPT_MASK_1);
1018                 schedule_delayed_work(&hdmi->edid_work, msecs_to_jiffies(10));
1019         }
1020
1021         return IRQ_HANDLED;
1022 }
1023
1024 static int sh_hdmi_display_on(struct sh_mobile_lcdc_entity *entity)
1025 {
1026         struct sh_hdmi *hdmi = entity_to_sh_hdmi(entity);
1027
1028         dev_dbg(hdmi->dev, "%s(%p): state %x\n", __func__, hdmi,
1029                 hdmi->hp_state);
1030
1031         /*
1032          * hp_state can be set to
1033          * HDMI_HOTPLUG_DISCONNECTED:   on monitor unplug
1034          * HDMI_HOTPLUG_CONNECTED:      on monitor plug-in
1035          * HDMI_HOTPLUG_EDID_DONE:      on EDID read completion
1036          */
1037         if (hdmi->hp_state == HDMI_HOTPLUG_EDID_DONE) {
1038                 /* PS mode d->e. All functions are active */
1039                 hdmi_bit_set(hdmi, 0xFC, 0x80, HDMI_SYSTEM_CTRL);
1040                 dev_dbg(hdmi->dev, "HDMI running\n");
1041         }
1042
1043         return hdmi->hp_state == HDMI_HOTPLUG_DISCONNECTED
1044                 ? SH_MOBILE_LCDC_DISPLAY_DISCONNECTED
1045                 : SH_MOBILE_LCDC_DISPLAY_CONNECTED;
1046 }
1047
1048 static void sh_hdmi_display_off(struct sh_mobile_lcdc_entity *entity)
1049 {
1050         struct sh_hdmi *hdmi = entity_to_sh_hdmi(entity);
1051
1052         dev_dbg(hdmi->dev, "%s(%p)\n", __func__, hdmi);
1053         /* PS mode e->a */
1054         hdmi_bit_set(hdmi, 0xFC, 0x10, HDMI_SYSTEM_CTRL);
1055 }
1056
1057 static const struct sh_mobile_lcdc_entity_ops sh_hdmi_ops = {
1058         .display_on = sh_hdmi_display_on,
1059         .display_off = sh_hdmi_display_off,
1060 };
1061
1062 /**
1063  * sh_hdmi_clk_configure() - set HDMI clock frequency and enable the clock
1064  * @hdmi:               driver context
1065  * @hdmi_rate:          HDMI clock frequency in Hz
1066  * @parent_rate:        if != 0 - set parent clock rate for optimal precision
1067  * return:              configured positive rate if successful
1068  *                      0 if couldn't set the rate, but managed to enable the
1069  *                      clock, negative error, if couldn't enable the clock
1070  */
1071 static long sh_hdmi_clk_configure(struct sh_hdmi *hdmi, unsigned long hdmi_rate,
1072                                   unsigned long parent_rate)
1073 {
1074         int ret;
1075
1076         if (parent_rate && clk_get_parent(hdmi->hdmi_clk)) {
1077                 ret = clk_set_rate(clk_get_parent(hdmi->hdmi_clk), parent_rate);
1078                 if (ret < 0) {
1079                         dev_warn(hdmi->dev, "Cannot set parent rate %ld: %d\n", parent_rate, ret);
1080                         hdmi_rate = clk_round_rate(hdmi->hdmi_clk, hdmi_rate);
1081                 } else {
1082                         dev_dbg(hdmi->dev, "HDMI set parent frequency %lu\n", parent_rate);
1083                 }
1084         }
1085
1086         ret = clk_set_rate(hdmi->hdmi_clk, hdmi_rate);
1087         if (ret < 0) {
1088                 dev_warn(hdmi->dev, "Cannot set rate %ld: %d\n", hdmi_rate, ret);
1089                 hdmi_rate = 0;
1090         } else {
1091                 dev_dbg(hdmi->dev, "HDMI set frequency %lu\n", hdmi_rate);
1092         }
1093
1094         return hdmi_rate;
1095 }
1096
1097 /* Hotplug interrupt occurred, read EDID */
1098 static void sh_hdmi_edid_work_fn(struct work_struct *work)
1099 {
1100         struct sh_hdmi *hdmi = container_of(work, struct sh_hdmi, edid_work.work);
1101         struct sh_mobile_lcdc_chan *ch = hdmi->entity.lcdc;
1102         int ret;
1103
1104         dev_dbg(hdmi->dev, "%s(%p): begin, hotplug status %d\n", __func__, hdmi,
1105                 hdmi->hp_state);
1106
1107         if (hdmi->hp_state == HDMI_HOTPLUG_CONNECTED) {
1108                 unsigned long parent_rate = 0, hdmi_rate;
1109
1110                 ret = sh_hdmi_read_edid(hdmi, &hdmi_rate, &parent_rate);
1111                 if (ret < 0)
1112                         goto out;
1113
1114                 hdmi->hp_state = HDMI_HOTPLUG_EDID_DONE;
1115
1116                 /* Reconfigure the clock */
1117                 ret = sh_hdmi_clk_configure(hdmi, hdmi_rate, parent_rate);
1118                 if (ret < 0)
1119                         goto out;
1120
1121                 msleep(10);
1122                 sh_hdmi_configure(hdmi);
1123                 /* Switched to another (d) power-save mode */
1124                 msleep(10);
1125
1126                 if (ch && ch->notify)
1127                         ch->notify(ch, SH_MOBILE_LCDC_EVENT_DISPLAY_CONNECT,
1128                                    &hdmi->mode, &hdmi->monspec);
1129         } else {
1130                 hdmi->monspec.modedb_len = 0;
1131                 fb_destroy_modedb(hdmi->monspec.modedb);
1132                 hdmi->monspec.modedb = NULL;
1133
1134                 if (ch && ch->notify)
1135                         ch->notify(ch, SH_MOBILE_LCDC_EVENT_DISPLAY_DISCONNECT,
1136                                    NULL, NULL);
1137
1138                 ret = 0;
1139         }
1140
1141 out:
1142         if (ret < 0 && ret != -EAGAIN)
1143                 hdmi->hp_state = HDMI_HOTPLUG_DISCONNECTED;
1144
1145         dev_dbg(hdmi->dev, "%s(%p): end\n", __func__, hdmi);
1146 }
1147
1148 static int __init sh_hdmi_probe(struct platform_device *pdev)
1149 {
1150         struct sh_mobile_hdmi_info *pdata = pdev->dev.platform_data;
1151         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1152         int irq = platform_get_irq(pdev, 0), ret;
1153         struct sh_hdmi *hdmi;
1154         long rate;
1155
1156         if (!res || !pdata || irq < 0)
1157                 return -ENODEV;
1158
1159         hdmi = kzalloc(sizeof(*hdmi), GFP_KERNEL);
1160         if (!hdmi) {
1161                 dev_err(&pdev->dev, "Cannot allocate device data\n");
1162                 return -ENOMEM;
1163         }
1164
1165         hdmi->dev = &pdev->dev;
1166         hdmi->entity.owner = THIS_MODULE;
1167         hdmi->entity.ops = &sh_hdmi_ops;
1168
1169         hdmi->hdmi_clk = clk_get(&pdev->dev, "ick");
1170         if (IS_ERR(hdmi->hdmi_clk)) {
1171                 ret = PTR_ERR(hdmi->hdmi_clk);
1172                 dev_err(&pdev->dev, "Unable to get clock: %d\n", ret);
1173                 goto egetclk;
1174         }
1175
1176         /* select register access functions */
1177         if (pdata->flags & HDMI_32BIT_REG) {
1178                 hdmi->write     = __hdmi_write32;
1179                 hdmi->read      = __hdmi_read32;
1180         } else {
1181                 hdmi->write     = __hdmi_write8;
1182                 hdmi->read      = __hdmi_read8;
1183         }
1184
1185         /* An arbitrary relaxed pixclock just to get things started: from standard 480p */
1186         rate = clk_round_rate(hdmi->hdmi_clk, PICOS2KHZ(37037));
1187         if (rate > 0)
1188                 rate = sh_hdmi_clk_configure(hdmi, rate, 0);
1189
1190         if (rate < 0) {
1191                 ret = rate;
1192                 goto erate;
1193         }
1194
1195         ret = clk_enable(hdmi->hdmi_clk);
1196         if (ret < 0) {
1197                 dev_err(hdmi->dev, "Cannot enable clock: %d\n", ret);
1198                 goto erate;
1199         }
1200
1201         dev_dbg(&pdev->dev, "Enabled HDMI clock at %luHz\n", rate);
1202
1203         if (!request_mem_region(res->start, resource_size(res), dev_name(&pdev->dev))) {
1204                 dev_err(&pdev->dev, "HDMI register region already claimed\n");
1205                 ret = -EBUSY;
1206                 goto ereqreg;
1207         }
1208
1209         hdmi->base = ioremap(res->start, resource_size(res));
1210         if (!hdmi->base) {
1211                 dev_err(&pdev->dev, "HDMI register region already claimed\n");
1212                 ret = -ENOMEM;
1213                 goto emap;
1214         }
1215
1216         platform_set_drvdata(pdev, &hdmi->entity);
1217
1218         INIT_DELAYED_WORK(&hdmi->edid_work, sh_hdmi_edid_work_fn);
1219
1220         pm_runtime_enable(&pdev->dev);
1221         pm_runtime_get_sync(&pdev->dev);
1222
1223         /* init interrupt polarity */
1224         if (pdata->flags & HDMI_OUTPUT_PUSH_PULL)
1225                 hdmi_bit_set(hdmi, 0x02, 0x02, HDMI_SYSTEM_CTRL);
1226
1227         if (pdata->flags & HDMI_OUTPUT_POLARITY_HI)
1228                 hdmi_bit_set(hdmi, 0x01, 0x01, HDMI_SYSTEM_CTRL);
1229
1230         /* Product and revision IDs are 0 in sh-mobile version */
1231         dev_info(&pdev->dev, "Detected HDMI controller 0x%x:0x%x\n",
1232                  hdmi_read(hdmi, HDMI_PRODUCT_ID), hdmi_read(hdmi, HDMI_REVISION_ID));
1233
1234         ret = request_irq(irq, sh_hdmi_hotplug, 0,
1235                           dev_name(&pdev->dev), hdmi);
1236         if (ret < 0) {
1237                 dev_err(&pdev->dev, "Unable to request irq: %d\n", ret);
1238                 goto ereqirq;
1239         }
1240
1241         ret = snd_soc_register_codec(&pdev->dev,
1242                         &soc_codec_dev_sh_hdmi, &sh_hdmi_dai, 1);
1243         if (ret < 0) {
1244                 dev_err(&pdev->dev, "codec registration failed\n");
1245                 goto ecodec;
1246         }
1247
1248         return 0;
1249
1250 ecodec:
1251         free_irq(irq, hdmi);
1252 ereqirq:
1253         pm_runtime_put(&pdev->dev);
1254         pm_runtime_disable(&pdev->dev);
1255         iounmap(hdmi->base);
1256 emap:
1257         release_mem_region(res->start, resource_size(res));
1258 ereqreg:
1259         clk_disable(hdmi->hdmi_clk);
1260 erate:
1261         clk_put(hdmi->hdmi_clk);
1262 egetclk:
1263         kfree(hdmi);
1264
1265         return ret;
1266 }
1267
1268 static int __exit sh_hdmi_remove(struct platform_device *pdev)
1269 {
1270         struct sh_hdmi *hdmi = entity_to_sh_hdmi(platform_get_drvdata(pdev));
1271         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1272         int irq = platform_get_irq(pdev, 0);
1273
1274         snd_soc_unregister_codec(&pdev->dev);
1275
1276         /* No new work will be scheduled, wait for running ISR */
1277         free_irq(irq, hdmi);
1278         /* Wait for already scheduled work */
1279         cancel_delayed_work_sync(&hdmi->edid_work);
1280         pm_runtime_put(&pdev->dev);
1281         pm_runtime_disable(&pdev->dev);
1282         clk_disable(hdmi->hdmi_clk);
1283         clk_put(hdmi->hdmi_clk);
1284         iounmap(hdmi->base);
1285         release_mem_region(res->start, resource_size(res));
1286         kfree(hdmi);
1287
1288         return 0;
1289 }
1290
1291 static struct platform_driver sh_hdmi_driver = {
1292         .remove         = __exit_p(sh_hdmi_remove),
1293         .driver = {
1294                 .name   = "sh-mobile-hdmi",
1295         },
1296 };
1297
1298 static int __init sh_hdmi_init(void)
1299 {
1300         return platform_driver_probe(&sh_hdmi_driver, sh_hdmi_probe);
1301 }
1302 module_init(sh_hdmi_init);
1303
1304 static void __exit sh_hdmi_exit(void)
1305 {
1306         platform_driver_unregister(&sh_hdmi_driver);
1307 }
1308 module_exit(sh_hdmi_exit);
1309
1310 MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
1311 MODULE_DESCRIPTION("SuperH / ARM-shmobile HDMI driver");
1312 MODULE_LICENSE("GPL v2");