drivers/video/sh_mobile_hdmi.c

   1 /*
   2  * SH-Mobile High-Definition Multimedia Interface (HDMI) driver
   3  * for SLISHDMI13T and SLIPHDMIT IP cores
   4  *
   5  * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/console.h>
  14 #include <linux/delay.h>
  15 #include <linux/err.h>
  16 #include <linux/init.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/slab.h>
  23 #include <linux/types.h>
  24 #include <linux/workqueue.h>
  25 #include <sound/soc.h>
  26 #include <sound/soc-dapm.h>
  27 #include <sound/initval.h>
  28
  29 #include <video/sh_mobile_hdmi.h>
  30 #include <video/sh_mobile_lcdc.h>
  31
  32 #include "sh_mobile_lcdcfb.h"
  33
  34 #define HDMI_SYSTEM_CTRL                        0x00 /* System control */
  35 #define HDMI_L_R_DATA_SWAP_CTRL_RPKT            0x01 /* L/R data swap control,
  36                                                         bits 19..16 of 20-bit N for Audio Clock Regeneration packet */
  37 #define HDMI_20_BIT_N_FOR_AUDIO_RPKT_15_8       0x02 /* bits 15..8 of 20-bit N for Audio Clock Regeneration packet */
  38 #define HDMI_20_BIT_N_FOR_AUDIO_RPKT_7_0        0x03 /* bits 7..0 of 20-bit N for Audio Clock Regeneration packet */
  39 #define HDMI_SPDIF_AUDIO_SAMP_FREQ_CTS          0x04 /* SPDIF audio sampling frequency,
  40                                                         bits 19..16 of Internal CTS */
  41 #define HDMI_INTERNAL_CTS_15_8                  0x05 /* bits 15..8 of Internal CTS */
  42 #define HDMI_INTERNAL_CTS_7_0                   0x06 /* bits 7..0 of Internal CTS */
  43 #define HDMI_EXTERNAL_CTS_19_16                 0x07 /* External CTS */
  44 #define HDMI_EXTERNAL_CTS_15_8                  0x08 /* External CTS */
  45 #define HDMI_EXTERNAL_CTS_7_0                   0x09 /* External CTS */
  46 #define HDMI_AUDIO_SETTING_1                    0x0A /* Audio setting.1 */
  47 #define HDMI_AUDIO_SETTING_2                    0x0B /* Audio setting.2 */
  48 #define HDMI_I2S_AUDIO_SET                      0x0C /* I2S audio setting */
  49 #define HDMI_DSD_AUDIO_SET                      0x0D /* DSD audio setting */
  50 #define HDMI_DEBUG_MONITOR_1                    0x0E /* Debug monitor.1 */
  51 #define HDMI_DEBUG_MONITOR_2                    0x0F /* Debug monitor.2 */
  52 #define HDMI_I2S_INPUT_PIN_SWAP                 0x10 /* I2S input pin swap */
  53 #define HDMI_AUDIO_STATUS_BITS_SETTING_1        0x11 /* Audio status bits setting.1 */
  54 #define HDMI_AUDIO_STATUS_BITS_SETTING_2        0x12 /* Audio status bits setting.2 */
  55 #define HDMI_CATEGORY_CODE                      0x13 /* Category code */
  56 #define HDMI_SOURCE_NUM_AUDIO_WORD_LEN          0x14 /* Source number/Audio word length */
  57 #define HDMI_AUDIO_VIDEO_SETTING_1              0x15 /* Audio/Video setting.1 */
  58 #define HDMI_VIDEO_SETTING_1                    0x16 /* Video setting.1 */
  59 #define HDMI_DEEP_COLOR_MODES                   0x17 /* Deep Color Modes */
  60
  61 /* 12 16- and 10-bit Color space conversion parameters: 0x18..0x2f */
  62 #define HDMI_COLOR_SPACE_CONVERSION_PARAMETERS  0x18
  63
  64 #define HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS      0x30 /* External video parameter settings */
  65 #define HDMI_EXTERNAL_H_TOTAL_7_0               0x31 /* External horizontal total (LSB) */
  66 #define HDMI_EXTERNAL_H_TOTAL_11_8              0x32 /* External horizontal total (MSB) */
  67 #define HDMI_EXTERNAL_H_BLANK_7_0               0x33 /* External horizontal blank (LSB) */
  68 #define HDMI_EXTERNAL_H_BLANK_9_8               0x34 /* External horizontal blank (MSB) */
  69 #define HDMI_EXTERNAL_H_DELAY_7_0               0x35 /* External horizontal delay (LSB) */
  70 #define HDMI_EXTERNAL_H_DELAY_9_8               0x36 /* External horizontal delay (MSB) */
  71 #define HDMI_EXTERNAL_H_DURATION_7_0            0x37 /* External horizontal duration (LSB) */
  72 #define HDMI_EXTERNAL_H_DURATION_9_8            0x38 /* External horizontal duration (MSB) */
  73 #define HDMI_EXTERNAL_V_TOTAL_7_0               0x39 /* External vertical total (LSB) */
  74 #define HDMI_EXTERNAL_V_TOTAL_9_8               0x3A /* External vertical total (MSB) */
  75 #define HDMI_AUDIO_VIDEO_SETTING_2              0x3B /* Audio/Video setting.2 */
  76 #define HDMI_EXTERNAL_V_BLANK                   0x3D /* External vertical blank */
  77 #define HDMI_EXTERNAL_V_DELAY                   0x3E /* External vertical delay */
  78 #define HDMI_EXTERNAL_V_DURATION                0x3F /* External vertical duration */
  79 #define HDMI_CTRL_PKT_MANUAL_SEND_CONTROL       0x40 /* Control packet manual send control */
  80 #define HDMI_CTRL_PKT_AUTO_SEND                 0x41 /* Control packet auto send with VSYNC control */
  81 #define HDMI_AUTO_CHECKSUM_OPTION               0x42 /* Auto checksum option */
  82 #define HDMI_VIDEO_SETTING_2                    0x45 /* Video setting.2 */
  83 #define HDMI_OUTPUT_OPTION                      0x46 /* Output option */
  84 #define HDMI_SLIPHDMIT_PARAM_OPTION             0x51 /* SLIPHDMIT parameter option */
  85 #define HDMI_HSYNC_PMENT_AT_EMB_7_0             0x52 /* HSYNC placement at embedded sync (LSB) */
  86 #define HDMI_HSYNC_PMENT_AT_EMB_15_8            0x53 /* HSYNC placement at embedded sync (MSB) */
  87 #define HDMI_VSYNC_PMENT_AT_EMB_7_0             0x54 /* VSYNC placement at embedded sync (LSB) */
  88 #define HDMI_VSYNC_PMENT_AT_EMB_14_8            0x55 /* VSYNC placement at embedded sync (MSB) */
  89 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_1         0x56 /* SLIPHDMIT parameter settings.1 */
  90 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_2         0x57 /* SLIPHDMIT parameter settings.2 */
  91 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_3         0x58 /* SLIPHDMIT parameter settings.3 */
  92 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_5         0x59 /* SLIPHDMIT parameter settings.5 */
  93 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_6         0x5A /* SLIPHDMIT parameter settings.6 */
  94 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_7         0x5B /* SLIPHDMIT parameter settings.7 */
  95 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_8         0x5C /* SLIPHDMIT parameter settings.8 */
  96 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_9         0x5D /* SLIPHDMIT parameter settings.9 */
  97 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_10        0x5E /* SLIPHDMIT parameter settings.10 */
  98 #define HDMI_CTRL_PKT_BUF_INDEX                 0x5F /* Control packet buffer index */
  99 #define HDMI_CTRL_PKT_BUF_ACCESS_HB0            0x60 /* Control packet data buffer access window - HB0 */
 100 #define HDMI_CTRL_PKT_BUF_ACCESS_HB1            0x61 /* Control packet data buffer access window - HB1 */
 101 #define HDMI_CTRL_PKT_BUF_ACCESS_HB2            0x62 /* Control packet data buffer access window - HB2 */
 102 #define HDMI_CTRL_PKT_BUF_ACCESS_PB0            0x63 /* Control packet data buffer access window - PB0 */
 103 #define HDMI_CTRL_PKT_BUF_ACCESS_PB1            0x64 /* Control packet data buffer access window - PB1 */
 104 #define HDMI_CTRL_PKT_BUF_ACCESS_PB2            0x65 /* Control packet data buffer access window - PB2 */
 105 #define HDMI_CTRL_PKT_BUF_ACCESS_PB3            0x66 /* Control packet data buffer access window - PB3 */
 106 #define HDMI_CTRL_PKT_BUF_ACCESS_PB4            0x67 /* Control packet data buffer access window - PB4 */
 107 #define HDMI_CTRL_PKT_BUF_ACCESS_PB5            0x68 /* Control packet data buffer access window - PB5 */
 108 #define HDMI_CTRL_PKT_BUF_ACCESS_PB6            0x69 /* Control packet data buffer access window - PB6 */
 109 #define HDMI_CTRL_PKT_BUF_ACCESS_PB7            0x6A /* Control packet data buffer access window - PB7 */
 110 #define HDMI_CTRL_PKT_BUF_ACCESS_PB8            0x6B /* Control packet data buffer access window - PB8 */
 111 #define HDMI_CTRL_PKT_BUF_ACCESS_PB9            0x6C /* Control packet data buffer access window - PB9 */
 112 #define HDMI_CTRL_PKT_BUF_ACCESS_PB10           0x6D /* Control packet data buffer access window - PB10 */
 113 #define HDMI_CTRL_PKT_BUF_ACCESS_PB11           0x6E /* Control packet data buffer access window - PB11 */
 114 #define HDMI_CTRL_PKT_BUF_ACCESS_PB12           0x6F /* Control packet data buffer access window - PB12 */
 115 #define HDMI_CTRL_PKT_BUF_ACCESS_PB13           0x70 /* Control packet data buffer access window - PB13 */
 116 #define HDMI_CTRL_PKT_BUF_ACCESS_PB14           0x71 /* Control packet data buffer access window - PB14 */
 117 #define HDMI_CTRL_PKT_BUF_ACCESS_PB15           0x72 /* Control packet data buffer access window - PB15 */
 118 #define HDMI_CTRL_PKT_BUF_ACCESS_PB16           0x73 /* Control packet data buffer access window - PB16 */
 119 #define HDMI_CTRL_PKT_BUF_ACCESS_PB17           0x74 /* Control packet data buffer access window - PB17 */
 120 #define HDMI_CTRL_PKT_BUF_ACCESS_PB18           0x75 /* Control packet data buffer access window - PB18 */
 121 #define HDMI_CTRL_PKT_BUF_ACCESS_PB19           0x76 /* Control packet data buffer access window - PB19 */
 122 #define HDMI_CTRL_PKT_BUF_ACCESS_PB20           0x77 /* Control packet data buffer access window - PB20 */
 123 #define HDMI_CTRL_PKT_BUF_ACCESS_PB21           0x78 /* Control packet data buffer access window - PB21 */
 124 #define HDMI_CTRL_PKT_BUF_ACCESS_PB22           0x79 /* Control packet data buffer access window - PB22 */
 125 #define HDMI_CTRL_PKT_BUF_ACCESS_PB23           0x7A /* Control packet data buffer access window - PB23 */
 126 #define HDMI_CTRL_PKT_BUF_ACCESS_PB24           0x7B /* Control packet data buffer access window - PB24 */
 127 #define HDMI_CTRL_PKT_BUF_ACCESS_PB25           0x7C /* Control packet data buffer access window - PB25 */
 128 #define HDMI_CTRL_PKT_BUF_ACCESS_PB26           0x7D /* Control packet data buffer access window - PB26 */
 129 #define HDMI_CTRL_PKT_BUF_ACCESS_PB27           0x7E /* Control packet data buffer access window - PB27 */
 130 #define HDMI_EDID_KSV_FIFO_ACCESS_WINDOW        0x80 /* EDID/KSV FIFO access window */
 131 #define HDMI_DDC_BUS_ACCESS_FREQ_CTRL_7_0       0x81 /* DDC bus access frequency control (LSB) */
 132 #define HDMI_DDC_BUS_ACCESS_FREQ_CTRL_15_8      0x82 /* DDC bus access frequency control (MSB) */
 133 #define HDMI_INTERRUPT_MASK_1                   0x92 /* Interrupt mask.1 */
 134 #define HDMI_INTERRUPT_MASK_2                   0x93 /* Interrupt mask.2 */
 135 #define HDMI_INTERRUPT_STATUS_1                 0x94 /* Interrupt status.1 */
 136 #define HDMI_INTERRUPT_STATUS_2                 0x95 /* Interrupt status.2 */
 137 #define HDMI_INTERRUPT_MASK_3                   0x96 /* Interrupt mask.3 */
 138 #define HDMI_INTERRUPT_MASK_4                   0x97 /* Interrupt mask.4 */
 139 #define HDMI_INTERRUPT_STATUS_3                 0x98 /* Interrupt status.3 */
 140 #define HDMI_INTERRUPT_STATUS_4                 0x99 /* Interrupt status.4 */
 141 #define HDMI_SOFTWARE_HDCP_CONTROL_1            0x9A /* Software HDCP control.1 */
 142 #define HDMI_FRAME_COUNTER                      0x9C /* Frame counter */
 143 #define HDMI_FRAME_COUNTER_FOR_RI_CHECK         0x9D /* Frame counter for Ri check */
 144 #define HDMI_HDCP_CONTROL                       0xAF /* HDCP control */
 145 #define HDMI_RI_FRAME_COUNT_REGISTER            0xB2 /* Ri frame count register */
 146 #define HDMI_DDC_BUS_CONTROL                    0xB7 /* DDC bus control */
 147 #define HDMI_HDCP_STATUS                        0xB8 /* HDCP status */
 148 #define HDMI_SHA0                               0xB9 /* sha0 */
 149 #define HDMI_SHA1                               0xBA /* sha1 */
 150 #define HDMI_SHA2                               0xBB /* sha2 */
 151 #define HDMI_SHA3                               0xBC /* sha3 */
 152 #define HDMI_SHA4                               0xBD /* sha4 */
 153 #define HDMI_BCAPS_READ                         0xBE /* BCAPS read / debug */
 154 #define HDMI_AKSV_BKSV_7_0_MONITOR              0xBF /* AKSV/BKSV[7:0] monitor */
 155 #define HDMI_AKSV_BKSV_15_8_MONITOR             0xC0 /* AKSV/BKSV[15:8] monitor */
 156 #define HDMI_AKSV_BKSV_23_16_MONITOR            0xC1 /* AKSV/BKSV[23:16] monitor */
 157 #define HDMI_AKSV_BKSV_31_24_MONITOR            0xC2 /* AKSV/BKSV[31:24] monitor */
 158 #define HDMI_AKSV_BKSV_39_32_MONITOR            0xC3 /* AKSV/BKSV[39:32] monitor */
 159 #define HDMI_EDID_SEGMENT_POINTER               0xC4 /* EDID segment pointer */
 160 #define HDMI_EDID_WORD_ADDRESS                  0xC5 /* EDID word address */
 161 #define HDMI_EDID_DATA_FIFO_ADDRESS             0xC6 /* EDID data FIFO address */
 162 #define HDMI_NUM_OF_HDMI_DEVICES                0xC7 /* Number of HDMI devices */
 163 #define HDMI_HDCP_ERROR_CODE                    0xC8 /* HDCP error code */
 164 #define HDMI_100MS_TIMER_SET                    0xC9 /* 100ms timer setting */
 165 #define HDMI_5SEC_TIMER_SET                     0xCA /* 5sec timer setting */
 166 #define HDMI_RI_READ_COUNT                      0xCB /* Ri read count */
 167 #define HDMI_AN_SEED                            0xCC /* An seed */
 168 #define HDMI_MAX_NUM_OF_RCIVRS_ALLOWED          0xCD /* Maximum number of receivers allowed */
 169 #define HDMI_HDCP_MEMORY_ACCESS_CONTROL_1       0xCE /* HDCP memory access control.1 */
 170 #define HDMI_HDCP_MEMORY_ACCESS_CONTROL_2       0xCF /* HDCP memory access control.2 */
 171 #define HDMI_HDCP_CONTROL_2                     0xD0 /* HDCP Control 2 */
 172 #define HDMI_HDCP_KEY_MEMORY_CONTROL            0xD2 /* HDCP Key Memory Control */
 173 #define HDMI_COLOR_SPACE_CONV_CONFIG_1          0xD3 /* Color space conversion configuration.1 */
 174 #define HDMI_VIDEO_SETTING_3                    0xD4 /* Video setting.3 */
 175 #define HDMI_RI_7_0                             0xD5 /* Ri[7:0] */
 176 #define HDMI_RI_15_8                            0xD6 /* Ri[15:8] */
 177 #define HDMI_PJ                                 0xD7 /* Pj */
 178 #define HDMI_SHA_RD                             0xD8 /* sha_rd */
 179 #define HDMI_RI_7_0_SAVED                       0xD9 /* Ri[7:0] saved */
 180 #define HDMI_RI_15_8_SAVED                      0xDA /* Ri[15:8] saved */
 181 #define HDMI_PJ_SAVED                           0xDB /* Pj saved */
 182 #define HDMI_NUM_OF_DEVICES                     0xDC /* Number of devices */
 183 #define HDMI_HOT_PLUG_MSENS_STATUS              0xDF /* Hot plug/MSENS status */
 184 #define HDMI_BCAPS_WRITE                        0xE0 /* bcaps */
 185 #define HDMI_BSTAT_7_0                          0xE1 /* bstat[7:0] */
 186 #define HDMI_BSTAT_15_8                         0xE2 /* bstat[15:8] */
 187 #define HDMI_BKSV_7_0                           0xE3 /* bksv[7:0] */
 188 #define HDMI_BKSV_15_8                          0xE4 /* bksv[15:8] */
 189 #define HDMI_BKSV_23_16                         0xE5 /* bksv[23:16] */
 190 #define HDMI_BKSV_31_24                         0xE6 /* bksv[31:24] */
 191 #define HDMI_BKSV_39_32                         0xE7 /* bksv[39:32] */
 192 #define HDMI_AN_7_0                             0xE8 /* An[7:0] */
 193 #define HDMI_AN_15_8                            0xE9 /* An [15:8] */
 194 #define HDMI_AN_23_16                           0xEA /* An [23:16] */
 195 #define HDMI_AN_31_24                           0xEB /* An [31:24] */
 196 #define HDMI_AN_39_32                           0xEC /* An [39:32] */
 197 #define HDMI_AN_47_40                           0xED /* An [47:40] */
 198 #define HDMI_AN_55_48                           0xEE /* An [55:48] */
 199 #define HDMI_AN_63_56                           0xEF /* An [63:56] */
 200 #define HDMI_PRODUCT_ID                         0xF0 /* Product ID */
 201 #define HDMI_REVISION_ID                        0xF1 /* Revision ID */
 202 #define HDMI_TEST_MODE                          0xFE /* Test mode */
 203
 204 enum hotplug_state {
 205         HDMI_HOTPLUG_DISCONNECTED,
 206         HDMI_HOTPLUG_CONNECTED,
 207         HDMI_HOTPLUG_EDID_DONE,
 208 };
 209
 210 struct sh_hdmi {
 211         struct sh_mobile_lcdc_entity entity;
 212
 213         void __iomem *base;
 214         enum hotplug_state hp_state;    /* hot-plug status */
 215         u8 preprogrammed_vic;           /* use a pre-programmed VIC or
 216                                            the external mode */
 217         u8 edid_block_addr;
 218         u8 edid_segment_nr;
 219         u8 edid_blocks;
 220         struct clk *hdmi_clk;
 221         struct device *dev;
 222         struct fb_info *info;
 223         struct mutex mutex;             /* Protect the info pointer */
 224         struct delayed_work edid_work;
 225         struct fb_var_screeninfo var;
 226         struct fb_monspecs monspec;
 227         struct notifier_block notifier;
 228 };
 229
 230 #define entity_to_sh_hdmi(e)    container_of(e, struct sh_hdmi, entity)
 231 #define notifier_to_hdmi(n)     container_of(n, struct sh_hdmi, notifier)
 232
 233 static void hdmi_write(struct sh_hdmi *hdmi, u8 data, u8 reg)
 234 {
 235         iowrite8(data, hdmi->base + reg);
 236 }
 237
 238 static u8 hdmi_read(struct sh_hdmi *hdmi, u8 reg)
 239 {
 240         return ioread8(hdmi->base + reg);
 241 }
 242
 243 /*
 244  *      HDMI sound
 245  */
 246 static unsigned int sh_hdmi_snd_read(struct snd_soc_codec *codec,
 247                                      unsigned int reg)
 248 {
 249         struct sh_hdmi *hdmi = snd_soc_codec_get_drvdata(codec);
 250
 251         return hdmi_read(hdmi, reg);
 252 }
 253
 254 static int sh_hdmi_snd_write(struct snd_soc_codec *codec,
 255                              unsigned int reg,
 256                              unsigned int value)
 257 {
 258         struct sh_hdmi *hdmi = snd_soc_codec_get_drvdata(codec);
 259
 260         hdmi_write(hdmi, value, reg);
 261         return 0;
 262 }
 263
 264 static struct snd_soc_dai_driver sh_hdmi_dai = {
 265         .name = "sh_mobile_hdmi-hifi",
 266         .playback = {
 267                 .stream_name = "Playback",
 268                 .channels_min = 2,
 269                 .channels_max = 8,
 270                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100  |
 271                          SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200  |
 272                          SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
 273                          SNDRV_PCM_RATE_192000,
 274                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 275         },
 276 };
 277
 278 static int sh_hdmi_snd_probe(struct snd_soc_codec *codec)
 279 {
 280         dev_info(codec->dev, "SH Mobile HDMI Audio Codec");
 281
 282         return 0;
 283 }
 284
 285 static struct snd_soc_codec_driver soc_codec_dev_sh_hdmi = {
 286         .probe          = sh_hdmi_snd_probe,
 287         .read           = sh_hdmi_snd_read,
 288         .write          = sh_hdmi_snd_write,
 289 };
 290
 291 /*
 292  *      HDMI video
 293  */
 294
 295 /* External video parameter settings */
 296 static void sh_hdmi_external_video_param(struct sh_hdmi *hdmi)
 297 {
 298         struct fb_var_screeninfo *var = &hdmi->var;
 299         u16 htotal, hblank, hdelay, vtotal, vblank, vdelay, voffset;
 300         u8 sync = 0;
 301
 302         htotal = var->xres + var->right_margin + var->left_margin + var->hsync_len;
 303
 304         hdelay = var->hsync_len + var->left_margin;
 305         hblank = var->right_margin + hdelay;
 306
 307         /*
 308          * Vertical timing looks a bit different in Figure 18,
 309          * but let's try the same first by setting offset = 0
 310          */
 311         vtotal = var->yres + var->upper_margin + var->lower_margin + var->vsync_len;
 312
 313         vdelay = var->vsync_len + var->upper_margin;
 314         vblank = var->lower_margin + vdelay;
 315         voffset = min(var->upper_margin / 2, 6U);
 316
 317         /*
 318          * [3]: VSYNC polarity: Positive
 319          * [2]: HSYNC polarity: Positive
 320          * [1]: Interlace/Progressive: Progressive
 321          * [0]: External video settings enable: used.
 322          */
 323         if (var->sync & FB_SYNC_HOR_HIGH_ACT)
 324                 sync |= 4;
 325         if (var->sync & FB_SYNC_VERT_HIGH_ACT)
 326                 sync |= 8;
 327
 328         dev_dbg(hdmi->dev, "H: %u, %u, %u, %u; V: %u, %u, %u, %u; sync 0x%x\n",
 329                 htotal, hblank, hdelay, var->hsync_len,
 330                 vtotal, vblank, vdelay, var->vsync_len, sync);
 331
 332         hdmi_write(hdmi, sync | (voffset << 4), HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS);
 333
 334         hdmi_write(hdmi, htotal, HDMI_EXTERNAL_H_TOTAL_7_0);
 335         hdmi_write(hdmi, htotal >> 8, HDMI_EXTERNAL_H_TOTAL_11_8);
 336
 337         hdmi_write(hdmi, hblank, HDMI_EXTERNAL_H_BLANK_7_0);
 338         hdmi_write(hdmi, hblank >> 8, HDMI_EXTERNAL_H_BLANK_9_8);
 339
 340         hdmi_write(hdmi, hdelay, HDMI_EXTERNAL_H_DELAY_7_0);
 341         hdmi_write(hdmi, hdelay >> 8, HDMI_EXTERNAL_H_DELAY_9_8);
 342
 343         hdmi_write(hdmi, var->hsync_len, HDMI_EXTERNAL_H_DURATION_7_0);
 344         hdmi_write(hdmi, var->hsync_len >> 8, HDMI_EXTERNAL_H_DURATION_9_8);
 345
 346         hdmi_write(hdmi, vtotal, HDMI_EXTERNAL_V_TOTAL_7_0);
 347         hdmi_write(hdmi, vtotal >> 8, HDMI_EXTERNAL_V_TOTAL_9_8);
 348
 349         hdmi_write(hdmi, vblank, HDMI_EXTERNAL_V_BLANK);
 350
 351         hdmi_write(hdmi, vdelay, HDMI_EXTERNAL_V_DELAY);
 352
 353         hdmi_write(hdmi, var->vsync_len, HDMI_EXTERNAL_V_DURATION);
 354
 355         /* Set bit 0 of HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS here for external mode */
 356         if (!hdmi->preprogrammed_vic)
 357                 hdmi_write(hdmi, sync | 1 | (voffset << 4),
 358                            HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS);
 359 }
 360
 361 /**
 362  * sh_hdmi_video_config()
 363  */
 364 static void sh_hdmi_video_config(struct sh_hdmi *hdmi)
 365 {
 366         /*
 367          * [7:4]: Audio sampling frequency: 48kHz
 368          * [3:1]: Input video format: RGB and YCbCr 4:4:4 (Y on Green)
 369          * [0]: Internal/External DE select: internal
 370          */
 371         hdmi_write(hdmi, 0x20, HDMI_AUDIO_VIDEO_SETTING_1);
 372
 373         /*
 374          * [7:6]: Video output format: RGB 4:4:4
 375          * [5:4]: Input video data width: 8 bit
 376          * [3:1]: EAV/SAV location: channel 1
 377          * [0]: Video input color space: RGB
 378          */
 379         hdmi_write(hdmi, 0x34, HDMI_VIDEO_SETTING_1);
 380
 381         /*
 382          * [7:6]: Together with bit [6] of HDMI_AUDIO_VIDEO_SETTING_2, which is
 383          * left at 0 by default, this configures 24bpp and sets the Color Depth
 384          * (CD) field in the General Control Packet
 385          */
 386         hdmi_write(hdmi, 0x20, HDMI_DEEP_COLOR_MODES);
 387 }
 388
 389 /**
 390  * sh_hdmi_audio_config()
 391  */
 392 static void sh_hdmi_audio_config(struct sh_hdmi *hdmi)
 393 {
 394         u8 data;
 395         struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
 396
 397         /*
 398          * [7:4] L/R data swap control
 399          * [3:0] appropriate N[19:16]
 400          */
 401         hdmi_write(hdmi, 0x00, HDMI_L_R_DATA_SWAP_CTRL_RPKT);
 402         /* appropriate N[15:8] */
 403         hdmi_write(hdmi, 0x18, HDMI_20_BIT_N_FOR_AUDIO_RPKT_15_8);
 404         /* appropriate N[7:0] */
 405         hdmi_write(hdmi, 0x00, HDMI_20_BIT_N_FOR_AUDIO_RPKT_7_0);
 406
 407         /* [7:4] 48 kHz SPDIF not used */
 408         hdmi_write(hdmi, 0x20, HDMI_SPDIF_AUDIO_SAMP_FREQ_CTS);
 409
 410         /*
 411          * [6:5] set required down sampling rate if required
 412          * [4:3] set required audio source
 413          */
 414         switch (pdata->flags & HDMI_SND_SRC_MASK) {
 415         default:
 416                 /* fall through */
 417         case HDMI_SND_SRC_I2S:
 418                 data = 0x0 << 3;
 419                 break;
 420         case HDMI_SND_SRC_SPDIF:
 421                 data = 0x1 << 3;
 422                 break;
 423         case HDMI_SND_SRC_DSD:
 424                 data = 0x2 << 3;
 425                 break;
 426         case HDMI_SND_SRC_HBR:
 427                 data = 0x3 << 3;
 428                 break;
 429         }
 430         hdmi_write(hdmi, data, HDMI_AUDIO_SETTING_1);
 431
 432         /* [3:0] set sending channel number for channel status */
 433         hdmi_write(hdmi, 0x40, HDMI_AUDIO_SETTING_2);
 434
 435         /*
 436          * [5:2] set valid I2S source input pin
 437          * [1:0] set input I2S source mode
 438          */
 439         hdmi_write(hdmi, 0x04, HDMI_I2S_AUDIO_SET);
 440
 441         /* [7:4] set valid DSD source input pin */
 442         hdmi_write(hdmi, 0x00, HDMI_DSD_AUDIO_SET);
 443
 444         /* [7:0] set appropriate I2S input pin swap settings if required */
 445         hdmi_write(hdmi, 0x00, HDMI_I2S_INPUT_PIN_SWAP);
 446
 447         /*
 448          * [7] set validity bit for channel status
 449          * [3:0] set original sample frequency for channel status
 450          */
 451         hdmi_write(hdmi, 0x00, HDMI_AUDIO_STATUS_BITS_SETTING_1);
 452
 453         /*
 454          * [7] set value for channel status
 455          * [6] set value for channel status
 456          * [5] set copyright bit for channel status
 457          * [4:2] set additional information for channel status
 458          * [1:0] set clock accuracy for channel status
 459          */
 460         hdmi_write(hdmi, 0x00, HDMI_AUDIO_STATUS_BITS_SETTING_2);
 461
 462         /* [7:0] set category code for channel status */
 463         hdmi_write(hdmi, 0x00, HDMI_CATEGORY_CODE);
 464
 465         /*
 466          * [7:4] set source number for channel status
 467          * [3:0] set word length for channel status
 468          */
 469         hdmi_write(hdmi, 0x00, HDMI_SOURCE_NUM_AUDIO_WORD_LEN);
 470
 471         /* [7:4] set sample frequency for channel status */
 472         hdmi_write(hdmi, 0x20, HDMI_AUDIO_VIDEO_SETTING_1);
 473 }
 474
 475 /**
 476  * sh_hdmi_phy_config() - configure the HDMI PHY for the used video mode
 477  */
 478 static void sh_hdmi_phy_config(struct sh_hdmi *hdmi)
 479 {
 480         if (hdmi->var.pixclock < 10000) {
 481                 /* for 1080p8bit 148MHz */
 482                 hdmi_write(hdmi, 0x1d, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
 483                 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
 484                 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
 485                 hdmi_write(hdmi, 0x4c, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
 486                 hdmi_write(hdmi, 0x1e, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
 487                 hdmi_write(hdmi, 0x48, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
 488                 hdmi_write(hdmi, 0x0e, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
 489                 hdmi_write(hdmi, 0x25, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
 490                 hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
 491         } else if (hdmi->var.pixclock < 30000) {
 492                 /* 720p, 8bit, 74.25MHz. Might need to be adjusted for other formats */
 493                 /*
 494                  * [1:0]        Speed_A
 495                  * [3:2]        Speed_B
 496                  * [4]          PLLA_Bypass
 497                  * [6]          DRV_TEST_EN
 498                  * [7]          DRV_TEST_IN
 499                  */
 500                 hdmi_write(hdmi, 0x0f, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
 501                 /* PLLB_CONFIG[17], PLLA_CONFIG[17] - not in PHY datasheet */
 502                 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
 503                 /*
 504                  * [2:0]        BGR_I_OFFSET
 505                  * [6:4]        BGR_V_OFFSET
 506                  */
 507                 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
 508                 /* PLLA_CONFIG[7:0]: VCO gain, VCO offset, LPF resistance[0] */
 509                 hdmi_write(hdmi, 0x44, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
 510                 /*
 511                  * PLLA_CONFIG[15:8]: regulator voltage[0], CP current,
 512                  * LPF capacitance, LPF resistance[1]
 513                  */
 514                 hdmi_write(hdmi, 0x32, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
 515                 /* PLLB_CONFIG[7:0]: LPF resistance[0], VCO offset, VCO gain */
 516                 hdmi_write(hdmi, 0x4A, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
 517                 /*
 518                  * PLLB_CONFIG[15:8]: regulator voltage[0], CP current,
 519                  * LPF capacitance, LPF resistance[1]
 520                  */
 521                 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
 522                 /* DRV_CONFIG, PE_CONFIG */
 523                 hdmi_write(hdmi, 0x25, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
 524                 /*
 525                  * [2:0]        AMON_SEL (4 == LPF voltage)
 526                  * [4]          PLLA_CONFIG[16]
 527                  * [5]          PLLB_CONFIG[16]
 528                  */
 529                 hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
 530         } else {
 531                 /* for 480p8bit 27MHz */
 532                 hdmi_write(hdmi, 0x19, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
 533                 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
 534                 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
 535                 hdmi_write(hdmi, 0x44, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
 536                 hdmi_write(hdmi, 0x32, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
 537                 hdmi_write(hdmi, 0x48, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
 538                 hdmi_write(hdmi, 0x0F, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
 539                 hdmi_write(hdmi, 0x20, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
 540                 hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
 541         }
 542 }
 543
 544 /**
 545  * sh_hdmi_avi_infoframe_setup() - Auxiliary Video Information InfoFrame CONTROL PACKET
 546  */
 547 static void sh_hdmi_avi_infoframe_setup(struct sh_hdmi *hdmi)
 548 {
 549         u8 vic;
 550
 551         /* AVI InfoFrame */
 552         hdmi_write(hdmi, 0x06, HDMI_CTRL_PKT_BUF_INDEX);
 553
 554         /* Packet Type = 0x82 */
 555         hdmi_write(hdmi, 0x82, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
 556
 557         /* Version = 0x02 */
 558         hdmi_write(hdmi, 0x02, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
 559
 560         /* Length = 13 (0x0D) */
 561         hdmi_write(hdmi, 0x0D, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
 562
 563         /* N. A. Checksum */
 564         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0);
 565
 566         /*
 567          * Y = RGB
 568          * A0 = No Data
 569          * B = Bar Data not valid
 570          * S = No Data
 571          */
 572         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB1);
 573
 574         /*
 575          * [7:6] C = Colorimetry: no data
 576          * [5:4] M = 2: 16:9, 1: 4:3 Picture Aspect Ratio
 577          * [3:0] R = 8: Active Frame Aspect Ratio: same as picture aspect ratio
 578          */
 579         hdmi_write(hdmi, 0x28, HDMI_CTRL_PKT_BUF_ACCESS_PB2);
 580
 581         /*
 582          * ITC = No Data
 583          * EC = xvYCC601
 584          * Q = Default (depends on video format)
 585          * SC = No Known non_uniform Scaling
 586          */
 587         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB3);
 588
 589         /*
 590          * VIC should be ignored if external config is used, so, we could just use 0,
 591          * but play safe and use a valid value in any case just in case
 592          */
 593         if (hdmi->preprogrammed_vic)
 594                 vic = hdmi->preprogrammed_vic;
 595         else
 596                 vic = 4;
 597         hdmi_write(hdmi, vic, HDMI_CTRL_PKT_BUF_ACCESS_PB4);
 598
 599         /* PR = No Repetition */
 600         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB5);
 601
 602         /* Line Number of End of Top Bar (lower 8 bits) */
 603         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB6);
 604
 605         /* Line Number of End of Top Bar (upper 8 bits) */
 606         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB7);
 607
 608         /* Line Number of Start of Bottom Bar (lower 8 bits) */
 609         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB8);
 610
 611         /* Line Number of Start of Bottom Bar (upper 8 bits) */
 612         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB9);
 613
 614         /* Pixel Number of End of Left Bar (lower 8 bits) */
 615         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB10);
 616
 617         /* Pixel Number of End of Left Bar (upper 8 bits) */
 618         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB11);
 619
 620         /* Pixel Number of Start of Right Bar (lower 8 bits) */
 621         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB12);
 622
 623         /* Pixel Number of Start of Right Bar (upper 8 bits) */
 624         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB13);
 625 }
 626
 627 /**
 628  * sh_hdmi_audio_infoframe_setup() - Audio InfoFrame of CONTROL PACKET
 629  */
 630 static void sh_hdmi_audio_infoframe_setup(struct sh_hdmi *hdmi)
 631 {
 632         /* Audio InfoFrame */
 633         hdmi_write(hdmi, 0x08, HDMI_CTRL_PKT_BUF_INDEX);
 634
 635         /* Packet Type = 0x84 */
 636         hdmi_write(hdmi, 0x84, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
 637
 638         /* Version Number = 0x01 */
 639         hdmi_write(hdmi, 0x01, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
 640
 641         /* 0 Length = 10 (0x0A) */
 642         hdmi_write(hdmi, 0x0A, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
 643
 644         /* n. a. Checksum */
 645         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0);
 646
 647         /* Audio Channel Count = Refer to Stream Header */
 648         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB1);
 649
 650         /* Refer to Stream Header */
 651         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB2);
 652
 653         /* Format depends on coding type (i.e. CT0...CT3) */
 654         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB3);
 655
 656         /* Speaker Channel Allocation = Front Right + Front Left */
 657         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB4);
 658
 659         /* Level Shift Value = 0 dB, Down - mix is permitted or no information */
 660         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB5);
 661
 662         /* Reserved (0) */
 663         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB6);
 664         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB7);
 665         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB8);
 666         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB9);
 667         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB10);
 668 }
 669
 670 /**
 671  * sh_hdmi_configure() - Initialise HDMI for output
 672  */
 673 static void sh_hdmi_configure(struct sh_hdmi *hdmi)
 674 {
 675         /* Configure video format */
 676         sh_hdmi_video_config(hdmi);
 677
 678         /* Configure audio format */
 679         sh_hdmi_audio_config(hdmi);
 680
 681         /* Configure PHY */
 682         sh_hdmi_phy_config(hdmi);
 683
 684         /* Auxiliary Video Information (AVI) InfoFrame */
 685         sh_hdmi_avi_infoframe_setup(hdmi);
 686
 687         /* Audio InfoFrame */
 688         sh_hdmi_audio_infoframe_setup(hdmi);
 689
 690         /*
 691          * Control packet auto send with VSYNC control: auto send
 692          * General control, Gamut metadata, ISRC, and ACP packets
 693          */
 694         hdmi_write(hdmi, 0x8E, HDMI_CTRL_PKT_AUTO_SEND);
 695
 696         /* FIXME */
 697         msleep(10);
 698
 699         /* PS mode b->d, reset PLLA and PLLB */
 700         hdmi_write(hdmi, 0x4C, HDMI_SYSTEM_CTRL);
 701
 702         udelay(10);
 703
 704         hdmi_write(hdmi, 0x40, HDMI_SYSTEM_CTRL);
 705 }
 706
 707 static unsigned long sh_hdmi_rate_error(struct sh_hdmi *hdmi,
 708                 const struct fb_videomode *mode,
 709                 unsigned long *hdmi_rate, unsigned long *parent_rate)
 710 {
 711         unsigned long target = PICOS2KHZ(mode->pixclock) * 1000, rate_error;
 712         struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
 713
 714         *hdmi_rate = clk_round_rate(hdmi->hdmi_clk, target);
 715         if ((long)*hdmi_rate < 0)
 716                 *hdmi_rate = clk_get_rate(hdmi->hdmi_clk);
 717
 718         rate_error = (long)*hdmi_rate > 0 ? abs(*hdmi_rate - target) : ULONG_MAX;
 719         if (rate_error && pdata->clk_optimize_parent)
 720                 rate_error = pdata->clk_optimize_parent(target, hdmi_rate, parent_rate);
 721         else if (clk_get_parent(hdmi->hdmi_clk))
 722                 *parent_rate = clk_get_rate(clk_get_parent(hdmi->hdmi_clk));
 723
 724         dev_dbg(hdmi->dev, "%u-%u-%u-%u x %u-%u-%u-%u\n",
 725                 mode->left_margin, mode->xres,
 726                 mode->right_margin, mode->hsync_len,
 727                 mode->upper_margin, mode->yres,
 728                 mode->lower_margin, mode->vsync_len);
 729
 730         dev_dbg(hdmi->dev, "\t@%lu(+/-%lu)Hz, e=%lu / 1000, r=%uHz, p=%luHz\n", target,
 731                 rate_error, rate_error ? 10000 / (10 * target / rate_error) : 0,
 732                 mode->refresh, *parent_rate);
 733
 734         return rate_error;
 735 }
 736
 737 static int sh_hdmi_read_edid(struct sh_hdmi *hdmi, unsigned long *hdmi_rate,
 738                              unsigned long *parent_rate)
 739 {
 740         struct fb_var_screeninfo tmpvar;
 741         struct fb_var_screeninfo *var = &tmpvar;
 742         const struct fb_videomode *mode, *found = NULL;
 743         struct fb_info *info = hdmi->info;
 744         struct fb_modelist *modelist = NULL;
 745         unsigned int f_width = 0, f_height = 0, f_refresh = 0;
 746         unsigned long found_rate_error = ULONG_MAX; /* silly compiler... */
 747         bool scanning = false, preferred_bad = false;
 748         u8 edid[128];
 749         char *forced;
 750         int i;
 751
 752         /* Read EDID */
 753         dev_dbg(hdmi->dev, "Read back EDID code:");
 754         for (i = 0; i < 128; i++) {
 755                 edid[i] = hdmi_read(hdmi, HDMI_EDID_KSV_FIFO_ACCESS_WINDOW);
 756 #ifdef DEBUG
 757                 if ((i % 16) == 0) {
 758                         printk(KERN_CONT "\n");
 759                         printk(KERN_DEBUG "%02X | %02X", i, edid[i]);
 760                 } else {
 761                         printk(KERN_CONT " %02X", edid[i]);
 762                 }
 763 #endif
 764         }
 765 #ifdef DEBUG
 766         printk(KERN_CONT "\n");
 767 #endif
 768
 769         if (!hdmi->edid_blocks) {
 770                 fb_edid_to_monspecs(edid, &hdmi->monspec);
 771                 hdmi->edid_blocks = edid[126] + 1;
 772
 773                 dev_dbg(hdmi->dev, "%d main modes, %d extension blocks\n",
 774                         hdmi->monspec.modedb_len, hdmi->edid_blocks - 1);
 775         } else {
 776                 dev_dbg(hdmi->dev, "Extension %u detected, DTD start %u\n",
 777                         edid[0], edid[2]);
 778                 fb_edid_add_monspecs(edid, &hdmi->monspec);
 779         }
 780
 781         if (hdmi->edid_blocks > hdmi->edid_segment_nr * 2 +
 782             (hdmi->edid_block_addr >> 7) + 1) {
 783                 /* More blocks to read */
 784                 if (hdmi->edid_block_addr) {
 785                         hdmi->edid_block_addr = 0;
 786                         hdmi->edid_segment_nr++;
 787                 } else {
 788                         hdmi->edid_block_addr = 0x80;
 789                 }
 790                 /* Set EDID word address  */
 791                 hdmi_write(hdmi, hdmi->edid_block_addr, HDMI_EDID_WORD_ADDRESS);
 792                 /* Enable EDID interrupt */
 793                 hdmi_write(hdmi, 0xC6, HDMI_INTERRUPT_MASK_1);
 794                 /* Set EDID segment pointer - starts reading EDID */
 795                 hdmi_write(hdmi, hdmi->edid_segment_nr, HDMI_EDID_SEGMENT_POINTER);
 796                 return -EAGAIN;
 797         }
 798
 799         /* All E-EDID blocks ready */
 800         dev_dbg(hdmi->dev, "%d main and extended modes\n", hdmi->monspec.modedb_len);
 801
 802         fb_get_options("sh_mobile_lcdc", &forced);
 803         if (forced && *forced) {
 804                 /* Only primitive parsing so far */
 805                 i = sscanf(forced, "%ux%u@%u",
 806                            &f_width, &f_height, &f_refresh);
 807                 if (i < 2) {
 808                         f_width = 0;
 809                         f_height = 0;
 810                 } else {
 811                         /* The user wants us to use the EDID data */
 812                         scanning = true;
 813                 }
 814                 dev_dbg(hdmi->dev, "Forced mode %ux%u@%uHz\n",
 815                         f_width, f_height, f_refresh);
 816         }
 817
 818         /* Walk monitor modes to find the best or the exact match */
 819         for (i = 0, mode = hdmi->monspec.modedb;
 820              i < hdmi->monspec.modedb_len && scanning;
 821              i++, mode++) {
 822                 unsigned long rate_error;
 823
 824                 if (!f_width && !f_height) {
 825                         /*
 826                          * A parameter string "video=sh_mobile_lcdc:0x0" means
 827                          * use the preferred EDID mode. If it is rejected by
 828                          * .fb_check_var(), keep looking, until an acceptable
 829                          * one is found.
 830                          */
 831                         if ((mode->flag & FB_MODE_IS_FIRST) || preferred_bad)
 832                                 scanning = false;
 833                         else
 834                                 continue;
 835                 } else if (f_width != mode->xres || f_height != mode->yres) {
 836                         /* No interest in unmatching modes */
 837                         continue;
 838                 }
 839
 840                 rate_error = sh_hdmi_rate_error(hdmi, mode, hdmi_rate, parent_rate);
 841
 842                 if (scanning) {
 843                         if (f_refresh == mode->refresh || (!f_refresh && !rate_error))
 844                                 /*
 845                                  * Exact match if either the refresh rate
 846                                  * matches or it hasn't been specified and we've
 847                                  * found a mode, for which we can configure the
 848                                  * clock precisely
 849                                  */
 850                                 scanning = false;
 851                         else if (found && found_rate_error <= rate_error)
 852                                 /*
 853                                  * We otherwise search for the closest matching
 854                                  * clock rate - either if no refresh rate has
 855                                  * been specified or we cannot find an exactly
 856                                  * matching one
 857                                  */
 858                                 continue;
 859                 }
 860
 861                 /* Check if supported: sufficient fb memory, supported clock-rate */
 862                 fb_videomode_to_var(var, mode);
 863
 864                 var->bits_per_pixel = info->var.bits_per_pixel;
 865
 866                 if (info && info->fbops->fb_check_var &&
 867                     info->fbops->fb_check_var(var, info)) {
 868                         scanning = true;
 869                         preferred_bad = true;
 870                         continue;
 871                 }
 872
 873                 found = mode;
 874                 found_rate_error = rate_error;
 875         }
 876
 877         hdmi->var.width = hdmi->monspec.max_x * 10;
 878         hdmi->var.height = hdmi->monspec.max_y * 10;
 879
 880         /*
 881          * TODO 1: if no ->info is present, postpone running the config until
 882          * after ->info first gets registered.
 883          * TODO 2: consider registering the HDMI platform device from the LCDC
 884          * driver, and passing ->info with HDMI platform data.
 885          */
 886         if (info && !found) {
 887                 modelist = info->modelist.next &&
 888                         !list_empty(&info->modelist) ?
 889                         list_entry(info->modelist.next,
 890                                    struct fb_modelist, list) :
 891                         NULL;
 892
 893                 if (modelist) {
 894                         found = &modelist->mode;
 895                         found_rate_error = sh_hdmi_rate_error(hdmi, found, hdmi_rate, parent_rate);
 896                 }
 897         }
 898
 899         /* No cookie today */
 900         if (!found)
 901                 return -ENXIO;
 902
 903         if (found->xres == 640 && found->yres == 480 && found->refresh == 60)
 904                 hdmi->preprogrammed_vic = 1;
 905         else if (found->xres == 720 && found->yres == 480 && found->refresh == 60)
 906                 hdmi->preprogrammed_vic = 2;
 907         else if (found->xres == 720 && found->yres == 576 && found->refresh == 50)
 908                 hdmi->preprogrammed_vic = 17;
 909         else if (found->xres == 1280 && found->yres == 720 && found->refresh == 60)
 910                 hdmi->preprogrammed_vic = 4;
 911         else if (found->xres == 1920 && found->yres == 1080 && found->refresh == 24)
 912                 hdmi->preprogrammed_vic = 32;
 913         else if (found->xres == 1920 && found->yres == 1080 && found->refresh == 50)
 914                 hdmi->preprogrammed_vic = 31;
 915         else if (found->xres == 1920 && found->yres == 1080 && found->refresh == 60)
 916                 hdmi->preprogrammed_vic = 16;
 917         else
 918                 hdmi->preprogrammed_vic = 0;
 919
 920         dev_dbg(hdmi->dev, "Using %s %s mode %ux%u@%uHz (%luHz), clock error %luHz\n",
 921                 modelist ? "default" : "EDID", hdmi->preprogrammed_vic ? "VIC" : "external",
 922                 found->xres, found->yres, found->refresh,
 923                 PICOS2KHZ(found->pixclock) * 1000, found_rate_error);
 924
 925         fb_videomode_to_var(&hdmi->var, found);
 926         sh_hdmi_external_video_param(hdmi);
 927
 928         return 0;
 929 }
 930
 931 static irqreturn_t sh_hdmi_hotplug(int irq, void *dev_id)
 932 {
 933         struct sh_hdmi *hdmi = dev_id;
 934         u8 status1, status2, mask1, mask2;
 935
 936         /* mode_b and PLLA and PLLB reset */
 937         hdmi_write(hdmi, 0x2C, HDMI_SYSTEM_CTRL);
 938
 939         /* How long shall reset be held? */
 940         udelay(10);
 941
 942         /* mode_b and PLLA and PLLB reset release */
 943         hdmi_write(hdmi, 0x20, HDMI_SYSTEM_CTRL);
 944
 945         status1 = hdmi_read(hdmi, HDMI_INTERRUPT_STATUS_1);
 946         status2 = hdmi_read(hdmi, HDMI_INTERRUPT_STATUS_2);
 947
 948         mask1 = hdmi_read(hdmi, HDMI_INTERRUPT_MASK_1);
 949         mask2 = hdmi_read(hdmi, HDMI_INTERRUPT_MASK_2);
 950
 951         /* Correct would be to ack only set bits, but the datasheet requires 0xff */
 952         hdmi_write(hdmi, 0xFF, HDMI_INTERRUPT_STATUS_1);
 953         hdmi_write(hdmi, 0xFF, HDMI_INTERRUPT_STATUS_2);
 954
 955         if (printk_ratelimit())
 956                 dev_dbg(hdmi->dev, "IRQ #%d: Status #1: 0x%x & 0x%x, #2: 0x%x & 0x%x\n",
 957                         irq, status1, mask1, status2, mask2);
 958
 959         if (!((status1 & mask1) | (status2 & mask2))) {
 960                 return IRQ_NONE;
 961         } else if (status1 & 0xc0) {
 962                 u8 msens;
 963
 964                 /* Datasheet specifies 10ms... */
 965                 udelay(500);
 966
 967                 msens = hdmi_read(hdmi, HDMI_HOT_PLUG_MSENS_STATUS);
 968                 dev_dbg(hdmi->dev, "MSENS 0x%x\n", msens);
 969                 /* Check, if hot plug & MSENS pin status are both high */
 970                 if ((msens & 0xC0) == 0xC0) {
 971                         /* Display plug in */
 972                         hdmi->edid_segment_nr = 0;
 973                         hdmi->edid_block_addr = 0;
 974                         hdmi->edid_blocks = 0;
 975                         hdmi->hp_state = HDMI_HOTPLUG_CONNECTED;
 976
 977                         /* Set EDID word address  */
 978                         hdmi_write(hdmi, 0x00, HDMI_EDID_WORD_ADDRESS);
 979                         /* Enable EDID interrupt */
 980                         hdmi_write(hdmi, 0xC6, HDMI_INTERRUPT_MASK_1);
 981                         /* Set EDID segment pointer - starts reading EDID */
 982                         hdmi_write(hdmi, 0x00, HDMI_EDID_SEGMENT_POINTER);
 983                 } else if (!(status1 & 0x80)) {
 984                         /* Display unplug, beware multiple interrupts */
 985                         if (hdmi->hp_state != HDMI_HOTPLUG_DISCONNECTED) {
 986                                 hdmi->hp_state = HDMI_HOTPLUG_DISCONNECTED;
 987                                 schedule_delayed_work(&hdmi->edid_work, 0);
 988                         }
 989                         /* display_off will switch back to mode_a */
 990                 }
 991         } else if (status1 & 2) {
 992                 /* EDID error interrupt: retry */
 993                 /* Set EDID word address  */
 994                 hdmi_write(hdmi, hdmi->edid_block_addr, HDMI_EDID_WORD_ADDRESS);
 995                 /* Set EDID segment pointer */
 996                 hdmi_write(hdmi, hdmi->edid_segment_nr, HDMI_EDID_SEGMENT_POINTER);
 997         } else if (status1 & 4) {
 998                 /* Disable EDID interrupt */
 999                 hdmi_write(hdmi, 0xC0, HDMI_INTERRUPT_MASK_1);
1000                 schedule_delayed_work(&hdmi->edid_work, msecs_to_jiffies(10));
1001         }
1002
1003         return IRQ_HANDLED;
1004 }
1005
1006 /* locking:     called with info->lock held, or before register_framebuffer() */
1007 static int sh_hdmi_display_on(struct sh_mobile_lcdc_entity *entity,
1008                               struct fb_info *info)
1009 {
1010         /*
1011          * info is guaranteed to be valid, when we are called, because our
1012          * FB_EVENT_FB_UNBIND notify is also called with info->lock held
1013          */
1014         struct sh_hdmi *hdmi = entity_to_sh_hdmi(entity);
1015         struct sh_mobile_lcdc_chan *ch = info->par;
1016
1017         dev_dbg(hdmi->dev, "%s(%p): state %x\n", __func__, hdmi, info->state);
1018
1019         /* No need to lock */
1020         hdmi->info = info;
1021
1022         /*
1023          * hp_state can be set to
1024          * HDMI_HOTPLUG_DISCONNECTED:   on monitor unplug
1025          * HDMI_HOTPLUG_CONNECTED:      on monitor plug-in
1026          * HDMI_HOTPLUG_EDID_DONE:      on EDID read completion
1027          */
1028         switch (hdmi->hp_state) {
1029         case HDMI_HOTPLUG_EDID_DONE:
1030                 /* PS mode d->e. All functions are active */
1031                 hdmi_write(hdmi, 0x80, HDMI_SYSTEM_CTRL);
1032                 dev_dbg(hdmi->dev, "HDMI running\n");
1033                 break;
1034         case HDMI_HOTPLUG_DISCONNECTED:
1035                 info->state = FBINFO_STATE_SUSPENDED;
1036         default:
1037                 hdmi->var = ch->display_var;
1038         }
1039
1040         return 0;
1041 }
1042
1043 /* locking: called with info->lock held */
1044 static void sh_hdmi_display_off(struct sh_mobile_lcdc_entity *entity)
1045 {
1046         struct sh_hdmi *hdmi = entity_to_sh_hdmi(entity);
1047
1048         dev_dbg(hdmi->dev, "%s(%p)\n", __func__, hdmi);
1049         /* PS mode e->a */
1050         hdmi_write(hdmi, 0x10, HDMI_SYSTEM_CTRL);
1051 }
1052
1053 static const struct sh_mobile_lcdc_entity_ops sh_hdmi_ops = {
1054         .display_on = sh_hdmi_display_on,
1055         .display_off = sh_hdmi_display_off,
1056 };
1057
1058 static bool sh_hdmi_must_reconfigure(struct sh_hdmi *hdmi)
1059 {
1060         struct fb_info *info = hdmi->info;
1061         struct sh_mobile_lcdc_chan *ch = info->par;
1062         struct fb_var_screeninfo *new_var = &hdmi->var, *old_var = &ch->display_var;
1063         struct fb_videomode mode1, mode2;
1064
1065         fb_var_to_videomode(&mode1, old_var);
1066         fb_var_to_videomode(&mode2, new_var);
1067
1068         dev_dbg(info->dev, "Old %ux%u, new %ux%u\n",
1069                 mode1.xres, mode1.yres, mode2.xres, mode2.yres);
1070
1071         if (fb_mode_is_equal(&mode1, &mode2)) {
1072                 /* It can be a different monitor with an equal video-mode */
1073                 old_var->width = new_var->width;
1074                 old_var->height = new_var->height;
1075                 return false;
1076         }
1077
1078         dev_dbg(info->dev, "Switching %u -> %u lines\n",
1079                 mode1.yres, mode2.yres);
1080         *old_var = *new_var;
1081
1082         return true;
1083 }
1084
1085 /**
1086  * sh_hdmi_clk_configure() - set HDMI clock frequency and enable the clock
1087  * @hdmi:               driver context
1088  * @hdmi_rate:          HDMI clock frequency in Hz
1089  * @parent_rate:        if != 0 - set parent clock rate for optimal precision
1090  * return:              configured positive rate if successful
1091  *                      0 if couldn't set the rate, but managed to enable the
1092  *                      clock, negative error, if couldn't enable the clock
1093  */
1094 static long sh_hdmi_clk_configure(struct sh_hdmi *hdmi, unsigned long hdmi_rate,
1095                                   unsigned long parent_rate)
1096 {
1097         int ret;
1098
1099         if (parent_rate && clk_get_parent(hdmi->hdmi_clk)) {
1100                 ret = clk_set_rate(clk_get_parent(hdmi->hdmi_clk), parent_rate);
1101                 if (ret < 0) {
1102                         dev_warn(hdmi->dev, "Cannot set parent rate %ld: %d\n", parent_rate, ret);
1103                         hdmi_rate = clk_round_rate(hdmi->hdmi_clk, hdmi_rate);
1104                 } else {
1105                         dev_dbg(hdmi->dev, "HDMI set parent frequency %lu\n", parent_rate);
1106                 }
1107         }
1108
1109         ret = clk_set_rate(hdmi->hdmi_clk, hdmi_rate);
1110         if (ret < 0) {
1111                 dev_warn(hdmi->dev, "Cannot set rate %ld: %d\n", hdmi_rate, ret);
1112                 hdmi_rate = 0;
1113         } else {
1114                 dev_dbg(hdmi->dev, "HDMI set frequency %lu\n", hdmi_rate);
1115         }
1116
1117         return hdmi_rate;
1118 }
1119
1120 /* Hotplug interrupt occurred, read EDID */
1121 static void sh_hdmi_edid_work_fn(struct work_struct *work)
1122 {
1123         struct sh_hdmi *hdmi = container_of(work, struct sh_hdmi, edid_work.work);
1124         struct fb_info *info;
1125         struct sh_mobile_lcdc_chan *ch;
1126         int ret;
1127
1128         dev_dbg(hdmi->dev, "%s(%p): begin, hotplug status %d\n", __func__, hdmi,
1129                 hdmi->hp_state);
1130
1131         mutex_lock(&hdmi->mutex);
1132
1133         info = hdmi->info;
1134
1135         if (hdmi->hp_state == HDMI_HOTPLUG_CONNECTED) {
1136                 unsigned long parent_rate = 0, hdmi_rate;
1137
1138                 ret = sh_hdmi_read_edid(hdmi, &hdmi_rate, &parent_rate);
1139                 if (ret < 0)
1140                         goto out;
1141
1142                 hdmi->hp_state = HDMI_HOTPLUG_EDID_DONE;
1143
1144                 /* Reconfigure the clock */
1145                 ret = sh_hdmi_clk_configure(hdmi, hdmi_rate, parent_rate);
1146                 if (ret < 0)
1147                         goto out;
1148
1149                 msleep(10);
1150                 sh_hdmi_configure(hdmi);
1151                 /* Switched to another (d) power-save mode */
1152                 msleep(10);
1153
1154                 if (!info)
1155                         goto out;
1156
1157                 ch = info->par;
1158
1159                 if (lock_fb_info(info)) {
1160                         console_lock();
1161
1162                         /* HDMI plug in */
1163                         if (!sh_hdmi_must_reconfigure(hdmi) &&
1164                             info->state == FBINFO_STATE_RUNNING) {
1165                                 /*
1166                                  * First activation with the default monitor - just turn
1167                                  * on, if we run a resume here, the logo disappears
1168                                  */
1169                                 info->var.width = hdmi->var.width;
1170                                 info->var.height = hdmi->var.height;
1171                                 sh_hdmi_display_on(&hdmi->entity, info);
1172                         } else {
1173                                 /* New monitor or have to wake up */
1174                                 fb_set_suspend(info, 0);
1175                         }
1176
1177                         console_unlock();
1178                         unlock_fb_info(info);
1179                 }
1180         } else {
1181                 ret = 0;
1182                 if (!info)
1183                         goto out;
1184
1185                 hdmi->monspec.modedb_len = 0;
1186                 fb_destroy_modedb(hdmi->monspec.modedb);
1187                 hdmi->monspec.modedb = NULL;
1188
1189                 if (lock_fb_info(info)) {
1190                         console_lock();
1191
1192                         /* HDMI disconnect */
1193                         fb_set_suspend(info, 1);
1194
1195                         console_unlock();
1196                         unlock_fb_info(info);
1197                 }
1198         }
1199
1200 out:
1201         if (ret < 0 && ret != -EAGAIN)
1202                 hdmi->hp_state = HDMI_HOTPLUG_DISCONNECTED;
1203         mutex_unlock(&hdmi->mutex);
1204
1205         dev_dbg(hdmi->dev, "%s(%p): end\n", __func__, hdmi);
1206 }
1207
1208 static int sh_hdmi_notify(struct notifier_block *nb,
1209                           unsigned long action, void *data)
1210 {
1211         struct fb_event *event = data;
1212         struct fb_info *info = event->info;
1213         struct sh_hdmi *hdmi = notifier_to_hdmi(nb);
1214
1215         if (hdmi->info != info)
1216                 return NOTIFY_DONE;
1217
1218         switch(action) {
1219         case FB_EVENT_FB_REGISTERED:
1220                 /* Unneeded, activation taken care by sh_hdmi_display_on() */
1221                 break;
1222         case FB_EVENT_FB_UNREGISTERED:
1223                 /*
1224                  * We are called from unregister_framebuffer() with the
1225                  * info->lock held. This is bad for us, because we can race with
1226                  * the scheduled work, which has to call fb_set_suspend(), which
1227                  * takes info->lock internally, so, sh_hdmi_edid_work_fn()
1228                  * cannot take and hold info->lock for the whole function
1229                  * duration. Using an additional lock creates a classical AB-BA
1230                  * lock up. Therefore, we have to release the info->lock
1231                  * temporarily, synchronise with the work queue and re-acquire
1232                  * the info->lock.
1233                  */
1234                 unlock_fb_info(info);
1235                 mutex_lock(&hdmi->mutex);
1236                 hdmi->info = NULL;
1237                 mutex_unlock(&hdmi->mutex);
1238                 lock_fb_info(info);
1239                 return NOTIFY_OK;
1240         }
1241         return NOTIFY_DONE;
1242 }
1243
1244 static int __init sh_hdmi_probe(struct platform_device *pdev)
1245 {
1246         struct sh_mobile_hdmi_info *pdata = pdev->dev.platform_data;
1247         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1248         int irq = platform_get_irq(pdev, 0), ret;
1249         struct sh_hdmi *hdmi;
1250         long rate;
1251
1252         if (!res || !pdata || irq < 0)
1253                 return -ENODEV;
1254
1255         hdmi = kzalloc(sizeof(*hdmi), GFP_KERNEL);
1256         if (!hdmi) {
1257                 dev_err(&pdev->dev, "Cannot allocate device data\n");
1258                 return -ENOMEM;
1259         }
1260
1261         mutex_init(&hdmi->mutex);
1262
1263         hdmi->dev = &pdev->dev;
1264         hdmi->entity.owner = THIS_MODULE;
1265         hdmi->entity.ops = &sh_hdmi_ops;
1266
1267         hdmi->hdmi_clk = clk_get(&pdev->dev, "ick");
1268         if (IS_ERR(hdmi->hdmi_clk)) {
1269                 ret = PTR_ERR(hdmi->hdmi_clk);
1270                 dev_err(&pdev->dev, "Unable to get clock: %d\n", ret);
1271                 goto egetclk;
1272         }
1273
1274         /* An arbitrary relaxed pixclock just to get things started: from standard 480p */
1275         rate = clk_round_rate(hdmi->hdmi_clk, PICOS2KHZ(37037));
1276         if (rate > 0)
1277                 rate = sh_hdmi_clk_configure(hdmi, rate, 0);
1278
1279         if (rate < 0) {
1280                 ret = rate;
1281                 goto erate;
1282         }
1283
1284         ret = clk_enable(hdmi->hdmi_clk);
1285         if (ret < 0) {
1286                 dev_err(hdmi->dev, "Cannot enable clock: %d\n", ret);
1287                 goto erate;
1288         }
1289
1290         dev_dbg(&pdev->dev, "Enabled HDMI clock at %luHz\n", rate);
1291
1292         if (!request_mem_region(res->start, resource_size(res), dev_name(&pdev->dev))) {
1293                 dev_err(&pdev->dev, "HDMI register region already claimed\n");
1294                 ret = -EBUSY;
1295                 goto ereqreg;
1296         }
1297
1298         hdmi->base = ioremap(res->start, resource_size(res));
1299         if (!hdmi->base) {
1300                 dev_err(&pdev->dev, "HDMI register region already claimed\n");
1301                 ret = -ENOMEM;
1302                 goto emap;
1303         }
1304
1305         platform_set_drvdata(pdev, &hdmi->entity);
1306
1307         INIT_DELAYED_WORK(&hdmi->edid_work, sh_hdmi_edid_work_fn);
1308
1309         pm_runtime_enable(&pdev->dev);
1310         pm_runtime_get_sync(&pdev->dev);
1311
1312         /* Product and revision IDs are 0 in sh-mobile version */
1313         dev_info(&pdev->dev, "Detected HDMI controller 0x%x:0x%x\n",
1314                  hdmi_read(hdmi, HDMI_PRODUCT_ID), hdmi_read(hdmi, HDMI_REVISION_ID));
1315
1316         ret = request_irq(irq, sh_hdmi_hotplug, 0,
1317                           dev_name(&pdev->dev), hdmi);
1318         if (ret < 0) {
1319                 dev_err(&pdev->dev, "Unable to request irq: %d\n", ret);
1320                 goto ereqirq;
1321         }
1322
1323         ret = snd_soc_register_codec(&pdev->dev,
1324                         &soc_codec_dev_sh_hdmi, &sh_hdmi_dai, 1);
1325         if (ret < 0) {
1326                 dev_err(&pdev->dev, "codec registration failed\n");
1327                 goto ecodec;
1328         }
1329
1330         hdmi->notifier.notifier_call = sh_hdmi_notify;
1331         fb_register_client(&hdmi->notifier);
1332
1333         return 0;
1334
1335 ecodec:
1336         free_irq(irq, hdmi);
1337 ereqirq:
1338         pm_runtime_put(&pdev->dev);
1339         pm_runtime_disable(&pdev->dev);
1340         iounmap(hdmi->base);
1341 emap:
1342         release_mem_region(res->start, resource_size(res));
1343 ereqreg:
1344         clk_disable(hdmi->hdmi_clk);
1345 erate:
1346         clk_put(hdmi->hdmi_clk);
1347 egetclk:
1348         mutex_destroy(&hdmi->mutex);
1349         kfree(hdmi);
1350
1351         return ret;
1352 }
1353
1354 static int __exit sh_hdmi_remove(struct platform_device *pdev)
1355 {
1356         struct sh_hdmi *hdmi = entity_to_sh_hdmi(platform_get_drvdata(pdev));
1357         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1358         int irq = platform_get_irq(pdev, 0);
1359
1360         snd_soc_unregister_codec(&pdev->dev);
1361
1362         fb_unregister_client(&hdmi->notifier);
1363
1364         /* No new work will be scheduled, wait for running ISR */
1365         free_irq(irq, hdmi);
1366         /* Wait for already scheduled work */
1367         cancel_delayed_work_sync(&hdmi->edid_work);
1368         pm_runtime_put(&pdev->dev);
1369         pm_runtime_disable(&pdev->dev);
1370         clk_disable(hdmi->hdmi_clk);
1371         clk_put(hdmi->hdmi_clk);
1372         iounmap(hdmi->base);
1373         release_mem_region(res->start, resource_size(res));
1374         mutex_destroy(&hdmi->mutex);
1375         kfree(hdmi);
1376
1377         return 0;
1378 }
1379
1380 static struct platform_driver sh_hdmi_driver = {
1381         .remove         = __exit_p(sh_hdmi_remove),
1382         .driver = {
1383                 .name   = "sh-mobile-hdmi",
1384         },
1385 };
1386
1387 static int __init sh_hdmi_init(void)
1388 {
1389         return platform_driver_probe(&sh_hdmi_driver, sh_hdmi_probe);
1390 }
1391 module_init(sh_hdmi_init);
1392
1393 static void __exit sh_hdmi_exit(void)
1394 {
1395         platform_driver_unregister(&sh_hdmi_driver);
1396 }
1397 module_exit(sh_hdmi_exit);
1398
1399 MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
1400 MODULE_DESCRIPTION("SuperH / ARM-shmobile HDMI driver");
1401 MODULE_LICENSE("GPL v2");