drivers/video/sh_mobile_lcdcfb.c

   1 /*
   2  * SuperH Mobile LCDC Framebuffer
   3  *
   4  * Copyright (c) 2008 Magnus Damm
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/delay.h>
  14 #include <linux/mm.h>
  15 #include <linux/fb.h>
  16 #include <linux/clk.h>
  17 #include <linux/pm_runtime.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/dma-mapping.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/vmalloc.h>
  22 #include <linux/ioctl.h>
  23 #include <linux/slab.h>
  24 #include <video/sh_mobile_lcdc.h>
  25 #include <asm/atomic.h>
  26
  27 #define PALETTE_NR 16
  28 #define SIDE_B_OFFSET 0x1000
  29 #define MIRROR_OFFSET 0x2000
  30
  31 /* shared registers */
  32 #define _LDDCKR 0x410
  33 #define _LDDCKSTPR 0x414
  34 #define _LDINTR 0x468
  35 #define _LDSR 0x46c
  36 #define _LDCNT1R 0x470
  37 #define _LDCNT2R 0x474
  38 #define _LDRCNTR 0x478
  39 #define _LDDDSR 0x47c
  40 #define _LDDWD0R 0x800
  41 #define _LDDRDR 0x840
  42 #define _LDDWAR 0x900
  43 #define _LDDRAR 0x904
  44
  45 /* shared registers and their order for context save/restore */
  46 static int lcdc_shared_regs[] = {
  47         _LDDCKR,
  48         _LDDCKSTPR,
  49         _LDINTR,
  50         _LDDDSR,
  51         _LDCNT1R,
  52         _LDCNT2R,
  53 };
  54 #define NR_SHARED_REGS ARRAY_SIZE(lcdc_shared_regs)
  55
  56 /* per-channel registers */
  57 enum { LDDCKPAT1R, LDDCKPAT2R, LDMT1R, LDMT2R, LDMT3R, LDDFR, LDSM1R,
  58        LDSM2R, LDSA1R, LDMLSR, LDHCNR, LDHSYNR, LDVLNR, LDVSYNR, LDPMR,
  59        LDHAJR,
  60        NR_CH_REGS };
  61
  62 static unsigned long lcdc_offs_mainlcd[NR_CH_REGS] = {
  63         [LDDCKPAT1R] = 0x400,
  64         [LDDCKPAT2R] = 0x404,
  65         [LDMT1R] = 0x418,
  66         [LDMT2R] = 0x41c,
  67         [LDMT3R] = 0x420,
  68         [LDDFR] = 0x424,
  69         [LDSM1R] = 0x428,
  70         [LDSM2R] = 0x42c,
  71         [LDSA1R] = 0x430,
  72         [LDMLSR] = 0x438,
  73         [LDHCNR] = 0x448,
  74         [LDHSYNR] = 0x44c,
  75         [LDVLNR] = 0x450,
  76         [LDVSYNR] = 0x454,
  77         [LDPMR] = 0x460,
  78         [LDHAJR] = 0x4a0,
  79 };
  80
  81 static unsigned long lcdc_offs_sublcd[NR_CH_REGS] = {
  82         [LDDCKPAT1R] = 0x408,
  83         [LDDCKPAT2R] = 0x40c,
  84         [LDMT1R] = 0x600,
  85         [LDMT2R] = 0x604,
  86         [LDMT3R] = 0x608,
  87         [LDDFR] = 0x60c,
  88         [LDSM1R] = 0x610,
  89         [LDSM2R] = 0x614,
  90         [LDSA1R] = 0x618,
  91         [LDMLSR] = 0x620,
  92         [LDHCNR] = 0x624,
  93         [LDHSYNR] = 0x628,
  94         [LDVLNR] = 0x62c,
  95         [LDVSYNR] = 0x630,
  96         [LDPMR] = 0x63c,
  97 };
  98
  99 #define START_LCDC      0x00000001
 100 #define LCDC_RESET      0x00000100
 101 #define DISPLAY_BEU     0x00000008
 102 #define LCDC_ENABLE     0x00000001
 103 #define LDINTR_FE       0x00000400
 104 #define LDINTR_VSE      0x00000200
 105 #define LDINTR_VEE      0x00000100
 106 #define LDINTR_FS       0x00000004
 107 #define LDINTR_VSS      0x00000002
 108 #define LDINTR_VES      0x00000001
 109 #define LDRCNTR_SRS     0x00020000
 110 #define LDRCNTR_SRC     0x00010000
 111 #define LDRCNTR_MRS     0x00000002
 112 #define LDRCNTR_MRC     0x00000001
 113 #define LDSR_MRS        0x00000100
 114
 115 struct sh_mobile_lcdc_priv;
 116 struct sh_mobile_lcdc_chan {
 117         struct sh_mobile_lcdc_priv *lcdc;
 118         unsigned long *reg_offs;
 119         unsigned long ldmt1r_value;
 120         unsigned long enabled; /* ME and SE in LDCNT2R */
 121         struct sh_mobile_lcdc_chan_cfg cfg;
 122         u32 pseudo_palette[PALETTE_NR];
 123         unsigned long saved_ch_regs[NR_CH_REGS];
 124         struct fb_info *info;
 125         dma_addr_t dma_handle;
 126         struct fb_deferred_io defio;
 127         struct scatterlist *sglist;
 128         unsigned long frame_end;
 129         unsigned long pan_offset;
 130         wait_queue_head_t frame_end_wait;
 131         struct completion vsync_completion;
 132 };
 133
 134 struct sh_mobile_lcdc_priv {
 135         void __iomem *base;
 136         int irq;
 137         atomic_t hw_usecnt;
 138         struct device *dev;
 139         struct clk *dot_clk;
 140         unsigned long lddckr;
 141         struct sh_mobile_lcdc_chan ch[2];
 142         struct notifier_block notifier;
 143         unsigned long saved_shared_regs[NR_SHARED_REGS];
 144         int started;
 145 };
 146
 147 static bool banked(int reg_nr)
 148 {
 149         switch (reg_nr) {
 150         case LDMT1R:
 151         case LDMT2R:
 152         case LDMT3R:
 153         case LDDFR:
 154         case LDSM1R:
 155         case LDSA1R:
 156         case LDMLSR:
 157         case LDHCNR:
 158         case LDHSYNR:
 159         case LDVLNR:
 160         case LDVSYNR:
 161                 return true;
 162         }
 163         return false;
 164 }
 165
 166 static void lcdc_write_chan(struct sh_mobile_lcdc_chan *chan,
 167                             int reg_nr, unsigned long data)
 168 {
 169         iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr]);
 170         if (banked(reg_nr))
 171                 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] +
 172                           SIDE_B_OFFSET);
 173 }
 174
 175 static void lcdc_write_chan_mirror(struct sh_mobile_lcdc_chan *chan,
 176                             int reg_nr, unsigned long data)
 177 {
 178         iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] +
 179                   MIRROR_OFFSET);
 180 }
 181
 182 static unsigned long lcdc_read_chan(struct sh_mobile_lcdc_chan *chan,
 183                                     int reg_nr)
 184 {
 185         return ioread32(chan->lcdc->base + chan->reg_offs[reg_nr]);
 186 }
 187
 188 static void lcdc_write(struct sh_mobile_lcdc_priv *priv,
 189                        unsigned long reg_offs, unsigned long data)
 190 {
 191         iowrite32(data, priv->base + reg_offs);
 192 }
 193
 194 static unsigned long lcdc_read(struct sh_mobile_lcdc_priv *priv,
 195                                unsigned long reg_offs)
 196 {
 197         return ioread32(priv->base + reg_offs);
 198 }
 199
 200 static void lcdc_wait_bit(struct sh_mobile_lcdc_priv *priv,
 201                           unsigned long reg_offs,
 202                           unsigned long mask, unsigned long until)
 203 {
 204         while ((lcdc_read(priv, reg_offs) & mask) != until)
 205                 cpu_relax();
 206 }
 207
 208 static int lcdc_chan_is_sublcd(struct sh_mobile_lcdc_chan *chan)
 209 {
 210         return chan->cfg.chan == LCDC_CHAN_SUBLCD;
 211 }
 212
 213 static void lcdc_sys_write_index(void *handle, unsigned long data)
 214 {
 215         struct sh_mobile_lcdc_chan *ch = handle;
 216
 217         lcdc_write(ch->lcdc, _LDDWD0R, data | 0x10000000);
 218         lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
 219         lcdc_write(ch->lcdc, _LDDWAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
 220         lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
 221 }
 222
 223 static void lcdc_sys_write_data(void *handle, unsigned long data)
 224 {
 225         struct sh_mobile_lcdc_chan *ch = handle;
 226
 227         lcdc_write(ch->lcdc, _LDDWD0R, data | 0x11000000);
 228         lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
 229         lcdc_write(ch->lcdc, _LDDWAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
 230         lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
 231 }
 232
 233 static unsigned long lcdc_sys_read_data(void *handle)
 234 {
 235         struct sh_mobile_lcdc_chan *ch = handle;
 236
 237         lcdc_write(ch->lcdc, _LDDRDR, 0x01000000);
 238         lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
 239         lcdc_write(ch->lcdc, _LDDRAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
 240         udelay(1);
 241         lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
 242
 243         return lcdc_read(ch->lcdc, _LDDRDR) & 0x3ffff;
 244 }
 245
 246 struct sh_mobile_lcdc_sys_bus_ops sh_mobile_lcdc_sys_bus_ops = {
 247         lcdc_sys_write_index,
 248         lcdc_sys_write_data,
 249         lcdc_sys_read_data,
 250 };
 251
 252 static void sh_mobile_lcdc_clk_on(struct sh_mobile_lcdc_priv *priv)
 253 {
 254         if (atomic_inc_and_test(&priv->hw_usecnt)) {
 255                 pm_runtime_get_sync(priv->dev);
 256                 if (priv->dot_clk)
 257                         clk_enable(priv->dot_clk);
 258         }
 259 }
 260
 261 static void sh_mobile_lcdc_clk_off(struct sh_mobile_lcdc_priv *priv)
 262 {
 263         if (atomic_sub_return(1, &priv->hw_usecnt) == -1) {
 264                 if (priv->dot_clk)
 265                         clk_disable(priv->dot_clk);
 266                 pm_runtime_put(priv->dev);
 267         }
 268 }
 269
 270 static int sh_mobile_lcdc_sginit(struct fb_info *info,
 271                                   struct list_head *pagelist)
 272 {
 273         struct sh_mobile_lcdc_chan *ch = info->par;
 274         unsigned int nr_pages_max = info->fix.smem_len >> PAGE_SHIFT;
 275         struct page *page;
 276         int nr_pages = 0;
 277
 278         sg_init_table(ch->sglist, nr_pages_max);
 279
 280         list_for_each_entry(page, pagelist, lru)
 281                 sg_set_page(&ch->sglist[nr_pages++], page, PAGE_SIZE, 0);
 282
 283         return nr_pages;
 284 }
 285
 286 static void sh_mobile_lcdc_deferred_io(struct fb_info *info,
 287                                        struct list_head *pagelist)
 288 {
 289         struct sh_mobile_lcdc_chan *ch = info->par;
 290         struct sh_mobile_lcdc_board_cfg *bcfg = &ch->cfg.board_cfg;
 291
 292         /* enable clocks before accessing hardware */
 293         sh_mobile_lcdc_clk_on(ch->lcdc);
 294
 295         /*
 296          * It's possible to get here without anything on the pagelist via
 297          * sh_mobile_lcdc_deferred_io_touch() or via a userspace fsync()
 298          * invocation. In the former case, the acceleration routines are
 299          * stepped in to when using the framebuffer console causing the
 300          * workqueue to be scheduled without any dirty pages on the list.
 301          *
 302          * Despite this, a panel update is still needed given that the
 303          * acceleration routines have their own methods for writing in
 304          * that still need to be updated.
 305          *
 306          * The fsync() and empty pagelist case could be optimized for,
 307          * but we don't bother, as any application exhibiting such
 308          * behaviour is fundamentally broken anyways.
 309          */
 310         if (!list_empty(pagelist)) {
 311                 unsigned int nr_pages = sh_mobile_lcdc_sginit(info, pagelist);
 312
 313                 /* trigger panel update */
 314                 dma_map_sg(info->dev, ch->sglist, nr_pages, DMA_TO_DEVICE);
 315                 if (bcfg->start_transfer)
 316                         bcfg->start_transfer(bcfg->board_data, ch,
 317                                              &sh_mobile_lcdc_sys_bus_ops);
 318                 lcdc_write_chan(ch, LDSM2R, 1);
 319                 dma_unmap_sg(info->dev, ch->sglist, nr_pages, DMA_TO_DEVICE);
 320         } else {
 321                 if (bcfg->start_transfer)
 322                         bcfg->start_transfer(bcfg->board_data, ch,
 323                                              &sh_mobile_lcdc_sys_bus_ops);
 324                 lcdc_write_chan(ch, LDSM2R, 1);
 325         }
 326 }
 327
 328 static void sh_mobile_lcdc_deferred_io_touch(struct fb_info *info)
 329 {
 330         struct fb_deferred_io *fbdefio = info->fbdefio;
 331
 332         if (fbdefio)
 333                 schedule_delayed_work(&info->deferred_work, fbdefio->delay);
 334 }
 335
 336 static irqreturn_t sh_mobile_lcdc_irq(int irq, void *data)
 337 {
 338         struct sh_mobile_lcdc_priv *priv = data;
 339         struct sh_mobile_lcdc_chan *ch;
 340         unsigned long tmp;
 341         unsigned long ldintr;
 342         int is_sub;
 343         int k;
 344
 345         /* acknowledge interrupt */
 346         ldintr = tmp = lcdc_read(priv, _LDINTR);
 347         /*
 348          * disable further VSYNC End IRQs, preserve all other enabled IRQs,
 349          * write 0 to bits 0-6 to ack all triggered IRQs.
 350          */
 351         tmp &= 0xffffff00 & ~LDINTR_VEE;
 352         lcdc_write(priv, _LDINTR, tmp);
 353
 354         /* figure out if this interrupt is for main or sub lcd */
 355         is_sub = (lcdc_read(priv, _LDSR) & (1 << 10)) ? 1 : 0;
 356
 357         /* wake up channel and disable clocks */
 358         for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
 359                 ch = &priv->ch[k];
 360
 361                 if (!ch->enabled)
 362                         continue;
 363
 364                 /* Frame Start */
 365                 if (ldintr & LDINTR_FS) {
 366                         if (is_sub == lcdc_chan_is_sublcd(ch)) {
 367                                 ch->frame_end = 1;
 368                                 wake_up(&ch->frame_end_wait);
 369
 370                                 sh_mobile_lcdc_clk_off(priv);
 371                         }
 372                 }
 373
 374                 /* VSYNC End */
 375                 if (ldintr & LDINTR_VES)
 376                         complete(&ch->vsync_completion);
 377         }
 378
 379         return IRQ_HANDLED;
 380 }
 381
 382 static void sh_mobile_lcdc_start_stop(struct sh_mobile_lcdc_priv *priv,
 383                                       int start)
 384 {
 385         unsigned long tmp = lcdc_read(priv, _LDCNT2R);
 386         int k;
 387
 388         /* start or stop the lcdc */
 389         if (start)
 390                 lcdc_write(priv, _LDCNT2R, tmp | START_LCDC);
 391         else
 392                 lcdc_write(priv, _LDCNT2R, tmp & ~START_LCDC);
 393
 394         /* wait until power is applied/stopped on all channels */
 395         for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
 396                 if (lcdc_read(priv, _LDCNT2R) & priv->ch[k].enabled)
 397                         while (1) {
 398                                 tmp = lcdc_read_chan(&priv->ch[k], LDPMR) & 3;
 399                                 if (start && tmp == 3)
 400                                         break;
 401                                 if (!start && tmp == 0)
 402                                         break;
 403                                 cpu_relax();
 404                         }
 405
 406         if (!start)
 407                 lcdc_write(priv, _LDDCKSTPR, 1); /* stop dotclock */
 408 }
 409
 410 static void sh_mobile_lcdc_geometry(struct sh_mobile_lcdc_chan *ch)
 411 {
 412         struct fb_var_screeninfo *var = &ch->info->var;
 413         unsigned long h_total, hsync_pos;
 414         u32 tmp;
 415
 416         tmp = ch->ldmt1r_value;
 417         tmp |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : 1 << 28;
 418         tmp |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : 1 << 27;
 419         tmp |= (ch->cfg.flags & LCDC_FLAGS_DWPOL) ? 1 << 26 : 0;
 420         tmp |= (ch->cfg.flags & LCDC_FLAGS_DIPOL) ? 1 << 25 : 0;
 421         tmp |= (ch->cfg.flags & LCDC_FLAGS_DAPOL) ? 1 << 24 : 0;
 422         tmp |= (ch->cfg.flags & LCDC_FLAGS_HSCNT) ? 1 << 17 : 0;
 423         tmp |= (ch->cfg.flags & LCDC_FLAGS_DWCNT) ? 1 << 16 : 0;
 424         lcdc_write_chan(ch, LDMT1R, tmp);
 425
 426         /* setup SYS bus */
 427         lcdc_write_chan(ch, LDMT2R, ch->cfg.sys_bus_cfg.ldmt2r);
 428         lcdc_write_chan(ch, LDMT3R, ch->cfg.sys_bus_cfg.ldmt3r);
 429
 430         /* horizontal configuration */
 431         h_total = var->xres + var->hsync_len +
 432                 var->left_margin + var->right_margin;
 433         tmp = h_total / 8; /* HTCN */
 434         tmp |= (var->xres / 8) << 16; /* HDCN */
 435         lcdc_write_chan(ch, LDHCNR, tmp);
 436
 437         hsync_pos = var->xres + var->right_margin;
 438         tmp = hsync_pos / 8; /* HSYNP */
 439         tmp |= (var->hsync_len / 8) << 16; /* HSYNW */
 440         lcdc_write_chan(ch, LDHSYNR, tmp);
 441
 442         /* vertical configuration */
 443         tmp = var->yres + var->vsync_len +
 444                 var->upper_margin + var->lower_margin; /* VTLN */
 445         tmp |= var->yres << 16; /* VDLN */
 446         lcdc_write_chan(ch, LDVLNR, tmp);
 447
 448         tmp = var->yres + var->lower_margin; /* VSYNP */
 449         tmp |= var->vsync_len << 16; /* VSYNW */
 450         lcdc_write_chan(ch, LDVSYNR, tmp);
 451
 452         /* Adjust horizontal synchronisation for HDMI */
 453         tmp = ((var->xres & 7) << 24) |
 454                 ((h_total & 7) << 16) |
 455                 ((var->hsync_len & 7) << 8) |
 456                 hsync_pos;
 457         lcdc_write_chan(ch, LDHAJR, tmp);
 458 }
 459
 460 static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
 461 {
 462         struct sh_mobile_lcdc_chan *ch;
 463         struct sh_mobile_lcdc_board_cfg *board_cfg;
 464         unsigned long tmp;
 465         int k, m;
 466         int ret = 0;
 467
 468         /* enable clocks before accessing the hardware */
 469         for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
 470                 if (priv->ch[k].enabled)
 471                         sh_mobile_lcdc_clk_on(priv);
 472
 473         /* reset */
 474         lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) | LCDC_RESET);
 475         lcdc_wait_bit(priv, _LDCNT2R, LCDC_RESET, 0);
 476
 477         /* enable LCDC channels */
 478         tmp = lcdc_read(priv, _LDCNT2R);
 479         tmp |= priv->ch[0].enabled;
 480         tmp |= priv->ch[1].enabled;
 481         lcdc_write(priv, _LDCNT2R, tmp);
 482
 483         /* read data from external memory, avoid using the BEU for now */
 484         lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) & ~DISPLAY_BEU);
 485
 486         /* stop the lcdc first */
 487         sh_mobile_lcdc_start_stop(priv, 0);
 488
 489         /* configure clocks */
 490         tmp = priv->lddckr;
 491         for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
 492                 ch = &priv->ch[k];
 493
 494                 if (!priv->ch[k].enabled)
 495                         continue;
 496
 497                 m = ch->cfg.clock_divider;
 498                 if (!m)
 499                         continue;
 500
 501                 if (m == 1)
 502                         m = 1 << 6;
 503                 tmp |= m << (lcdc_chan_is_sublcd(ch) ? 8 : 0);
 504
 505                 lcdc_write_chan(ch, LDDCKPAT1R, 0x00000000);
 506                 lcdc_write_chan(ch, LDDCKPAT2R, (1 << (m/2)) - 1);
 507         }
 508
 509         lcdc_write(priv, _LDDCKR, tmp);
 510
 511         /* start dotclock again */
 512         lcdc_write(priv, _LDDCKSTPR, 0);
 513         lcdc_wait_bit(priv, _LDDCKSTPR, ~0, 0);
 514
 515         /* interrupts are disabled to begin with */
 516         lcdc_write(priv, _LDINTR, 0);
 517
 518         for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
 519                 ch = &priv->ch[k];
 520
 521                 if (!ch->enabled)
 522                         continue;
 523
 524                 sh_mobile_lcdc_geometry(ch);
 525
 526                 /* power supply */
 527                 lcdc_write_chan(ch, LDPMR, 0);
 528
 529                 board_cfg = &ch->cfg.board_cfg;
 530                 if (board_cfg->setup_sys)
 531                         ret = board_cfg->setup_sys(board_cfg->board_data, ch,
 532                                                    &sh_mobile_lcdc_sys_bus_ops);
 533                 if (ret)
 534                         return ret;
 535         }
 536
 537         /* word and long word swap */
 538         lcdc_write(priv, _LDDDSR, lcdc_read(priv, _LDDDSR) | 6);
 539
 540         for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
 541                 ch = &priv->ch[k];
 542
 543                 if (!priv->ch[k].enabled)
 544                         continue;
 545
 546                 /* set bpp format in PKF[4:0] */
 547                 tmp = lcdc_read_chan(ch, LDDFR);
 548                 tmp &= ~(0x0001001f);
 549                 tmp |= (ch->info->var.bits_per_pixel == 16) ? 3 : 0;
 550                 lcdc_write_chan(ch, LDDFR, tmp);
 551
 552                 /* point out our frame buffer */
 553                 lcdc_write_chan(ch, LDSA1R, ch->info->fix.smem_start);
 554
 555                 /* set line size */
 556                 lcdc_write_chan(ch, LDMLSR, ch->info->fix.line_length);
 557
 558                 /* setup deferred io if SYS bus */
 559                 tmp = ch->cfg.sys_bus_cfg.deferred_io_msec;
 560                 if (ch->ldmt1r_value & (1 << 12) && tmp) {
 561                         ch->defio.deferred_io = sh_mobile_lcdc_deferred_io;
 562                         ch->defio.delay = msecs_to_jiffies(tmp);
 563                         ch->info->fbdefio = &ch->defio;
 564                         fb_deferred_io_init(ch->info);
 565
 566                         /* one-shot mode */
 567                         lcdc_write_chan(ch, LDSM1R, 1);
 568
 569                         /* enable "Frame End Interrupt Enable" bit */
 570                         lcdc_write(priv, _LDINTR, LDINTR_FE);
 571
 572                 } else {
 573                         /* continuous read mode */
 574                         lcdc_write_chan(ch, LDSM1R, 0);
 575                 }
 576         }
 577
 578         /* display output */
 579         lcdc_write(priv, _LDCNT1R, LCDC_ENABLE);
 580
 581         /* start the lcdc */
 582         sh_mobile_lcdc_start_stop(priv, 1);
 583         priv->started = 1;
 584
 585         /* tell the board code to enable the panel */
 586         for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
 587                 ch = &priv->ch[k];
 588                 if (!ch->enabled)
 589                         continue;
 590
 591                 board_cfg = &ch->cfg.board_cfg;
 592                 if (board_cfg->display_on)
 593                         board_cfg->display_on(board_cfg->board_data, ch->info);
 594         }
 595
 596         return 0;
 597 }
 598
 599 static void sh_mobile_lcdc_stop(struct sh_mobile_lcdc_priv *priv)
 600 {
 601         struct sh_mobile_lcdc_chan *ch;
 602         struct sh_mobile_lcdc_board_cfg *board_cfg;
 603         int k;
 604
 605         /* clean up deferred io and ask board code to disable panel */
 606         for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
 607                 ch = &priv->ch[k];
 608                 if (!ch->enabled)
 609                         continue;
 610
 611                 /* deferred io mode:
 612                  * flush frame, and wait for frame end interrupt
 613                  * clean up deferred io and enable clock
 614                  */
 615                 if (ch->info && ch->info->fbdefio) {
 616                         ch->frame_end = 0;
 617                         schedule_delayed_work(&ch->info->deferred_work, 0);
 618                         wait_event(ch->frame_end_wait, ch->frame_end);
 619                         fb_deferred_io_cleanup(ch->info);
 620                         ch->info->fbdefio = NULL;
 621                         sh_mobile_lcdc_clk_on(priv);
 622                 }
 623
 624                 board_cfg = &ch->cfg.board_cfg;
 625                 if (board_cfg->display_off)
 626                         board_cfg->display_off(board_cfg->board_data);
 627         }
 628
 629         /* stop the lcdc */
 630         if (priv->started) {
 631                 sh_mobile_lcdc_start_stop(priv, 0);
 632                 priv->started = 0;
 633         }
 634
 635         /* stop clocks */
 636         for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
 637                 if (priv->ch[k].enabled)
 638                         sh_mobile_lcdc_clk_off(priv);
 639 }
 640
 641 static int sh_mobile_lcdc_check_interface(struct sh_mobile_lcdc_chan *ch)
 642 {
 643         int ifm, miftyp;
 644
 645         switch (ch->cfg.interface_type) {
 646         case RGB8: ifm = 0; miftyp = 0; break;
 647         case RGB9: ifm = 0; miftyp = 4; break;
 648         case RGB12A: ifm = 0; miftyp = 5; break;
 649         case RGB12B: ifm = 0; miftyp = 6; break;
 650         case RGB16: ifm = 0; miftyp = 7; break;
 651         case RGB18: ifm = 0; miftyp = 10; break;
 652         case RGB24: ifm = 0; miftyp = 11; break;
 653         case SYS8A: ifm = 1; miftyp = 0; break;
 654         case SYS8B: ifm = 1; miftyp = 1; break;
 655         case SYS8C: ifm = 1; miftyp = 2; break;
 656         case SYS8D: ifm = 1; miftyp = 3; break;
 657         case SYS9: ifm = 1; miftyp = 4; break;
 658         case SYS12: ifm = 1; miftyp = 5; break;
 659         case SYS16A: ifm = 1; miftyp = 7; break;
 660         case SYS16B: ifm = 1; miftyp = 8; break;
 661         case SYS16C: ifm = 1; miftyp = 9; break;
 662         case SYS18: ifm = 1; miftyp = 10; break;
 663         case SYS24: ifm = 1; miftyp = 11; break;
 664         default: goto bad;
 665         }
 666
 667         /* SUBLCD only supports SYS interface */
 668         if (lcdc_chan_is_sublcd(ch)) {
 669                 if (ifm == 0)
 670                         goto bad;
 671                 else
 672                         ifm = 0;
 673         }
 674
 675         ch->ldmt1r_value = (ifm << 12) | miftyp;
 676         return 0;
 677  bad:
 678         return -EINVAL;
 679 }
 680
 681 static int sh_mobile_lcdc_setup_clocks(struct platform_device *pdev,
 682                                        int clock_source,
 683                                        struct sh_mobile_lcdc_priv *priv)
 684 {
 685         char *str;
 686         int icksel;
 687
 688         switch (clock_source) {
 689         case LCDC_CLK_BUS: str = "bus_clk"; icksel = 0; break;
 690         case LCDC_CLK_PERIPHERAL: str = "peripheral_clk"; icksel = 1; break;
 691         case LCDC_CLK_EXTERNAL: str = NULL; icksel = 2; break;
 692         default:
 693                 return -EINVAL;
 694         }
 695
 696         priv->lddckr = icksel << 16;
 697
 698         if (str) {
 699                 priv->dot_clk = clk_get(&pdev->dev, str);
 700                 if (IS_ERR(priv->dot_clk)) {
 701                         dev_err(&pdev->dev, "cannot get dot clock %s\n", str);
 702                         return PTR_ERR(priv->dot_clk);
 703                 }
 704         }
 705
 706         /* Runtime PM support involves two step for this driver:
 707          * 1) Enable Runtime PM
 708          * 2) Force Runtime PM Resume since hardware is accessed from probe()
 709          */
 710         priv->dev = &pdev->dev;
 711         pm_runtime_enable(priv->dev);
 712         pm_runtime_resume(priv->dev);
 713         return 0;
 714 }
 715
 716 static int sh_mobile_lcdc_setcolreg(u_int regno,
 717                                     u_int red, u_int green, u_int blue,
 718                                     u_int transp, struct fb_info *info)
 719 {
 720         u32 *palette = info->pseudo_palette;
 721
 722         if (regno >= PALETTE_NR)
 723                 return -EINVAL;
 724
 725         /* only FB_VISUAL_TRUECOLOR supported */
 726
 727         red >>= 16 - info->var.red.length;
 728         green >>= 16 - info->var.green.length;
 729         blue >>= 16 - info->var.blue.length;
 730         transp >>= 16 - info->var.transp.length;
 731
 732         palette[regno] = (red << info->var.red.offset) |
 733           (green << info->var.green.offset) |
 734           (blue << info->var.blue.offset) |
 735           (transp << info->var.transp.offset);
 736
 737         return 0;
 738 }
 739
 740 static struct fb_fix_screeninfo sh_mobile_lcdc_fix  = {
 741         .id =           "SH Mobile LCDC",
 742         .type =         FB_TYPE_PACKED_PIXELS,
 743         .visual =       FB_VISUAL_TRUECOLOR,
 744         .accel =        FB_ACCEL_NONE,
 745         .xpanstep =     0,
 746         .ypanstep =     1,
 747         .ywrapstep =    0,
 748 };
 749
 750 static void sh_mobile_lcdc_fillrect(struct fb_info *info,
 751                                     const struct fb_fillrect *rect)
 752 {
 753         sys_fillrect(info, rect);
 754         sh_mobile_lcdc_deferred_io_touch(info);
 755 }
 756
 757 static void sh_mobile_lcdc_copyarea(struct fb_info *info,
 758                                     const struct fb_copyarea *area)
 759 {
 760         sys_copyarea(info, area);
 761         sh_mobile_lcdc_deferred_io_touch(info);
 762 }
 763
 764 static void sh_mobile_lcdc_imageblit(struct fb_info *info,
 765                                      const struct fb_image *image)
 766 {
 767         sys_imageblit(info, image);
 768         sh_mobile_lcdc_deferred_io_touch(info);
 769 }
 770
 771 static int sh_mobile_fb_pan_display(struct fb_var_screeninfo *var,
 772                                      struct fb_info *info)
 773 {
 774         struct sh_mobile_lcdc_chan *ch = info->par;
 775         struct sh_mobile_lcdc_priv *priv = ch->lcdc;
 776         unsigned long ldrcntr;
 777         unsigned long new_pan_offset;
 778
 779         new_pan_offset = (var->yoffset * info->fix.line_length) +
 780                 (var->xoffset * (info->var.bits_per_pixel / 8));
 781
 782         if (new_pan_offset == ch->pan_offset)
 783                 return 0;       /* No change, do nothing */
 784
 785         ldrcntr = lcdc_read(priv, _LDRCNTR);
 786
 787         /* Set the source address for the next refresh */
 788         lcdc_write_chan_mirror(ch, LDSA1R, ch->dma_handle + new_pan_offset);
 789         if (lcdc_chan_is_sublcd(ch))
 790                 lcdc_write(ch->lcdc, _LDRCNTR, ldrcntr ^ LDRCNTR_SRS);
 791         else
 792                 lcdc_write(ch->lcdc, _LDRCNTR, ldrcntr ^ LDRCNTR_MRS);
 793
 794         ch->pan_offset = new_pan_offset;
 795
 796         sh_mobile_lcdc_deferred_io_touch(info);
 797
 798         return 0;
 799 }
 800
 801 static int sh_mobile_wait_for_vsync(struct fb_info *info)
 802 {
 803         struct sh_mobile_lcdc_chan *ch = info->par;
 804         unsigned long ldintr;
 805         int ret;
 806
 807         /* Enable VSync End interrupt */
 808         ldintr = lcdc_read(ch->lcdc, _LDINTR);
 809         ldintr |= LDINTR_VEE;
 810         lcdc_write(ch->lcdc, _LDINTR, ldintr);
 811
 812         ret = wait_for_completion_interruptible_timeout(&ch->vsync_completion,
 813                                                         msecs_to_jiffies(100));
 814         if (!ret)
 815                 return -ETIMEDOUT;
 816
 817         return 0;
 818 }
 819
 820 static int sh_mobile_ioctl(struct fb_info *info, unsigned int cmd,
 821                        unsigned long arg)
 822 {
 823         int retval;
 824
 825         switch (cmd) {
 826         case FBIO_WAITFORVSYNC:
 827                 retval = sh_mobile_wait_for_vsync(info);
 828                 break;
 829
 830         default:
 831                 retval = -ENOIOCTLCMD;
 832                 break;
 833         }
 834         return retval;
 835 }
 836
 837 static struct fb_ops sh_mobile_lcdc_ops = {
 838         .owner          = THIS_MODULE,
 839         .fb_setcolreg   = sh_mobile_lcdc_setcolreg,
 840         .fb_read        = fb_sys_read,
 841         .fb_write       = fb_sys_write,
 842         .fb_fillrect    = sh_mobile_lcdc_fillrect,
 843         .fb_copyarea    = sh_mobile_lcdc_copyarea,
 844         .fb_imageblit   = sh_mobile_lcdc_imageblit,
 845         .fb_pan_display = sh_mobile_fb_pan_display,
 846         .fb_ioctl       = sh_mobile_ioctl,
 847 };
 848
 849 static int sh_mobile_lcdc_set_bpp(struct fb_var_screeninfo *var, int bpp)
 850 {
 851         switch (bpp) {
 852         case 16: /* PKF[4:0] = 00011 - RGB 565 */
 853                 var->red.offset = 11;
 854                 var->red.length = 5;
 855                 var->green.offset = 5;
 856                 var->green.length = 6;
 857                 var->blue.offset = 0;
 858                 var->blue.length = 5;
 859                 var->transp.offset = 0;
 860                 var->transp.length = 0;
 861                 break;
 862
 863         case 32: /* PKF[4:0] = 00000 - RGB 888
 864                   * sh7722 pdf says 00RRGGBB but reality is GGBB00RR
 865                   * this may be because LDDDSR has word swap enabled..
 866                   */
 867                 var->red.offset = 0;
 868                 var->red.length = 8;
 869                 var->green.offset = 24;
 870                 var->green.length = 8;
 871                 var->blue.offset = 16;
 872                 var->blue.length = 8;
 873                 var->transp.offset = 0;
 874                 var->transp.length = 0;
 875                 break;
 876         default:
 877                 return -EINVAL;
 878         }
 879         var->bits_per_pixel = bpp;
 880         var->red.msb_right = 0;
 881         var->green.msb_right = 0;
 882         var->blue.msb_right = 0;
 883         var->transp.msb_right = 0;
 884         return 0;
 885 }
 886
 887 static int sh_mobile_lcdc_suspend(struct device *dev)
 888 {
 889         struct platform_device *pdev = to_platform_device(dev);
 890
 891         sh_mobile_lcdc_stop(platform_get_drvdata(pdev));
 892         return 0;
 893 }
 894
 895 static int sh_mobile_lcdc_resume(struct device *dev)
 896 {
 897         struct platform_device *pdev = to_platform_device(dev);
 898
 899         return sh_mobile_lcdc_start(platform_get_drvdata(pdev));
 900 }
 901
 902 static int sh_mobile_lcdc_runtime_suspend(struct device *dev)
 903 {
 904         struct platform_device *pdev = to_platform_device(dev);
 905         struct sh_mobile_lcdc_priv *p = platform_get_drvdata(pdev);
 906         struct sh_mobile_lcdc_chan *ch;
 907         int k, n;
 908
 909         /* save per-channel registers */
 910         for (k = 0; k < ARRAY_SIZE(p->ch); k++) {
 911                 ch = &p->ch[k];
 912                 if (!ch->enabled)
 913                         continue;
 914                 for (n = 0; n < NR_CH_REGS; n++)
 915                         ch->saved_ch_regs[n] = lcdc_read_chan(ch, n);
 916         }
 917
 918         /* save shared registers */
 919         for (n = 0; n < NR_SHARED_REGS; n++)
 920                 p->saved_shared_regs[n] = lcdc_read(p, lcdc_shared_regs[n]);
 921
 922         /* turn off LCDC hardware */
 923         lcdc_write(p, _LDCNT1R, 0);
 924         return 0;
 925 }
 926
 927 static int sh_mobile_lcdc_runtime_resume(struct device *dev)
 928 {
 929         struct platform_device *pdev = to_platform_device(dev);
 930         struct sh_mobile_lcdc_priv *p = platform_get_drvdata(pdev);
 931         struct sh_mobile_lcdc_chan *ch;
 932         int k, n;
 933
 934         /* restore per-channel registers */
 935         for (k = 0; k < ARRAY_SIZE(p->ch); k++) {
 936                 ch = &p->ch[k];
 937                 if (!ch->enabled)
 938                         continue;
 939                 for (n = 0; n < NR_CH_REGS; n++)
 940                         lcdc_write_chan(ch, n, ch->saved_ch_regs[n]);
 941         }
 942
 943         /* restore shared registers */
 944         for (n = 0; n < NR_SHARED_REGS; n++)
 945                 lcdc_write(p, lcdc_shared_regs[n], p->saved_shared_regs[n]);
 946
 947         return 0;
 948 }
 949
 950 static const struct dev_pm_ops sh_mobile_lcdc_dev_pm_ops = {
 951         .suspend = sh_mobile_lcdc_suspend,
 952         .resume = sh_mobile_lcdc_resume,
 953         .runtime_suspend = sh_mobile_lcdc_runtime_suspend,
 954         .runtime_resume = sh_mobile_lcdc_runtime_resume,
 955 };
 956
 957 static int sh_mobile_lcdc_notify(struct notifier_block *nb,
 958                                  unsigned long action, void *data)
 959 {
 960         struct fb_event *event = data;
 961         struct fb_info *info = event->info;
 962         struct sh_mobile_lcdc_chan *ch = info->par;
 963         struct sh_mobile_lcdc_board_cfg *board_cfg = &ch->cfg.board_cfg;
 964         struct fb_var_screeninfo *var;
 965
 966         if (&ch->lcdc->notifier != nb)
 967                 return 0;
 968
 969         dev_dbg(info->dev, "%s(): action = %lu, data = %p\n",
 970                 __func__, action, event->data);
 971
 972         switch(action) {
 973         case FB_EVENT_SUSPEND:
 974                 if (board_cfg->display_off)
 975                         board_cfg->display_off(board_cfg->board_data);
 976                 pm_runtime_put(info->device);
 977                 break;
 978         case FB_EVENT_RESUME:
 979                 var = &info->var;
 980
 981                 /* HDMI must be enabled before LCDC configuration */
 982                 if (board_cfg->display_on)
 983                         board_cfg->display_on(board_cfg->board_data, ch->info);
 984
 985                 /* Check if the new display is not in our modelist */
 986                 if (ch->info->modelist.next &&
 987                     !fb_match_mode(var, &ch->info->modelist)) {
 988                         struct fb_videomode mode;
 989                         int ret;
 990
 991                         /* Can we handle this display? */
 992                         if (var->xres > ch->cfg.lcd_cfg.xres ||
 993                             var->yres > ch->cfg.lcd_cfg.yres)
 994                                 return -ENOMEM;
 995
 996                         /* Add to the modelist */
 997                         fb_var_to_videomode(&mode, var);
 998                         ret = fb_add_videomode(&mode, &ch->info->modelist);
 999                         if (ret < 0)
1000                                 return ret;
1001                 }
1002
1003                 pm_runtime_get_sync(info->device);
1004
1005                 sh_mobile_lcdc_geometry(ch);
1006
1007                 break;
1008         }
1009
1010         return 0;
1011 }
1012
1013 static int sh_mobile_lcdc_remove(struct platform_device *pdev);
1014
1015 static int __devinit sh_mobile_lcdc_probe(struct platform_device *pdev)
1016 {
1017         struct fb_info *info;
1018         struct sh_mobile_lcdc_priv *priv;
1019         struct sh_mobile_lcdc_info *pdata = pdev->dev.platform_data;
1020         struct sh_mobile_lcdc_chan_cfg *cfg;
1021         struct resource *res;
1022         int error;
1023         void *buf;
1024         int i, j;
1025
1026         if (!pdata) {
1027                 dev_err(&pdev->dev, "no platform data defined\n");
1028                 return -EINVAL;
1029         }
1030
1031         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1032         i = platform_get_irq(pdev, 0);
1033         if (!res || i < 0) {
1034                 dev_err(&pdev->dev, "cannot get platform resources\n");
1035                 return -ENOENT;
1036         }
1037
1038         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1039         if (!priv) {
1040                 dev_err(&pdev->dev, "cannot allocate device data\n");
1041                 return -ENOMEM;
1042         }
1043
1044         platform_set_drvdata(pdev, priv);
1045
1046         error = request_irq(i, sh_mobile_lcdc_irq, IRQF_DISABLED,
1047                             dev_name(&pdev->dev), priv);
1048         if (error) {
1049                 dev_err(&pdev->dev, "unable to request irq\n");
1050                 goto err1;
1051         }
1052
1053         priv->irq = i;
1054         atomic_set(&priv->hw_usecnt, -1);
1055
1056         j = 0;
1057         for (i = 0; i < ARRAY_SIZE(pdata->ch); i++) {
1058                 struct sh_mobile_lcdc_chan *ch = priv->ch + j;
1059
1060                 ch->lcdc = priv;
1061                 memcpy(&ch->cfg, &pdata->ch[i], sizeof(pdata->ch[i]));
1062
1063                 error = sh_mobile_lcdc_check_interface(ch);
1064                 if (error) {
1065                         dev_err(&pdev->dev, "unsupported interface type\n");
1066                         goto err1;
1067                 }
1068                 init_waitqueue_head(&ch->frame_end_wait);
1069                 init_completion(&ch->vsync_completion);
1070                 ch->pan_offset = 0;
1071
1072                 switch (pdata->ch[i].chan) {
1073                 case LCDC_CHAN_MAINLCD:
1074                         ch->enabled = 1 << 1;
1075                         ch->reg_offs = lcdc_offs_mainlcd;
1076                         j++;
1077                         break;
1078                 case LCDC_CHAN_SUBLCD:
1079                         ch->enabled = 1 << 2;
1080                         ch->reg_offs = lcdc_offs_sublcd;
1081                         j++;
1082                         break;
1083                 }
1084         }
1085
1086         if (!j) {
1087                 dev_err(&pdev->dev, "no channels defined\n");
1088                 error = -EINVAL;
1089                 goto err1;
1090         }
1091
1092         priv->base = ioremap_nocache(res->start, resource_size(res));
1093         if (!priv->base)
1094                 goto err1;
1095
1096         error = sh_mobile_lcdc_setup_clocks(pdev, pdata->clock_source, priv);
1097         if (error) {
1098                 dev_err(&pdev->dev, "unable to setup clocks\n");
1099                 goto err1;
1100         }
1101
1102         for (i = 0; i < j; i++) {
1103                 struct fb_var_screeninfo *var;
1104                 const struct fb_videomode *lcd_cfg;
1105                 struct sh_mobile_lcdc_chan *ch = priv->ch + i;
1106
1107                 cfg = &ch->cfg;
1108
1109                 ch->info = framebuffer_alloc(0, &pdev->dev);
1110                 if (!ch->info) {
1111                         dev_err(&pdev->dev, "unable to allocate fb_info\n");
1112                         error = -ENOMEM;
1113                         break;
1114                 }
1115
1116                 info = ch->info;
1117                 var = &info->var;
1118                 lcd_cfg = &cfg->lcd_cfg;
1119                 info->fbops = &sh_mobile_lcdc_ops;
1120                 fb_videomode_to_var(var, lcd_cfg);
1121                 /* Default Y virtual resolution is 2x panel size */
1122                 var->yres_virtual = var->yres * 2;
1123
1124                 error = sh_mobile_lcdc_set_bpp(var, cfg->bpp);
1125                 if (error)
1126                         break;
1127
1128                 info->fix = sh_mobile_lcdc_fix;
1129                 info->fix.line_length = lcd_cfg->xres * (cfg->bpp / 8);
1130                 info->fix.smem_len = info->fix.line_length *
1131                         var->yres_virtual;
1132
1133                 buf = dma_alloc_coherent(&pdev->dev, info->fix.smem_len,
1134                                          &ch->dma_handle, GFP_KERNEL);
1135                 if (!buf) {
1136                         dev_err(&pdev->dev, "unable to allocate buffer\n");
1137                         error = -ENOMEM;
1138                         break;
1139                 }
1140
1141                 info->pseudo_palette = &ch->pseudo_palette;
1142                 info->flags = FBINFO_FLAG_DEFAULT;
1143
1144                 error = fb_alloc_cmap(&info->cmap, PALETTE_NR, 0);
1145                 if (error < 0) {
1146                         dev_err(&pdev->dev, "unable to allocate cmap\n");
1147                         dma_free_coherent(&pdev->dev, info->fix.smem_len,
1148                                           buf, ch->dma_handle);
1149                         break;
1150                 }
1151
1152                 info->fix.smem_start = ch->dma_handle;
1153                 info->screen_base = buf;
1154                 info->device = &pdev->dev;
1155                 info->par = ch;
1156         }
1157
1158         if (error)
1159                 goto err1;
1160
1161         error = sh_mobile_lcdc_start(priv);
1162         if (error) {
1163                 dev_err(&pdev->dev, "unable to start hardware\n");
1164                 goto err1;
1165         }
1166
1167         for (i = 0; i < j; i++) {
1168                 struct sh_mobile_lcdc_chan *ch = priv->ch + i;
1169
1170                 info = ch->info;
1171
1172                 if (info->fbdefio) {
1173                         ch->sglist = vmalloc(sizeof(struct scatterlist) *
1174                                         info->fix.smem_len >> PAGE_SHIFT);
1175                         if (!ch->sglist) {
1176                                 dev_err(&pdev->dev, "cannot allocate sglist\n");
1177                                 goto err1;
1178                         }
1179                 }
1180
1181                 error = register_framebuffer(info);
1182                 if (error < 0)
1183                         goto err1;
1184
1185                 dev_info(info->dev,
1186                          "registered %s/%s as %dx%d %dbpp.\n",
1187                          pdev->name,
1188                          (ch->cfg.chan == LCDC_CHAN_MAINLCD) ?
1189                          "mainlcd" : "sublcd",
1190                          (int) ch->cfg.lcd_cfg.xres,
1191                          (int) ch->cfg.lcd_cfg.yres,
1192                          ch->cfg.bpp);
1193
1194                 /* deferred io mode: disable clock to save power */
1195                 if (info->fbdefio || info->state == FBINFO_STATE_SUSPENDED)
1196                         sh_mobile_lcdc_clk_off(priv);
1197         }
1198
1199         /* Failure ignored */
1200         priv->notifier.notifier_call = sh_mobile_lcdc_notify;
1201         fb_register_client(&priv->notifier);
1202
1203         return 0;
1204 err1:
1205         sh_mobile_lcdc_remove(pdev);
1206
1207         return error;
1208 }
1209
1210 static int sh_mobile_lcdc_remove(struct platform_device *pdev)
1211 {
1212         struct sh_mobile_lcdc_priv *priv = platform_get_drvdata(pdev);
1213         struct fb_info *info;
1214         int i;
1215
1216         fb_unregister_client(&priv->notifier);
1217
1218         for (i = 0; i < ARRAY_SIZE(priv->ch); i++)
1219                 if (priv->ch[i].info && priv->ch[i].info->dev)
1220                         unregister_framebuffer(priv->ch[i].info);
1221
1222         sh_mobile_lcdc_stop(priv);
1223
1224         for (i = 0; i < ARRAY_SIZE(priv->ch); i++) {
1225                 info = priv->ch[i].info;
1226
1227                 if (!info || !info->device)
1228                         continue;
1229
1230                 if (priv->ch[i].sglist)
1231                         vfree(priv->ch[i].sglist);
1232
1233                 dma_free_coherent(&pdev->dev, info->fix.smem_len,
1234                                   info->screen_base, priv->ch[i].dma_handle);
1235                 fb_dealloc_cmap(&info->cmap);
1236                 framebuffer_release(info);
1237         }
1238
1239         if (priv->dot_clk)
1240                 clk_put(priv->dot_clk);
1241
1242         if (priv->dev)
1243                 pm_runtime_disable(priv->dev);
1244
1245         if (priv->base)
1246                 iounmap(priv->base);
1247
1248         if (priv->irq)
1249                 free_irq(priv->irq, priv);
1250         kfree(priv);
1251         return 0;
1252 }
1253
1254 static struct platform_driver sh_mobile_lcdc_driver = {
1255         .driver         = {
1256                 .name           = "sh_mobile_lcdc_fb",
1257                 .owner          = THIS_MODULE,
1258                 .pm             = &sh_mobile_lcdc_dev_pm_ops,
1259         },
1260         .probe          = sh_mobile_lcdc_probe,
1261         .remove         = sh_mobile_lcdc_remove,
1262 };
1263
1264 static int __init sh_mobile_lcdc_init(void)
1265 {
1266         return platform_driver_register(&sh_mobile_lcdc_driver);
1267 }
1268
1269 static void __exit sh_mobile_lcdc_exit(void)
1270 {
1271         platform_driver_unregister(&sh_mobile_lcdc_driver);
1272 }
1273
1274 module_init(sh_mobile_lcdc_init);
1275 module_exit(sh_mobile_lcdc_exit);
1276
1277 MODULE_DESCRIPTION("SuperH Mobile LCDC Framebuffer driver");
1278 MODULE_AUTHOR("Magnus Damm <damm@opensource.se>");
1279 MODULE_LICENSE("GPL v2");