2 * SuperH Mobile LCDC Framebuffer
4 * Copyright (c) 2008 Magnus Damm
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/delay.h>
16 #include <linux/clk.h>
17 #include <linux/platform_device.h>
18 #include <linux/dma-mapping.h>
19 #include <video/sh_mobile_lcdc.h>
23 struct sh_mobile_lcdc_priv;
24 struct sh_mobile_lcdc_chan {
25 struct sh_mobile_lcdc_priv *lcdc;
26 unsigned long *reg_offs;
27 unsigned long ldmt1r_value;
28 unsigned long enabled; /* ME and SE in LDCNT2R */
29 struct sh_mobile_lcdc_chan_cfg cfg;
30 u32 pseudo_palette[PALETTE_NR];
32 dma_addr_t dma_handle;
35 struct sh_mobile_lcdc_priv {
37 #ifdef CONFIG_HAVE_CLK
42 struct sh_mobile_lcdc_chan ch[2];
45 /* shared registers */
47 #define _LDDCKSTPR 0x414
50 #define _LDCNT1R 0x470
51 #define _LDCNT2R 0x474
53 #define _LDDWD0R 0x800
58 /* per-channel registers */
59 enum { LDDCKPAT1R, LDDCKPAT2R, LDMT1R, LDMT2R, LDMT3R, LDDFR, LDSM1R,
60 LDSA1R, LDMLSR, LDHCNR, LDHSYNR, LDVLNR, LDVSYNR, LDPMR };
62 static unsigned long lcdc_offs_mainlcd[] = {
79 static unsigned long lcdc_offs_sublcd[] = {
96 #define START_LCDC 0x00000001
97 #define LCDC_RESET 0x00000100
98 #define DISPLAY_BEU 0x00000008
99 #define LCDC_ENABLE 0x00000001
101 static void lcdc_write_chan(struct sh_mobile_lcdc_chan *chan,
102 int reg_nr, unsigned long data)
104 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr]);
107 static unsigned long lcdc_read_chan(struct sh_mobile_lcdc_chan *chan,
110 return ioread32(chan->lcdc->base + chan->reg_offs[reg_nr]);
113 static void lcdc_write(struct sh_mobile_lcdc_priv *priv,
114 unsigned long reg_offs, unsigned long data)
116 iowrite32(data, priv->base + reg_offs);
119 static unsigned long lcdc_read(struct sh_mobile_lcdc_priv *priv,
120 unsigned long reg_offs)
122 return ioread32(priv->base + reg_offs);
125 static void lcdc_wait_bit(struct sh_mobile_lcdc_priv *priv,
126 unsigned long reg_offs,
127 unsigned long mask, unsigned long until)
129 while ((lcdc_read(priv, reg_offs) & mask) != until)
133 static int lcdc_chan_is_sublcd(struct sh_mobile_lcdc_chan *chan)
135 return chan->cfg.chan == LCDC_CHAN_SUBLCD;
138 static void lcdc_sys_write_index(void *handle, unsigned long data)
140 struct sh_mobile_lcdc_chan *ch = handle;
142 lcdc_write(ch->lcdc, _LDDWD0R, data | 0x10000000);
143 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
144 lcdc_write(ch->lcdc, _LDDWAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
147 static void lcdc_sys_write_data(void *handle, unsigned long data)
149 struct sh_mobile_lcdc_chan *ch = handle;
151 lcdc_write(ch->lcdc, _LDDWD0R, data | 0x11000000);
152 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
153 lcdc_write(ch->lcdc, _LDDWAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
156 static unsigned long lcdc_sys_read_data(void *handle)
158 struct sh_mobile_lcdc_chan *ch = handle;
160 lcdc_write(ch->lcdc, _LDDRDR, 0x01000000);
161 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
162 lcdc_write(ch->lcdc, _LDDRAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
165 return lcdc_read(ch->lcdc, _LDDRDR) & 0xffff;
168 struct sh_mobile_lcdc_sys_bus_ops sh_mobile_lcdc_sys_bus_ops = {
169 lcdc_sys_write_index,
174 static void sh_mobile_lcdc_start_stop(struct sh_mobile_lcdc_priv *priv,
177 unsigned long tmp = lcdc_read(priv, _LDCNT2R);
180 /* start or stop the lcdc */
182 lcdc_write(priv, _LDCNT2R, tmp | START_LCDC);
184 lcdc_write(priv, _LDCNT2R, tmp & ~START_LCDC);
186 /* wait until power is applied/stopped on all channels */
187 for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
188 if (lcdc_read(priv, _LDCNT2R) & priv->ch[k].enabled)
190 tmp = lcdc_read_chan(&priv->ch[k], LDPMR) & 3;
191 if (start && tmp == 3)
193 if (!start && tmp == 0)
199 lcdc_write(priv, _LDDCKSTPR, 1); /* stop dotclock */
202 static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
204 struct sh_mobile_lcdc_chan *ch;
205 struct fb_videomode *lcd_cfg;
206 struct sh_mobile_lcdc_board_cfg *board_cfg;
211 #ifdef CONFIG_HAVE_CLK
212 clk_enable(priv->clk);
214 clk_enable(priv->dot_clk);
217 lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) | LCDC_RESET);
218 lcdc_wait_bit(priv, _LDCNT2R, LCDC_RESET, 0);
220 /* enable LCDC channels */
221 tmp = lcdc_read(priv, _LDCNT2R);
222 tmp |= priv->ch[0].enabled;
223 tmp |= priv->ch[1].enabled;
224 lcdc_write(priv, _LDCNT2R, tmp);
226 /* read data from external memory, avoid using the BEU for now */
227 lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) & ~DISPLAY_BEU);
229 /* stop the lcdc first */
230 sh_mobile_lcdc_start_stop(priv, 0);
232 /* configure clocks */
234 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
237 if (!priv->ch[k].enabled)
240 m = ch->cfg.clock_divider;
246 tmp |= m << (lcdc_chan_is_sublcd(ch) ? 8 : 0);
248 lcdc_write_chan(ch, LDDCKPAT1R, 0x00000000);
249 lcdc_write_chan(ch, LDDCKPAT2R, (1 << (m/2)) - 1);
252 lcdc_write(priv, _LDDCKR, tmp);
254 /* start dotclock again */
255 lcdc_write(priv, _LDDCKSTPR, 0);
256 lcdc_wait_bit(priv, _LDDCKSTPR, ~0, 0);
258 /* interrupts are disabled */
259 lcdc_write(priv, _LDINTR, 0);
261 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
263 lcd_cfg = &ch->cfg.lcd_cfg;
268 tmp = ch->ldmt1r_value;
269 tmp |= (lcd_cfg->sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : 1 << 28;
270 tmp |= (lcd_cfg->sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : 1 << 27;
271 tmp |= (ch->cfg.flags & LCDC_FLAGS_DWPOL) ? 1 << 26 : 0;
272 tmp |= (ch->cfg.flags & LCDC_FLAGS_DIPOL) ? 1 << 25 : 0;
273 tmp |= (ch->cfg.flags & LCDC_FLAGS_DAPOL) ? 1 << 24 : 0;
274 tmp |= (ch->cfg.flags & LCDC_FLAGS_HSCNT) ? 1 << 17 : 0;
275 tmp |= (ch->cfg.flags & LCDC_FLAGS_DWCNT) ? 1 << 16 : 0;
276 lcdc_write_chan(ch, LDMT1R, tmp);
279 lcdc_write_chan(ch, LDMT2R, ch->cfg.sys_bus_cfg.ldmt2r);
280 lcdc_write_chan(ch, LDMT3R, ch->cfg.sys_bus_cfg.ldmt3r);
282 /* horizontal configuration */
283 tmp = lcd_cfg->xres + lcd_cfg->hsync_len;
284 tmp += lcd_cfg->left_margin;
285 tmp += lcd_cfg->right_margin;
287 tmp |= (lcd_cfg->xres / 8) << 16; /* HDCN */
288 lcdc_write_chan(ch, LDHCNR, tmp);
291 tmp += lcd_cfg->right_margin;
292 tmp /= 8; /* HSYNP */
293 tmp |= (lcd_cfg->hsync_len / 8) << 16; /* HSYNW */
294 lcdc_write_chan(ch, LDHSYNR, tmp);
297 lcdc_write_chan(ch, LDPMR, 0);
299 /* vertical configuration */
300 tmp = lcd_cfg->yres + lcd_cfg->vsync_len;
301 tmp += lcd_cfg->upper_margin;
302 tmp += lcd_cfg->lower_margin; /* VTLN */
303 tmp |= lcd_cfg->yres << 16; /* VDLN */
304 lcdc_write_chan(ch, LDVLNR, tmp);
307 tmp += lcd_cfg->lower_margin; /* VSYNP */
308 tmp |= lcd_cfg->vsync_len << 16; /* VSYNW */
309 lcdc_write_chan(ch, LDVSYNR, tmp);
311 board_cfg = &ch->cfg.board_cfg;
312 if (board_cfg->setup_sys)
313 ret = board_cfg->setup_sys(board_cfg->board_data, ch,
314 &sh_mobile_lcdc_sys_bus_ops);
319 /* --- display_lcdc_data() --- */
320 lcdc_write(priv, _LDINTR, 0x00000f00);
322 /* word and long word swap */
323 lcdc_write(priv, _LDDDSR, lcdc_read(priv, _LDDDSR) | 6);
325 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
328 if (!priv->ch[k].enabled)
331 /* set bpp format in PKF[4:0] */
332 tmp = lcdc_read_chan(ch, LDDFR);
333 tmp &= ~(0x0001001f);
334 tmp |= (priv->ch[k].info.var.bits_per_pixel == 16) ? 3 : 0;
335 lcdc_write_chan(ch, LDDFR, tmp);
337 /* point out our frame buffer */
338 lcdc_write_chan(ch, LDSA1R, ch->info.fix.smem_start);
341 lcdc_write_chan(ch, LDMLSR, ch->info.fix.line_length);
343 /* continuous read mode */
344 lcdc_write_chan(ch, LDSM1R, 0);
348 lcdc_write(priv, _LDCNT1R, LCDC_ENABLE);
351 sh_mobile_lcdc_start_stop(priv, 1);
353 /* tell the board code to enable the panel */
354 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
356 board_cfg = &ch->cfg.board_cfg;
357 if (board_cfg->display_on)
358 board_cfg->display_on(board_cfg->board_data);
364 static void sh_mobile_lcdc_stop(struct sh_mobile_lcdc_priv *priv)
366 struct sh_mobile_lcdc_chan *ch;
367 struct sh_mobile_lcdc_board_cfg *board_cfg;
370 /* tell the board code to disable the panel */
371 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
373 board_cfg = &ch->cfg.board_cfg;
374 if (board_cfg->display_off)
375 board_cfg->display_off(board_cfg->board_data);
379 sh_mobile_lcdc_start_stop(priv, 0);
381 #ifdef CONFIG_HAVE_CLK
383 clk_disable(priv->dot_clk);
384 clk_disable(priv->clk);
388 static int sh_mobile_lcdc_check_interface(struct sh_mobile_lcdc_chan *ch)
392 switch (ch->cfg.interface_type) {
393 case RGB8: ifm = 0; miftyp = 0; break;
394 case RGB9: ifm = 0; miftyp = 4; break;
395 case RGB12A: ifm = 0; miftyp = 5; break;
396 case RGB12B: ifm = 0; miftyp = 6; break;
397 case RGB16: ifm = 0; miftyp = 7; break;
398 case RGB18: ifm = 0; miftyp = 10; break;
399 case RGB24: ifm = 0; miftyp = 11; break;
400 case SYS8A: ifm = 1; miftyp = 0; break;
401 case SYS8B: ifm = 1; miftyp = 1; break;
402 case SYS8C: ifm = 1; miftyp = 2; break;
403 case SYS8D: ifm = 1; miftyp = 3; break;
404 case SYS9: ifm = 1; miftyp = 4; break;
405 case SYS12: ifm = 1; miftyp = 5; break;
406 case SYS16A: ifm = 1; miftyp = 7; break;
407 case SYS16B: ifm = 1; miftyp = 8; break;
408 case SYS16C: ifm = 1; miftyp = 9; break;
409 case SYS18: ifm = 1; miftyp = 10; break;
410 case SYS24: ifm = 1; miftyp = 11; break;
414 /* SUBLCD only supports SYS interface */
415 if (lcdc_chan_is_sublcd(ch)) {
422 ch->ldmt1r_value = (ifm << 12) | miftyp;
428 static int sh_mobile_lcdc_setup_clocks(struct platform_device *pdev,
430 struct sh_mobile_lcdc_priv *priv)
432 #ifdef CONFIG_HAVE_CLK
438 switch (clock_source) {
439 case LCDC_CLK_BUS: str = "bus_clk"; icksel = 0; break;
440 case LCDC_CLK_PERIPHERAL: str = "peripheral_clk"; icksel = 1; break;
441 case LCDC_CLK_EXTERNAL: str = NULL; icksel = 2; break;
446 priv->lddckr = icksel << 16;
448 #ifdef CONFIG_HAVE_CLK
449 snprintf(clk_name, sizeof(clk_name), "lcdc%d", pdev->id);
450 priv->clk = clk_get(&pdev->dev, clk_name);
451 if (IS_ERR(priv->clk)) {
452 dev_err(&pdev->dev, "cannot get clock \"%s\"\n", clk_name);
453 return PTR_ERR(priv->clk);
457 priv->dot_clk = clk_get(&pdev->dev, str);
458 if (IS_ERR(priv->dot_clk)) {
459 dev_err(&pdev->dev, "cannot get dot clock %s\n", str);
461 return PTR_ERR(priv->dot_clk);
469 static int sh_mobile_lcdc_setcolreg(u_int regno,
470 u_int red, u_int green, u_int blue,
471 u_int transp, struct fb_info *info)
473 u32 *palette = info->pseudo_palette;
475 if (regno >= PALETTE_NR)
478 /* only FB_VISUAL_TRUECOLOR supported */
480 red >>= 16 - info->var.red.length;
481 green >>= 16 - info->var.green.length;
482 blue >>= 16 - info->var.blue.length;
483 transp >>= 16 - info->var.transp.length;
485 palette[regno] = (red << info->var.red.offset) |
486 (green << info->var.green.offset) |
487 (blue << info->var.blue.offset) |
488 (transp << info->var.transp.offset);
493 static struct fb_fix_screeninfo sh_mobile_lcdc_fix = {
494 .id = "SH Mobile LCDC",
495 .type = FB_TYPE_PACKED_PIXELS,
496 .visual = FB_VISUAL_TRUECOLOR,
497 .accel = FB_ACCEL_NONE,
500 static struct fb_ops sh_mobile_lcdc_ops = {
501 .fb_setcolreg = sh_mobile_lcdc_setcolreg,
502 .fb_read = fb_sys_read,
503 .fb_write = fb_sys_write,
504 .fb_fillrect = sys_fillrect,
505 .fb_copyarea = sys_copyarea,
506 .fb_imageblit = sys_imageblit,
509 static int sh_mobile_lcdc_set_bpp(struct fb_var_screeninfo *var, int bpp)
512 case 16: /* PKF[4:0] = 00011 - RGB 565 */
513 var->red.offset = 11;
515 var->green.offset = 5;
516 var->green.length = 6;
517 var->blue.offset = 0;
518 var->blue.length = 5;
519 var->transp.offset = 0;
520 var->transp.length = 0;
523 case 32: /* PKF[4:0] = 00000 - RGB 888
524 * sh7722 pdf says 00RRGGBB but reality is GGBB00RR
525 * this may be because LDDDSR has word swap enabled..
529 var->green.offset = 24;
530 var->green.length = 8;
531 var->blue.offset = 16;
532 var->blue.length = 8;
533 var->transp.offset = 0;
534 var->transp.length = 0;
539 var->bits_per_pixel = bpp;
540 var->red.msb_right = 0;
541 var->green.msb_right = 0;
542 var->blue.msb_right = 0;
543 var->transp.msb_right = 0;
547 static int sh_mobile_lcdc_remove(struct platform_device *pdev);
549 static int __init sh_mobile_lcdc_probe(struct platform_device *pdev)
551 struct fb_info *info;
552 struct sh_mobile_lcdc_priv *priv;
553 struct sh_mobile_lcdc_info *pdata;
554 struct sh_mobile_lcdc_chan_cfg *cfg;
555 struct resource *res;
560 if (!pdev->dev.platform_data) {
561 dev_err(&pdev->dev, "no platform data defined\n");
566 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
568 dev_err(&pdev->dev, "cannot find IO resource\n");
573 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
575 dev_err(&pdev->dev, "cannot allocate device data\n");
580 platform_set_drvdata(pdev, priv);
581 pdata = pdev->dev.platform_data;
584 for (i = 0; i < ARRAY_SIZE(pdata->ch); i++) {
585 priv->ch[j].lcdc = priv;
586 memcpy(&priv->ch[j].cfg, &pdata->ch[i], sizeof(pdata->ch[i]));
588 error = sh_mobile_lcdc_check_interface(&priv->ch[i]);
590 dev_err(&pdev->dev, "unsupported interface type\n");
594 switch (pdata->ch[i].chan) {
595 case LCDC_CHAN_MAINLCD:
596 priv->ch[j].enabled = 1 << 1;
597 priv->ch[j].reg_offs = lcdc_offs_mainlcd;
600 case LCDC_CHAN_SUBLCD:
601 priv->ch[j].enabled = 1 << 2;
602 priv->ch[j].reg_offs = lcdc_offs_sublcd;
609 dev_err(&pdev->dev, "no channels defined\n");
614 error = sh_mobile_lcdc_setup_clocks(pdev, pdata->clock_source, priv);
616 dev_err(&pdev->dev, "unable to setup clocks\n");
620 priv->base = ioremap_nocache(res->start, (res->end - res->start) + 1);
622 for (i = 0; i < j; i++) {
623 info = &priv->ch[i].info;
624 cfg = &priv->ch[i].cfg;
626 info->fbops = &sh_mobile_lcdc_ops;
627 info->var.xres = info->var.xres_virtual = cfg->lcd_cfg.xres;
628 info->var.yres = info->var.yres_virtual = cfg->lcd_cfg.yres;
629 info->var.width = cfg->lcd_size_cfg.width;
630 info->var.height = cfg->lcd_size_cfg.height;
631 info->var.activate = FB_ACTIVATE_NOW;
632 error = sh_mobile_lcdc_set_bpp(&info->var, cfg->bpp);
636 info->fix = sh_mobile_lcdc_fix;
637 info->fix.line_length = cfg->lcd_cfg.xres * (cfg->bpp / 8);
638 info->fix.smem_len = info->fix.line_length * cfg->lcd_cfg.yres;
640 buf = dma_alloc_coherent(&pdev->dev, info->fix.smem_len,
641 &priv->ch[i].dma_handle, GFP_KERNEL);
643 dev_err(&pdev->dev, "unable to allocate buffer\n");
648 info->pseudo_palette = &priv->ch[i].pseudo_palette;
649 info->flags = FBINFO_FLAG_DEFAULT;
651 error = fb_alloc_cmap(&info->cmap, PALETTE_NR, 0);
653 dev_err(&pdev->dev, "unable to allocate cmap\n");
654 dma_free_coherent(&pdev->dev, info->fix.smem_len,
655 buf, priv->ch[i].dma_handle);
659 memset(buf, 0, info->fix.smem_len);
660 info->fix.smem_start = priv->ch[i].dma_handle;
661 info->screen_base = buf;
662 info->device = &pdev->dev;
668 error = sh_mobile_lcdc_start(priv);
670 dev_err(&pdev->dev, "unable to start hardware\n");
674 for (i = 0; i < j; i++) {
675 error = register_framebuffer(&priv->ch[i].info);
680 for (i = 0; i < j; i++) {
681 info = &priv->ch[i].info;
683 "registered %s/%s as %dx%d %dbpp.\n",
685 (priv->ch[i].cfg.chan == LCDC_CHAN_MAINLCD) ?
686 "mainlcd" : "sublcd",
687 (int) priv->ch[i].cfg.lcd_cfg.xres,
688 (int) priv->ch[i].cfg.lcd_cfg.yres,
689 priv->ch[i].cfg.bpp);
694 sh_mobile_lcdc_remove(pdev);
699 static int sh_mobile_lcdc_remove(struct platform_device *pdev)
701 struct sh_mobile_lcdc_priv *priv = platform_get_drvdata(pdev);
702 struct fb_info *info;
705 for (i = 0; i < ARRAY_SIZE(priv->ch); i++)
706 if (priv->ch[i].info.dev)
707 unregister_framebuffer(&priv->ch[i].info);
709 sh_mobile_lcdc_stop(priv);
711 for (i = 0; i < ARRAY_SIZE(priv->ch); i++) {
712 info = &priv->ch[i].info;
717 dma_free_coherent(&pdev->dev, info->fix.smem_len,
718 info->screen_base, priv->ch[i].dma_handle);
719 fb_dealloc_cmap(&info->cmap);
722 #ifdef CONFIG_HAVE_CLK
724 clk_put(priv->dot_clk);
735 static struct platform_driver sh_mobile_lcdc_driver = {
737 .name = "sh_mobile_lcdc_fb",
738 .owner = THIS_MODULE,
740 .probe = sh_mobile_lcdc_probe,
741 .remove = sh_mobile_lcdc_remove,
744 static int __init sh_mobile_lcdc_init(void)
746 return platform_driver_register(&sh_mobile_lcdc_driver);
749 static void __exit sh_mobile_lcdc_exit(void)
751 platform_driver_unregister(&sh_mobile_lcdc_driver);
754 module_init(sh_mobile_lcdc_init);
755 module_exit(sh_mobile_lcdc_exit);
757 MODULE_DESCRIPTION("SuperH Mobile LCDC Framebuffer driver");
758 MODULE_AUTHOR("Magnus Damm <damm@opensource.se>");
759 MODULE_LICENSE("GPL v2");