2 * SuperH Mobile LCDC Framebuffer
4 * Copyright (c) 2008 Magnus Damm
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/delay.h>
16 #include <linux/clk.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/platform_device.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/interrupt.h>
21 #include <linux/vmalloc.h>
22 #include <linux/ioctl.h>
23 #include <linux/slab.h>
24 #include <video/sh_mobile_lcdc.h>
25 #include <asm/atomic.h>
28 #define SIDE_B_OFFSET 0x1000
29 #define MIRROR_OFFSET 0x2000
31 /* shared registers */
33 #define _LDDCKSTPR 0x414
36 #define _LDCNT1R 0x470
37 #define _LDCNT2R 0x474
38 #define _LDRCNTR 0x478
40 #define _LDDWD0R 0x800
45 /* shared registers and their order for context save/restore */
46 static int lcdc_shared_regs[] = {
54 #define NR_SHARED_REGS ARRAY_SIZE(lcdc_shared_regs)
56 /* per-channel registers */
57 enum { LDDCKPAT1R, LDDCKPAT2R, LDMT1R, LDMT2R, LDMT3R, LDDFR, LDSM1R,
58 LDSM2R, LDSA1R, LDMLSR, LDHCNR, LDHSYNR, LDVLNR, LDVSYNR, LDPMR,
61 static unsigned long lcdc_offs_mainlcd[NR_CH_REGS] = {
79 static unsigned long lcdc_offs_sublcd[NR_CH_REGS] = {
97 #define START_LCDC 0x00000001
98 #define LCDC_RESET 0x00000100
99 #define DISPLAY_BEU 0x00000008
100 #define LCDC_ENABLE 0x00000001
101 #define LDINTR_FE 0x00000400
102 #define LDINTR_VSE 0x00000200
103 #define LDINTR_VEE 0x00000100
104 #define LDINTR_FS 0x00000004
105 #define LDINTR_VSS 0x00000002
106 #define LDINTR_VES 0x00000001
107 #define LDRCNTR_SRS 0x00020000
108 #define LDRCNTR_SRC 0x00010000
109 #define LDRCNTR_MRS 0x00000002
110 #define LDRCNTR_MRC 0x00000001
111 #define LDSR_MRS 0x00000100
113 struct sh_mobile_lcdc_priv;
114 struct sh_mobile_lcdc_chan {
115 struct sh_mobile_lcdc_priv *lcdc;
116 unsigned long *reg_offs;
117 unsigned long ldmt1r_value;
118 unsigned long enabled; /* ME and SE in LDCNT2R */
119 struct sh_mobile_lcdc_chan_cfg cfg;
120 u32 pseudo_palette[PALETTE_NR];
121 unsigned long saved_ch_regs[NR_CH_REGS];
122 struct fb_info *info;
123 dma_addr_t dma_handle;
124 struct fb_deferred_io defio;
125 struct scatterlist *sglist;
126 unsigned long frame_end;
127 unsigned long pan_offset;
128 wait_queue_head_t frame_end_wait;
129 struct completion vsync_completion;
132 struct sh_mobile_lcdc_priv {
138 unsigned long lddckr;
139 struct sh_mobile_lcdc_chan ch[2];
140 unsigned long saved_shared_regs[NR_SHARED_REGS];
144 static bool banked(int reg_nr)
163 static void lcdc_write_chan(struct sh_mobile_lcdc_chan *chan,
164 int reg_nr, unsigned long data)
166 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr]);
168 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] +
172 static void lcdc_write_chan_mirror(struct sh_mobile_lcdc_chan *chan,
173 int reg_nr, unsigned long data)
175 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] +
179 static unsigned long lcdc_read_chan(struct sh_mobile_lcdc_chan *chan,
182 return ioread32(chan->lcdc->base + chan->reg_offs[reg_nr]);
185 static void lcdc_write(struct sh_mobile_lcdc_priv *priv,
186 unsigned long reg_offs, unsigned long data)
188 iowrite32(data, priv->base + reg_offs);
191 static unsigned long lcdc_read(struct sh_mobile_lcdc_priv *priv,
192 unsigned long reg_offs)
194 return ioread32(priv->base + reg_offs);
197 static void lcdc_wait_bit(struct sh_mobile_lcdc_priv *priv,
198 unsigned long reg_offs,
199 unsigned long mask, unsigned long until)
201 while ((lcdc_read(priv, reg_offs) & mask) != until)
205 static int lcdc_chan_is_sublcd(struct sh_mobile_lcdc_chan *chan)
207 return chan->cfg.chan == LCDC_CHAN_SUBLCD;
210 static void lcdc_sys_write_index(void *handle, unsigned long data)
212 struct sh_mobile_lcdc_chan *ch = handle;
214 lcdc_write(ch->lcdc, _LDDWD0R, data | 0x10000000);
215 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
216 lcdc_write(ch->lcdc, _LDDWAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
217 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
220 static void lcdc_sys_write_data(void *handle, unsigned long data)
222 struct sh_mobile_lcdc_chan *ch = handle;
224 lcdc_write(ch->lcdc, _LDDWD0R, data | 0x11000000);
225 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
226 lcdc_write(ch->lcdc, _LDDWAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
227 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
230 static unsigned long lcdc_sys_read_data(void *handle)
232 struct sh_mobile_lcdc_chan *ch = handle;
234 lcdc_write(ch->lcdc, _LDDRDR, 0x01000000);
235 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
236 lcdc_write(ch->lcdc, _LDDRAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
238 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
240 return lcdc_read(ch->lcdc, _LDDRDR) & 0x3ffff;
243 struct sh_mobile_lcdc_sys_bus_ops sh_mobile_lcdc_sys_bus_ops = {
244 lcdc_sys_write_index,
249 static void sh_mobile_lcdc_clk_on(struct sh_mobile_lcdc_priv *priv)
251 if (atomic_inc_and_test(&priv->hw_usecnt)) {
252 pm_runtime_get_sync(priv->dev);
254 clk_enable(priv->dot_clk);
258 static void sh_mobile_lcdc_clk_off(struct sh_mobile_lcdc_priv *priv)
260 if (atomic_sub_return(1, &priv->hw_usecnt) == -1) {
262 clk_disable(priv->dot_clk);
263 pm_runtime_put(priv->dev);
267 static int sh_mobile_lcdc_sginit(struct fb_info *info,
268 struct list_head *pagelist)
270 struct sh_mobile_lcdc_chan *ch = info->par;
271 unsigned int nr_pages_max = info->fix.smem_len >> PAGE_SHIFT;
275 sg_init_table(ch->sglist, nr_pages_max);
277 list_for_each_entry(page, pagelist, lru)
278 sg_set_page(&ch->sglist[nr_pages++], page, PAGE_SIZE, 0);
283 static void sh_mobile_lcdc_deferred_io(struct fb_info *info,
284 struct list_head *pagelist)
286 struct sh_mobile_lcdc_chan *ch = info->par;
287 struct sh_mobile_lcdc_board_cfg *bcfg = &ch->cfg.board_cfg;
289 /* enable clocks before accessing hardware */
290 sh_mobile_lcdc_clk_on(ch->lcdc);
293 * It's possible to get here without anything on the pagelist via
294 * sh_mobile_lcdc_deferred_io_touch() or via a userspace fsync()
295 * invocation. In the former case, the acceleration routines are
296 * stepped in to when using the framebuffer console causing the
297 * workqueue to be scheduled without any dirty pages on the list.
299 * Despite this, a panel update is still needed given that the
300 * acceleration routines have their own methods for writing in
301 * that still need to be updated.
303 * The fsync() and empty pagelist case could be optimized for,
304 * but we don't bother, as any application exhibiting such
305 * behaviour is fundamentally broken anyways.
307 if (!list_empty(pagelist)) {
308 unsigned int nr_pages = sh_mobile_lcdc_sginit(info, pagelist);
310 /* trigger panel update */
311 dma_map_sg(info->dev, ch->sglist, nr_pages, DMA_TO_DEVICE);
312 if (bcfg->start_transfer)
313 bcfg->start_transfer(bcfg->board_data, ch,
314 &sh_mobile_lcdc_sys_bus_ops);
315 lcdc_write_chan(ch, LDSM2R, 1);
316 dma_unmap_sg(info->dev, ch->sglist, nr_pages, DMA_TO_DEVICE);
318 if (bcfg->start_transfer)
319 bcfg->start_transfer(bcfg->board_data, ch,
320 &sh_mobile_lcdc_sys_bus_ops);
321 lcdc_write_chan(ch, LDSM2R, 1);
325 static void sh_mobile_lcdc_deferred_io_touch(struct fb_info *info)
327 struct fb_deferred_io *fbdefio = info->fbdefio;
330 schedule_delayed_work(&info->deferred_work, fbdefio->delay);
333 static irqreturn_t sh_mobile_lcdc_irq(int irq, void *data)
335 struct sh_mobile_lcdc_priv *priv = data;
336 struct sh_mobile_lcdc_chan *ch;
338 unsigned long ldintr;
342 /* acknowledge interrupt */
343 ldintr = tmp = lcdc_read(priv, _LDINTR);
345 * disable further VSYNC End IRQs, preserve all other enabled IRQs,
346 * write 0 to bits 0-6 to ack all triggered IRQs.
348 tmp &= 0xffffff00 & ~LDINTR_VEE;
349 lcdc_write(priv, _LDINTR, tmp);
351 /* figure out if this interrupt is for main or sub lcd */
352 is_sub = (lcdc_read(priv, _LDSR) & (1 << 10)) ? 1 : 0;
354 /* wake up channel and disable clocks */
355 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
362 if (ldintr & LDINTR_FS) {
363 if (is_sub == lcdc_chan_is_sublcd(ch)) {
365 wake_up(&ch->frame_end_wait);
367 sh_mobile_lcdc_clk_off(priv);
372 if (ldintr & LDINTR_VES)
373 complete(&ch->vsync_completion);
379 static void sh_mobile_lcdc_start_stop(struct sh_mobile_lcdc_priv *priv,
382 unsigned long tmp = lcdc_read(priv, _LDCNT2R);
385 /* start or stop the lcdc */
387 lcdc_write(priv, _LDCNT2R, tmp | START_LCDC);
389 lcdc_write(priv, _LDCNT2R, tmp & ~START_LCDC);
391 /* wait until power is applied/stopped on all channels */
392 for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
393 if (lcdc_read(priv, _LDCNT2R) & priv->ch[k].enabled)
395 tmp = lcdc_read_chan(&priv->ch[k], LDPMR) & 3;
396 if (start && tmp == 3)
398 if (!start && tmp == 0)
404 lcdc_write(priv, _LDDCKSTPR, 1); /* stop dotclock */
407 static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
409 struct sh_mobile_lcdc_chan *ch;
410 struct fb_videomode *lcd_cfg;
411 struct sh_mobile_lcdc_board_cfg *board_cfg;
416 /* enable clocks before accessing the hardware */
417 for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
418 if (priv->ch[k].enabled)
419 sh_mobile_lcdc_clk_on(priv);
422 lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) | LCDC_RESET);
423 lcdc_wait_bit(priv, _LDCNT2R, LCDC_RESET, 0);
425 /* enable LCDC channels */
426 tmp = lcdc_read(priv, _LDCNT2R);
427 tmp |= priv->ch[0].enabled;
428 tmp |= priv->ch[1].enabled;
429 lcdc_write(priv, _LDCNT2R, tmp);
431 /* read data from external memory, avoid using the BEU for now */
432 lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) & ~DISPLAY_BEU);
434 /* stop the lcdc first */
435 sh_mobile_lcdc_start_stop(priv, 0);
437 /* configure clocks */
439 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
442 if (!priv->ch[k].enabled)
445 m = ch->cfg.clock_divider;
451 tmp |= m << (lcdc_chan_is_sublcd(ch) ? 8 : 0);
453 lcdc_write_chan(ch, LDDCKPAT1R, 0x00000000);
454 lcdc_write_chan(ch, LDDCKPAT2R, (1 << (m/2)) - 1);
457 lcdc_write(priv, _LDDCKR, tmp);
459 /* start dotclock again */
460 lcdc_write(priv, _LDDCKSTPR, 0);
461 lcdc_wait_bit(priv, _LDDCKSTPR, ~0, 0);
463 /* interrupts are disabled to begin with */
464 lcdc_write(priv, _LDINTR, 0);
466 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
468 lcd_cfg = &ch->cfg.lcd_cfg;
473 tmp = ch->ldmt1r_value;
474 tmp |= (lcd_cfg->sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : 1 << 28;
475 tmp |= (lcd_cfg->sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : 1 << 27;
476 tmp |= (ch->cfg.flags & LCDC_FLAGS_DWPOL) ? 1 << 26 : 0;
477 tmp |= (ch->cfg.flags & LCDC_FLAGS_DIPOL) ? 1 << 25 : 0;
478 tmp |= (ch->cfg.flags & LCDC_FLAGS_DAPOL) ? 1 << 24 : 0;
479 tmp |= (ch->cfg.flags & LCDC_FLAGS_HSCNT) ? 1 << 17 : 0;
480 tmp |= (ch->cfg.flags & LCDC_FLAGS_DWCNT) ? 1 << 16 : 0;
481 lcdc_write_chan(ch, LDMT1R, tmp);
484 lcdc_write_chan(ch, LDMT2R, ch->cfg.sys_bus_cfg.ldmt2r);
485 lcdc_write_chan(ch, LDMT3R, ch->cfg.sys_bus_cfg.ldmt3r);
487 /* horizontal configuration */
488 tmp = lcd_cfg->xres + lcd_cfg->hsync_len;
489 tmp += lcd_cfg->left_margin;
490 tmp += lcd_cfg->right_margin;
492 tmp |= (lcd_cfg->xres / 8) << 16; /* HDCN */
493 lcdc_write_chan(ch, LDHCNR, tmp);
496 tmp += lcd_cfg->right_margin;
497 tmp /= 8; /* HSYNP */
498 tmp |= (lcd_cfg->hsync_len / 8) << 16; /* HSYNW */
499 lcdc_write_chan(ch, LDHSYNR, tmp);
502 lcdc_write_chan(ch, LDPMR, 0);
504 /* vertical configuration */
505 tmp = lcd_cfg->yres + lcd_cfg->vsync_len;
506 tmp += lcd_cfg->upper_margin;
507 tmp += lcd_cfg->lower_margin; /* VTLN */
508 tmp |= lcd_cfg->yres << 16; /* VDLN */
509 lcdc_write_chan(ch, LDVLNR, tmp);
512 tmp += lcd_cfg->lower_margin; /* VSYNP */
513 tmp |= lcd_cfg->vsync_len << 16; /* VSYNW */
514 lcdc_write_chan(ch, LDVSYNR, tmp);
516 board_cfg = &ch->cfg.board_cfg;
517 if (board_cfg->setup_sys)
518 ret = board_cfg->setup_sys(board_cfg->board_data, ch,
519 &sh_mobile_lcdc_sys_bus_ops);
524 /* word and long word swap */
525 lcdc_write(priv, _LDDDSR, lcdc_read(priv, _LDDDSR) | 6);
527 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
530 if (!priv->ch[k].enabled)
533 /* set bpp format in PKF[4:0] */
534 tmp = lcdc_read_chan(ch, LDDFR);
535 tmp &= ~(0x0001001f);
536 tmp |= (ch->info->var.bits_per_pixel == 16) ? 3 : 0;
537 lcdc_write_chan(ch, LDDFR, tmp);
539 /* point out our frame buffer */
540 lcdc_write_chan(ch, LDSA1R, ch->info->fix.smem_start);
543 lcdc_write_chan(ch, LDMLSR, ch->info->fix.line_length);
545 /* setup deferred io if SYS bus */
546 tmp = ch->cfg.sys_bus_cfg.deferred_io_msec;
547 if (ch->ldmt1r_value & (1 << 12) && tmp) {
548 ch->defio.deferred_io = sh_mobile_lcdc_deferred_io;
549 ch->defio.delay = msecs_to_jiffies(tmp);
550 ch->info->fbdefio = &ch->defio;
551 fb_deferred_io_init(ch->info);
554 lcdc_write_chan(ch, LDSM1R, 1);
556 /* enable "Frame End Interrupt Enable" bit */
557 lcdc_write(priv, _LDINTR, LDINTR_FE);
560 /* continuous read mode */
561 lcdc_write_chan(ch, LDSM1R, 0);
566 lcdc_write(priv, _LDCNT1R, LCDC_ENABLE);
569 sh_mobile_lcdc_start_stop(priv, 1);
572 /* tell the board code to enable the panel */
573 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
578 board_cfg = &ch->cfg.board_cfg;
579 if (board_cfg->display_on)
580 board_cfg->display_on(board_cfg->board_data);
586 static void sh_mobile_lcdc_stop(struct sh_mobile_lcdc_priv *priv)
588 struct sh_mobile_lcdc_chan *ch;
589 struct sh_mobile_lcdc_board_cfg *board_cfg;
592 /* clean up deferred io and ask board code to disable panel */
593 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
599 * flush frame, and wait for frame end interrupt
600 * clean up deferred io and enable clock
602 if (ch->info->fbdefio) {
604 schedule_delayed_work(&ch->info->deferred_work, 0);
605 wait_event(ch->frame_end_wait, ch->frame_end);
606 fb_deferred_io_cleanup(ch->info);
607 ch->info->fbdefio = NULL;
608 sh_mobile_lcdc_clk_on(priv);
611 board_cfg = &ch->cfg.board_cfg;
612 if (board_cfg->display_off)
613 board_cfg->display_off(board_cfg->board_data);
618 sh_mobile_lcdc_start_stop(priv, 0);
623 for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
624 if (priv->ch[k].enabled)
625 sh_mobile_lcdc_clk_off(priv);
628 static int sh_mobile_lcdc_check_interface(struct sh_mobile_lcdc_chan *ch)
632 switch (ch->cfg.interface_type) {
633 case RGB8: ifm = 0; miftyp = 0; break;
634 case RGB9: ifm = 0; miftyp = 4; break;
635 case RGB12A: ifm = 0; miftyp = 5; break;
636 case RGB12B: ifm = 0; miftyp = 6; break;
637 case RGB16: ifm = 0; miftyp = 7; break;
638 case RGB18: ifm = 0; miftyp = 10; break;
639 case RGB24: ifm = 0; miftyp = 11; break;
640 case SYS8A: ifm = 1; miftyp = 0; break;
641 case SYS8B: ifm = 1; miftyp = 1; break;
642 case SYS8C: ifm = 1; miftyp = 2; break;
643 case SYS8D: ifm = 1; miftyp = 3; break;
644 case SYS9: ifm = 1; miftyp = 4; break;
645 case SYS12: ifm = 1; miftyp = 5; break;
646 case SYS16A: ifm = 1; miftyp = 7; break;
647 case SYS16B: ifm = 1; miftyp = 8; break;
648 case SYS16C: ifm = 1; miftyp = 9; break;
649 case SYS18: ifm = 1; miftyp = 10; break;
650 case SYS24: ifm = 1; miftyp = 11; break;
654 /* SUBLCD only supports SYS interface */
655 if (lcdc_chan_is_sublcd(ch)) {
662 ch->ldmt1r_value = (ifm << 12) | miftyp;
668 static int sh_mobile_lcdc_setup_clocks(struct platform_device *pdev,
670 struct sh_mobile_lcdc_priv *priv)
675 switch (clock_source) {
676 case LCDC_CLK_BUS: str = "bus_clk"; icksel = 0; break;
677 case LCDC_CLK_PERIPHERAL: str = "peripheral_clk"; icksel = 1; break;
678 case LCDC_CLK_EXTERNAL: str = NULL; icksel = 2; break;
683 priv->lddckr = icksel << 16;
686 priv->dot_clk = clk_get(&pdev->dev, str);
687 if (IS_ERR(priv->dot_clk)) {
688 dev_err(&pdev->dev, "cannot get dot clock %s\n", str);
689 return PTR_ERR(priv->dot_clk);
692 atomic_set(&priv->hw_usecnt, -1);
694 /* Runtime PM support involves two step for this driver:
695 * 1) Enable Runtime PM
696 * 2) Force Runtime PM Resume since hardware is accessed from probe()
698 priv->dev = &pdev->dev;
699 pm_runtime_enable(priv->dev);
700 pm_runtime_resume(priv->dev);
704 static int sh_mobile_lcdc_setcolreg(u_int regno,
705 u_int red, u_int green, u_int blue,
706 u_int transp, struct fb_info *info)
708 u32 *palette = info->pseudo_palette;
710 if (regno >= PALETTE_NR)
713 /* only FB_VISUAL_TRUECOLOR supported */
715 red >>= 16 - info->var.red.length;
716 green >>= 16 - info->var.green.length;
717 blue >>= 16 - info->var.blue.length;
718 transp >>= 16 - info->var.transp.length;
720 palette[regno] = (red << info->var.red.offset) |
721 (green << info->var.green.offset) |
722 (blue << info->var.blue.offset) |
723 (transp << info->var.transp.offset);
728 static struct fb_fix_screeninfo sh_mobile_lcdc_fix = {
729 .id = "SH Mobile LCDC",
730 .type = FB_TYPE_PACKED_PIXELS,
731 .visual = FB_VISUAL_TRUECOLOR,
732 .accel = FB_ACCEL_NONE,
738 static void sh_mobile_lcdc_fillrect(struct fb_info *info,
739 const struct fb_fillrect *rect)
741 sys_fillrect(info, rect);
742 sh_mobile_lcdc_deferred_io_touch(info);
745 static void sh_mobile_lcdc_copyarea(struct fb_info *info,
746 const struct fb_copyarea *area)
748 sys_copyarea(info, area);
749 sh_mobile_lcdc_deferred_io_touch(info);
752 static void sh_mobile_lcdc_imageblit(struct fb_info *info,
753 const struct fb_image *image)
755 sys_imageblit(info, image);
756 sh_mobile_lcdc_deferred_io_touch(info);
759 static int sh_mobile_fb_pan_display(struct fb_var_screeninfo *var,
760 struct fb_info *info)
762 struct sh_mobile_lcdc_chan *ch = info->par;
763 struct sh_mobile_lcdc_priv *priv = ch->lcdc;
764 unsigned long ldrcntr;
765 unsigned long new_pan_offset;
767 new_pan_offset = (var->yoffset * info->fix.line_length) +
768 (var->xoffset * (info->var.bits_per_pixel / 8));
770 if (new_pan_offset == ch->pan_offset)
771 return 0; /* No change, do nothing */
773 ldrcntr = lcdc_read(priv, _LDRCNTR);
775 /* Set the source address for the next refresh */
776 lcdc_write_chan_mirror(ch, LDSA1R, ch->dma_handle + new_pan_offset);
777 if (lcdc_chan_is_sublcd(ch))
778 lcdc_write(ch->lcdc, _LDRCNTR, ldrcntr ^ LDRCNTR_SRS);
780 lcdc_write(ch->lcdc, _LDRCNTR, ldrcntr ^ LDRCNTR_MRS);
782 ch->pan_offset = new_pan_offset;
784 sh_mobile_lcdc_deferred_io_touch(info);
789 static int sh_mobile_wait_for_vsync(struct fb_info *info)
791 struct sh_mobile_lcdc_chan *ch = info->par;
792 unsigned long ldintr;
795 /* Enable VSync End interrupt */
796 ldintr = lcdc_read(ch->lcdc, _LDINTR);
797 ldintr |= LDINTR_VEE;
798 lcdc_write(ch->lcdc, _LDINTR, ldintr);
800 ret = wait_for_completion_interruptible_timeout(&ch->vsync_completion,
801 msecs_to_jiffies(100));
808 static int sh_mobile_ioctl(struct fb_info *info, unsigned int cmd,
814 case FBIO_WAITFORVSYNC:
815 retval = sh_mobile_wait_for_vsync(info);
819 retval = -ENOIOCTLCMD;
826 static struct fb_ops sh_mobile_lcdc_ops = {
827 .owner = THIS_MODULE,
828 .fb_setcolreg = sh_mobile_lcdc_setcolreg,
829 .fb_read = fb_sys_read,
830 .fb_write = fb_sys_write,
831 .fb_fillrect = sh_mobile_lcdc_fillrect,
832 .fb_copyarea = sh_mobile_lcdc_copyarea,
833 .fb_imageblit = sh_mobile_lcdc_imageblit,
834 .fb_pan_display = sh_mobile_fb_pan_display,
835 .fb_ioctl = sh_mobile_ioctl,
838 static int sh_mobile_lcdc_set_bpp(struct fb_var_screeninfo *var, int bpp)
841 case 16: /* PKF[4:0] = 00011 - RGB 565 */
842 var->red.offset = 11;
844 var->green.offset = 5;
845 var->green.length = 6;
846 var->blue.offset = 0;
847 var->blue.length = 5;
848 var->transp.offset = 0;
849 var->transp.length = 0;
852 case 32: /* PKF[4:0] = 00000 - RGB 888
853 * sh7722 pdf says 00RRGGBB but reality is GGBB00RR
854 * this may be because LDDDSR has word swap enabled..
858 var->green.offset = 24;
859 var->green.length = 8;
860 var->blue.offset = 16;
861 var->blue.length = 8;
862 var->transp.offset = 0;
863 var->transp.length = 0;
868 var->bits_per_pixel = bpp;
869 var->red.msb_right = 0;
870 var->green.msb_right = 0;
871 var->blue.msb_right = 0;
872 var->transp.msb_right = 0;
876 static int sh_mobile_lcdc_suspend(struct device *dev)
878 struct platform_device *pdev = to_platform_device(dev);
880 sh_mobile_lcdc_stop(platform_get_drvdata(pdev));
884 static int sh_mobile_lcdc_resume(struct device *dev)
886 struct platform_device *pdev = to_platform_device(dev);
888 return sh_mobile_lcdc_start(platform_get_drvdata(pdev));
891 static int sh_mobile_lcdc_runtime_suspend(struct device *dev)
893 struct platform_device *pdev = to_platform_device(dev);
894 struct sh_mobile_lcdc_priv *p = platform_get_drvdata(pdev);
895 struct sh_mobile_lcdc_chan *ch;
898 /* save per-channel registers */
899 for (k = 0; k < ARRAY_SIZE(p->ch); k++) {
903 for (n = 0; n < NR_CH_REGS; n++)
904 ch->saved_ch_regs[n] = lcdc_read_chan(ch, n);
907 /* save shared registers */
908 for (n = 0; n < NR_SHARED_REGS; n++)
909 p->saved_shared_regs[n] = lcdc_read(p, lcdc_shared_regs[n]);
911 /* turn off LCDC hardware */
912 lcdc_write(p, _LDCNT1R, 0);
916 static int sh_mobile_lcdc_runtime_resume(struct device *dev)
918 struct platform_device *pdev = to_platform_device(dev);
919 struct sh_mobile_lcdc_priv *p = platform_get_drvdata(pdev);
920 struct sh_mobile_lcdc_chan *ch;
923 /* restore per-channel registers */
924 for (k = 0; k < ARRAY_SIZE(p->ch); k++) {
928 for (n = 0; n < NR_CH_REGS; n++)
929 lcdc_write_chan(ch, n, ch->saved_ch_regs[n]);
932 /* restore shared registers */
933 for (n = 0; n < NR_SHARED_REGS; n++)
934 lcdc_write(p, lcdc_shared_regs[n], p->saved_shared_regs[n]);
939 static const struct dev_pm_ops sh_mobile_lcdc_dev_pm_ops = {
940 .suspend = sh_mobile_lcdc_suspend,
941 .resume = sh_mobile_lcdc_resume,
942 .runtime_suspend = sh_mobile_lcdc_runtime_suspend,
943 .runtime_resume = sh_mobile_lcdc_runtime_resume,
946 static int sh_mobile_lcdc_remove(struct platform_device *pdev);
948 static int __devinit sh_mobile_lcdc_probe(struct platform_device *pdev)
950 struct fb_info *info;
951 struct sh_mobile_lcdc_priv *priv;
952 struct sh_mobile_lcdc_info *pdata;
953 struct sh_mobile_lcdc_chan_cfg *cfg;
954 struct resource *res;
959 if (!pdev->dev.platform_data) {
960 dev_err(&pdev->dev, "no platform data defined\n");
964 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
965 i = platform_get_irq(pdev, 0);
967 dev_err(&pdev->dev, "cannot get platform resources\n");
971 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
973 dev_err(&pdev->dev, "cannot allocate device data\n");
977 platform_set_drvdata(pdev, priv);
979 error = request_irq(i, sh_mobile_lcdc_irq, IRQF_DISABLED,
980 dev_name(&pdev->dev), priv);
982 dev_err(&pdev->dev, "unable to request irq\n");
987 pdata = pdev->dev.platform_data;
990 for (i = 0; i < ARRAY_SIZE(pdata->ch); i++) {
991 priv->ch[j].lcdc = priv;
992 memcpy(&priv->ch[j].cfg, &pdata->ch[i], sizeof(pdata->ch[i]));
994 error = sh_mobile_lcdc_check_interface(&priv->ch[i]);
996 dev_err(&pdev->dev, "unsupported interface type\n");
999 init_waitqueue_head(&priv->ch[i].frame_end_wait);
1000 init_completion(&priv->ch[i].vsync_completion);
1001 priv->ch[j].pan_offset = 0;
1003 switch (pdata->ch[i].chan) {
1004 case LCDC_CHAN_MAINLCD:
1005 priv->ch[j].enabled = 1 << 1;
1006 priv->ch[j].reg_offs = lcdc_offs_mainlcd;
1009 case LCDC_CHAN_SUBLCD:
1010 priv->ch[j].enabled = 1 << 2;
1011 priv->ch[j].reg_offs = lcdc_offs_sublcd;
1018 dev_err(&pdev->dev, "no channels defined\n");
1023 error = sh_mobile_lcdc_setup_clocks(pdev, pdata->clock_source, priv);
1025 dev_err(&pdev->dev, "unable to setup clocks\n");
1029 priv->base = ioremap_nocache(res->start, (res->end - res->start) + 1);
1031 for (i = 0; i < j; i++) {
1032 cfg = &priv->ch[i].cfg;
1034 priv->ch[i].info = framebuffer_alloc(0, &pdev->dev);
1035 if (!priv->ch[i].info) {
1036 dev_err(&pdev->dev, "unable to allocate fb_info\n");
1041 info = priv->ch[i].info;
1042 info->fbops = &sh_mobile_lcdc_ops;
1043 info->var.xres = info->var.xres_virtual = cfg->lcd_cfg.xres;
1044 info->var.yres = cfg->lcd_cfg.yres;
1045 /* Default Y virtual resolution is 2x panel size */
1046 info->var.yres_virtual = info->var.yres * 2;
1047 info->var.width = cfg->lcd_size_cfg.width;
1048 info->var.height = cfg->lcd_size_cfg.height;
1049 info->var.activate = FB_ACTIVATE_NOW;
1050 error = sh_mobile_lcdc_set_bpp(&info->var, cfg->bpp);
1054 info->fix = sh_mobile_lcdc_fix;
1055 info->fix.line_length = cfg->lcd_cfg.xres * (cfg->bpp / 8);
1056 info->fix.smem_len = info->fix.line_length *
1057 info->var.yres_virtual;
1059 buf = dma_alloc_coherent(&pdev->dev, info->fix.smem_len,
1060 &priv->ch[i].dma_handle, GFP_KERNEL);
1062 dev_err(&pdev->dev, "unable to allocate buffer\n");
1067 info->pseudo_palette = &priv->ch[i].pseudo_palette;
1068 info->flags = FBINFO_FLAG_DEFAULT;
1070 error = fb_alloc_cmap(&info->cmap, PALETTE_NR, 0);
1072 dev_err(&pdev->dev, "unable to allocate cmap\n");
1073 dma_free_coherent(&pdev->dev, info->fix.smem_len,
1074 buf, priv->ch[i].dma_handle);
1078 memset(buf, 0, info->fix.smem_len);
1079 info->fix.smem_start = priv->ch[i].dma_handle;
1080 info->screen_base = buf;
1081 info->device = &pdev->dev;
1082 info->par = &priv->ch[i];
1088 error = sh_mobile_lcdc_start(priv);
1090 dev_err(&pdev->dev, "unable to start hardware\n");
1094 for (i = 0; i < j; i++) {
1095 struct sh_mobile_lcdc_chan *ch = priv->ch + i;
1099 if (info->fbdefio) {
1100 ch->sglist = vmalloc(sizeof(struct scatterlist) *
1101 info->fix.smem_len >> PAGE_SHIFT);
1103 dev_err(&pdev->dev, "cannot allocate sglist\n");
1108 error = register_framebuffer(info);
1113 "registered %s/%s as %dx%d %dbpp.\n",
1115 (ch->cfg.chan == LCDC_CHAN_MAINLCD) ?
1116 "mainlcd" : "sublcd",
1117 (int) ch->cfg.lcd_cfg.xres,
1118 (int) ch->cfg.lcd_cfg.yres,
1121 /* deferred io mode: disable clock to save power */
1123 sh_mobile_lcdc_clk_off(priv);
1128 sh_mobile_lcdc_remove(pdev);
1133 static int sh_mobile_lcdc_remove(struct platform_device *pdev)
1135 struct sh_mobile_lcdc_priv *priv = platform_get_drvdata(pdev);
1136 struct fb_info *info;
1139 for (i = 0; i < ARRAY_SIZE(priv->ch); i++)
1140 if (priv->ch[i].info && priv->ch[i].info->dev)
1141 unregister_framebuffer(priv->ch[i].info);
1143 sh_mobile_lcdc_stop(priv);
1145 for (i = 0; i < ARRAY_SIZE(priv->ch); i++) {
1146 info = priv->ch[i].info;
1148 if (!info || !info->device)
1151 if (priv->ch[i].sglist)
1152 vfree(priv->ch[i].sglist);
1154 dma_free_coherent(&pdev->dev, info->fix.smem_len,
1155 info->screen_base, priv->ch[i].dma_handle);
1156 fb_dealloc_cmap(&info->cmap);
1157 framebuffer_release(info);
1161 clk_put(priv->dot_clk);
1164 pm_runtime_disable(priv->dev);
1167 iounmap(priv->base);
1170 free_irq(priv->irq, priv);
1175 static struct platform_driver sh_mobile_lcdc_driver = {
1177 .name = "sh_mobile_lcdc_fb",
1178 .owner = THIS_MODULE,
1179 .pm = &sh_mobile_lcdc_dev_pm_ops,
1181 .probe = sh_mobile_lcdc_probe,
1182 .remove = sh_mobile_lcdc_remove,
1185 static int __init sh_mobile_lcdc_init(void)
1187 return platform_driver_register(&sh_mobile_lcdc_driver);
1190 static void __exit sh_mobile_lcdc_exit(void)
1192 platform_driver_unregister(&sh_mobile_lcdc_driver);
1195 module_init(sh_mobile_lcdc_init);
1196 module_exit(sh_mobile_lcdc_exit);
1198 MODULE_DESCRIPTION("SuperH Mobile LCDC Framebuffer driver");
1199 MODULE_AUTHOR("Magnus Damm <damm@opensource.se>");
1200 MODULE_LICENSE("GPL v2");