4 * Mode initializing code (CRT1 section) for
5 * for SiS 300/305/540/630/730,
6 * SiS 315/550/[M]650/651/[M]661[FGM]X/[M]74x[GX]/330/[M]76x[GX],
7 * XGI Volari V3XT/V5/V8, Z7
8 * (Universal module for Linux kernel framebuffer and X.org/XFree86 4.x)
10 * Copyright (C) 2001-2005 by Thomas Winischhofer, Vienna, Austria
12 * If distributed as part of the Linux kernel, the following license terms
15 * * This program is free software; you can redistribute it and/or modify
16 * * it under the terms of the GNU General Public License as published by
17 * * the Free Software Foundation; either version 2 of the named License,
18 * * or any later version.
20 * * This program is distributed in the hope that it will be useful,
21 * * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * * GNU General Public License for more details.
25 * * You should have received a copy of the GNU General Public License
26 * * along with this program; if not, write to the Free Software
27 * * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA
29 * Otherwise, the following license terms apply:
31 * * Redistribution and use in source and binary forms, with or without
32 * * modification, are permitted provided that the following conditions
34 * * 1) Redistributions of source code must retain the above copyright
35 * * notice, this list of conditions and the following disclaimer.
36 * * 2) Redistributions in binary form must reproduce the above copyright
37 * * notice, this list of conditions and the following disclaimer in the
38 * * documentation and/or other materials provided with the distribution.
39 * * 3) The name of the author may not be used to endorse or promote products
40 * * derived from this software without specific prior written permission.
42 * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
43 * * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
44 * * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
45 * * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
46 * * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
47 * * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
48 * * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
49 * * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
50 * * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
51 * * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
53 * Author: Thomas Winischhofer <thomas@winischhofer.net>
55 * Formerly based on non-functional code-fragements for 300 series by SiS, Inc.
65 #ifdef CONFIG_FB_SIS_300
69 #ifdef CONFIG_FB_SIS_315
73 #if defined(ALLOC_PRAGMA)
74 #pragma alloc_text(PAGE,SiSSetMode)
77 /*********************************************/
78 /* POINTER INITIALIZATION */
79 /*********************************************/
81 #if defined(CONFIG_FB_SIS_300) || defined(CONFIG_FB_SIS_315)
83 InitCommonPointer(struct SiS_Private *SiS_Pr)
85 SiS_Pr->SiS_SModeIDTable = SiS_SModeIDTable;
86 SiS_Pr->SiS_StResInfo = SiS_StResInfo;
87 SiS_Pr->SiS_ModeResInfo = SiS_ModeResInfo;
88 SiS_Pr->SiS_StandTable = SiS_StandTable;
90 SiS_Pr->SiS_NTSCTiming = SiS_NTSCTiming;
91 SiS_Pr->SiS_PALTiming = SiS_PALTiming;
92 SiS_Pr->SiS_HiTVSt1Timing = SiS_HiTVSt1Timing;
93 SiS_Pr->SiS_HiTVSt2Timing = SiS_HiTVSt2Timing;
95 SiS_Pr->SiS_HiTVExtTiming = SiS_HiTVExtTiming;
96 SiS_Pr->SiS_HiTVGroup3Data = SiS_HiTVGroup3Data;
97 SiS_Pr->SiS_HiTVGroup3Simu = SiS_HiTVGroup3Simu;
99 SiS_Pr->SiS_HiTVTextTiming = SiS_HiTVTextTiming;
100 SiS_Pr->SiS_HiTVGroup3Text = SiS_HiTVGroup3Text;
103 SiS_Pr->SiS_StPALData = SiS_StPALData;
104 SiS_Pr->SiS_ExtPALData = SiS_ExtPALData;
105 SiS_Pr->SiS_StNTSCData = SiS_StNTSCData;
106 SiS_Pr->SiS_ExtNTSCData = SiS_ExtNTSCData;
107 SiS_Pr->SiS_St1HiTVData = SiS_StHiTVData;
108 SiS_Pr->SiS_St2HiTVData = SiS_St2HiTVData;
109 SiS_Pr->SiS_ExtHiTVData = SiS_ExtHiTVData;
110 SiS_Pr->SiS_St525iData = SiS_StNTSCData;
111 SiS_Pr->SiS_St525pData = SiS_St525pData;
112 SiS_Pr->SiS_St750pData = SiS_St750pData;
113 SiS_Pr->SiS_Ext525iData = SiS_ExtNTSCData;
114 SiS_Pr->SiS_Ext525pData = SiS_ExtNTSCData;
115 SiS_Pr->SiS_Ext750pData = SiS_Ext750pData;
117 SiS_Pr->pSiS_OutputSelect = &SiS_OutputSelect;
118 SiS_Pr->pSiS_SoftSetting = &SiS_SoftSetting;
120 SiS_Pr->SiS_LCD1280x720Data = SiS_LCD1280x720Data;
121 SiS_Pr->SiS_StLCD1280x768_2Data = SiS_StLCD1280x768_2Data;
122 SiS_Pr->SiS_ExtLCD1280x768_2Data = SiS_ExtLCD1280x768_2Data;
123 SiS_Pr->SiS_LCD1280x800Data = SiS_LCD1280x800Data;
124 SiS_Pr->SiS_LCD1280x800_2Data = SiS_LCD1280x800_2Data;
125 SiS_Pr->SiS_LCD1280x854Data = SiS_LCD1280x854Data;
126 SiS_Pr->SiS_LCD1280x960Data = SiS_LCD1280x960Data;
127 SiS_Pr->SiS_StLCD1400x1050Data = SiS_StLCD1400x1050Data;
128 SiS_Pr->SiS_ExtLCD1400x1050Data = SiS_ExtLCD1400x1050Data;
129 SiS_Pr->SiS_LCD1680x1050Data = SiS_LCD1680x1050Data;
130 SiS_Pr->SiS_StLCD1600x1200Data = SiS_StLCD1600x1200Data;
131 SiS_Pr->SiS_ExtLCD1600x1200Data = SiS_ExtLCD1600x1200Data;
132 SiS_Pr->SiS_NoScaleData = SiS_NoScaleData;
134 SiS_Pr->SiS_LVDS320x240Data_1 = SiS_LVDS320x240Data_1;
135 SiS_Pr->SiS_LVDS320x240Data_2 = SiS_LVDS320x240Data_2;
136 SiS_Pr->SiS_LVDS640x480Data_1 = SiS_LVDS640x480Data_1;
137 SiS_Pr->SiS_LVDS800x600Data_1 = SiS_LVDS800x600Data_1;
138 SiS_Pr->SiS_LVDS1024x600Data_1 = SiS_LVDS1024x600Data_1;
139 SiS_Pr->SiS_LVDS1024x768Data_1 = SiS_LVDS1024x768Data_1;
141 SiS_Pr->SiS_LVDSCRT1320x240_1 = SiS_LVDSCRT1320x240_1;
142 SiS_Pr->SiS_LVDSCRT1320x240_2 = SiS_LVDSCRT1320x240_2;
143 SiS_Pr->SiS_LVDSCRT1320x240_2_H = SiS_LVDSCRT1320x240_2_H;
144 SiS_Pr->SiS_LVDSCRT1320x240_3 = SiS_LVDSCRT1320x240_3;
145 SiS_Pr->SiS_LVDSCRT1320x240_3_H = SiS_LVDSCRT1320x240_3_H;
146 SiS_Pr->SiS_LVDSCRT1640x480_1 = SiS_LVDSCRT1640x480_1;
147 SiS_Pr->SiS_LVDSCRT1640x480_1_H = SiS_LVDSCRT1640x480_1_H;
149 SiS_Pr->SiS_LVDSCRT11024x600_1 = SiS_LVDSCRT11024x600_1;
150 SiS_Pr->SiS_LVDSCRT11024x600_1_H = SiS_LVDSCRT11024x600_1_H;
151 SiS_Pr->SiS_LVDSCRT11024x600_2 = SiS_LVDSCRT11024x600_2;
152 SiS_Pr->SiS_LVDSCRT11024x600_2_H = SiS_LVDSCRT11024x600_2_H;
155 SiS_Pr->SiS_CHTVUNTSCData = SiS_CHTVUNTSCData;
156 SiS_Pr->SiS_CHTVONTSCData = SiS_CHTVONTSCData;
158 SiS_Pr->SiS_PanelMinLVDS = Panel_800x600; /* lowest value LVDS/LCDA */
159 SiS_Pr->SiS_PanelMin301 = Panel_1024x768; /* lowest value 301 */
163 #ifdef CONFIG_FB_SIS_300
165 InitTo300Pointer(struct SiS_Private *SiS_Pr)
167 InitCommonPointer(SiS_Pr);
169 SiS_Pr->SiS_VBModeIDTable = SiS300_VBModeIDTable;
170 SiS_Pr->SiS_EModeIDTable = SiS300_EModeIDTable;
171 SiS_Pr->SiS_RefIndex = SiS300_RefIndex;
172 SiS_Pr->SiS_CRT1Table = SiS300_CRT1Table;
173 if(SiS_Pr->ChipType == SIS_300) {
174 SiS_Pr->SiS_MCLKData_0 = SiS300_MCLKData_300; /* 300 */
176 SiS_Pr->SiS_MCLKData_0 = SiS300_MCLKData_630; /* 630, 730 */
178 SiS_Pr->SiS_VCLKData = SiS300_VCLKData;
179 SiS_Pr->SiS_VBVCLKData = (struct SiS_VBVCLKData *)SiS300_VCLKData;
181 SiS_Pr->SiS_SR15 = SiS300_SR15;
183 SiS_Pr->SiS_PanelDelayTbl = SiS300_PanelDelayTbl;
184 SiS_Pr->SiS_PanelDelayTblLVDS = SiS300_PanelDelayTbl;
186 SiS_Pr->SiS_ExtLCD1024x768Data = SiS300_ExtLCD1024x768Data;
187 SiS_Pr->SiS_St2LCD1024x768Data = SiS300_St2LCD1024x768Data;
188 SiS_Pr->SiS_ExtLCD1280x1024Data = SiS300_ExtLCD1280x1024Data;
189 SiS_Pr->SiS_St2LCD1280x1024Data = SiS300_St2LCD1280x1024Data;
191 SiS_Pr->SiS_CRT2Part2_1024x768_1 = SiS300_CRT2Part2_1024x768_1;
192 SiS_Pr->SiS_CRT2Part2_1024x768_2 = SiS300_CRT2Part2_1024x768_2;
193 SiS_Pr->SiS_CRT2Part2_1024x768_3 = SiS300_CRT2Part2_1024x768_3;
195 SiS_Pr->SiS_CHTVUPALData = SiS300_CHTVUPALData;
196 SiS_Pr->SiS_CHTVOPALData = SiS300_CHTVOPALData;
197 SiS_Pr->SiS_CHTVUPALMData = SiS_CHTVUNTSCData; /* not supported on 300 series */
198 SiS_Pr->SiS_CHTVOPALMData = SiS_CHTVONTSCData; /* not supported on 300 series */
199 SiS_Pr->SiS_CHTVUPALNData = SiS300_CHTVUPALData; /* not supported on 300 series */
200 SiS_Pr->SiS_CHTVOPALNData = SiS300_CHTVOPALData; /* not supported on 300 series */
201 SiS_Pr->SiS_CHTVSOPALData = SiS300_CHTVSOPALData;
203 SiS_Pr->SiS_LVDS848x480Data_1 = SiS300_LVDS848x480Data_1;
204 SiS_Pr->SiS_LVDS848x480Data_2 = SiS300_LVDS848x480Data_2;
205 SiS_Pr->SiS_LVDSBARCO1024Data_1 = SiS300_LVDSBARCO1024Data_1;
206 SiS_Pr->SiS_LVDSBARCO1366Data_1 = SiS300_LVDSBARCO1366Data_1;
207 SiS_Pr->SiS_LVDSBARCO1366Data_2 = SiS300_LVDSBARCO1366Data_2;
209 SiS_Pr->SiS_PanelType04_1a = SiS300_PanelType04_1a;
210 SiS_Pr->SiS_PanelType04_2a = SiS300_PanelType04_2a;
211 SiS_Pr->SiS_PanelType04_1b = SiS300_PanelType04_1b;
212 SiS_Pr->SiS_PanelType04_2b = SiS300_PanelType04_2b;
214 SiS_Pr->SiS_CHTVCRT1UNTSC = SiS300_CHTVCRT1UNTSC;
215 SiS_Pr->SiS_CHTVCRT1ONTSC = SiS300_CHTVCRT1ONTSC;
216 SiS_Pr->SiS_CHTVCRT1UPAL = SiS300_CHTVCRT1UPAL;
217 SiS_Pr->SiS_CHTVCRT1OPAL = SiS300_CHTVCRT1OPAL;
218 SiS_Pr->SiS_CHTVCRT1SOPAL = SiS300_CHTVCRT1SOPAL;
219 SiS_Pr->SiS_CHTVReg_UNTSC = SiS300_CHTVReg_UNTSC;
220 SiS_Pr->SiS_CHTVReg_ONTSC = SiS300_CHTVReg_ONTSC;
221 SiS_Pr->SiS_CHTVReg_UPAL = SiS300_CHTVReg_UPAL;
222 SiS_Pr->SiS_CHTVReg_OPAL = SiS300_CHTVReg_OPAL;
223 SiS_Pr->SiS_CHTVReg_UPALM = SiS300_CHTVReg_UNTSC; /* not supported on 300 series */
224 SiS_Pr->SiS_CHTVReg_OPALM = SiS300_CHTVReg_ONTSC; /* not supported on 300 series */
225 SiS_Pr->SiS_CHTVReg_UPALN = SiS300_CHTVReg_UPAL; /* not supported on 300 series */
226 SiS_Pr->SiS_CHTVReg_OPALN = SiS300_CHTVReg_OPAL; /* not supported on 300 series */
227 SiS_Pr->SiS_CHTVReg_SOPAL = SiS300_CHTVReg_SOPAL;
228 SiS_Pr->SiS_CHTVVCLKUNTSC = SiS300_CHTVVCLKUNTSC;
229 SiS_Pr->SiS_CHTVVCLKONTSC = SiS300_CHTVVCLKONTSC;
230 SiS_Pr->SiS_CHTVVCLKUPAL = SiS300_CHTVVCLKUPAL;
231 SiS_Pr->SiS_CHTVVCLKOPAL = SiS300_CHTVVCLKOPAL;
232 SiS_Pr->SiS_CHTVVCLKUPALM = SiS300_CHTVVCLKUNTSC; /* not supported on 300 series */
233 SiS_Pr->SiS_CHTVVCLKOPALM = SiS300_CHTVVCLKONTSC; /* not supported on 300 series */
234 SiS_Pr->SiS_CHTVVCLKUPALN = SiS300_CHTVVCLKUPAL; /* not supported on 300 series */
235 SiS_Pr->SiS_CHTVVCLKOPALN = SiS300_CHTVVCLKOPAL; /* not supported on 300 series */
236 SiS_Pr->SiS_CHTVVCLKSOPAL = SiS300_CHTVVCLKSOPAL;
240 #ifdef CONFIG_FB_SIS_315
242 InitTo310Pointer(struct SiS_Private *SiS_Pr)
244 InitCommonPointer(SiS_Pr);
246 SiS_Pr->SiS_EModeIDTable = SiS310_EModeIDTable;
247 SiS_Pr->SiS_RefIndex = SiS310_RefIndex;
248 SiS_Pr->SiS_CRT1Table = SiS310_CRT1Table;
249 if(SiS_Pr->ChipType >= SIS_340) {
250 SiS_Pr->SiS_MCLKData_0 = SiS310_MCLKData_0_340; /* 340 + XGI */
251 } else if(SiS_Pr->ChipType >= SIS_761) {
252 SiS_Pr->SiS_MCLKData_0 = SiS310_MCLKData_0_761; /* 761 - preliminary */
253 } else if(SiS_Pr->ChipType >= SIS_760) {
254 SiS_Pr->SiS_MCLKData_0 = SiS310_MCLKData_0_760; /* 760 */
255 } else if(SiS_Pr->ChipType >= SIS_661) {
256 SiS_Pr->SiS_MCLKData_0 = SiS310_MCLKData_0_660; /* 661/741 */
257 } else if(SiS_Pr->ChipType == SIS_330) {
258 SiS_Pr->SiS_MCLKData_0 = SiS310_MCLKData_0_330; /* 330 */
259 } else if(SiS_Pr->ChipType > SIS_315PRO) {
260 SiS_Pr->SiS_MCLKData_0 = SiS310_MCLKData_0_650; /* 550, 650, 740 */
262 SiS_Pr->SiS_MCLKData_0 = SiS310_MCLKData_0_315; /* 315 */
264 if(SiS_Pr->ChipType >= SIS_340) {
265 SiS_Pr->SiS_MCLKData_1 = SiS310_MCLKData_1_340;
267 SiS_Pr->SiS_MCLKData_1 = SiS310_MCLKData_1;
269 SiS_Pr->SiS_VCLKData = SiS310_VCLKData;
270 SiS_Pr->SiS_VBVCLKData = SiS310_VBVCLKData;
272 SiS_Pr->SiS_SR15 = SiS310_SR15;
274 SiS_Pr->SiS_PanelDelayTbl = SiS310_PanelDelayTbl;
275 SiS_Pr->SiS_PanelDelayTblLVDS = SiS310_PanelDelayTblLVDS;
277 SiS_Pr->SiS_St2LCD1024x768Data = SiS310_St2LCD1024x768Data;
278 SiS_Pr->SiS_ExtLCD1024x768Data = SiS310_ExtLCD1024x768Data;
279 SiS_Pr->SiS_St2LCD1280x1024Data = SiS310_St2LCD1280x1024Data;
280 SiS_Pr->SiS_ExtLCD1280x1024Data = SiS310_ExtLCD1280x1024Data;
282 SiS_Pr->SiS_CRT2Part2_1024x768_1 = SiS310_CRT2Part2_1024x768_1;
284 SiS_Pr->SiS_CHTVUPALData = SiS310_CHTVUPALData;
285 SiS_Pr->SiS_CHTVOPALData = SiS310_CHTVOPALData;
286 SiS_Pr->SiS_CHTVUPALMData = SiS310_CHTVUPALMData;
287 SiS_Pr->SiS_CHTVOPALMData = SiS310_CHTVOPALMData;
288 SiS_Pr->SiS_CHTVUPALNData = SiS310_CHTVUPALNData;
289 SiS_Pr->SiS_CHTVOPALNData = SiS310_CHTVOPALNData;
290 SiS_Pr->SiS_CHTVSOPALData = SiS310_CHTVSOPALData;
292 SiS_Pr->SiS_CHTVCRT1UNTSC = SiS310_CHTVCRT1UNTSC;
293 SiS_Pr->SiS_CHTVCRT1ONTSC = SiS310_CHTVCRT1ONTSC;
294 SiS_Pr->SiS_CHTVCRT1UPAL = SiS310_CHTVCRT1UPAL;
295 SiS_Pr->SiS_CHTVCRT1OPAL = SiS310_CHTVCRT1OPAL;
296 SiS_Pr->SiS_CHTVCRT1SOPAL = SiS310_CHTVCRT1OPAL;
298 SiS_Pr->SiS_CHTVReg_UNTSC = SiS310_CHTVReg_UNTSC;
299 SiS_Pr->SiS_CHTVReg_ONTSC = SiS310_CHTVReg_ONTSC;
300 SiS_Pr->SiS_CHTVReg_UPAL = SiS310_CHTVReg_UPAL;
301 SiS_Pr->SiS_CHTVReg_OPAL = SiS310_CHTVReg_OPAL;
302 SiS_Pr->SiS_CHTVReg_UPALM = SiS310_CHTVReg_UPALM;
303 SiS_Pr->SiS_CHTVReg_OPALM = SiS310_CHTVReg_OPALM;
304 SiS_Pr->SiS_CHTVReg_UPALN = SiS310_CHTVReg_UPALN;
305 SiS_Pr->SiS_CHTVReg_OPALN = SiS310_CHTVReg_OPALN;
306 SiS_Pr->SiS_CHTVReg_SOPAL = SiS310_CHTVReg_OPAL;
308 SiS_Pr->SiS_CHTVVCLKUNTSC = SiS310_CHTVVCLKUNTSC;
309 SiS_Pr->SiS_CHTVVCLKONTSC = SiS310_CHTVVCLKONTSC;
310 SiS_Pr->SiS_CHTVVCLKUPAL = SiS310_CHTVVCLKUPAL;
311 SiS_Pr->SiS_CHTVVCLKOPAL = SiS310_CHTVVCLKOPAL;
312 SiS_Pr->SiS_CHTVVCLKUPALM = SiS310_CHTVVCLKUPALM;
313 SiS_Pr->SiS_CHTVVCLKOPALM = SiS310_CHTVVCLKOPALM;
314 SiS_Pr->SiS_CHTVVCLKUPALN = SiS310_CHTVVCLKUPALN;
315 SiS_Pr->SiS_CHTVVCLKOPALN = SiS310_CHTVVCLKOPALN;
316 SiS_Pr->SiS_CHTVVCLKSOPAL = SiS310_CHTVVCLKOPAL;
321 SiSInitPtr(struct SiS_Private *SiS_Pr)
323 if(SiS_Pr->ChipType < SIS_315H) {
324 #ifdef CONFIG_FB_SIS_300
325 InitTo300Pointer(SiS_Pr);
330 #ifdef CONFIG_FB_SIS_315
331 InitTo310Pointer(SiS_Pr);
339 /*********************************************/
340 /* HELPER: Get ModeID */
341 /*********************************************/
345 SiS_GetModeID(int VGAEngine, unsigned int VBFlags, int HDisplay, int VDisplay,
346 int Depth, bool FSTN, int LCDwidth, int LCDheight)
348 unsigned short ModeIndex = 0;
353 if(VDisplay == 200) ModeIndex = ModeIndex_320x200[Depth];
354 else if(VDisplay == 240) {
355 if((VBFlags & CRT2_LCD) && (FSTN))
356 ModeIndex = ModeIndex_320x240_FSTN[Depth];
358 ModeIndex = ModeIndex_320x240[Depth];
362 if((!(VBFlags & CRT1_LCDA)) || ((LCDwidth >= 800) && (LCDwidth >= 600))) {
363 if(VDisplay == 300) ModeIndex = ModeIndex_400x300[Depth];
367 if((!(VBFlags & CRT1_LCDA)) || ((LCDwidth >= 1024) && (LCDwidth >= 768))) {
368 if(VDisplay == 384) ModeIndex = ModeIndex_512x384[Depth];
372 if(VDisplay == 480) ModeIndex = ModeIndex_640x480[Depth];
373 else if(VDisplay == 400) ModeIndex = ModeIndex_640x400[Depth];
376 if(VDisplay == 480) ModeIndex = ModeIndex_720x480[Depth];
377 else if(VDisplay == 576) ModeIndex = ModeIndex_720x576[Depth];
380 if(VDisplay == 576) ModeIndex = ModeIndex_768x576[Depth];
383 if(VDisplay == 600) ModeIndex = ModeIndex_800x600[Depth];
384 else if(VDisplay == 480) ModeIndex = ModeIndex_800x480[Depth];
387 if(VDisplay == 480) ModeIndex = ModeIndex_848x480[Depth];
390 if(VDisplay == 480) ModeIndex = ModeIndex_856x480[Depth];
393 if(VGAEngine == SIS_315_VGA) {
394 if(VDisplay == 540) ModeIndex = ModeIndex_960x540[Depth];
395 else if(VDisplay == 600) ModeIndex = ModeIndex_960x600[Depth];
399 if(VDisplay == 576) ModeIndex = ModeIndex_1024x576[Depth];
400 else if(VDisplay == 768) ModeIndex = ModeIndex_1024x768[Depth];
401 else if(VGAEngine == SIS_300_VGA) {
402 if(VDisplay == 600) ModeIndex = ModeIndex_1024x600[Depth];
406 if(VDisplay == 864) ModeIndex = ModeIndex_1152x864[Depth];
407 if(VGAEngine == SIS_300_VGA) {
408 if(VDisplay == 768) ModeIndex = ModeIndex_1152x768[Depth];
414 ModeIndex = ModeIndex_1280x720[Depth];
417 if(VGAEngine == SIS_300_VGA) {
418 ModeIndex = ModeIndex_300_1280x768[Depth];
420 ModeIndex = ModeIndex_310_1280x768[Depth];
424 if(VGAEngine == SIS_315_VGA) {
425 ModeIndex = ModeIndex_1280x800[Depth];
429 if(VGAEngine == SIS_315_VGA) {
430 ModeIndex = ModeIndex_1280x854[Depth];
434 ModeIndex = ModeIndex_1280x960[Depth];
437 ModeIndex = ModeIndex_1280x1024[Depth];
442 if(VDisplay == 768) ModeIndex = ModeIndex_1360x768[Depth];
443 if(VGAEngine == SIS_300_VGA) {
444 if(VDisplay == 1024) ModeIndex = ModeIndex_300_1360x1024[Depth];
448 if(VGAEngine == SIS_315_VGA) {
449 if(VDisplay == 1050) {
450 ModeIndex = ModeIndex_1400x1050[Depth];
455 if(VDisplay == 1200) ModeIndex = ModeIndex_1600x1200[Depth];
458 if(VGAEngine == SIS_315_VGA) {
459 if(VDisplay == 1050) ModeIndex = ModeIndex_1680x1050[Depth];
463 if(VDisplay == 1440) ModeIndex = ModeIndex_1920x1440[Depth];
464 else if(VGAEngine == SIS_315_VGA) {
465 if(VDisplay == 1080) ModeIndex = ModeIndex_1920x1080[Depth];
469 if(VDisplay == 1536) {
470 if(VGAEngine == SIS_300_VGA) {
471 ModeIndex = ModeIndex_300_2048x1536[Depth];
473 ModeIndex = ModeIndex_310_2048x1536[Depth];
483 SiS_GetModeID_LCD(int VGAEngine, unsigned int VBFlags, int HDisplay, int VDisplay,
484 int Depth, bool FSTN, unsigned short CustomT, int LCDwidth, int LCDheight,
485 unsigned int VBFlags2)
487 unsigned short ModeIndex = 0;
489 if(VBFlags2 & (VB2_LVDS | VB2_30xBDH)) {
494 if((CustomT != CUT_PANEL848) && (CustomT != CUT_PANEL856)) {
495 if(VDisplay == 200) {
496 if(!FSTN) ModeIndex = ModeIndex_320x200[Depth];
497 } else if(VDisplay == 240) {
498 if(!FSTN) ModeIndex = ModeIndex_320x240[Depth];
499 else if(VGAEngine == SIS_315_VGA) {
500 ModeIndex = ModeIndex_320x240_FSTN[Depth];
506 if((CustomT != CUT_PANEL848) && (CustomT != CUT_PANEL856)) {
507 if(!((VGAEngine == SIS_300_VGA) && (VBFlags2 & VB2_TRUMPION))) {
508 if(VDisplay == 300) ModeIndex = ModeIndex_400x300[Depth];
513 if((CustomT != CUT_PANEL848) && (CustomT != CUT_PANEL856)) {
514 if(!((VGAEngine == SIS_300_VGA) && (VBFlags2 & VB2_TRUMPION))) {
515 if(LCDwidth >= 1024 && LCDwidth != 1152 && LCDheight >= 768) {
516 if(VDisplay == 384) {
517 ModeIndex = ModeIndex_512x384[Depth];
524 if(VDisplay == 480) ModeIndex = ModeIndex_640x480[Depth];
525 else if(VDisplay == 400) {
526 if((CustomT != CUT_PANEL848) && (CustomT != CUT_PANEL856))
527 ModeIndex = ModeIndex_640x400[Depth];
531 if(VDisplay == 600) ModeIndex = ModeIndex_800x600[Depth];
534 if(CustomT == CUT_PANEL848) {
535 if(VDisplay == 480) ModeIndex = ModeIndex_848x480[Depth];
539 if(CustomT == CUT_PANEL856) {
540 if(VDisplay == 480) ModeIndex = ModeIndex_856x480[Depth];
544 if(VDisplay == 768) ModeIndex = ModeIndex_1024x768[Depth];
545 else if(VGAEngine == SIS_300_VGA) {
546 if((VDisplay == 600) && (LCDheight == 600)) {
547 ModeIndex = ModeIndex_1024x600[Depth];
552 if(VGAEngine == SIS_300_VGA) {
553 if((VDisplay == 768) && (LCDheight == 768)) {
554 ModeIndex = ModeIndex_1152x768[Depth];
559 if(VDisplay == 1024) ModeIndex = ModeIndex_1280x1024[Depth];
560 else if(VGAEngine == SIS_315_VGA) {
561 if((VDisplay == 768) && (LCDheight == 768)) {
562 ModeIndex = ModeIndex_310_1280x768[Depth];
567 if(VGAEngine == SIS_300_VGA) {
568 if(CustomT == CUT_BARCO1366) {
569 if(VDisplay == 1024) ModeIndex = ModeIndex_300_1360x1024[Depth];
572 if(CustomT == CUT_PANEL848) {
573 if(VDisplay == 768) ModeIndex = ModeIndex_1360x768[Depth];
577 if(VGAEngine == SIS_315_VGA) {
578 if(VDisplay == 1050) ModeIndex = ModeIndex_1400x1050[Depth];
582 if(VGAEngine == SIS_315_VGA) {
583 if(VDisplay == 1200) ModeIndex = ModeIndex_1600x1200[Depth];
588 } else if(VBFlags2 & VB2_SISBRIDGE) {
593 if(VDisplay == 200) ModeIndex = ModeIndex_320x200[Depth];
594 else if(VDisplay == 240) ModeIndex = ModeIndex_320x240[Depth];
597 if(LCDwidth >= 800 && LCDheight >= 600) {
598 if(VDisplay == 300) ModeIndex = ModeIndex_400x300[Depth];
602 if(LCDwidth >= 1024 && LCDheight >= 768 && LCDwidth != 1152) {
603 if(VDisplay == 384) ModeIndex = ModeIndex_512x384[Depth];
607 if(VDisplay == 480) ModeIndex = ModeIndex_640x480[Depth];
608 else if(VDisplay == 400) ModeIndex = ModeIndex_640x400[Depth];
611 if(VGAEngine == SIS_315_VGA) {
612 if(VDisplay == 480) ModeIndex = ModeIndex_720x480[Depth];
613 else if(VDisplay == 576) ModeIndex = ModeIndex_720x576[Depth];
617 if(VGAEngine == SIS_315_VGA) {
618 if(VDisplay == 576) ModeIndex = ModeIndex_768x576[Depth];
622 if(VDisplay == 600) ModeIndex = ModeIndex_800x600[Depth];
623 if(VGAEngine == SIS_315_VGA) {
624 if(VDisplay == 480) ModeIndex = ModeIndex_800x480[Depth];
628 if(VGAEngine == SIS_315_VGA) {
629 if(VDisplay == 480) ModeIndex = ModeIndex_848x480[Depth];
633 if(VGAEngine == SIS_315_VGA) {
634 if(VDisplay == 480) ModeIndex = ModeIndex_856x480[Depth];
638 if(VGAEngine == SIS_315_VGA) {
639 if(VDisplay == 540) ModeIndex = ModeIndex_960x540[Depth];
640 else if(VDisplay == 600) ModeIndex = ModeIndex_960x600[Depth];
644 if(VDisplay == 768) ModeIndex = ModeIndex_1024x768[Depth];
645 if(VGAEngine == SIS_315_VGA) {
646 if(VDisplay == 576) ModeIndex = ModeIndex_1024x576[Depth];
650 if(VGAEngine == SIS_315_VGA) {
651 if(VDisplay == 864) ModeIndex = ModeIndex_1152x864[Depth];
657 ModeIndex = ModeIndex_1280x720[Depth];
659 if(VGAEngine == SIS_300_VGA) {
660 ModeIndex = ModeIndex_300_1280x768[Depth];
662 ModeIndex = ModeIndex_310_1280x768[Depth];
666 if(VGAEngine == SIS_315_VGA) {
667 ModeIndex = ModeIndex_1280x800[Depth];
671 if(VGAEngine == SIS_315_VGA) {
672 ModeIndex = ModeIndex_1280x854[Depth];
676 ModeIndex = ModeIndex_1280x960[Depth];
679 ModeIndex = ModeIndex_1280x1024[Depth];
684 if(VGAEngine == SIS_315_VGA) { /* OVER1280 only? */
685 if(VDisplay == 768) ModeIndex = ModeIndex_1360x768[Depth];
689 if(VGAEngine == SIS_315_VGA) {
690 if(VBFlags2 & VB2_LCDOVER1280BRIDGE) {
691 if(VDisplay == 1050) ModeIndex = ModeIndex_1400x1050[Depth];
696 if(VGAEngine == SIS_315_VGA) {
697 if(VBFlags2 & VB2_LCDOVER1280BRIDGE) {
698 if(VDisplay == 1200) ModeIndex = ModeIndex_1600x1200[Depth];
702 #ifndef VB_FORBID_CRT2LCD_OVER_1600
704 if(VGAEngine == SIS_315_VGA) {
705 if(VBFlags2 & VB2_LCDOVER1280BRIDGE) {
706 if(VDisplay == 1050) ModeIndex = ModeIndex_1680x1050[Depth];
711 if(VGAEngine == SIS_315_VGA) {
712 if(VBFlags2 & VB2_LCDOVER1600BRIDGE) {
713 if(VDisplay == 1440) ModeIndex = ModeIndex_1920x1440[Depth];
718 if(VGAEngine == SIS_315_VGA) {
719 if(VBFlags2 & VB2_LCDOVER1600BRIDGE) {
720 if(VDisplay == 1536) ModeIndex = ModeIndex_310_2048x1536[Depth];
732 SiS_GetModeID_TV(int VGAEngine, unsigned int VBFlags, int HDisplay, int VDisplay, int Depth,
733 unsigned int VBFlags2)
735 unsigned short ModeIndex = 0;
737 if(VBFlags2 & VB2_CHRONTEL) {
742 if(VGAEngine == SIS_315_VGA) {
743 if(VDisplay == 384) ModeIndex = ModeIndex_512x384[Depth];
747 if(VDisplay == 480) ModeIndex = ModeIndex_640x480[Depth];
748 else if(VDisplay == 400) ModeIndex = ModeIndex_640x400[Depth];
751 if(VDisplay == 600) ModeIndex = ModeIndex_800x600[Depth];
754 if(VGAEngine == SIS_315_VGA) {
755 if(VDisplay == 768) ModeIndex = ModeIndex_1024x768[Depth];
760 } else if(VBFlags2 & VB2_SISTVBRIDGE) {
765 if(VDisplay == 200) ModeIndex = ModeIndex_320x200[Depth];
766 else if(VDisplay == 240) ModeIndex = ModeIndex_320x240[Depth];
769 if(VDisplay == 300) ModeIndex = ModeIndex_400x300[Depth];
772 if( ((VBFlags & TV_YPBPR) && (VBFlags & (TV_YPBPR750P | TV_YPBPR1080I))) ||
773 (VBFlags & TV_HIVISION) ||
774 ((!(VBFlags & (TV_YPBPR | TV_PALM))) && (VBFlags & TV_PAL)) ) {
775 if(VDisplay == 384) ModeIndex = ModeIndex_512x384[Depth];
779 if(VDisplay == 480) ModeIndex = ModeIndex_640x480[Depth];
780 else if(VDisplay == 400) ModeIndex = ModeIndex_640x400[Depth];
783 if((!(VBFlags & TV_HIVISION)) && (!((VBFlags & TV_YPBPR) && (VBFlags & TV_YPBPR1080I)))) {
784 if(VDisplay == 480) {
785 ModeIndex = ModeIndex_720x480[Depth];
786 } else if(VDisplay == 576) {
787 if( ((VBFlags & TV_YPBPR) && (VBFlags & TV_YPBPR750P)) ||
788 ((!(VBFlags & (TV_YPBPR | TV_PALM))) && (VBFlags & TV_PAL)) )
789 ModeIndex = ModeIndex_720x576[Depth];
794 if((!(VBFlags & TV_HIVISION)) && (!((VBFlags & TV_YPBPR) && (VBFlags & TV_YPBPR1080I)))) {
795 if( ((VBFlags & TV_YPBPR) && (VBFlags & TV_YPBPR750P)) ||
796 ((!(VBFlags & (TV_YPBPR | TV_PALM))) && (VBFlags & TV_PAL)) ) {
797 if(VDisplay == 576) ModeIndex = ModeIndex_768x576[Depth];
802 if(VDisplay == 600) ModeIndex = ModeIndex_800x600[Depth];
803 else if(VDisplay == 480) {
804 if(!((VBFlags & TV_YPBPR) && (VBFlags & TV_YPBPR750P))) {
805 ModeIndex = ModeIndex_800x480[Depth];
810 if(VGAEngine == SIS_315_VGA) {
811 if(VDisplay == 600) {
812 if((VBFlags & TV_HIVISION) || ((VBFlags & TV_YPBPR) && (VBFlags & TV_YPBPR1080I))) {
813 ModeIndex = ModeIndex_960x600[Depth];
819 if(VDisplay == 768) {
820 if(VBFlags2 & VB2_30xBLV) {
821 ModeIndex = ModeIndex_1024x768[Depth];
823 } else if(VDisplay == 576) {
824 if( (VBFlags & TV_HIVISION) ||
825 ((VBFlags & TV_YPBPR) && (VBFlags & TV_YPBPR1080I)) ||
826 ((VBFlags2 & VB2_30xBLV) &&
827 ((!(VBFlags & (TV_YPBPR | TV_PALM))) && (VBFlags & TV_PAL))) ) {
828 ModeIndex = ModeIndex_1024x576[Depth];
833 if(VDisplay == 720) {
834 if((VBFlags & TV_HIVISION) ||
835 ((VBFlags & TV_YPBPR) && (VBFlags & (TV_YPBPR1080I | TV_YPBPR750P)))) {
836 ModeIndex = ModeIndex_1280x720[Depth];
838 } else if(VDisplay == 1024) {
839 if((VBFlags & TV_HIVISION) ||
840 ((VBFlags & TV_YPBPR) && (VBFlags & TV_YPBPR1080I))) {
841 ModeIndex = ModeIndex_1280x1024[Depth];
851 SiS_GetModeID_VGA2(int VGAEngine, unsigned int VBFlags, int HDisplay, int VDisplay, int Depth,
852 unsigned int VBFlags2)
854 if(!(VBFlags2 & VB2_SISVGA2BRIDGE)) return 0;
856 if(HDisplay >= 1920) return 0;
861 if(VDisplay == 1200) {
862 if(VGAEngine != SIS_315_VGA) return 0;
863 if(!(VBFlags2 & VB2_30xB)) return 0;
867 if(VDisplay == 1050) {
868 if(VGAEngine != SIS_315_VGA) return 0;
869 if(!(VBFlags2 & VB2_30xB)) return 0;
874 return SiS_GetModeID(VGAEngine, 0, HDisplay, VDisplay, Depth, false, 0, 0);
878 /*********************************************/
879 /* HELPER: SetReg, GetReg */
880 /*********************************************/
883 SiS_SetReg(SISIOADDRESS port, unsigned short index, unsigned short data)
885 outb((u8)index, port);
886 outb((u8)data, port + 1);
890 SiS_SetRegByte(SISIOADDRESS port, unsigned short data)
892 outb((u8)data, port);
896 SiS_SetRegShort(SISIOADDRESS port, unsigned short data)
898 outw((u16)data, port);
902 SiS_SetRegLong(SISIOADDRESS port, unsigned int data)
904 outl((u32)data, port);
908 SiS_GetReg(SISIOADDRESS port, unsigned short index)
910 outb((u8)index, port);
911 return inb(port + 1);
915 SiS_GetRegByte(SISIOADDRESS port)
921 SiS_GetRegShort(SISIOADDRESS port)
927 SiS_GetRegLong(SISIOADDRESS port)
933 SiS_SetRegANDOR(SISIOADDRESS Port, unsigned short Index, unsigned short DataAND, unsigned short DataOR)
937 temp = SiS_GetReg(Port, Index);
938 temp = (temp & (DataAND)) | DataOR;
939 SiS_SetReg(Port, Index, temp);
943 SiS_SetRegAND(SISIOADDRESS Port, unsigned short Index, unsigned short DataAND)
947 temp = SiS_GetReg(Port, Index);
949 SiS_SetReg(Port, Index, temp);
953 SiS_SetRegOR(SISIOADDRESS Port, unsigned short Index, unsigned short DataOR)
957 temp = SiS_GetReg(Port, Index);
959 SiS_SetReg(Port, Index, temp);
962 /*********************************************/
963 /* HELPER: DisplayOn, DisplayOff */
964 /*********************************************/
967 SiS_DisplayOn(struct SiS_Private *SiS_Pr)
969 SiS_SetRegAND(SiS_Pr->SiS_P3c4,0x01,0xDF);
973 SiS_DisplayOff(struct SiS_Private *SiS_Pr)
975 SiS_SetRegOR(SiS_Pr->SiS_P3c4,0x01,0x20);
979 /*********************************************/
980 /* HELPER: Init Port Addresses */
981 /*********************************************/
984 SiSRegInit(struct SiS_Private *SiS_Pr, SISIOADDRESS BaseAddr)
986 SiS_Pr->SiS_P3c4 = BaseAddr + 0x14;
987 SiS_Pr->SiS_P3d4 = BaseAddr + 0x24;
988 SiS_Pr->SiS_P3c0 = BaseAddr + 0x10;
989 SiS_Pr->SiS_P3ce = BaseAddr + 0x1e;
990 SiS_Pr->SiS_P3c2 = BaseAddr + 0x12;
991 SiS_Pr->SiS_P3ca = BaseAddr + 0x1a;
992 SiS_Pr->SiS_P3c6 = BaseAddr + 0x16;
993 SiS_Pr->SiS_P3c7 = BaseAddr + 0x17;
994 SiS_Pr->SiS_P3c8 = BaseAddr + 0x18;
995 SiS_Pr->SiS_P3c9 = BaseAddr + 0x19;
996 SiS_Pr->SiS_P3cb = BaseAddr + 0x1b;
997 SiS_Pr->SiS_P3cc = BaseAddr + 0x1c;
998 SiS_Pr->SiS_P3cd = BaseAddr + 0x1d;
999 SiS_Pr->SiS_P3da = BaseAddr + 0x2a;
1000 SiS_Pr->SiS_Part1Port = BaseAddr + SIS_CRT2_PORT_04;
1001 SiS_Pr->SiS_Part2Port = BaseAddr + SIS_CRT2_PORT_10;
1002 SiS_Pr->SiS_Part3Port = BaseAddr + SIS_CRT2_PORT_12;
1003 SiS_Pr->SiS_Part4Port = BaseAddr + SIS_CRT2_PORT_14;
1004 SiS_Pr->SiS_Part5Port = BaseAddr + SIS_CRT2_PORT_14 + 2;
1005 SiS_Pr->SiS_DDC_Port = BaseAddr + 0x14;
1006 SiS_Pr->SiS_VidCapt = BaseAddr + SIS_VIDEO_CAPTURE;
1007 SiS_Pr->SiS_VidPlay = BaseAddr + SIS_VIDEO_PLAYBACK;
1010 /*********************************************/
1011 /* HELPER: GetSysFlags */
1012 /*********************************************/
1015 SiS_GetSysFlags(struct SiS_Private *SiS_Pr)
1017 unsigned char cr5f, temp1, temp2;
1019 /* 661 and newer: NEVER write non-zero to SR11[7:4] */
1020 /* (SR11 is used for DDC and in enable/disablebridge) */
1021 SiS_Pr->SiS_SensibleSR11 = false;
1022 SiS_Pr->SiS_MyCR63 = 0x63;
1023 if(SiS_Pr->ChipType >= SIS_330) {
1024 SiS_Pr->SiS_MyCR63 = 0x53;
1025 if(SiS_Pr->ChipType >= SIS_661) {
1026 SiS_Pr->SiS_SensibleSR11 = true;
1030 /* You should use the macros, not these flags directly */
1032 SiS_Pr->SiS_SysFlags = 0;
1033 if(SiS_Pr->ChipType == SIS_650) {
1034 cr5f = SiS_GetReg(SiS_Pr->SiS_P3d4,0x5f) & 0xf0;
1035 SiS_SetRegAND(SiS_Pr->SiS_P3d4,0x5c,0x07);
1036 temp1 = SiS_GetReg(SiS_Pr->SiS_P3d4,0x5c) & 0xf8;
1037 SiS_SetRegOR(SiS_Pr->SiS_P3d4,0x5c,0xf8);
1038 temp2 = SiS_GetReg(SiS_Pr->SiS_P3d4,0x5c) & 0xf8;
1039 if((!temp1) || (temp2)) {
1044 SiS_Pr->SiS_SysFlags |= SF_IsM650;
1049 SiS_Pr->SiS_SysFlags |= SF_Is651;
1055 temp1 = SiS_GetReg(SiS_Pr->SiS_P3d4,0x5c) & 0xf8;
1057 case 0x00: SiS_Pr->SiS_SysFlags |= SF_IsM652; break;
1058 case 0x40: SiS_Pr->SiS_SysFlags |= SF_IsM653; break;
1059 default: SiS_Pr->SiS_SysFlags |= SF_IsM650; break;
1063 SiS_Pr->SiS_SysFlags |= SF_Is652;
1066 SiS_Pr->SiS_SysFlags |= SF_IsM650;
1072 if(SiS_Pr->ChipType >= SIS_760 && SiS_Pr->ChipType <= SIS_761) {
1073 if(SiS_GetReg(SiS_Pr->SiS_P3d4,0x78) & 0x30) {
1074 SiS_Pr->SiS_SysFlags |= SF_760LFB;
1076 if(SiS_GetReg(SiS_Pr->SiS_P3d4,0x79) & 0xf0) {
1077 SiS_Pr->SiS_SysFlags |= SF_760UMA;
1082 /*********************************************/
1083 /* HELPER: Init PCI & Engines */
1084 /*********************************************/
1087 SiSInitPCIetc(struct SiS_Private *SiS_Pr)
1089 switch(SiS_Pr->ChipType) {
1090 #ifdef CONFIG_FB_SIS_300
1095 /* Set - PCI LINEAR ADDRESSING ENABLE (0x80)
1096 * - RELOCATED VGA IO ENABLED (0x20)
1097 * - MMIO ENABLED (0x01)
1098 * Leave other bits untouched.
1100 SiS_SetRegOR(SiS_Pr->SiS_P3c4,0x20,0xa1);
1101 /* - Enable 2D (0x40)
1102 * - Enable 3D (0x02)
1103 * - Enable 3D Vertex command fetch (0x10) ?
1104 * - Enable 3D command parser (0x08) ?
1106 SiS_SetRegOR(SiS_Pr->SiS_P3c4,0x1E,0x5A);
1109 #ifdef CONFIG_FB_SIS_315
1124 SiS_SetRegOR(SiS_Pr->SiS_P3c4,0x20,0xa1);
1125 /* - Enable 3D G/L transformation engine (0x80)
1126 * - Enable 2D (0x40)
1127 * - Enable 3D vertex command fetch (0x10)
1128 * - Enable 3D command parser (0x08)
1129 * - Enable 3D (0x02)
1131 SiS_SetRegOR(SiS_Pr->SiS_P3c4,0x1E,0xDA);
1136 SiS_SetRegOR(SiS_Pr->SiS_P3c4,0x20,0xa1);
1137 /* No 3D engine ! */
1138 /* - Enable 2D (0x40)
1141 SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x1E,0x60,0x40);
1149 /*********************************************/
1150 /* HELPER: SetLVDSetc */
1151 /*********************************************/
1155 SiSSetLVDSetc(struct SiS_Private *SiS_Pr)
1157 unsigned short temp;
1159 SiS_Pr->SiS_IF_DEF_LVDS = 0;
1160 SiS_Pr->SiS_IF_DEF_TRUMPION = 0;
1161 SiS_Pr->SiS_IF_DEF_CH70xx = 0;
1162 SiS_Pr->SiS_IF_DEF_CONEX = 0;
1164 SiS_Pr->SiS_ChrontelInit = 0;
1166 if(SiS_Pr->ChipType == XGI_20) return;
1168 /* Check for SiS30x first */
1169 temp = SiS_GetReg(SiS_Pr->SiS_Part4Port,0x00);
1170 if((temp == 1) || (temp == 2)) return;
1172 switch(SiS_Pr->ChipType) {
1173 #ifdef CONFIG_FB_SIS_300
1177 temp = (SiS_GetReg(SiS_Pr->SiS_P3d4,0x37) & 0x0e) >> 1;
1178 if((temp >= 2) && (temp <= 5)) SiS_Pr->SiS_IF_DEF_LVDS = 1;
1179 if(temp == 3) SiS_Pr->SiS_IF_DEF_TRUMPION = 1;
1180 if((temp == 4) || (temp == 5)) {
1181 /* Save power status (and error check) - UNUSED */
1182 SiS_Pr->SiS_Backup70xx = SiS_GetCH700x(SiS_Pr, 0x0e);
1183 SiS_Pr->SiS_IF_DEF_CH70xx = 1;
1187 #ifdef CONFIG_FB_SIS_315
1192 temp = (SiS_GetReg(SiS_Pr->SiS_P3d4,0x37) & 0x0e) >> 1;
1193 if((temp >= 2) && (temp <= 3)) SiS_Pr->SiS_IF_DEF_LVDS = 1;
1194 if(temp == 3) SiS_Pr->SiS_IF_DEF_CH70xx = 2;
1204 temp = (SiS_GetReg(SiS_Pr->SiS_P3d4,0x38) & 0xe0) >> 5;
1205 if((temp >= 2) && (temp <= 3)) SiS_Pr->SiS_IF_DEF_LVDS = 1;
1206 if(temp == 3) SiS_Pr->SiS_IF_DEF_CH70xx = 2;
1207 if(temp == 4) SiS_Pr->SiS_IF_DEF_CONEX = 1; /* Not yet supported */
1215 /*********************************************/
1216 /* HELPER: Enable DSTN/FSTN */
1217 /*********************************************/
1220 SiS_SetEnableDstn(struct SiS_Private *SiS_Pr, int enable)
1222 SiS_Pr->SiS_IF_DEF_DSTN = enable ? 1 : 0;
1226 SiS_SetEnableFstn(struct SiS_Private *SiS_Pr, int enable)
1228 SiS_Pr->SiS_IF_DEF_FSTN = enable ? 1 : 0;
1231 /*********************************************/
1232 /* HELPER: Get modeflag */
1233 /*********************************************/
1236 SiS_GetModeFlag(struct SiS_Private *SiS_Pr, unsigned short ModeNo,
1237 unsigned short ModeIdIndex)
1239 if(SiS_Pr->UseCustomMode) {
1240 return SiS_Pr->CModeFlag;
1241 } else if(ModeNo <= 0x13) {
1242 return SiS_Pr->SiS_SModeIDTable[ModeIdIndex].St_ModeFlag;
1244 return SiS_Pr->SiS_EModeIDTable[ModeIdIndex].Ext_ModeFlag;
1248 /*********************************************/
1249 /* HELPER: Determine ROM usage */
1250 /*********************************************/
1253 SiSDetermineROMLayout661(struct SiS_Private *SiS_Pr)
1255 unsigned char *ROMAddr = SiS_Pr->VirtualRomBase;
1256 unsigned short romversoffs, romvmaj = 1, romvmin = 0;
1258 if(SiS_Pr->ChipType >= XGI_20) {
1259 /* XGI ROMs don't qualify */
1261 } else if(SiS_Pr->ChipType >= SIS_761) {
1262 /* I very much assume 761, 340 and newer will use new layout */
1264 } else if(SiS_Pr->ChipType >= SIS_661) {
1265 if((ROMAddr[0x1a] == 'N') &&
1266 (ROMAddr[0x1b] == 'e') &&
1267 (ROMAddr[0x1c] == 'w') &&
1268 (ROMAddr[0x1d] == 'V')) {
1271 romversoffs = ROMAddr[0x16] | (ROMAddr[0x17] << 8);
1273 if((ROMAddr[romversoffs+1] == '.') || (ROMAddr[romversoffs+4] == '.')) {
1274 romvmaj = ROMAddr[romversoffs] - '0';
1275 romvmin = ((ROMAddr[romversoffs+2] -'0') * 10) + (ROMAddr[romversoffs+3] - '0');
1278 if((romvmaj != 0) || (romvmin >= 92)) {
1281 } else if(IS_SIS650740) {
1282 if((ROMAddr[0x1a] == 'N') &&
1283 (ROMAddr[0x1b] == 'e') &&
1284 (ROMAddr[0x1c] == 'w') &&
1285 (ROMAddr[0x1d] == 'V')) {
1293 SiSDetermineROMUsage(struct SiS_Private *SiS_Pr)
1295 unsigned char *ROMAddr = SiS_Pr->VirtualRomBase;
1296 unsigned short romptr = 0;
1298 SiS_Pr->SiS_UseROM = false;
1299 SiS_Pr->SiS_ROMNew = false;
1300 SiS_Pr->SiS_PWDOffset = 0;
1302 if(SiS_Pr->ChipType >= XGI_20) return;
1304 if((ROMAddr) && (SiS_Pr->UseROM)) {
1305 if(SiS_Pr->ChipType == SIS_300) {
1306 /* 300: We check if the code starts below 0x220 by
1307 * checking the jmp instruction at the beginning
1308 * of the BIOS image.
1310 if((ROMAddr[3] == 0xe9) && ((ROMAddr[5] << 8) | ROMAddr[4]) > 0x21a)
1311 SiS_Pr->SiS_UseROM = true;
1312 } else if(SiS_Pr->ChipType < SIS_315H) {
1313 /* Sony's VAIO BIOS 1.09 follows the standard, so perhaps
1314 * the others do as well
1316 SiS_Pr->SiS_UseROM = true;
1318 /* 315/330 series stick to the standard(s) */
1319 SiS_Pr->SiS_UseROM = true;
1320 if((SiS_Pr->SiS_ROMNew = SiSDetermineROMLayout661(SiS_Pr))) {
1321 SiS_Pr->SiS_EMIOffset = 14;
1322 SiS_Pr->SiS_PWDOffset = 17;
1323 SiS_Pr->SiS661LCD2TableSize = 36;
1324 /* Find out about LCD data table entry size */
1325 if((romptr = SISGETROMW(0x0102))) {
1326 if(ROMAddr[romptr + (32 * 16)] == 0xff)
1327 SiS_Pr->SiS661LCD2TableSize = 32;
1328 else if(ROMAddr[romptr + (34 * 16)] == 0xff)
1329 SiS_Pr->SiS661LCD2TableSize = 34;
1330 else if(ROMAddr[romptr + (36 * 16)] == 0xff) /* 0.94, 2.05.00+ */
1331 SiS_Pr->SiS661LCD2TableSize = 36;
1332 else if( (ROMAddr[romptr + (38 * 16)] == 0xff) || /* 2.00.00 - 2.02.00 */
1333 (ROMAddr[0x6F] & 0x01) ) { /* 2.03.00 - <2.05.00 */
1334 SiS_Pr->SiS661LCD2TableSize = 38; /* UMC data layout abandoned at 2.05.00 */
1335 SiS_Pr->SiS_EMIOffset = 16;
1336 SiS_Pr->SiS_PWDOffset = 19;
1344 /*********************************************/
1345 /* HELPER: SET SEGMENT REGISTERS */
1346 /*********************************************/
1349 SiS_SetSegRegLower(struct SiS_Private *SiS_Pr, unsigned short value)
1351 unsigned short temp;
1354 temp = SiS_GetRegByte(SiS_Pr->SiS_P3cb) & 0xf0;
1355 temp |= (value >> 4);
1356 SiS_SetRegByte(SiS_Pr->SiS_P3cb, temp);
1357 temp = SiS_GetRegByte(SiS_Pr->SiS_P3cd) & 0xf0;
1358 temp |= (value & 0x0f);
1359 SiS_SetRegByte(SiS_Pr->SiS_P3cd, temp);
1363 SiS_SetSegRegUpper(struct SiS_Private *SiS_Pr, unsigned short value)
1365 unsigned short temp;
1368 temp = SiS_GetRegByte(SiS_Pr->SiS_P3cb) & 0x0f;
1369 temp |= (value & 0xf0);
1370 SiS_SetRegByte(SiS_Pr->SiS_P3cb, temp);
1371 temp = SiS_GetRegByte(SiS_Pr->SiS_P3cd) & 0x0f;
1372 temp |= (value << 4);
1373 SiS_SetRegByte(SiS_Pr->SiS_P3cd, temp);
1377 SiS_SetSegmentReg(struct SiS_Private *SiS_Pr, unsigned short value)
1379 SiS_SetSegRegLower(SiS_Pr, value);
1380 SiS_SetSegRegUpper(SiS_Pr, value);
1384 SiS_ResetSegmentReg(struct SiS_Private *SiS_Pr)
1386 SiS_SetSegmentReg(SiS_Pr, 0);
1390 SiS_SetSegmentRegOver(struct SiS_Private *SiS_Pr, unsigned short value)
1392 unsigned short temp = value >> 8;
1395 temp |= (temp << 4);
1396 SiS_SetReg(SiS_Pr->SiS_P3c4,0x1d,temp);
1397 SiS_SetSegmentReg(SiS_Pr, value);
1401 SiS_ResetSegmentRegOver(struct SiS_Private *SiS_Pr)
1403 SiS_SetSegmentRegOver(SiS_Pr, 0);
1407 SiS_ResetSegmentRegisters(struct SiS_Private *SiS_Pr)
1409 if((IS_SIS65x) || (SiS_Pr->ChipType >= SIS_661)) {
1410 SiS_ResetSegmentReg(SiS_Pr);
1411 SiS_ResetSegmentRegOver(SiS_Pr);
1415 /*********************************************/
1416 /* HELPER: GetVBType */
1417 /*********************************************/
1421 SiS_GetVBType(struct SiS_Private *SiS_Pr)
1423 unsigned short flag = 0, rev = 0, nolcd = 0;
1424 unsigned short p4_0f, p4_25, p4_27;
1426 SiS_Pr->SiS_VBType = 0;
1428 if((SiS_Pr->SiS_IF_DEF_LVDS) || (SiS_Pr->SiS_IF_DEF_CONEX))
1431 if(SiS_Pr->ChipType == XGI_20)
1434 flag = SiS_GetReg(SiS_Pr->SiS_Part4Port,0x00);
1439 rev = SiS_GetReg(SiS_Pr->SiS_Part4Port,0x01);
1442 SiS_Pr->SiS_VBType = VB_SIS302B;
1443 } else if(flag == 1) {
1445 SiS_Pr->SiS_VBType = VB_SIS301C;
1446 } else if(rev >= 0xB0) {
1447 SiS_Pr->SiS_VBType = VB_SIS301B;
1448 /* Check if 30xB DH version (no LCD support, use Panel Link instead) */
1449 nolcd = SiS_GetReg(SiS_Pr->SiS_Part4Port,0x23);
1450 if(!(nolcd & 0x02)) SiS_Pr->SiS_VBType |= VB_NoLCD;
1452 SiS_Pr->SiS_VBType = VB_SIS301;
1455 if(SiS_Pr->SiS_VBType & (VB_SIS301B | VB_SIS301C | VB_SIS302B)) {
1457 flag = SiS_GetReg(SiS_Pr->SiS_Part4Port,0x39);
1458 if(flag == 0xff) SiS_Pr->SiS_VBType = VB_SIS302LV;
1459 else SiS_Pr->SiS_VBType = VB_SIS301C; /* VB_SIS302ELV; */
1460 } else if(rev >= 0xD0) {
1461 SiS_Pr->SiS_VBType = VB_SIS301LV;
1464 if(SiS_Pr->SiS_VBType & (VB_SIS301C | VB_SIS301LV | VB_SIS302LV | VB_SIS302ELV)) {
1465 p4_0f = SiS_GetReg(SiS_Pr->SiS_Part4Port,0x0f);
1466 p4_25 = SiS_GetReg(SiS_Pr->SiS_Part4Port,0x25);
1467 p4_27 = SiS_GetReg(SiS_Pr->SiS_Part4Port,0x27);
1468 SiS_SetRegAND(SiS_Pr->SiS_Part4Port,0x0f,0x7f);
1469 SiS_SetRegOR(SiS_Pr->SiS_Part4Port,0x25,0x08);
1470 SiS_SetRegAND(SiS_Pr->SiS_Part4Port,0x27,0xfd);
1471 if(SiS_GetReg(SiS_Pr->SiS_Part4Port,0x26) & 0x08) {
1472 SiS_Pr->SiS_VBType |= VB_UMC;
1474 SiS_SetReg(SiS_Pr->SiS_Part4Port,0x27,p4_27);
1475 SiS_SetReg(SiS_Pr->SiS_Part4Port,0x25,p4_25);
1476 SiS_SetReg(SiS_Pr->SiS_Part4Port,0x0f,p4_0f);
1480 /*********************************************/
1481 /* HELPER: Check RAM size */
1482 /*********************************************/
1485 SiS_CheckMemorySize(struct SiS_Private *SiS_Pr, unsigned short ModeNo,
1486 unsigned short ModeIdIndex)
1488 unsigned short AdapterMemSize = SiS_Pr->VideoMemorySize / (1024*1024);
1489 unsigned short modeflag = SiS_GetModeFlag(SiS_Pr, ModeNo, ModeIdIndex);
1490 unsigned short memorysize = ((modeflag & MemoryInfoFlag) >> MemorySizeShift) + 1;
1492 if(!AdapterMemSize) return true;
1494 if(AdapterMemSize < memorysize) return false;
1498 /*********************************************/
1499 /* HELPER: Get DRAM type */
1500 /*********************************************/
1502 #ifdef CONFIG_FB_SIS_315
1503 static unsigned char
1504 SiS_Get310DRAMType(struct SiS_Private *SiS_Pr)
1508 if((*SiS_Pr->pSiS_SoftSetting) & SoftDRAMType) {
1509 data = (*SiS_Pr->pSiS_SoftSetting) & 0x03;
1511 if(SiS_Pr->ChipType >= XGI_20) {
1512 /* Do I need this? SR17 seems to be zero anyway... */
1514 } else if(SiS_Pr->ChipType >= SIS_340) {
1517 } if(SiS_Pr->ChipType >= SIS_661) {
1518 if(SiS_Pr->SiS_ROMNew) {
1519 data = ((SiS_GetReg(SiS_Pr->SiS_P3d4,0x78) & 0xc0) >> 6);
1521 data = SiS_GetReg(SiS_Pr->SiS_P3d4,0x78) & 0x07;
1523 } else if(IS_SIS550650740) {
1524 data = SiS_GetReg(SiS_Pr->SiS_P3c4,0x13) & 0x07;
1525 } else { /* 315, 330 */
1526 data = SiS_GetReg(SiS_Pr->SiS_P3c4,0x3a) & 0x03;
1527 if(SiS_Pr->ChipType == SIS_330) {
1529 switch(SiS_GetReg(SiS_Pr->SiS_P3d4,0x5f) & 0x30) {
1530 case 0x00: data = 1; break;
1531 case 0x10: data = 3; break;
1532 case 0x20: data = 3; break;
1533 case 0x30: data = 2; break;
1545 static unsigned short
1546 SiS_GetMCLK(struct SiS_Private *SiS_Pr)
1548 unsigned char *ROMAddr = SiS_Pr->VirtualRomBase;
1549 unsigned short index;
1551 index = SiS_Get310DRAMType(SiS_Pr);
1552 if(SiS_Pr->ChipType >= SIS_661) {
1553 if(SiS_Pr->SiS_ROMNew) {
1554 return((unsigned short)(SISGETROMW((0x90 + (index * 5) + 3))));
1556 return(SiS_Pr->SiS_MCLKData_0[index].CLOCK);
1557 } else if(index >= 4) {
1558 return(SiS_Pr->SiS_MCLKData_1[index - 4].CLOCK);
1560 return(SiS_Pr->SiS_MCLKData_0[index].CLOCK);
1565 /*********************************************/
1566 /* HELPER: ClearBuffer */
1567 /*********************************************/
1570 SiS_ClearBuffer(struct SiS_Private *SiS_Pr, unsigned short ModeNo)
1572 unsigned char SISIOMEMTYPE *memaddr = SiS_Pr->VideoMemoryAddress;
1573 unsigned int memsize = SiS_Pr->VideoMemorySize;
1574 unsigned short SISIOMEMTYPE *pBuffer;
1577 if(!memaddr || !memsize) return;
1579 if(SiS_Pr->SiS_ModeType >= ModeEGA) {
1581 memset_io(memaddr, 0, memsize);
1583 pBuffer = (unsigned short SISIOMEMTYPE *)memaddr;
1584 for(i = 0; i < 0x4000; i++) writew(0x0000, &pBuffer[i]);
1586 } else if(SiS_Pr->SiS_ModeType < ModeCGA) {
1587 pBuffer = (unsigned short SISIOMEMTYPE *)memaddr;
1588 for(i = 0; i < 0x4000; i++) writew(0x0720, &pBuffer[i]);
1590 memset_io(memaddr, 0, 0x8000);
1594 /*********************************************/
1595 /* HELPER: SearchModeID */
1596 /*********************************************/
1599 SiS_SearchModeID(struct SiS_Private *SiS_Pr, unsigned short *ModeNo,
1600 unsigned short *ModeIdIndex)
1602 unsigned char VGAINFO = SiS_Pr->SiS_VGAINFO;
1604 if((*ModeNo) <= 0x13) {
1606 if((*ModeNo) <= 0x05) (*ModeNo) |= 0x01;
1608 for((*ModeIdIndex) = 0; ;(*ModeIdIndex)++) {
1609 if(SiS_Pr->SiS_SModeIDTable[(*ModeIdIndex)].St_ModeID == (*ModeNo)) break;
1610 if(SiS_Pr->SiS_SModeIDTable[(*ModeIdIndex)].St_ModeID == 0xFF) return false;
1613 if((*ModeNo) == 0x07) {
1614 if(VGAINFO & 0x10) (*ModeIdIndex)++; /* 400 lines */
1615 /* else 350 lines */
1617 if((*ModeNo) <= 0x03) {
1618 if(!(VGAINFO & 0x80)) (*ModeIdIndex)++;
1619 if(VGAINFO & 0x10) (*ModeIdIndex)++; /* 400 lines */
1620 /* else 350 lines */
1622 /* else 200 lines */
1626 for((*ModeIdIndex) = 0; ;(*ModeIdIndex)++) {
1627 if(SiS_Pr->SiS_EModeIDTable[(*ModeIdIndex)].Ext_ModeID == (*ModeNo)) break;
1628 if(SiS_Pr->SiS_EModeIDTable[(*ModeIdIndex)].Ext_ModeID == 0xFF) return false;
1635 /*********************************************/
1636 /* HELPER: GetModePtr */
1637 /*********************************************/
1640 SiS_GetModePtr(struct SiS_Private *SiS_Pr, unsigned short ModeNo, unsigned short ModeIdIndex)
1642 unsigned short index;
1644 if(ModeNo <= 0x13) {
1645 index = SiS_Pr->SiS_SModeIDTable[ModeIdIndex].St_StTableIndex;
1647 if(SiS_Pr->SiS_ModeType <= ModeEGA) index = 0x1B;
1653 /*********************************************/
1654 /* HELPERS: Get some indices */
1655 /*********************************************/
1658 SiS_GetRefCRTVCLK(struct SiS_Private *SiS_Pr, unsigned short Index, int UseWide)
1660 if(SiS_Pr->SiS_RefIndex[Index].Ext_InfoFlag & HaveWideTiming) {
1662 return SiS_Pr->SiS_RefIndex[Index].Ext_CRTVCLK_WIDE;
1664 return SiS_Pr->SiS_RefIndex[Index].Ext_CRTVCLK_NORM;
1667 return SiS_Pr->SiS_RefIndex[Index].Ext_CRTVCLK;
1672 SiS_GetRefCRT1CRTC(struct SiS_Private *SiS_Pr, unsigned short Index, int UseWide)
1674 if(SiS_Pr->SiS_RefIndex[Index].Ext_InfoFlag & HaveWideTiming) {
1676 return SiS_Pr->SiS_RefIndex[Index].Ext_CRT1CRTC_WIDE;
1678 return SiS_Pr->SiS_RefIndex[Index].Ext_CRT1CRTC_NORM;
1681 return SiS_Pr->SiS_RefIndex[Index].Ext_CRT1CRTC;
1685 /*********************************************/
1686 /* HELPER: LowModeTests */
1687 /*********************************************/
1690 SiS_DoLowModeTest(struct SiS_Private *SiS_Pr, unsigned short ModeNo)
1692 unsigned short temp, temp1, temp2;
1694 if((ModeNo != 0x03) && (ModeNo != 0x10) && (ModeNo != 0x12))
1696 temp = SiS_GetReg(SiS_Pr->SiS_P3d4,0x11);
1697 SiS_SetRegOR(SiS_Pr->SiS_P3d4,0x11,0x80);
1698 temp1 = SiS_GetReg(SiS_Pr->SiS_P3d4,0x00);
1699 SiS_SetReg(SiS_Pr->SiS_P3d4,0x00,0x55);
1700 temp2 = SiS_GetReg(SiS_Pr->SiS_P3d4,0x00);
1701 SiS_SetReg(SiS_Pr->SiS_P3d4,0x00,temp1);
1702 SiS_SetReg(SiS_Pr->SiS_P3d4,0x11,temp);
1703 if((SiS_Pr->ChipType >= SIS_315H) ||
1704 (SiS_Pr->ChipType == SIS_300)) {
1705 if(temp2 == 0x55) return false;
1708 if(temp2 != 0x55) return true;
1710 SiS_SetRegOR(SiS_Pr->SiS_P3d4,0x35,0x01);
1717 SiS_SetLowModeTest(struct SiS_Private *SiS_Pr, unsigned short ModeNo)
1719 if(SiS_DoLowModeTest(SiS_Pr, ModeNo)) {
1720 SiS_Pr->SiS_SetFlag |= LowModeTests;
1724 /*********************************************/
1725 /* HELPER: OPEN/CLOSE CRT1 CRTC */
1726 /*********************************************/
1729 SiS_OpenCRTC(struct SiS_Private *SiS_Pr)
1732 SiS_SetRegAND(SiS_Pr->SiS_P3d4,0x51,0x1f);
1733 if(IS_SIS651) SiS_SetRegOR(SiS_Pr->SiS_P3d4,0x51,0x20);
1734 SiS_SetRegAND(SiS_Pr->SiS_P3d4,0x56,0xe7);
1735 } else if(IS_SIS661741660760) {
1736 SiS_SetRegAND(SiS_Pr->SiS_P3d4,0x61,0xf7);
1737 SiS_SetRegAND(SiS_Pr->SiS_P3d4,0x51,0x1f);
1738 SiS_SetRegAND(SiS_Pr->SiS_P3d4,0x56,0xe7);
1739 if(!SiS_Pr->SiS_ROMNew) {
1740 SiS_SetRegAND(SiS_Pr->SiS_P3d4,0x3a,0xef);
1746 SiS_CloseCRTC(struct SiS_Private *SiS_Pr)
1748 #if 0 /* This locks some CRTC registers. We don't want that. */
1749 unsigned short temp1 = 0, temp2 = 0;
1751 if(IS_SIS661741660760) {
1752 if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA) {
1753 temp1 = 0xa0; temp2 = 0x08;
1755 SiS_SetRegANDOR(SiS_Pr->SiS_P3d4,0x51,0x1f,temp1);
1756 SiS_SetRegANDOR(SiS_Pr->SiS_P3d4,0x56,0xe7,temp2);
1762 SiS_HandleCRT1(struct SiS_Private *SiS_Pr)
1764 /* Enable CRT1 gating */
1765 SiS_SetRegAND(SiS_Pr->SiS_P3d4,SiS_Pr->SiS_MyCR63,0xbf);
1767 if(!(SiS_GetReg(SiS_Pr->SiS_P3c4,0x15) & 0x01)) {
1768 if((SiS_GetReg(SiS_Pr->SiS_P3c4,0x15) & 0x0a) ||
1769 (SiS_GetReg(SiS_Pr->SiS_P3c4,0x16) & 0x01)) {
1770 SiS_SetRegOR(SiS_Pr->SiS_P3d4,SiS_Pr->SiS_MyCR63,0x40);
1776 /*********************************************/
1777 /* HELPER: GetColorDepth */
1778 /*********************************************/
1781 SiS_GetColorDepth(struct SiS_Private *SiS_Pr, unsigned short ModeNo,
1782 unsigned short ModeIdIndex)
1784 static const unsigned short ColorDepth[6] = { 1, 2, 4, 4, 6, 8 };
1785 unsigned short modeflag;
1788 /* Do NOT check UseCustomMode, will skrew up FIFO */
1789 if(ModeNo == 0xfe) {
1790 modeflag = SiS_Pr->CModeFlag;
1791 } else if(ModeNo <= 0x13) {
1792 modeflag = SiS_Pr->SiS_SModeIDTable[ModeIdIndex].St_ModeFlag;
1794 modeflag = SiS_Pr->SiS_EModeIDTable[ModeIdIndex].Ext_ModeFlag;
1797 index = (modeflag & ModeTypeMask) - ModeEGA;
1798 if(index < 0) index = 0;
1799 return ColorDepth[index];
1802 /*********************************************/
1803 /* HELPER: GetOffset */
1804 /*********************************************/
1807 SiS_GetOffset(struct SiS_Private *SiS_Pr, unsigned short ModeNo,
1808 unsigned short ModeIdIndex, unsigned short RRTI)
1810 unsigned short xres, temp, colordepth, infoflag;
1812 if(SiS_Pr->UseCustomMode) {
1813 infoflag = SiS_Pr->CInfoFlag;
1814 xres = SiS_Pr->CHDisplay;
1816 infoflag = SiS_Pr->SiS_RefIndex[RRTI].Ext_InfoFlag;
1817 xres = SiS_Pr->SiS_RefIndex[RRTI].XRes;
1820 colordepth = SiS_GetColorDepth(SiS_Pr, ModeNo, ModeIdIndex);
1823 if(infoflag & InterlaceMode) temp <<= 1;
1825 if(xres % 16) temp += (colordepth >> 1);
1830 /*********************************************/
1832 /*********************************************/
1835 SiS_SetSeqRegs(struct SiS_Private *SiS_Pr, unsigned short StandTableIndex)
1837 unsigned char SRdata;
1840 SiS_SetReg(SiS_Pr->SiS_P3c4,0x00,0x03);
1842 /* or "display off" */
1843 SRdata = SiS_Pr->SiS_StandTable[StandTableIndex].SR[0] | 0x20;
1845 /* determine whether to force x8 dotclock */
1846 if((SiS_Pr->SiS_VBType & VB_SISVB) || (SiS_Pr->SiS_IF_DEF_LVDS)) {
1848 if(SiS_Pr->SiS_VBInfo & (SetCRT2ToLCD | SetCRT2ToTV)) {
1849 if(SiS_Pr->SiS_VBInfo & SetInSlaveMode) SRdata |= 0x01;
1850 } else if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA) SRdata |= 0x01;
1854 SiS_SetReg(SiS_Pr->SiS_P3c4,0x01,SRdata);
1856 for(i = 2; i <= 4; i++) {
1857 SRdata = SiS_Pr->SiS_StandTable[StandTableIndex].SR[i - 1];
1858 SiS_SetReg(SiS_Pr->SiS_P3c4,i,SRdata);
1862 /*********************************************/
1864 /*********************************************/
1867 SiS_SetMiscRegs(struct SiS_Private *SiS_Pr, unsigned short StandTableIndex)
1869 unsigned char Miscdata;
1871 Miscdata = SiS_Pr->SiS_StandTable[StandTableIndex].MISC;
1873 if(SiS_Pr->ChipType < SIS_661) {
1874 if(SiS_Pr->SiS_VBType & VB_SIS30xBLV) {
1875 if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA) {
1881 SiS_SetRegByte(SiS_Pr->SiS_P3c2,Miscdata);
1884 /*********************************************/
1886 /*********************************************/
1889 SiS_SetCRTCRegs(struct SiS_Private *SiS_Pr, unsigned short StandTableIndex)
1891 unsigned char CRTCdata;
1895 SiS_SetRegAND(SiS_Pr->SiS_P3d4,0x11,0x7f);
1897 for(i = 0; i <= 0x18; i++) {
1898 CRTCdata = SiS_Pr->SiS_StandTable[StandTableIndex].CRTC[i];
1899 SiS_SetReg(SiS_Pr->SiS_P3d4,i,CRTCdata);
1902 if(SiS_Pr->ChipType >= SIS_661) {
1903 SiS_OpenCRTC(SiS_Pr);
1904 for(i = 0x13; i <= 0x14; i++) {
1905 CRTCdata = SiS_Pr->SiS_StandTable[StandTableIndex].CRTC[i];
1906 SiS_SetReg(SiS_Pr->SiS_P3d4,i,CRTCdata);
1908 } else if( ( (SiS_Pr->ChipType == SIS_630) ||
1909 (SiS_Pr->ChipType == SIS_730) ) &&
1910 (SiS_Pr->ChipRevision >= 0x30) ) {
1911 if(SiS_Pr->SiS_VBInfo & SetInSlaveMode) {
1912 if(SiS_Pr->SiS_VBInfo & (SetCRT2ToLCD | SetCRT2ToTV)) {
1913 SiS_SetReg(SiS_Pr->SiS_P3d4,0x18,0xFE);
1919 /*********************************************/
1921 /*********************************************/
1924 SiS_SetATTRegs(struct SiS_Private *SiS_Pr, unsigned short StandTableIndex)
1926 unsigned char ARdata;
1929 for(i = 0; i <= 0x13; i++) {
1930 ARdata = SiS_Pr->SiS_StandTable[StandTableIndex].ATTR[i];
1933 /* Pixel shift. If screen on LCD or TV is shifted left or right,
1934 * this might be the cause.
1936 if(SiS_Pr->SiS_VBType & VB_SIS30xBLV) {
1937 if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA) ARdata = 0;
1939 if(SiS_Pr->SiS_IF_DEF_LVDS == 1) {
1940 if(SiS_Pr->SiS_IF_DEF_CH70xx != 0) {
1941 if(SiS_Pr->SiS_VBInfo & SetCRT2ToTV) {
1942 if(SiS_Pr->SiS_VBInfo & SetInSlaveMode) ARdata = 0;
1946 if(SiS_Pr->ChipType >= SIS_661) {
1947 if(SiS_Pr->SiS_VBInfo & (SetCRT2ToTV | SetCRT2ToLCD)) {
1948 if(SiS_Pr->SiS_VBInfo & SetInSlaveMode) ARdata = 0;
1950 } else if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCD) {
1951 if(SiS_Pr->ChipType >= SIS_315H) {
1952 if(IS_SIS550650740660) {
1953 /* 315, 330 don't do this */
1954 if(SiS_Pr->SiS_VBType & VB_SIS30xB) {
1955 if(SiS_Pr->SiS_VBInfo & SetInSlaveMode) ARdata = 0;
1961 if(SiS_Pr->SiS_VBInfo & SetInSlaveMode) ARdata = 0;
1965 SiS_GetRegByte(SiS_Pr->SiS_P3da); /* reset 3da */
1966 SiS_SetRegByte(SiS_Pr->SiS_P3c0,i); /* set index */
1967 SiS_SetRegByte(SiS_Pr->SiS_P3c0,ARdata); /* set data */
1970 SiS_GetRegByte(SiS_Pr->SiS_P3da); /* reset 3da */
1971 SiS_SetRegByte(SiS_Pr->SiS_P3c0,0x14); /* set index */
1972 SiS_SetRegByte(SiS_Pr->SiS_P3c0,0x00); /* set data */
1974 SiS_GetRegByte(SiS_Pr->SiS_P3da);
1975 SiS_SetRegByte(SiS_Pr->SiS_P3c0,0x20); /* Enable Attribute */
1976 SiS_GetRegByte(SiS_Pr->SiS_P3da);
1979 /*********************************************/
1981 /*********************************************/
1984 SiS_SetGRCRegs(struct SiS_Private *SiS_Pr, unsigned short StandTableIndex)
1986 unsigned char GRdata;
1989 for(i = 0; i <= 0x08; i++) {
1990 GRdata = SiS_Pr->SiS_StandTable[StandTableIndex].GRC[i];
1991 SiS_SetReg(SiS_Pr->SiS_P3ce,i,GRdata);
1994 if(SiS_Pr->SiS_ModeType > ModeVGA) {
1995 /* 256 color disable */
1996 SiS_SetRegAND(SiS_Pr->SiS_P3ce,0x05,0xBF);
2000 /*********************************************/
2001 /* CLEAR EXTENDED REGISTERS */
2002 /*********************************************/
2005 SiS_ClearExt1Regs(struct SiS_Private *SiS_Pr, unsigned short ModeNo)
2009 for(i = 0x0A; i <= 0x0E; i++) {
2010 SiS_SetReg(SiS_Pr->SiS_P3c4,i,0x00);
2013 if(SiS_Pr->ChipType >= SIS_315H) {
2014 SiS_SetRegAND(SiS_Pr->SiS_P3c4,0x37,0xFE);
2015 if(ModeNo <= 0x13) {
2016 if(ModeNo == 0x06 || ModeNo >= 0x0e) {
2017 SiS_SetReg(SiS_Pr->SiS_P3c4,0x0e,0x20);
2023 /*********************************************/
2025 /*********************************************/
2028 SiS_ResetCRT1VCLK(struct SiS_Private *SiS_Pr)
2030 if(SiS_Pr->ChipType >= SIS_315H) {
2031 if(SiS_Pr->ChipType < SIS_661) {
2032 if(SiS_Pr->SiS_IF_DEF_LVDS == 0) return;
2035 if((SiS_Pr->SiS_IF_DEF_LVDS == 0) &&
2036 (!(SiS_Pr->SiS_VBType & VB_SIS30xBLV)) ) {
2041 SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x31,0xcf,0x20);
2042 SiS_SetReg(SiS_Pr->SiS_P3c4,0x2B,SiS_Pr->SiS_VCLKData[1].SR2B);
2043 SiS_SetReg(SiS_Pr->SiS_P3c4,0x2C,SiS_Pr->SiS_VCLKData[1].SR2C);
2044 SiS_SetReg(SiS_Pr->SiS_P3c4,0x2D,0x80);
2045 SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x31,0xcf,0x10);
2046 SiS_SetReg(SiS_Pr->SiS_P3c4,0x2B,SiS_Pr->SiS_VCLKData[0].SR2B);
2047 SiS_SetReg(SiS_Pr->SiS_P3c4,0x2C,SiS_Pr->SiS_VCLKData[0].SR2C);
2048 SiS_SetReg(SiS_Pr->SiS_P3c4,0x2D,0x80);
2051 /*********************************************/
2053 /*********************************************/
2056 SiS_SetCRT1Sync(struct SiS_Private *SiS_Pr, unsigned short RRTI)
2058 unsigned short sync;
2060 if(SiS_Pr->UseCustomMode) {
2061 sync = SiS_Pr->CInfoFlag >> 8;
2063 sync = SiS_Pr->SiS_RefIndex[RRTI].Ext_InfoFlag >> 8;
2068 SiS_SetRegByte(SiS_Pr->SiS_P3c2,sync);
2071 /*********************************************/
2073 /*********************************************/
2076 SiS_SetCRT1CRTC(struct SiS_Private *SiS_Pr, unsigned short ModeNo,
2077 unsigned short ModeIdIndex, unsigned short RRTI)
2079 unsigned short temp, i, j, modeflag;
2080 unsigned char *crt1data = NULL;
2082 modeflag = SiS_GetModeFlag(SiS_Pr, ModeNo, ModeIdIndex);
2084 if(SiS_Pr->UseCustomMode) {
2086 crt1data = &SiS_Pr->CCRT1CRTC[0];
2090 temp = SiS_GetRefCRT1CRTC(SiS_Pr, RRTI, SiS_Pr->SiS_UseWide);
2092 /* Alternate for 1600x1200 LCDA */
2093 if((temp == 0x20) && (SiS_Pr->Alternate1600x1200)) temp = 0x57;
2095 crt1data = (unsigned char *)&SiS_Pr->SiS_CRT1Table[temp].CR[0];
2100 SiS_SetRegAND(SiS_Pr->SiS_P3d4,0x11,0x7f);
2102 for(i = 0, j = 0; i <= 7; i++, j++) {
2103 SiS_SetReg(SiS_Pr->SiS_P3d4,j,crt1data[i]);
2105 for(j = 0x10; i <= 10; i++, j++) {
2106 SiS_SetReg(SiS_Pr->SiS_P3d4,j,crt1data[i]);
2108 for(j = 0x15; i <= 12; i++, j++) {
2109 SiS_SetReg(SiS_Pr->SiS_P3d4,j,crt1data[i]);
2111 for(j = 0x0A; i <= 15; i++, j++) {
2112 SiS_SetReg(SiS_Pr->SiS_P3c4,j,crt1data[i]);
2115 SiS_SetReg(SiS_Pr->SiS_P3c4,0x0E,crt1data[16] & 0xE0);
2117 temp = (crt1data[16] & 0x01) << 5;
2118 if(modeflag & DoubleScanMode) temp |= 0x80;
2119 SiS_SetRegANDOR(SiS_Pr->SiS_P3d4,0x09,0x5F,temp);
2121 if(SiS_Pr->SiS_ModeType > ModeVGA) {
2122 SiS_SetReg(SiS_Pr->SiS_P3d4,0x14,0x4F);
2125 #ifdef CONFIG_FB_SIS_315
2126 if(SiS_Pr->ChipType == XGI_20) {
2127 SiS_SetReg(SiS_Pr->SiS_P3d4,0x04,crt1data[4] - 1);
2128 if(!(temp = crt1data[5] & 0x1f)) {
2129 SiS_SetRegAND(SiS_Pr->SiS_P3c4,0x0c,0xfb);
2131 SiS_SetRegANDOR(SiS_Pr->SiS_P3d4,0x05,0xe0,((temp - 1) & 0x1f));
2132 temp = (crt1data[16] >> 5) + 3;
2133 if(temp > 7) temp -= 7;
2134 SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x0e,0x1f,(temp << 5));
2139 /*********************************************/
2140 /* OFFSET & PITCH */
2141 /*********************************************/
2142 /* (partly overruled by SetPitch() in XF86) */
2143 /*********************************************/
2146 SiS_SetCRT1Offset(struct SiS_Private *SiS_Pr, unsigned short ModeNo,
2147 unsigned short ModeIdIndex, unsigned short RRTI)
2149 unsigned short temp, DisplayUnit, infoflag;
2151 if(SiS_Pr->UseCustomMode) {
2152 infoflag = SiS_Pr->CInfoFlag;
2154 infoflag = SiS_Pr->SiS_RefIndex[RRTI].Ext_InfoFlag;
2157 DisplayUnit = SiS_GetOffset(SiS_Pr, ModeNo, ModeIdIndex, RRTI);
2159 temp = (DisplayUnit >> 8) & 0x0f;
2160 SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x0E,0xF0,temp);
2162 SiS_SetReg(SiS_Pr->SiS_P3d4,0x13,DisplayUnit & 0xFF);
2164 if(infoflag & InterlaceMode) DisplayUnit >>= 1;
2167 temp = (DisplayUnit >> 8) + 1;
2168 if(DisplayUnit & 0xff) temp++;
2169 if(SiS_Pr->ChipType == XGI_20) {
2170 if(ModeNo == 0x4a || ModeNo == 0x49) temp--;
2172 SiS_SetReg(SiS_Pr->SiS_P3c4,0x10,temp);
2175 /*********************************************/
2177 /*********************************************/
2180 SiS_SetCRT1VCLK(struct SiS_Private *SiS_Pr, unsigned short ModeNo,
2181 unsigned short ModeIdIndex, unsigned short RRTI)
2183 unsigned short index = 0, clka, clkb;
2185 if(SiS_Pr->UseCustomMode) {
2186 clka = SiS_Pr->CSR2B;
2187 clkb = SiS_Pr->CSR2C;
2189 index = SiS_GetVCLK2Ptr(SiS_Pr, ModeNo, ModeIdIndex, RRTI);
2190 if((SiS_Pr->SiS_VBType & VB_SIS30xBLV) &&
2191 (SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA)) {
2192 /* Alternate for 1600x1200 LCDA */
2193 if((index == 0x21) && (SiS_Pr->Alternate1600x1200)) index = 0x72;
2194 clka = SiS_Pr->SiS_VBVCLKData[index].Part4_A;
2195 clkb = SiS_Pr->SiS_VBVCLKData[index].Part4_B;
2197 clka = SiS_Pr->SiS_VCLKData[index].SR2B;
2198 clkb = SiS_Pr->SiS_VCLKData[index].SR2C;
2202 SiS_SetRegAND(SiS_Pr->SiS_P3c4,0x31,0xCF);
2204 SiS_SetReg(SiS_Pr->SiS_P3c4,0x2b,clka);
2205 SiS_SetReg(SiS_Pr->SiS_P3c4,0x2c,clkb);
2207 if(SiS_Pr->ChipType >= SIS_315H) {
2208 #ifdef CONFIG_FB_SIS_315
2209 SiS_SetReg(SiS_Pr->SiS_P3c4,0x2D,0x01);
2210 if(SiS_Pr->ChipType == XGI_20) {
2211 unsigned short mf = SiS_GetModeFlag(SiS_Pr, ModeNo, ModeIdIndex);
2213 SiS_SetReg(SiS_Pr->SiS_P3c4,0x2b,SiS_GetReg(SiS_Pr->SiS_P3c4,0x2b));
2214 clkb = SiS_GetReg(SiS_Pr->SiS_P3c4,0x2c);
2215 clkb = (((clkb & 0x1f) << 1) + 1) | (clkb & 0xe0);
2216 SiS_SetReg(SiS_Pr->SiS_P3c4,0x2c,clkb);
2221 SiS_SetReg(SiS_Pr->SiS_P3c4,0x2D,0x80);
2225 /*********************************************/
2227 /*********************************************/
2229 #ifdef CONFIG_FB_SIS_300
2231 SiS_GetFIFOThresholdIndex300(struct SiS_Private *SiS_Pr, unsigned short *idx1,
2232 unsigned short *idx2)
2234 unsigned short temp1, temp2;
2235 static const unsigned char ThTiming[8] = {
2236 1, 2, 2, 3, 0, 1, 1, 2
2239 temp1 = temp2 = (SiS_GetReg(SiS_Pr->SiS_P3c4,0x18) & 0x62) >> 1;
2240 (*idx2) = (unsigned short)(ThTiming[((temp2 >> 3) | temp1) & 0x07]);
2241 (*idx1) = (unsigned short)(SiS_GetReg(SiS_Pr->SiS_P3c4,0x16) >> 6) & 0x03;
2242 (*idx1) |= (unsigned short)(((SiS_GetReg(SiS_Pr->SiS_P3c4,0x14) >> 4) & 0x0c));
2246 static unsigned short
2247 SiS_GetFIFOThresholdA300(unsigned short idx1, unsigned short idx2)
2249 static const unsigned char ThLowA[8 * 3] = {
2250 61, 3,52, 5,68, 7,100,11,
2251 43, 3,42, 5,54, 7, 78,11,
2252 34, 3,37, 5,47, 7, 67,11
2255 return (unsigned short)((ThLowA[idx1 + 1] * idx2) + ThLowA[idx1]);
2259 SiS_GetFIFOThresholdB300(unsigned short idx1, unsigned short idx2)
2261 static const unsigned char ThLowB[8 * 3] = {
2262 81, 4,72, 6,88, 8,120,12,
2263 55, 4,54, 6,66, 8, 90,12,
2264 42, 4,45, 6,55, 8, 75,12
2267 return (unsigned short)((ThLowB[idx1 + 1] * idx2) + ThLowB[idx1]);
2270 static unsigned short
2271 SiS_DoCalcDelay(struct SiS_Private *SiS_Pr, unsigned short MCLK, unsigned short VCLK,
2272 unsigned short colordepth, unsigned short key)
2274 unsigned short idx1, idx2;
2275 unsigned int longtemp = VCLK * colordepth;
2277 SiS_GetFIFOThresholdIndex300(SiS_Pr, &idx1, &idx2);
2280 longtemp *= SiS_GetFIFOThresholdA300(idx1, idx2);
2282 longtemp *= SiS_GetFIFOThresholdB300(idx1, idx2);
2284 idx1 = longtemp % (MCLK * 16);
2285 longtemp /= (MCLK * 16);
2286 if(idx1) longtemp++;
2287 return (unsigned short)longtemp;
2290 static unsigned short
2291 SiS_CalcDelay(struct SiS_Private *SiS_Pr, unsigned short VCLK,
2292 unsigned short colordepth, unsigned short MCLK)
2294 unsigned short temp1, temp2;
2296 temp2 = SiS_DoCalcDelay(SiS_Pr, MCLK, VCLK, colordepth, 0);
2297 temp1 = SiS_DoCalcDelay(SiS_Pr, MCLK, VCLK, colordepth, 1);
2298 if(temp1 < 4) temp1 = 4;
2300 if(temp2 < temp1) temp2 = temp1;
2305 SiS_SetCRT1FIFO_300(struct SiS_Private *SiS_Pr, unsigned short ModeNo,
2306 unsigned short RefreshRateTableIndex)
2308 unsigned short ThresholdLow = 0;
2309 unsigned short temp, index, VCLK, MCLK, colorth;
2310 static const unsigned short colortharray[6] = { 1, 1, 2, 2, 3, 4 };
2315 if(SiS_Pr->UseCustomMode) {
2316 VCLK = SiS_Pr->CSRClock;
2318 index = SiS_GetRefCRTVCLK(SiS_Pr, RefreshRateTableIndex, SiS_Pr->SiS_UseWide);
2319 VCLK = SiS_Pr->SiS_VCLKData[index].CLOCK;
2322 /* Get half colordepth */
2323 colorth = colortharray[(SiS_Pr->SiS_ModeType - ModeEGA)];
2326 index = SiS_GetReg(SiS_Pr->SiS_P3c4,0x3A) & 0x07;
2327 MCLK = SiS_Pr->SiS_MCLKData_0[index].CLOCK;
2329 temp = SiS_GetReg(SiS_Pr->SiS_P3d4,0x35) & 0xc3;
2330 SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x16,0x3c,temp);
2333 ThresholdLow = SiS_CalcDelay(SiS_Pr, VCLK, colorth, MCLK) + 1;
2334 if(ThresholdLow < 0x13) break;
2335 SiS_SetRegAND(SiS_Pr->SiS_P3c4,0x16,0xfc);
2336 ThresholdLow = 0x13;
2337 temp = SiS_GetReg(SiS_Pr->SiS_P3c4,0x16) >> 6;
2339 SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x16,0x3f,((temp - 1) << 6));
2342 } else ThresholdLow = 2;
2344 /* Write CRT/CPU threshold low, CRT/Engine threshold high */
2345 temp = (ThresholdLow << 4) | 0x0f;
2346 SiS_SetReg(SiS_Pr->SiS_P3c4,0x08,temp);
2348 temp = (ThresholdLow & 0x10) << 1;
2349 if(ModeNo > 0x13) temp |= 0x40;
2350 SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x0f,0x9f,temp);
2353 SiS_SetReg(SiS_Pr->SiS_P3c4,0x3B,0x09);
2355 /* Write CRT/CPU threshold high */
2356 temp = ThresholdLow + 3;
2357 if(temp > 0x0f) temp = 0x0f;
2358 SiS_SetReg(SiS_Pr->SiS_P3c4,0x09,temp);
2362 SiS_GetLatencyFactor630(struct SiS_Private *SiS_Pr, unsigned short index)
2364 static const unsigned char LatencyFactor[] = {
2365 97, 88, 86, 79, 77, 0, /* 64 bit BQ=2 */
2366 0, 87, 85, 78, 76, 54, /* 64 bit BQ=1 */
2367 97, 88, 86, 79, 77, 0, /* 128 bit BQ=2 */
2368 0, 79, 77, 70, 68, 48, /* 128 bit BQ=1 */
2369 80, 72, 69, 63, 61, 0, /* 64 bit BQ=2 */
2370 0, 70, 68, 61, 59, 37, /* 64 bit BQ=1 */
2371 86, 77, 75, 68, 66, 0, /* 128 bit BQ=2 */
2372 0, 68, 66, 59, 57, 37 /* 128 bit BQ=1 */
2374 static const unsigned char LatencyFactor730[] = {
2382 if(SiS_Pr->ChipType == SIS_730) {
2383 return (unsigned short)LatencyFactor730[index];
2385 return (unsigned short)LatencyFactor[index];
2389 static unsigned short
2390 SiS_CalcDelay2(struct SiS_Private *SiS_Pr, unsigned char key)
2392 unsigned short index;
2394 if(SiS_Pr->ChipType == SIS_730) {
2395 index = ((key & 0x0f) * 3) + ((key & 0xc0) >> 6);
2397 index = (key & 0xe0) >> 5;
2398 if(key & 0x10) index += 6;
2399 if(!(key & 0x01)) index += 24;
2400 if(SiS_GetReg(SiS_Pr->SiS_P3c4,0x14) & 0x80) index += 12;
2402 return SiS_GetLatencyFactor630(SiS_Pr, index);
2406 SiS_SetCRT1FIFO_630(struct SiS_Private *SiS_Pr, unsigned short ModeNo,
2407 unsigned short RefreshRateTableIndex)
2409 unsigned short ThresholdLow = 0;
2410 unsigned short i, data, VCLK, MCLK16, colorth = 0;
2411 unsigned int templ, datal;
2412 const unsigned char *queuedata = NULL;
2413 static const unsigned char FQBQData[21] = {
2414 0x01,0x21,0x41,0x61,0x81,
2415 0x31,0x51,0x71,0x91,0xb1,
2416 0x00,0x20,0x40,0x60,0x80,
2417 0x30,0x50,0x70,0x90,0xb0,
2420 static const unsigned char FQBQData730[16] = {
2428 static const unsigned short colortharray[6] = {
2437 if(SiS_Pr->UseCustomMode) {
2438 VCLK = SiS_Pr->CSRClock;
2440 data = SiS_GetRefCRTVCLK(SiS_Pr, RefreshRateTableIndex, SiS_Pr->SiS_UseWide);
2441 VCLK = SiS_Pr->SiS_VCLKData[data].CLOCK;
2445 data = SiS_GetReg(SiS_Pr->SiS_P3c4,0x1A) & 0x07;
2446 MCLK16 = SiS_Pr->SiS_MCLKData_0[data].CLOCK * 16;
2448 /* Get half colordepth */
2449 colorth = colortharray[(SiS_Pr->SiS_ModeType - ModeEGA)];
2451 if(SiS_Pr->ChipType == SIS_730) {
2452 queuedata = &FQBQData730[0];
2454 queuedata = &FQBQData[0];
2458 templ = SiS_CalcDelay2(SiS_Pr, queuedata[i]) * VCLK * colorth;
2460 datal = templ % MCLK16;
2461 templ = (templ / MCLK16) + 1;
2465 if(queuedata[i + 1] == 0xFF) {
2466 ThresholdLow = 0x13;
2471 ThresholdLow = templ;
2474 } while(queuedata[i] != 0xFF);
2478 if(SiS_Pr->ChipType != SIS_730) i = 9;
2479 ThresholdLow = 0x02;
2483 /* Write CRT/CPU threshold low, CRT/Engine threshold high */
2484 data = ((ThresholdLow & 0x0f) << 4) | 0x0f;
2485 SiS_SetReg(SiS_Pr->SiS_P3c4,0x08,data);
2487 data = (ThresholdLow & 0x10) << 1;
2488 SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x0F,0xDF,data);
2491 SiS_SetReg(SiS_Pr->SiS_P3c4,0x3B,0x09);
2493 /* Write CRT/CPU threshold high (gap = 3) */
2494 data = ThresholdLow + 3;
2495 if(data > 0x0f) data = 0x0f;
2496 SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x09,0x80,data);
2498 /* Write foreground and background queue */
2499 templ = sisfb_read_nbridge_pci_dword(SiS_Pr, 0x50);
2501 if(SiS_Pr->ChipType == SIS_730) {
2503 templ &= 0xfffff9ff;
2504 templ |= ((queuedata[i] & 0xc0) << 3);
2508 templ &= 0xf0ffffff;
2509 if( (ModeNo <= 0x13) &&
2510 (SiS_Pr->ChipType == SIS_630) &&
2511 (SiS_Pr->ChipRevision >= 0x30) ) {
2512 templ |= 0x0b000000;
2514 templ |= ((queuedata[i] & 0xf0) << 20);
2519 sisfb_write_nbridge_pci_dword(SiS_Pr, 0x50, templ);
2520 templ = sisfb_read_nbridge_pci_dword(SiS_Pr, 0xA0);
2522 /* GUI grant timer (PCI config 0xA3) */
2523 if(SiS_Pr->ChipType == SIS_730) {
2525 templ &= 0x00ffffff;
2526 datal = queuedata[i] << 8;
2527 templ |= (((datal & 0x0f00) | ((datal & 0x3000) >> 8)) << 20);
2531 templ &= 0xf0ffffff;
2532 templ |= ((queuedata[i] & 0x0f) << 24);
2536 sisfb_write_nbridge_pci_dword(SiS_Pr, 0xA0, templ);
2538 #endif /* CONFIG_FB_SIS_300 */
2540 #ifdef CONFIG_FB_SIS_315
2542 SiS_SetCRT1FIFO_310(struct SiS_Private *SiS_Pr, unsigned short ModeNo, unsigned short ModeIdIndex)
2544 unsigned short modeflag;
2546 /* disable auto-threshold */
2547 SiS_SetRegAND(SiS_Pr->SiS_P3c4,0x3D,0xFE);
2549 modeflag = SiS_GetModeFlag(SiS_Pr, ModeNo, ModeIdIndex);
2551 SiS_SetReg(SiS_Pr->SiS_P3c4,0x08,0xAE);
2552 SiS_SetRegAND(SiS_Pr->SiS_P3c4,0x09,0xF0);
2554 if(SiS_Pr->ChipType >= XGI_20) {
2555 SiS_SetReg(SiS_Pr->SiS_P3c4,0x08,0x34);
2556 SiS_SetRegOR(SiS_Pr->SiS_P3c4,0x3D,0x01);
2557 } else if(SiS_Pr->ChipType >= SIS_661) {
2558 if(!(modeflag & HalfDCLK)) {
2559 SiS_SetReg(SiS_Pr->SiS_P3c4,0x08,0x34);
2560 SiS_SetRegOR(SiS_Pr->SiS_P3c4,0x3D,0x01);
2563 if((!(modeflag & DoubleScanMode)) || (!(modeflag & HalfDCLK))) {
2564 SiS_SetReg(SiS_Pr->SiS_P3c4,0x08,0x34);
2565 SiS_SetRegOR(SiS_Pr->SiS_P3c4,0x3D,0x01);
2572 /*********************************************/
2573 /* MODE REGISTERS */
2574 /*********************************************/
2577 SiS_SetVCLKState(struct SiS_Private *SiS_Pr, unsigned short ModeNo,
2578 unsigned short RefreshRateTableIndex, unsigned short ModeIdIndex)
2580 unsigned short data = 0, VCLK = 0, index = 0;
2583 if(SiS_Pr->UseCustomMode) {
2584 VCLK = SiS_Pr->CSRClock;
2586 index = SiS_GetVCLK2Ptr(SiS_Pr, ModeNo, ModeIdIndex, RefreshRateTableIndex);
2587 VCLK = SiS_Pr->SiS_VCLKData[index].CLOCK;
2591 if(SiS_Pr->ChipType < SIS_315H) {
2592 #ifdef CONFIG_FB_SIS_300
2593 if(VCLK > 150) data |= 0x80;
2594 SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x07,0x7B,data);
2597 if(VCLK >= 150) data |= 0x08;
2598 SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x32,0xF7,data);
2600 } else if(SiS_Pr->ChipType < XGI_20) {
2601 #ifdef CONFIG_FB_SIS_315
2602 if(VCLK >= 166) data |= 0x0c;
2603 SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x32,0xf3,data);
2606 SiS_SetRegAND(SiS_Pr->SiS_P3c4,0x1f,0xe7);
2610 #ifdef CONFIG_FB_SIS_315
2611 if(VCLK >= 200) data |= 0x0c;
2612 if(SiS_Pr->ChipType == XGI_20) data &= ~0x04;
2613 SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x32,0xf3,data);
2614 if(SiS_Pr->ChipType != XGI_20) {
2615 data = SiS_GetReg(SiS_Pr->SiS_P3c4,0x1f) & 0xe7;
2616 if(VCLK < 200) data |= 0x10;
2617 SiS_SetReg(SiS_Pr->SiS_P3c4,0x1f,data);
2623 if(SiS_Pr->ChipType >= SIS_661) {
2625 SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x07,0xE8,0x10);
2630 if(VCLK >= 260) data = 0x00;
2631 else if(VCLK >= 160) data = 0x01;
2632 else if(VCLK >= 135) data = 0x02;
2634 if(SiS_Pr->ChipType == SIS_540) {
2635 if((VCLK == 203) || (VCLK < 234)) data = 0x02;
2638 if(SiS_Pr->ChipType < SIS_315H) {
2639 SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x07,0xFC,data);
2641 if(SiS_Pr->ChipType > SIS_315PRO) {
2642 if(ModeNo > 0x13) data &= 0xfc;
2644 SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x07,0xF8,data);
2651 SiS_SetCRT1ModeRegs(struct SiS_Private *SiS_Pr, unsigned short ModeNo,
2652 unsigned short ModeIdIndex, unsigned short RRTI)
2654 unsigned short data, infoflag = 0, modeflag, resindex;
2655 #ifdef CONFIG_FB_SIS_315
2656 unsigned char *ROMAddr = SiS_Pr->VirtualRomBase;
2657 unsigned short data2, data3;
2660 modeflag = SiS_GetModeFlag(SiS_Pr, ModeNo, ModeIdIndex);
2662 if(SiS_Pr->UseCustomMode) {
2663 infoflag = SiS_Pr->CInfoFlag;
2665 resindex = SiS_GetResInfo(SiS_Pr, ModeNo, ModeIdIndex);
2667 infoflag = SiS_Pr->SiS_RefIndex[RRTI].Ext_InfoFlag;
2672 SiS_SetRegAND(SiS_Pr->SiS_P3c4,0x1F,0x3F);
2676 if(SiS_Pr->SiS_ModeType > ModeEGA) {
2678 data |= ((SiS_Pr->SiS_ModeType - ModeVGA) << 2);
2680 if(infoflag & InterlaceMode) data |= 0x20;
2682 SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x06,0xC0,data);
2684 if(SiS_Pr->ChipType != SIS_300) {
2686 if(infoflag & InterlaceMode) {
2687 /* data = (Hsync / 8) - ((Htotal / 8) / 2) + 3 */
2688 int hrs = (SiS_GetReg(SiS_Pr->SiS_P3d4,0x04) |
2689 ((SiS_GetReg(SiS_Pr->SiS_P3c4,0x0b) & 0xc0) << 2)) - 3;
2690 int hto = (SiS_GetReg(SiS_Pr->SiS_P3d4,0x00) |
2691 ((SiS_GetReg(SiS_Pr->SiS_P3c4,0x0b) & 0x03) << 8)) + 5;
2692 data = hrs - (hto >> 1) + 3;
2694 SiS_SetReg(SiS_Pr->SiS_P3d4,0x19,data);
2695 SiS_SetRegANDOR(SiS_Pr->SiS_P3d4,0x1a,0xFC,((data >> 8) & 0x03));
2698 if(modeflag & HalfDCLK) {
2699 SiS_SetRegOR(SiS_Pr->SiS_P3c4,0x01,0x08);
2703 if(modeflag & LineCompareOff) data = 0x08;
2704 if(SiS_Pr->ChipType == SIS_300) {
2705 SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x0F,0xF7,data);
2707 if(SiS_Pr->ChipType >= XGI_20) data |= 0x20;
2708 if(SiS_Pr->SiS_ModeType == ModeEGA) {
2713 SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x0F,0xB7,data);
2716 #ifdef CONFIG_FB_SIS_315
2717 if(SiS_Pr->ChipType >= SIS_315H) {
2718 SiS_SetRegAND(SiS_Pr->SiS_P3c4,0x31,0xfb);
2721 if(SiS_Pr->ChipType == SIS_315PRO) {
2723 data = SiS_Pr->SiS_SR15[(2 * 4) + SiS_Get310DRAMType(SiS_Pr)];
2724 if(SiS_Pr->SiS_ModeType == ModeText) {
2727 data2 = SiS_GetOffset(SiS_Pr, ModeNo, ModeIdIndex, RRTI) >> 1;
2728 if(infoflag & InterlaceMode) data2 >>= 1;
2729 data3 = SiS_GetColorDepth(SiS_Pr, ModeNo, ModeIdIndex) >> 1;
2730 if(data3) data2 /= data3;
2736 SiS_SetReg(SiS_Pr->SiS_P3c4,0x17,data);
2738 } else if((SiS_Pr->ChipType == SIS_330) || (SiS_Pr->SiS_SysFlags & SF_760LFB)) {
2740 data = SiS_Get310DRAMType(SiS_Pr);
2741 if(SiS_Pr->ChipType == SIS_330) {
2742 data = SiS_Pr->SiS_SR15[(2 * 4) + data];
2744 if(SiS_Pr->SiS_ROMNew) data = ROMAddr[0xf6];
2745 else if(SiS_Pr->SiS_UseROM) data = ROMAddr[0x100 + data];
2748 if(SiS_Pr->SiS_ModeType <= ModeEGA) {
2751 if(SiS_Pr->UseCustomMode) {
2752 data2 = SiS_Pr->CSRClock;
2754 data2 = SiS_GetVCLK2Ptr(SiS_Pr, ModeNo, ModeIdIndex, RRTI);
2755 data2 = SiS_Pr->SiS_VCLKData[data2].CLOCK;
2758 data3 = SiS_GetColorDepth(SiS_Pr, ModeNo, ModeIdIndex) >> 1;
2759 if(data3) data2 *= data3;
2761 data2 = ((unsigned int)(SiS_GetMCLK(SiS_Pr) * 1024)) / data2;
2763 if(SiS_Pr->ChipType == SIS_330) {
2764 if(SiS_Pr->SiS_ModeType != Mode16Bpp) {
2765 if (data2 >= 0x19c) data = 0xba;
2766 else if(data2 >= 0x140) data = 0x7a;
2767 else if(data2 >= 0x101) data = 0x3a;
2768 else if(data2 >= 0xf5) data = 0x32;
2769 else if(data2 >= 0xe2) data = 0x2a;
2770 else if(data2 >= 0xc4) data = 0x22;
2771 else if(data2 >= 0xac) data = 0x1a;
2772 else if(data2 >= 0x9e) data = 0x12;
2773 else if(data2 >= 0x8e) data = 0x0a;
2776 if(data2 >= 0x127) data = 0xba;
2779 } else { /* 76x+LFB */
2780 if (data2 >= 0x190) data = 0xba;
2781 else if(data2 >= 0xff) data = 0x7a;
2782 else if(data2 >= 0xd3) data = 0x3a;
2783 else if(data2 >= 0xa9) data = 0x1a;
2784 else if(data2 >= 0x93) data = 0x0a;
2788 SiS_SetReg(SiS_Pr->SiS_P3c4,0x17,data);
2792 /* TODO: Check SiS340 */
2796 if(SiS_Pr->SiS_ModeType != ModeText) {
2798 if(SiS_Pr->SiS_ModeType != ModeEGA) {
2802 SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x21,0x1F,data);
2804 SiS_SetVCLKState(SiS_Pr, ModeNo, RRTI, ModeIdIndex);
2806 #ifdef CONFIG_FB_SIS_315
2807 if(((SiS_Pr->ChipType >= SIS_315H) && (SiS_Pr->ChipType < SIS_661)) ||
2808 (SiS_Pr->ChipType == XGI_40)) {
2809 if(SiS_GetReg(SiS_Pr->SiS_P3d4,0x31) & 0x40) {
2810 SiS_SetReg(SiS_Pr->SiS_P3d4,0x52,0x2c);
2812 SiS_SetReg(SiS_Pr->SiS_P3d4,0x52,0x6c);
2814 } else if(SiS_Pr->ChipType == XGI_20) {
2815 if(SiS_GetReg(SiS_Pr->SiS_P3d4,0x31) & 0x40) {
2816 SiS_SetReg(SiS_Pr->SiS_P3d4,0x52,0x33);
2818 SiS_SetReg(SiS_Pr->SiS_P3d4,0x52,0x73);
2820 SiS_SetReg(SiS_Pr->SiS_P3d4,0x51,0x02);
2825 #ifdef CONFIG_FB_SIS_315
2827 SiS_SetupDualChip(struct SiS_Private *SiS_Pr)
2830 /* TODO: Find out about IOAddress2 */
2831 SISIOADDRESS P2_3c2 = SiS_Pr->IOAddress2 + 0x12;
2832 SISIOADDRESS P2_3c4 = SiS_Pr->IOAddress2 + 0x14;
2833 SISIOADDRESS P2_3ce = SiS_Pr->IOAddress2 + 0x1e;
2836 if((SiS_Pr->ChipRevision != 0) ||
2837 (!(SiS_GetReg(SiS_Pr->SiS_P3c4,0x3a) & 0x04)))
2840 for(i = 0; i <= 4; i++) { /* SR00 - SR04 */
2841 SiS_SetReg(P2_3c4,i,SiS_GetReg(SiS_Pr->SiS_P3c4,i));
2843 for(i = 0; i <= 8; i++) { /* GR00 - GR08 */
2844 SiS_SetReg(P2_3ce,i,SiS_GetReg(SiS_Pr->SiS_P3ce,i));
2846 SiS_SetReg(P2_3c4,0x05,0x86);
2847 SiS_SetReg(P2_3c4,0x06,SiS_GetReg(SiS_Pr->SiS_P3c4,0x06)); /* SR06 */
2848 SiS_SetReg(P2_3c4,0x21,SiS_GetReg(SiS_Pr->SiS_P3c4,0x21)); /* SR21 */
2849 SiS_SetRegByte(P2_3c2,SiS_GetRegByte(SiS_Pr->SiS_P3cc)); /* MISC */
2850 SiS_SetReg(P2_3c4,0x05,0x00);
2855 /*********************************************/
2857 /*********************************************/
2860 SiS_WriteDAC(struct SiS_Private *SiS_Pr, SISIOADDRESS DACData, unsigned short shiftflag,
2861 unsigned short dl, unsigned short ah, unsigned short al, unsigned short dh)
2863 unsigned short d1, d2, d3;
2866 case 0: d1 = dh; d2 = ah; d3 = al; break;
2867 case 1: d1 = ah; d2 = al; d3 = dh; break;
2868 default: d1 = al; d2 = dh; d3 = ah;
2870 SiS_SetRegByte(DACData, (d1 << shiftflag));
2871 SiS_SetRegByte(DACData, (d2 << shiftflag));
2872 SiS_SetRegByte(DACData, (d3 << shiftflag));
2876 SiS_LoadDAC(struct SiS_Private *SiS_Pr, unsigned short ModeNo, unsigned short ModeIdIndex)
2878 unsigned short data, data2, time, i, j, k, m, n, o;
2879 unsigned short si, di, bx, sf;
2880 SISIOADDRESS DACAddr, DACData;
2881 const unsigned char *table = NULL;
2883 data = SiS_GetModeFlag(SiS_Pr, ModeNo, ModeIdIndex) & DACInfoFlag;
2886 if(data == 0x00) table = SiS_MDA_DAC;
2887 else if(data == 0x08) table = SiS_CGA_DAC;
2888 else if(data == 0x10) table = SiS_EGA_DAC;
2889 else if(data == 0x18) {
2892 table = SiS_VGA_DAC;
2895 if( ( (SiS_Pr->SiS_VBInfo & SetCRT2ToLCD) && /* 301B-DH LCD */
2896 (SiS_Pr->SiS_VBType & VB_NoLCD) ) ||
2897 (SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA) || /* LCDA */
2898 (!(SiS_Pr->SiS_SetFlag & ProgrammingCRT2)) ) { /* Programming CRT1 */
2899 SiS_SetRegByte(SiS_Pr->SiS_P3c6,0xFF);
2900 DACAddr = SiS_Pr->SiS_P3c8;
2901 DACData = SiS_Pr->SiS_P3c9;
2904 DACAddr = SiS_Pr->SiS_Part5Port;
2905 DACData = SiS_Pr->SiS_Part5Port + 1;
2909 SiS_SetRegByte(DACAddr,0x00);
2911 for(i = 0; i < j; i++) {
2913 for(k = 0; k < 3; k++) {
2915 if(data & 0x01) data2 += 0x2A;
2916 if(data & 0x02) data2 += 0x15;
2917 SiS_SetRegByte(DACData, (data2 << sf));
2923 for(i = 16; i < 32; i++) {
2924 data = table[i] << sf;
2925 for(k = 0; k < 3; k++) SiS_SetRegByte(DACData, data);
2928 for(m = 0; m < 9; m++) {
2931 for(n = 0; n < 3; n++) {
2932 for(o = 0; o < 5; o++) {
2933 SiS_WriteDAC(SiS_Pr, DACData, sf, n, table[di], table[bx], table[si]);
2937 for(o = 0; o < 3; o++) {
2938 SiS_WriteDAC(SiS_Pr, DACData, sf, n, table[di], table[si], table[bx]);
2947 /*********************************************/
2948 /* SET CRT1 REGISTER GROUP */
2949 /*********************************************/
2952 SiS_SetCRT1Group(struct SiS_Private *SiS_Pr, unsigned short ModeNo, unsigned short ModeIdIndex)
2954 unsigned short StandTableIndex, RefreshRateTableIndex;
2956 SiS_Pr->SiS_CRT1Mode = ModeNo;
2958 StandTableIndex = SiS_GetModePtr(SiS_Pr, ModeNo, ModeIdIndex);
2960 if(SiS_Pr->SiS_SetFlag & LowModeTests) {
2961 if(SiS_Pr->SiS_VBInfo & (SetSimuScanMode | SwitchCRT2)) {
2962 SiS_DisableBridge(SiS_Pr);
2966 SiS_ResetSegmentRegisters(SiS_Pr);
2968 SiS_SetSeqRegs(SiS_Pr, StandTableIndex);
2969 SiS_SetMiscRegs(SiS_Pr, StandTableIndex);
2970 SiS_SetCRTCRegs(SiS_Pr, StandTableIndex);
2971 SiS_SetATTRegs(SiS_Pr, StandTableIndex);
2972 SiS_SetGRCRegs(SiS_Pr, StandTableIndex);
2973 SiS_ClearExt1Regs(SiS_Pr, ModeNo);
2974 SiS_ResetCRT1VCLK(SiS_Pr);
2976 SiS_Pr->SiS_SelectCRT2Rate = 0;
2977 SiS_Pr->SiS_SetFlag &= (~ProgrammingCRT2);
2979 if(SiS_Pr->SiS_VBInfo & SetSimuScanMode) {
2980 if(SiS_Pr->SiS_VBInfo & SetInSlaveMode) {
2981 SiS_Pr->SiS_SetFlag |= ProgrammingCRT2;
2985 if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA) {
2986 SiS_Pr->SiS_SetFlag |= ProgrammingCRT2;
2989 RefreshRateTableIndex = SiS_GetRatePtr(SiS_Pr, ModeNo, ModeIdIndex);
2991 if(!(SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA)) {
2992 SiS_Pr->SiS_SetFlag &= ~ProgrammingCRT2;
2995 if(RefreshRateTableIndex != 0xFFFF) {
2996 SiS_SetCRT1Sync(SiS_Pr, RefreshRateTableIndex);
2997 SiS_SetCRT1CRTC(SiS_Pr, ModeNo, ModeIdIndex, RefreshRateTableIndex);
2998 SiS_SetCRT1Offset(SiS_Pr, ModeNo, ModeIdIndex, RefreshRateTableIndex);
2999 SiS_SetCRT1VCLK(SiS_Pr, ModeNo, ModeIdIndex, RefreshRateTableIndex);
3002 switch(SiS_Pr->ChipType) {
3003 #ifdef CONFIG_FB_SIS_300
3005 SiS_SetCRT1FIFO_300(SiS_Pr, ModeNo, RefreshRateTableIndex);
3010 SiS_SetCRT1FIFO_630(SiS_Pr, ModeNo, RefreshRateTableIndex);
3014 #ifdef CONFIG_FB_SIS_315
3015 if(SiS_Pr->ChipType == XGI_20) {
3016 unsigned char sr2b = 0, sr2c = 0;
3019 case 0x01: sr2b = 0x4e; sr2c = 0xe9; break;
3022 case 0x0d: sr2b = 0x1b; sr2c = 0xe3; break;
3025 SiS_SetReg(SiS_Pr->SiS_P3c4,0x2b,sr2b);
3026 SiS_SetReg(SiS_Pr->SiS_P3c4,0x2c,sr2c);
3027 SiS_SetRegByte(SiS_Pr->SiS_P3c2,(SiS_GetRegByte(SiS_Pr->SiS_P3cc) | 0x0c));
3030 SiS_SetCRT1FIFO_310(SiS_Pr, ModeNo, ModeIdIndex);
3035 SiS_SetCRT1ModeRegs(SiS_Pr, ModeNo, ModeIdIndex, RefreshRateTableIndex);
3037 #ifdef CONFIG_FB_SIS_315
3038 if(SiS_Pr->ChipType == XGI_40) {
3039 SiS_SetupDualChip(SiS_Pr);
3043 SiS_LoadDAC(SiS_Pr, ModeNo, ModeIdIndex);
3045 if(SiS_Pr->SiS_flag_clearbuffer) {
3046 SiS_ClearBuffer(SiS_Pr, ModeNo);
3049 if(!(SiS_Pr->SiS_VBInfo & (SetSimuScanMode | SwitchCRT2 | SetCRT2ToLCDA))) {
3050 SiS_WaitRetrace1(SiS_Pr);
3051 SiS_DisplayOn(SiS_Pr);
3055 /*********************************************/
3056 /* HELPER: VIDEO BRIDGE PROG CLK */
3057 /*********************************************/
3060 SiS_InitVB(struct SiS_Private *SiS_Pr)
3062 unsigned char *ROMAddr = SiS_Pr->VirtualRomBase;
3064 SiS_Pr->Init_P4_0E = 0;
3065 if(SiS_Pr->SiS_ROMNew) {
3066 SiS_Pr->Init_P4_0E = ROMAddr[0x82];
3067 } else if(SiS_Pr->ChipType >= XGI_40) {
3068 if(SiS_Pr->SiS_XGIROM) {
3069 SiS_Pr->Init_P4_0E = ROMAddr[0x80];
3075 SiS_ResetVB(struct SiS_Private *SiS_Pr)
3077 #ifdef CONFIG_FB_SIS_315
3078 unsigned char *ROMAddr = SiS_Pr->VirtualRomBase;
3079 unsigned short temp;
3081 /* VB programming clock */
3082 if(SiS_Pr->SiS_UseROM) {
3083 if(SiS_Pr->ChipType < SIS_330) {
3084 temp = ROMAddr[VB310Data_1_2_Offset] | 0x40;
3085 if(SiS_Pr->SiS_ROMNew) temp = ROMAddr[0x80] | 0x40;
3086 SiS_SetReg(SiS_Pr->SiS_Part1Port,0x02,temp);
3087 } else if(SiS_Pr->ChipType >= SIS_661 && SiS_Pr->ChipType < XGI_20) {
3088 temp = ROMAddr[0x7e] | 0x40;
3089 if(SiS_Pr->SiS_ROMNew) temp = ROMAddr[0x80] | 0x40;
3090 SiS_SetReg(SiS_Pr->SiS_Part1Port,0x02,temp);
3092 } else if(SiS_Pr->ChipType >= XGI_40) {
3094 if(SiS_Pr->SiS_XGIROM) temp |= ROMAddr[0x7e];
3095 /* Can we do this on any chipset? */
3096 SiS_SetReg(SiS_Pr->SiS_Part1Port,0x02,temp);
3101 /*********************************************/
3102 /* HELPER: SET VIDEO/CAPTURE REGISTERS */
3103 /*********************************************/
3106 SiS_StrangeStuff(struct SiS_Private *SiS_Pr)
3108 /* SiS65x and XGI set up some sort of "lock mode" for text
3109 * which locks CRT2 in some way to CRT1 timing. Disable
3112 #ifdef CONFIG_FB_SIS_315
3113 if((IS_SIS651) || (IS_SISM650) ||
3114 SiS_Pr->ChipType == SIS_340 ||
3115 SiS_Pr->ChipType == XGI_40) {
3116 SiS_SetReg(SiS_Pr->SiS_VidCapt, 0x3f, 0x00); /* Fiddle with capture regs */
3117 SiS_SetReg(SiS_Pr->SiS_VidCapt, 0x00, 0x00);
3118 SiS_SetReg(SiS_Pr->SiS_VidPlay, 0x00, 0x86); /* (BIOS does NOT unlock) */
3119 SiS_SetRegAND(SiS_Pr->SiS_VidPlay, 0x30, 0xfe); /* Fiddle with video regs */
3120 SiS_SetRegAND(SiS_Pr->SiS_VidPlay, 0x3f, 0xef);
3122 /* !!! This does not support modes < 0x13 !!! */
3126 /*********************************************/
3127 /* HELPER: SET AGP TIMING FOR SiS760 */
3128 /*********************************************/
3131 SiS_Handle760(struct SiS_Private *SiS_Pr)
3133 #ifdef CONFIG_FB_SIS_315
3134 unsigned int somebase;
3135 unsigned char temp1, temp2, temp3;
3137 if( (SiS_Pr->ChipType != SIS_760) ||
3138 ((SiS_GetReg(SiS_Pr->SiS_P3d4, 0x5c) & 0xf8) != 0x80) ||
3139 (!(SiS_Pr->SiS_SysFlags & SF_760LFB)) ||
3140 (!(SiS_Pr->SiS_SysFlags & SF_760UMA)) )
3143 somebase = sisfb_read_mio_pci_word(SiS_Pr, 0x74);
3146 if(somebase == 0) return;
3148 temp3 = SiS_GetRegByte((somebase + 0x85)) & 0xb7;
3150 if(SiS_GetReg(SiS_Pr->SiS_P3d4,0x31) & 0x40) {
3159 sisfb_write_nbridge_pci_byte(SiS_Pr, 0x7e, temp1);
3160 sisfb_write_nbridge_pci_byte(SiS_Pr, 0x8d, temp2);
3162 SiS_SetRegByte((somebase + 0x85), temp3);
3166 /*********************************************/
3168 /*********************************************/
3171 SiSSetMode(struct SiS_Private *SiS_Pr, unsigned short ModeNo)
3173 SISIOADDRESS BaseAddr = SiS_Pr->IOAddress;
3174 unsigned short RealModeNo, ModeIdIndex;
3175 unsigned char backupreg = 0;
3176 unsigned short KeepLockReg;
3178 SiS_Pr->UseCustomMode = false;
3179 SiS_Pr->CRT1UsesCustomMode = false;
3181 SiS_Pr->SiS_flag_clearbuffer = 0;
3183 if(SiS_Pr->UseCustomMode) {
3186 if(!(ModeNo & 0x80)) SiS_Pr->SiS_flag_clearbuffer = 1;
3190 /* Don't use FSTN mode for CRT1 */
3191 RealModeNo = ModeNo;
3192 if(ModeNo == 0x5b) ModeNo = 0x56;
3195 SiSRegInit(SiS_Pr, BaseAddr);
3196 SiS_GetSysFlags(SiS_Pr);
3198 SiS_Pr->SiS_VGAINFO = 0x11;
3200 KeepLockReg = SiS_GetReg(SiS_Pr->SiS_P3c4,0x05);
3201 SiS_SetReg(SiS_Pr->SiS_P3c4,0x05,0x86);
3203 SiSInitPCIetc(SiS_Pr);
3204 SiSSetLVDSetc(SiS_Pr);
3205 SiSDetermineROMUsage(SiS_Pr);
3207 SiS_UnLockCRT2(SiS_Pr);
3209 if(!SiS_Pr->UseCustomMode) {
3210 if(!(SiS_SearchModeID(SiS_Pr, &ModeNo, &ModeIdIndex))) return false;
3215 SiS_GetVBType(SiS_Pr);
3217 /* Init/restore some VB registers */
3219 if(SiS_Pr->SiS_VBType & VB_SIS30xBLV) {
3220 if(SiS_Pr->ChipType >= SIS_315H) {
3221 SiS_ResetVB(SiS_Pr);
3222 SiS_SetRegOR(SiS_Pr->SiS_P3c4,0x32,0x10);
3223 SiS_SetRegOR(SiS_Pr->SiS_Part2Port,0x00,0x0c);
3224 backupreg = SiS_GetReg(SiS_Pr->SiS_P3d4,0x38);
3226 backupreg = SiS_GetReg(SiS_Pr->SiS_P3d4,0x35);
3230 /* Get VB information (connectors, connected devices) */
3231 SiS_GetVBInfo(SiS_Pr, ModeNo, ModeIdIndex, (SiS_Pr->UseCustomMode) ? 0 : 1);
3232 SiS_SetYPbPr(SiS_Pr);
3233 SiS_SetTVMode(SiS_Pr, ModeNo, ModeIdIndex);
3234 SiS_GetLCDResInfo(SiS_Pr, ModeNo, ModeIdIndex);
3235 SiS_SetLowModeTest(SiS_Pr, ModeNo);
3237 /* Check memory size (kernel framebuffer driver only) */
3238 if(!SiS_CheckMemorySize(SiS_Pr, ModeNo, ModeIdIndex)) {
3242 SiS_OpenCRTC(SiS_Pr);
3244 if(SiS_Pr->UseCustomMode) {
3245 SiS_Pr->CRT1UsesCustomMode = true;
3246 SiS_Pr->CSRClock_CRT1 = SiS_Pr->CSRClock;
3247 SiS_Pr->CModeFlag_CRT1 = SiS_Pr->CModeFlag;
3249 SiS_Pr->CRT1UsesCustomMode = false;
3252 /* Set mode on CRT1 */
3253 if( (SiS_Pr->SiS_VBInfo & (SetSimuScanMode | SetCRT2ToLCDA)) ||
3254 (!(SiS_Pr->SiS_VBInfo & SwitchCRT2)) ) {
3255 SiS_SetCRT1Group(SiS_Pr, ModeNo, ModeIdIndex);
3258 /* Set mode on CRT2 */
3259 if(SiS_Pr->SiS_VBInfo & (SetSimuScanMode | SwitchCRT2 | SetCRT2ToLCDA)) {
3260 if( (SiS_Pr->SiS_VBType & VB_SISVB) ||
3261 (SiS_Pr->SiS_IF_DEF_LVDS == 1) ||
3262 (SiS_Pr->SiS_IF_DEF_CH70xx != 0) ||
3263 (SiS_Pr->SiS_IF_DEF_TRUMPION != 0) ) {
3264 SiS_SetCRT2Group(SiS_Pr, RealModeNo);
3268 SiS_HandleCRT1(SiS_Pr);
3270 SiS_StrangeStuff(SiS_Pr);
3272 SiS_DisplayOn(SiS_Pr);
3273 SiS_SetRegByte(SiS_Pr->SiS_P3c6,0xFF);
3275 #ifdef CONFIG_FB_SIS_315
3276 if(SiS_Pr->ChipType >= SIS_315H) {
3277 if(SiS_Pr->SiS_IF_DEF_LVDS == 1) {
3278 if(!(SiS_IsDualEdge(SiS_Pr))) {
3279 SiS_SetRegAND(SiS_Pr->SiS_Part1Port,0x13,0xfb);
3285 if(SiS_Pr->SiS_VBType & VB_SIS30xBLV) {
3286 if(SiS_Pr->ChipType >= SIS_315H) {
3287 #ifdef CONFIG_FB_SIS_315
3288 if(!SiS_Pr->SiS_ROMNew) {
3289 if(SiS_IsVAMode(SiS_Pr)) {
3290 SiS_SetRegOR(SiS_Pr->SiS_P3d4,0x35,0x01);
3292 SiS_SetRegAND(SiS_Pr->SiS_P3d4,0x35,0xFE);
3296 SiS_SetReg(SiS_Pr->SiS_P3d4,0x38,backupreg);
3298 if((IS_SIS650) && (SiS_GetReg(SiS_Pr->SiS_P3d4,0x30) & 0xfc)) {
3299 if((ModeNo == 0x03) || (ModeNo == 0x10)) {
3300 SiS_SetRegOR(SiS_Pr->SiS_P3d4,0x51,0x80);
3301 SiS_SetRegOR(SiS_Pr->SiS_P3d4,0x56,0x08);
3305 if(SiS_GetReg(SiS_Pr->SiS_P3d4,0x30) & SetCRT2ToLCD) {
3306 SiS_SetRegAND(SiS_Pr->SiS_P3d4,0x38,0xfc);
3309 } else if((SiS_Pr->ChipType == SIS_630) ||
3310 (SiS_Pr->ChipType == SIS_730)) {
3311 SiS_SetReg(SiS_Pr->SiS_P3d4,0x35,backupreg);
3315 SiS_CloseCRTC(SiS_Pr);
3317 SiS_Handle760(SiS_Pr);
3319 /* We never lock registers in XF86 */
3320 if(KeepLockReg != 0xA1) SiS_SetReg(SiS_Pr->SiS_P3c4,0x05,0x00);
3326 #define BITMASK(h,l) (((unsigned)(1U << ((h)-(l)+1))-1)<<(l))
3327 #define GENMASK(mask) BITMASK(1?mask,0?mask)
3328 #define GETBITS(var,mask) (((var) & GENMASK(mask)) >> (0?mask))
3329 #define GETBITSTR(val,from,to) ((GETBITS(val,from)) << (0?to))
3333 SiS_CalcCRRegisters(struct SiS_Private *SiS_Pr, int depth)
3335 int x = 1; /* Fix sync */
3337 SiS_Pr->CCRT1CRTC[0] = ((SiS_Pr->CHTotal >> 3) - 5) & 0xff; /* CR0 */
3338 SiS_Pr->CCRT1CRTC[1] = (SiS_Pr->CHDisplay >> 3) - 1; /* CR1 */
3339 SiS_Pr->CCRT1CRTC[2] = (SiS_Pr->CHBlankStart >> 3) - 1; /* CR2 */
3340 SiS_Pr->CCRT1CRTC[3] = (((SiS_Pr->CHBlankEnd >> 3) - 1) & 0x1F) | 0x80; /* CR3 */
3341 SiS_Pr->CCRT1CRTC[4] = (SiS_Pr->CHSyncStart >> 3) + 3; /* CR4 */
3342 SiS_Pr->CCRT1CRTC[5] = ((((SiS_Pr->CHBlankEnd >> 3) - 1) & 0x20) << 2) | /* CR5 */
3343 (((SiS_Pr->CHSyncEnd >> 3) + 3) & 0x1F);
3345 SiS_Pr->CCRT1CRTC[6] = (SiS_Pr->CVTotal - 2) & 0xFF; /* CR6 */
3346 SiS_Pr->CCRT1CRTC[7] = (((SiS_Pr->CVTotal - 2) & 0x100) >> 8) /* CR7 */
3347 | (((SiS_Pr->CVDisplay - 1) & 0x100) >> 7)
3348 | (((SiS_Pr->CVSyncStart - x) & 0x100) >> 6)
3349 | (((SiS_Pr->CVBlankStart- 1) & 0x100) >> 5)
3351 | (((SiS_Pr->CVTotal - 2) & 0x200) >> 4)
3352 | (((SiS_Pr->CVDisplay - 1) & 0x200) >> 3)
3353 | (((SiS_Pr->CVSyncStart - x) & 0x200) >> 2);
3355 SiS_Pr->CCRT1CRTC[16] = ((((SiS_Pr->CVBlankStart - 1) & 0x200) >> 4) >> 5); /* CR9 */
3358 if(SiS_Pr->CHDisplay >= 1600) SiS_Pr->CCRT1CRTC[16] |= 0x60; /* SRE */
3359 else if(SiS_Pr->CHDisplay >= 640) SiS_Pr->CCRT1CRTC[16] |= 0x40;
3362 SiS_Pr->CCRT1CRTC[8] = (SiS_Pr->CVSyncStart - x) & 0xFF; /* CR10 */
3363 SiS_Pr->CCRT1CRTC[9] = ((SiS_Pr->CVSyncEnd - x) & 0x0F) | 0x80; /* CR11 */
3364 SiS_Pr->CCRT1CRTC[10] = (SiS_Pr->CVDisplay - 1) & 0xFF; /* CR12 */
3365 SiS_Pr->CCRT1CRTC[11] = (SiS_Pr->CVBlankStart - 1) & 0xFF; /* CR15 */
3366 SiS_Pr->CCRT1CRTC[12] = (SiS_Pr->CVBlankEnd - 1) & 0xFF; /* CR16 */
3368 SiS_Pr->CCRT1CRTC[13] = /* SRA */
3369 GETBITSTR((SiS_Pr->CVTotal -2), 10:10, 0:0) |
3370 GETBITSTR((SiS_Pr->CVDisplay -1), 10:10, 1:1) |
3371 GETBITSTR((SiS_Pr->CVBlankStart-1), 10:10, 2:2) |
3372 GETBITSTR((SiS_Pr->CVSyncStart -x), 10:10, 3:3) |
3373 GETBITSTR((SiS_Pr->CVBlankEnd -1), 8:8, 4:4) |
3374 GETBITSTR((SiS_Pr->CVSyncEnd ), 4:4, 5:5) ;
3376 SiS_Pr->CCRT1CRTC[14] = /* SRB */
3377 GETBITSTR((SiS_Pr->CHTotal >> 3) - 5, 9:8, 1:0) |
3378 GETBITSTR((SiS_Pr->CHDisplay >> 3) - 1, 9:8, 3:2) |
3379 GETBITSTR((SiS_Pr->CHBlankStart >> 3) - 1, 9:8, 5:4) |
3380 GETBITSTR((SiS_Pr->CHSyncStart >> 3) + 3, 9:8, 7:6) ;
3383 SiS_Pr->CCRT1CRTC[15] = /* SRC */
3384 GETBITSTR((SiS_Pr->CHBlankEnd >> 3) - 1, 7:6, 1:0) |
3385 GETBITSTR((SiS_Pr->CHSyncEnd >> 3) + 3, 5:5, 2:2) ;
3389 SiS_CalcLCDACRT1Timing(struct SiS_Private *SiS_Pr, unsigned short ModeNo,
3390 unsigned short ModeIdIndex)
3392 unsigned short modeflag, tempax, tempbx = 0, remaining = 0;
3393 unsigned short VGAHDE = SiS_Pr->SiS_VGAHDE;
3396 /* 1:1 data: use data set by setcrt1crtc() */
3397 if(SiS_Pr->SiS_LCDInfo & LCDPass11) return;
3399 modeflag = SiS_GetModeFlag(SiS_Pr, ModeNo, ModeIdIndex);
3401 if(modeflag & HalfDCLK) VGAHDE >>= 1;
3403 SiS_Pr->CHDisplay = VGAHDE;
3404 SiS_Pr->CHBlankStart = VGAHDE;
3406 SiS_Pr->CVDisplay = SiS_Pr->SiS_VGAVDE;
3407 SiS_Pr->CVBlankStart = SiS_Pr->SiS_VGAVDE;
3409 if(SiS_Pr->ChipType < SIS_315H) {
3410 #ifdef CONFIG_FB_SIS_300
3411 tempbx = SiS_Pr->SiS_VGAHT;
3412 if(SiS_Pr->SiS_LCDInfo & DontExpandLCD) {
3413 tempbx = SiS_Pr->PanelHT;
3415 if(modeflag & HalfDCLK) tempbx >>= 1;
3416 remaining = tempbx % 8;
3419 #ifdef CONFIG_FB_SIS_315
3420 /* OK for LCDA, LVDS */
3421 tempbx = SiS_Pr->PanelHT - SiS_Pr->PanelXRes;
3422 tempax = SiS_Pr->SiS_VGAHDE; /* not /2 ! */
3423 if(SiS_Pr->SiS_LCDInfo & DontExpandLCD) {
3424 tempax = SiS_Pr->PanelXRes;
3427 if(modeflag & HalfDCLK) tempbx -= VGAHDE;
3430 SiS_Pr->CHTotal = SiS_Pr->CHBlankEnd = tempbx;
3432 if(SiS_Pr->ChipType < SIS_315H) {
3433 #ifdef CONFIG_FB_SIS_300
3434 if(SiS_Pr->SiS_VGAHDE == SiS_Pr->PanelXRes) {
3435 SiS_Pr->CHSyncStart = SiS_Pr->SiS_VGAHDE + ((SiS_Pr->PanelHRS + 1) & ~1);
3436 SiS_Pr->CHSyncEnd = SiS_Pr->CHSyncStart + SiS_Pr->PanelHRE;
3437 if(modeflag & HalfDCLK) {
3438 SiS_Pr->CHSyncStart >>= 1;
3439 SiS_Pr->CHSyncEnd >>= 1;
3441 } else if(SiS_Pr->SiS_LCDInfo & DontExpandLCD) {
3442 tempax = (SiS_Pr->PanelXRes - SiS_Pr->SiS_VGAHDE) >> 1;
3443 tempbx = (SiS_Pr->PanelHRS + 1) & ~1;
3444 if(modeflag & HalfDCLK) {
3448 SiS_Pr->CHSyncStart = (VGAHDE + tempax + tempbx + 7) & ~7;
3449 tempax = SiS_Pr->PanelHRE + 7;
3450 if(modeflag & HalfDCLK) tempax >>= 1;
3451 SiS_Pr->CHSyncEnd = (SiS_Pr->CHSyncStart + tempax) & ~7;
3453 SiS_Pr->CHSyncStart = SiS_Pr->SiS_VGAHDE;
3454 if(modeflag & HalfDCLK) {
3455 SiS_Pr->CHSyncStart >>= 1;
3456 tempax = ((SiS_Pr->CHTotal - SiS_Pr->CHSyncStart) / 3) << 1;
3457 SiS_Pr->CHSyncEnd = SiS_Pr->CHSyncStart + tempax;
3459 SiS_Pr->CHSyncEnd = (SiS_Pr->CHSyncStart + (SiS_Pr->CHTotal / 10) + 7) & ~7;
3460 SiS_Pr->CHSyncStart += 8;
3465 #ifdef CONFIG_FB_SIS_315
3467 if(SiS_Pr->SiS_LCDInfo & DontExpandLCD) {
3468 tempbx = SiS_Pr->PanelXRes;
3469 if(modeflag & HalfDCLK) tempbx >>= 1;
3470 tempax += ((tempbx - tempax) >> 1);
3472 tempax += SiS_Pr->PanelHRS;
3473 SiS_Pr->CHSyncStart = tempax;
3474 tempax += SiS_Pr->PanelHRE;
3475 SiS_Pr->CHSyncEnd = tempax;
3479 tempbx = SiS_Pr->PanelVT - SiS_Pr->PanelYRes;
3480 tempax = SiS_Pr->SiS_VGAVDE;
3481 if(SiS_Pr->SiS_LCDInfo & DontExpandLCD) {
3482 tempax = SiS_Pr->PanelYRes;
3483 } else if(SiS_Pr->ChipType < SIS_315H) {
3484 #ifdef CONFIG_FB_SIS_300
3485 /* Stupid hack for 640x400/320x200 */
3486 if(SiS_Pr->SiS_LCDResInfo == Panel_1024x768) {
3487 if((tempax + tempbx) == 438) tempbx += 16;
3488 } else if((SiS_Pr->SiS_LCDResInfo == Panel_800x600) ||
3489 (SiS_Pr->SiS_LCDResInfo == Panel_1024x600)) {
3491 tempbx = SiS_Pr->SiS_VGAVT;
3495 SiS_Pr->CVTotal = SiS_Pr->CVBlankEnd = tempbx + tempax;
3497 tempax = SiS_Pr->SiS_VGAVDE;
3498 if(SiS_Pr->SiS_LCDInfo & DontExpandLCD) {
3499 tempax += (SiS_Pr->PanelYRes - tempax) >> 1;
3501 tempax += SiS_Pr->PanelVRS;
3502 SiS_Pr->CVSyncStart = tempax;
3503 tempax += SiS_Pr->PanelVRE;
3504 SiS_Pr->CVSyncEnd = tempax;
3505 if(SiS_Pr->ChipType < SIS_315H) {
3506 SiS_Pr->CVSyncStart--;
3507 SiS_Pr->CVSyncEnd--;
3510 SiS_CalcCRRegisters(SiS_Pr, 8);
3511 SiS_Pr->CCRT1CRTC[15] &= ~0xF8;
3512 SiS_Pr->CCRT1CRTC[15] |= (remaining << 4);
3513 SiS_Pr->CCRT1CRTC[16] &= ~0xE0;
3515 SiS_SetRegAND(SiS_Pr->SiS_P3d4,0x11,0x7f);
3517 for(i = 0, j = 0; i <= 7; i++, j++) {
3518 SiS_SetReg(SiS_Pr->SiS_P3d4,j,SiS_Pr->CCRT1CRTC[i]);
3520 for(j = 0x10; i <= 10; i++, j++) {
3521 SiS_SetReg(SiS_Pr->SiS_P3d4,j,SiS_Pr->CCRT1CRTC[i]);
3523 for(j = 0x15; i <= 12; i++, j++) {
3524 SiS_SetReg(SiS_Pr->SiS_P3d4,j,SiS_Pr->CCRT1CRTC[i]);
3526 for(j = 0x0A; i <= 15; i++, j++) {
3527 SiS_SetReg(SiS_Pr->SiS_P3c4,j,SiS_Pr->CCRT1CRTC[i]);
3530 tempax = SiS_Pr->CCRT1CRTC[16] & 0xE0;
3531 SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x0E,0x1F,tempax);
3533 tempax = (SiS_Pr->CCRT1CRTC[16] & 0x01) << 5;
3534 if(modeflag & DoubleScanMode) tempax |= 0x80;
3535 SiS_SetRegANDOR(SiS_Pr->SiS_P3d4,0x09,0x5F,tempax);
3540 SiS_Generic_ConvertCRData(struct SiS_Private *SiS_Pr, unsigned char *crdata,
3542 struct fb_var_screeninfo *var, bool writeres
3545 unsigned short HRE, HBE, HRS, HBS, HDE, HT;
3546 unsigned short VRE, VBE, VRS, VBS, VDE, VT;
3547 unsigned char sr_data, cr_data, cr_data2;
3548 int A, B, C, D, E, F, temp;
3550 sr_data = crdata[14];
3552 /* Horizontal total */
3553 HT = crdata[0] | ((unsigned short)(sr_data & 0x03) << 8);
3556 /* Horizontal display enable end */
3557 HDE = crdata[1] | ((unsigned short)(sr_data & 0x0C) << 6);
3560 /* Horizontal retrace (=sync) start */
3561 HRS = crdata[4] | ((unsigned short)(sr_data & 0xC0) << 2);
3564 /* Horizontal blank start */
3565 HBS = crdata[2] | ((unsigned short)(sr_data & 0x30) << 4);
3567 sr_data = crdata[15];
3568 cr_data = crdata[5];
3570 /* Horizontal blank end */
3571 HBE = (crdata[3] & 0x1f) |
3572 ((unsigned short)(cr_data & 0x80) >> 2) |
3573 ((unsigned short)(sr_data & 0x03) << 6);
3575 /* Horizontal retrace (=sync) end */
3576 HRE = (cr_data & 0x1f) | ((sr_data & 0x04) << 3);
3578 temp = HBE - ((E - 1) & 255);
3579 B = (temp > 0) ? temp : (temp + 256);
3581 temp = HRE - ((E + F + 3) & 63);
3582 C = (temp > 0) ? temp : (temp + 64);
3586 if(writeres) var->xres = xres = E * 8;
3587 var->left_margin = D * 8;
3588 var->right_margin = F * 8;
3589 var->hsync_len = C * 8;
3592 sr_data = crdata[13];
3593 cr_data = crdata[7];
3595 /* Vertical total */
3597 ((unsigned short)(cr_data & 0x01) << 8) |
3598 ((unsigned short)(cr_data & 0x20) << 4) |
3599 ((unsigned short)(sr_data & 0x01) << 10);
3602 /* Vertical display enable end */
3604 ((unsigned short)(cr_data & 0x02) << 7) |
3605 ((unsigned short)(cr_data & 0x40) << 3) |
3606 ((unsigned short)(sr_data & 0x02) << 9);
3609 /* Vertical retrace (=sync) start */
3611 ((unsigned short)(cr_data & 0x04) << 6) |
3612 ((unsigned short)(cr_data & 0x80) << 2) |
3613 ((unsigned short)(sr_data & 0x08) << 7);
3616 cr_data2 = (crdata[16] & 0x01) << 5;
3618 /* Vertical blank start */
3620 ((unsigned short)(cr_data & 0x08) << 5) |
3621 ((unsigned short)(cr_data2 & 0x20) << 4) |
3622 ((unsigned short)(sr_data & 0x04) << 8);
3624 /* Vertical blank end */
3625 VBE = crdata[12] | ((unsigned short)(sr_data & 0x10) << 4);
3626 temp = VBE - ((E - 1) & 511);
3627 B = (temp > 0) ? temp : (temp + 512);
3629 /* Vertical retrace (=sync) end */
3630 VRE = (crdata[9] & 0x0f) | ((sr_data & 0x20) >> 1);
3631 temp = VRE - ((E + F - 1) & 31);
3632 C = (temp > 0) ? temp : (temp + 32);
3636 if(writeres) var->yres = yres = E;
3637 var->upper_margin = D;
3638 var->lower_margin = F;
3641 if((xres == 320) && ((yres == 200) || (yres == 240))) {
3642 /* Terrible hack, but correct CRTC data for
3643 * these modes only produces a black screen...
3644 * (HRE is 0, leading into a too large C and
3645 * a negative D. The CRT controller does not
3646 * seem to like correcting HRE to 50)
3648 var->left_margin = (400 - 376);
3649 var->right_margin = (328 - 320);
3650 var->hsync_len = (376 - 328);