drivers/video/sunxi_display.c

   1 /*
   2  * Display driver for Allwinner SoCs.
   3  *
   4  * (C) Copyright 2013-2014 Luc Verhaegen <libv@skynet.be>
   5  * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/display.h>
  14 #include <asm/arch/gpio.h>
  15 #include <asm/global_data.h>
  16 #include <asm/gpio.h>
  17 #include <asm/io.h>
  18 #include <errno.h>
  19 #include <fdtdec.h>
  20 #include <fdt_support.h>
  21 #include <video_fb.h>
  22 #include "videomodes.h"
  23 #include "ssd2828.h"
  24
  25 DECLARE_GLOBAL_DATA_PTR;
  26
  27 enum sunxi_monitor {
  28         sunxi_monitor_none,
  29         sunxi_monitor_dvi,
  30         sunxi_monitor_hdmi,
  31         sunxi_monitor_lcd,
  32         sunxi_monitor_vga,
  33 };
  34 #define SUNXI_MONITOR_LAST sunxi_monitor_vga
  35
  36 struct sunxi_display {
  37         GraphicDevice graphic_device;
  38         enum sunxi_monitor monitor;
  39         unsigned int depth;
  40 } sunxi_display;
  41
  42 #ifdef CONFIG_VIDEO_HDMI
  43
  44 /*
  45  * Wait up to 200ms for value to be set in given part of reg.
  46  */
  47 static int await_completion(u32 *reg, u32 mask, u32 val)
  48 {
  49         unsigned long tmo = timer_get_us() + 200000;
  50
  51         while ((readl(reg) & mask) != val) {
  52                 if (timer_get_us() > tmo) {
  53                         printf("DDC: timeout reading EDID\n");
  54                         return -ETIME;
  55                 }
  56         }
  57         return 0;
  58 }
  59
  60 static int sunxi_hdmi_hpd_detect(int hpd_delay)
  61 {
  62         struct sunxi_ccm_reg * const ccm =
  63                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  64         struct sunxi_hdmi_reg * const hdmi =
  65                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
  66         unsigned long tmo = timer_get_us() + hpd_delay * 1000;
  67
  68         /* Set pll3 to 300MHz */
  69         clock_set_pll3(300000000);
  70
  71         /* Set hdmi parent to pll3 */
  72         clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK,
  73                         CCM_HDMI_CTRL_PLL3);
  74
  75         /* Set ahb gating to pass */
  76 #ifdef CONFIG_MACH_SUN6I
  77         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
  78 #endif
  79         setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
  80
  81         /* Clock on */
  82         setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
  83
  84         writel(SUNXI_HDMI_CTRL_ENABLE, &hdmi->ctrl);
  85         writel(SUNXI_HDMI_PAD_CTRL0_HDP, &hdmi->pad_ctrl0);
  86
  87         while (timer_get_us() < tmo) {
  88                 if (readl(&hdmi->hpd) & SUNXI_HDMI_HPD_DETECT)
  89                         return 1;
  90         }
  91
  92         return 0;
  93 }
  94
  95 static void sunxi_hdmi_shutdown(void)
  96 {
  97         struct sunxi_ccm_reg * const ccm =
  98                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  99         struct sunxi_hdmi_reg * const hdmi =
 100                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 101
 102         clrbits_le32(&hdmi->ctrl, SUNXI_HDMI_CTRL_ENABLE);
 103         clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
 104         clrbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
 105 #ifdef CONFIG_MACH_SUN6I
 106         clrbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
 107 #endif
 108         clock_set_pll3(0);
 109 }
 110
 111 static int sunxi_hdmi_ddc_do_command(u32 cmnd, int offset, int n)
 112 {
 113         struct sunxi_hdmi_reg * const hdmi =
 114                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 115
 116         setbits_le32(&hdmi->ddc_fifo_ctrl, SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR);
 117         writel(SUNXI_HMDI_DDC_ADDR_EDDC_SEGMENT(offset >> 8) |
 118                SUNXI_HMDI_DDC_ADDR_EDDC_ADDR |
 119                SUNXI_HMDI_DDC_ADDR_OFFSET(offset) |
 120                SUNXI_HMDI_DDC_ADDR_SLAVE_ADDR, &hdmi->ddc_addr);
 121 #ifndef CONFIG_MACH_SUN6I
 122         writel(n, &hdmi->ddc_byte_count);
 123         writel(cmnd, &hdmi->ddc_cmnd);
 124 #else
 125         writel(n << 16 | cmnd, &hdmi->ddc_cmnd);
 126 #endif
 127         setbits_le32(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_START);
 128
 129         return await_completion(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_START, 0);
 130 }
 131
 132 static int sunxi_hdmi_ddc_read(int offset, u8 *buf, int count)
 133 {
 134         struct sunxi_hdmi_reg * const hdmi =
 135                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 136         int i, n;
 137
 138         while (count > 0) {
 139                 if (count > 16)
 140                         n = 16;
 141                 else
 142                         n = count;
 143
 144                 if (sunxi_hdmi_ddc_do_command(
 145                                 SUNXI_HDMI_DDC_CMND_EXPLICIT_EDDC_READ,
 146                                 offset, n))
 147                         return -ETIME;
 148
 149                 for (i = 0; i < n; i++)
 150                         *buf++ = readb(&hdmi->ddc_fifo_data);
 151
 152                 offset += n;
 153                 count -= n;
 154         }
 155
 156         return 0;
 157 }
 158
 159 static int sunxi_hdmi_edid_get_block(int block, u8 *buf)
 160 {
 161         int r, retries = 2;
 162
 163         do {
 164                 r = sunxi_hdmi_ddc_read(block * 128, buf, 128);
 165                 if (r)
 166                         continue;
 167                 r = edid_check_checksum(buf);
 168                 if (r) {
 169                         printf("EDID block %d: checksum error%s\n",
 170                                block, retries ? ", retrying" : "");
 171                 }
 172         } while (r && retries--);
 173
 174         return r;
 175 }
 176
 177 static int sunxi_hdmi_edid_get_mode(struct ctfb_res_modes *mode)
 178 {
 179         struct edid1_info edid1;
 180         struct edid_cea861_info cea681[4];
 181         struct edid_detailed_timing *t =
 182                 (struct edid_detailed_timing *)edid1.monitor_details.timing;
 183         struct sunxi_hdmi_reg * const hdmi =
 184                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 185         struct sunxi_ccm_reg * const ccm =
 186                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 187         int i, r, ext_blocks = 0;
 188
 189         /* SUNXI_HDMI_CTRL_ENABLE & PAD_CTRL0 are already set by hpd_detect */
 190         writel(SUNXI_HDMI_PAD_CTRL1 | SUNXI_HDMI_PAD_CTRL1_HALVE,
 191                &hdmi->pad_ctrl1);
 192         writel(SUNXI_HDMI_PLL_CTRL | SUNXI_HDMI_PLL_CTRL_DIV(15),
 193                &hdmi->pll_ctrl);
 194         writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0);
 195
 196         /* Reset i2c controller */
 197         setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE);
 198         writel(SUNXI_HMDI_DDC_CTRL_ENABLE |
 199                SUNXI_HMDI_DDC_CTRL_SDA_ENABLE |
 200                SUNXI_HMDI_DDC_CTRL_SCL_ENABLE |
 201                SUNXI_HMDI_DDC_CTRL_RESET, &hdmi->ddc_ctrl);
 202         if (await_completion(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_RESET, 0))
 203                 return -EIO;
 204
 205         writel(SUNXI_HDMI_DDC_CLOCK, &hdmi->ddc_clock);
 206 #ifndef CONFIG_MACH_SUN6I
 207         writel(SUNXI_HMDI_DDC_LINE_CTRL_SDA_ENABLE |
 208                SUNXI_HMDI_DDC_LINE_CTRL_SCL_ENABLE, &hdmi->ddc_line_ctrl);
 209 #endif
 210
 211         r = sunxi_hdmi_edid_get_block(0, (u8 *)&edid1);
 212         if (r == 0) {
 213                 r = edid_check_info(&edid1);
 214                 if (r) {
 215                         printf("EDID: invalid EDID data\n");
 216                         r = -EINVAL;
 217                 }
 218         }
 219         if (r == 0) {
 220                 ext_blocks = edid1.extension_flag;
 221                 if (ext_blocks > 4)
 222                         ext_blocks = 4;
 223                 for (i = 0; i < ext_blocks; i++) {
 224                         if (sunxi_hdmi_edid_get_block(1 + i,
 225                                                 (u8 *)&cea681[i]) != 0) {
 226                                 ext_blocks = i;
 227                                 break;
 228                         }
 229                 }
 230         }
 231
 232         /* Disable DDC engine, no longer needed */
 233         clrbits_le32(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_ENABLE);
 234         clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE);
 235
 236         if (r)
 237                 return r;
 238
 239         /* We want version 1.3 or 1.2 with detailed timing info */
 240         if (edid1.version != 1 || (edid1.revision < 3 &&
 241                         !EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(edid1))) {
 242                 printf("EDID: unsupported version %d.%d\n",
 243                        edid1.version, edid1.revision);
 244                 return -EINVAL;
 245         }
 246
 247         /* Take the first usable detailed timing */
 248         for (i = 0; i < 4; i++, t++) {
 249                 r = video_edid_dtd_to_ctfb_res_modes(t, mode);
 250                 if (r == 0)
 251                         break;
 252         }
 253         if (i == 4) {
 254                 printf("EDID: no usable detailed timing found\n");
 255                 return -ENOENT;
 256         }
 257
 258         /* Check for basic audio support, if found enable hdmi output */
 259         sunxi_display.monitor = sunxi_monitor_dvi;
 260         for (i = 0; i < ext_blocks; i++) {
 261                 if (cea681[i].extension_tag != EDID_CEA861_EXTENSION_TAG ||
 262                     cea681[i].revision < 2)
 263                         continue;
 264
 265                 if (EDID_CEA861_SUPPORTS_BASIC_AUDIO(cea681[i]))
 266                         sunxi_display.monitor = sunxi_monitor_hdmi;
 267         }
 268
 269         return 0;
 270 }
 271
 272 #endif /* CONFIG_VIDEO_HDMI */
 273
 274 /*
 275  * This is the entity that mixes and matches the different layers and inputs.
 276  * Allwinner calls it the back-end, but i like composer better.
 277  */
 278 static void sunxi_composer_init(void)
 279 {
 280         struct sunxi_ccm_reg * const ccm =
 281                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 282         struct sunxi_de_be_reg * const de_be =
 283                 (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
 284         int i;
 285
 286 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
 287         /* Reset off */
 288         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE_BE0);
 289 #endif
 290
 291         /* Clocks on */
 292         setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE_BE0);
 293         setbits_le32(&ccm->dram_clk_gate, 1 << CCM_DRAM_GATE_OFFSET_DE_BE0);
 294         clock_set_de_mod_clock(&ccm->be0_clk_cfg, 300000000);
 295
 296         /* Engine bug, clear registers after reset */
 297         for (i = 0x0800; i < 0x1000; i += 4)
 298                 writel(0, SUNXI_DE_BE0_BASE + i);
 299
 300         setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_ENABLE);
 301 }
 302
 303 static void sunxi_composer_mode_set(const struct ctfb_res_modes *mode,
 304                                     unsigned int address)
 305 {
 306         struct sunxi_de_be_reg * const de_be =
 307                 (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
 308
 309         writel(SUNXI_DE_BE_HEIGHT(mode->yres) | SUNXI_DE_BE_WIDTH(mode->xres),
 310                &de_be->disp_size);
 311         writel(SUNXI_DE_BE_HEIGHT(mode->yres) | SUNXI_DE_BE_WIDTH(mode->xres),
 312                &de_be->layer0_size);
 313         writel(SUNXI_DE_BE_LAYER_STRIDE(mode->xres), &de_be->layer0_stride);
 314         writel(address << 3, &de_be->layer0_addr_low32b);
 315         writel(address >> 29, &de_be->layer0_addr_high4b);
 316         writel(SUNXI_DE_BE_LAYER_ATTR1_FMT_XRGB8888, &de_be->layer0_attr1_ctrl);
 317
 318         setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_LAYER0_ENABLE);
 319 }
 320
 321 static void sunxi_composer_enable(void)
 322 {
 323         struct sunxi_de_be_reg * const de_be =
 324                 (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
 325
 326         setbits_le32(&de_be->reg_ctrl, SUNXI_DE_BE_REG_CTRL_LOAD_REGS);
 327         setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_START);
 328 }
 329
 330 /*
 331  * LCDC, what allwinner calls a CRTC, so timing controller and serializer.
 332  */
 333 static void sunxi_lcdc_pll_set(int tcon, int dotclock,
 334                                int *clk_div, int *clk_double)
 335 {
 336         struct sunxi_ccm_reg * const ccm =
 337                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 338         int value, n, m, min_m, max_m, diff;
 339         int best_n = 0, best_m = 0, best_diff = 0x0FFFFFFF;
 340         int best_double = 0;
 341
 342         if (tcon == 0) {
 343 #ifdef CONFIG_VIDEO_LCD_IF_PARALLEL
 344                 min_m = 6;
 345                 max_m = 127;
 346 #endif
 347 #ifdef CONFIG_VIDEO_LCD_IF_LVDS
 348                 min_m = max_m = 7;
 349 #endif
 350         } else {
 351                 min_m = 1;
 352                 max_m = 15;
 353         }
 354
 355         /*
 356          * Find the lowest divider resulting in a matching clock, if there
 357          * is no match, pick the closest lower clock, as monitors tend to
 358          * not sync to higher frequencies.
 359          */
 360         for (m = min_m; m <= max_m; m++) {
 361                 n = (m * dotclock) / 3000;
 362
 363                 if ((n >= 9) && (n <= 127)) {
 364                         value = (3000 * n) / m;
 365                         diff = dotclock - value;
 366                         if (diff < best_diff) {
 367                                 best_diff = diff;
 368                                 best_m = m;
 369                                 best_n = n;
 370                                 best_double = 0;
 371                         }
 372                 }
 373
 374                 /* These are just duplicates */
 375                 if (!(m & 1))
 376                         continue;
 377
 378                 n = (m * dotclock) / 6000;
 379                 if ((n >= 9) && (n <= 127)) {
 380                         value = (6000 * n) / m;
 381                         diff = dotclock - value;
 382                         if (diff < best_diff) {
 383                                 best_diff = diff;
 384                                 best_m = m;
 385                                 best_n = n;
 386                                 best_double = 1;
 387                         }
 388                 }
 389         }
 390
 391         debug("dotclock: %dkHz = %dkHz: (%d * 3MHz * %d) / %d\n",
 392               dotclock, (best_double + 1) * 3000 * best_n / best_m,
 393               best_double + 1, best_n, best_m);
 394
 395         clock_set_pll3(best_n * 3000000);
 396
 397         if (tcon == 0) {
 398                 writel(CCM_LCD_CH0_CTRL_GATE | CCM_LCD_CH0_CTRL_RST |
 399                        (best_double ? CCM_LCD_CH0_CTRL_PLL3_2X :
 400                                       CCM_LCD_CH0_CTRL_PLL3),
 401                        &ccm->lcd0_ch0_clk_cfg);
 402         } else {
 403                 writel(CCM_LCD_CH1_CTRL_GATE |
 404                        (best_double ? CCM_LCD_CH1_CTRL_PLL3_2X :
 405                                       CCM_LCD_CH1_CTRL_PLL3) |
 406                        CCM_LCD_CH1_CTRL_M(best_m), &ccm->lcd0_ch1_clk_cfg);
 407         }
 408
 409         *clk_div = best_m;
 410         *clk_double = best_double;
 411 }
 412
 413 static void sunxi_lcdc_init(void)
 414 {
 415         struct sunxi_ccm_reg * const ccm =
 416                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 417         struct sunxi_lcdc_reg * const lcdc =
 418                 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
 419
 420         /* Reset off */
 421 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
 422         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);
 423 #else
 424         setbits_le32(&ccm->lcd0_ch0_clk_cfg, CCM_LCD_CH0_CTRL_RST);
 425 #endif
 426
 427         /* Clock on */
 428         setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0);
 429 #ifdef CONFIG_VIDEO_LCD_IF_LVDS
 430         setbits_le32(&ccm->lvds_clk_cfg, CCM_LVDS_CTRL_RST);
 431 #endif
 432
 433         /* Init lcdc */
 434         writel(0, &lcdc->ctrl); /* Disable tcon */
 435         writel(0, &lcdc->int0); /* Disable all interrupts */
 436
 437         /* Disable tcon0 dot clock */
 438         clrbits_le32(&lcdc->tcon0_dclk, SUNXI_LCDC_TCON0_DCLK_ENABLE);
 439
 440         /* Set all io lines to tristate */
 441         writel(0xffffffff, &lcdc->tcon0_io_tristate);
 442         writel(0xffffffff, &lcdc->tcon1_io_tristate);
 443 }
 444
 445 static void sunxi_lcdc_enable(void)
 446 {
 447         struct sunxi_lcdc_reg * const lcdc =
 448                 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
 449
 450         setbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_TCON_ENABLE);
 451 #ifdef CONFIG_VIDEO_LCD_IF_LVDS
 452         setbits_le32(&lcdc->tcon0_lvds_intf, SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE);
 453         setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0);
 454         setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_UPDATE);
 455         udelay(2); /* delay at least 1200 ns */
 456         setbits_le32(&lcdc->lvds_ana1, SUNXI_LCDC_LVDS_ANA1_INIT1);
 457         udelay(1); /* delay at least 120 ns */
 458         setbits_le32(&lcdc->lvds_ana1, SUNXI_LCDC_LVDS_ANA1_INIT2);
 459         setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_UPDATE);
 460 #endif
 461 }
 462
 463 static void sunxi_lcdc_panel_enable(void)
 464 {
 465         int pin;
 466
 467         /*
 468          * Start with backlight disabled to avoid the screen flashing to
 469          * white while the lcd inits.
 470          */
 471         pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_EN);
 472         if (pin != -1) {
 473                 gpio_request(pin, "lcd_backlight_enable");
 474                 gpio_direction_output(pin, 0);
 475         }
 476
 477         pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_PWM);
 478         if (pin != -1) {
 479                 gpio_request(pin, "lcd_backlight_pwm");
 480                 /* backlight pwm is inverted, set to 1 to disable backlight */
 481                 gpio_direction_output(pin, 1);
 482         }
 483
 484         /* Give the backlight some time to turn off and power up the panel. */
 485         mdelay(40);
 486         pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_POWER);
 487         if (pin != -1) {
 488                 gpio_request(pin, "lcd_power");
 489                 gpio_direction_output(pin, 1);
 490         }
 491 }
 492
 493 static void sunxi_lcdc_backlight_enable(void)
 494 {
 495         int pin;
 496
 497         /*
 498          * We want to have scanned out at least one frame before enabling the
 499          * backlight to avoid the screen flashing to white when we enable it.
 500          */
 501         mdelay(40);
 502
 503         pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_EN);
 504         if (pin != -1)
 505                 gpio_direction_output(pin, 1);
 506
 507         pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_PWM);
 508         if (pin != -1) {
 509                 /* backlight pwm is inverted, set to 0 to enable backlight */
 510                 gpio_direction_output(pin, 0);
 511         }
 512 }
 513
 514 static int sunxi_lcdc_get_clk_delay(const struct ctfb_res_modes *mode)
 515 {
 516         int delay;
 517
 518         delay = mode->lower_margin + mode->vsync_len + mode->upper_margin - 2;
 519         return (delay > 30) ? 30 : delay;
 520 }
 521
 522 static void sunxi_lcdc_tcon0_mode_set(const struct ctfb_res_modes *mode)
 523 {
 524         struct sunxi_lcdc_reg * const lcdc =
 525                 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
 526         int bp, clk_delay, clk_div, clk_double, pin, total, val;
 527
 528         for (pin = SUNXI_GPD(0); pin <= SUNXI_GPD(27); pin++)
 529 #ifdef CONFIG_VIDEO_LCD_IF_PARALLEL
 530                 sunxi_gpio_set_cfgpin(pin, SUNXI_GPD0_LCD0);
 531 #endif
 532 #ifdef CONFIG_VIDEO_LCD_IF_LVDS
 533                 sunxi_gpio_set_cfgpin(pin, SUNXI_GPD0_LVDS0);
 534 #endif
 535
 536         sunxi_lcdc_pll_set(0, mode->pixclock_khz, &clk_div, &clk_double);
 537
 538         /* Use tcon0 */
 539         clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
 540                         SUNXI_LCDC_CTRL_IO_MAP_TCON0);
 541
 542         clk_delay = sunxi_lcdc_get_clk_delay(mode);
 543         writel(SUNXI_LCDC_TCON0_CTRL_ENABLE |
 544                SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(clk_delay), &lcdc->tcon0_ctrl);
 545
 546         writel(SUNXI_LCDC_TCON0_DCLK_ENABLE |
 547                SUNXI_LCDC_TCON0_DCLK_DIV(clk_div), &lcdc->tcon0_dclk);
 548
 549         writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
 550                &lcdc->tcon0_timing_active);
 551
 552         bp = mode->hsync_len + mode->left_margin;
 553         total = mode->xres + mode->right_margin + bp;
 554         writel(SUNXI_LCDC_TCON0_TIMING_H_TOTAL(total) |
 555                SUNXI_LCDC_TCON0_TIMING_H_BP(bp), &lcdc->tcon0_timing_h);
 556
 557         bp = mode->vsync_len + mode->upper_margin;
 558         total = mode->yres + mode->lower_margin + bp;
 559         writel(SUNXI_LCDC_TCON0_TIMING_V_TOTAL(total) |
 560                SUNXI_LCDC_TCON0_TIMING_V_BP(bp), &lcdc->tcon0_timing_v);
 561
 562 #ifdef CONFIG_VIDEO_LCD_IF_PARALLEL
 563         writel(SUNXI_LCDC_X(mode->hsync_len) | SUNXI_LCDC_Y(mode->vsync_len),
 564                &lcdc->tcon0_timing_sync);
 565
 566         writel(0, &lcdc->tcon0_hv_intf);
 567         writel(0, &lcdc->tcon0_cpu_intf);
 568 #endif
 569 #ifdef CONFIG_VIDEO_LCD_IF_LVDS
 570         val = (sunxi_display.depth == 18) ? 1 : 0;
 571         writel(SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(val), &lcdc->tcon0_lvds_intf);
 572 #endif
 573
 574         if (sunxi_display.depth == 18 || sunxi_display.depth == 16) {
 575                 writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[0]);
 576                 writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[1]);
 577                 writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[2]);
 578                 writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[3]);
 579                 writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[4]);
 580                 writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[5]);
 581                 writel(SUNXI_LCDC_TCON0_FRM_TAB0, &lcdc->tcon0_frm_table[0]);
 582                 writel(SUNXI_LCDC_TCON0_FRM_TAB1, &lcdc->tcon0_frm_table[1]);
 583                 writel(SUNXI_LCDC_TCON0_FRM_TAB2, &lcdc->tcon0_frm_table[2]);
 584                 writel(SUNXI_LCDC_TCON0_FRM_TAB3, &lcdc->tcon0_frm_table[3]);
 585                 writel(((sunxi_display.depth == 18) ?
 586                         SUNXI_LCDC_TCON0_FRM_CTRL_RGB666 :
 587                         SUNXI_LCDC_TCON0_FRM_CTRL_RGB565),
 588                        &lcdc->tcon0_frm_ctrl);
 589         }
 590
 591         val = SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(CONFIG_VIDEO_LCD_DCLK_PHASE);
 592         if (!(mode->sync & FB_SYNC_HOR_HIGH_ACT))
 593                 val |= SUNXI_LCDC_TCON_HSYNC_MASK;
 594         if (!(mode->sync & FB_SYNC_VERT_HIGH_ACT))
 595                 val |= SUNXI_LCDC_TCON_VSYNC_MASK;
 596         writel(val, &lcdc->tcon0_io_polarity);
 597
 598         writel(0, &lcdc->tcon0_io_tristate);
 599 }
 600
 601 #if defined CONFIG_VIDEO_HDMI || defined CONFIG_VIDEO_VGA
 602 static void sunxi_lcdc_tcon1_mode_set(const struct ctfb_res_modes *mode,
 603                                       int *clk_div, int *clk_double,
 604                                       bool use_portd_hvsync)
 605 {
 606         struct sunxi_lcdc_reg * const lcdc =
 607                 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
 608         int bp, clk_delay, total, val;
 609
 610         /* Use tcon1 */
 611         clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
 612                         SUNXI_LCDC_CTRL_IO_MAP_TCON1);
 613
 614         clk_delay = sunxi_lcdc_get_clk_delay(mode);
 615         writel(SUNXI_LCDC_TCON1_CTRL_ENABLE |
 616                SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(clk_delay), &lcdc->tcon1_ctrl);
 617
 618         writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
 619                &lcdc->tcon1_timing_source);
 620         writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
 621                &lcdc->tcon1_timing_scale);
 622         writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
 623                &lcdc->tcon1_timing_out);
 624
 625         bp = mode->hsync_len + mode->left_margin;
 626         total = mode->xres + mode->right_margin + bp;
 627         writel(SUNXI_LCDC_TCON1_TIMING_H_TOTAL(total) |
 628                SUNXI_LCDC_TCON1_TIMING_H_BP(bp), &lcdc->tcon1_timing_h);
 629
 630         bp = mode->vsync_len + mode->upper_margin;
 631         total = mode->yres + mode->lower_margin + bp;
 632         writel(SUNXI_LCDC_TCON1_TIMING_V_TOTAL(total) |
 633                SUNXI_LCDC_TCON1_TIMING_V_BP(bp), &lcdc->tcon1_timing_v);
 634
 635         writel(SUNXI_LCDC_X(mode->hsync_len) | SUNXI_LCDC_Y(mode->vsync_len),
 636                &lcdc->tcon1_timing_sync);
 637
 638         if (use_portd_hvsync) {
 639                 sunxi_gpio_set_cfgpin(SUNXI_GPD(26), SUNXI_GPD0_LCD0);
 640                 sunxi_gpio_set_cfgpin(SUNXI_GPD(27), SUNXI_GPD0_LCD0);
 641
 642                 val = 0;
 643                 if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
 644                         val |= SUNXI_LCDC_TCON_HSYNC_MASK;
 645                 if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
 646                         val |= SUNXI_LCDC_TCON_VSYNC_MASK;
 647                 writel(val, &lcdc->tcon1_io_polarity);
 648
 649                 clrbits_le32(&lcdc->tcon1_io_tristate,
 650                              SUNXI_LCDC_TCON_VSYNC_MASK |
 651                              SUNXI_LCDC_TCON_HSYNC_MASK);
 652         }
 653         sunxi_lcdc_pll_set(1, mode->pixclock_khz, clk_div, clk_double);
 654 }
 655 #endif /* CONFIG_VIDEO_HDMI || defined CONFIG_VIDEO_VGA */
 656
 657 #ifdef CONFIG_VIDEO_HDMI
 658
 659 static void sunxi_hdmi_setup_info_frames(const struct ctfb_res_modes *mode)
 660 {
 661         struct sunxi_hdmi_reg * const hdmi =
 662                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 663         u8 checksum = 0;
 664         u8 avi_info_frame[17] = {
 665                 0x82, 0x02, 0x0d, 0x00, 0x12, 0x00, 0x88, 0x00,
 666                 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 667                 0x00
 668         };
 669         u8 vendor_info_frame[19] = {
 670                 0x81, 0x01, 0x06, 0x29, 0x03, 0x0c, 0x00, 0x40,
 671                 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 672                 0x00, 0x00, 0x00
 673         };
 674         int i;
 675
 676         if (mode->pixclock_khz <= 27000)
 677                 avi_info_frame[5] = 0x40; /* SD-modes, ITU601 colorspace */
 678         else
 679                 avi_info_frame[5] = 0x80; /* HD-modes, ITU709 colorspace */
 680
 681         if (mode->xres * 100 / mode->yres < 156)
 682                 avi_info_frame[5] |= 0x18; /* 4 : 3 */
 683         else
 684                 avi_info_frame[5] |= 0x28; /* 16 : 9 */
 685
 686         for (i = 0; i < ARRAY_SIZE(avi_info_frame); i++)
 687                 checksum += avi_info_frame[i];
 688
 689         avi_info_frame[3] = 0x100 - checksum;
 690
 691         for (i = 0; i < ARRAY_SIZE(avi_info_frame); i++)
 692                 writeb(avi_info_frame[i], &hdmi->avi_info_frame[i]);
 693
 694         writel(SUNXI_HDMI_QCP_PACKET0, &hdmi->qcp_packet0);
 695         writel(SUNXI_HDMI_QCP_PACKET1, &hdmi->qcp_packet1);
 696
 697         for (i = 0; i < ARRAY_SIZE(vendor_info_frame); i++)
 698                 writeb(vendor_info_frame[i], &hdmi->vendor_info_frame[i]);
 699
 700         writel(SUNXI_HDMI_PKT_CTRL0, &hdmi->pkt_ctrl0);
 701         writel(SUNXI_HDMI_PKT_CTRL1, &hdmi->pkt_ctrl1);
 702
 703         setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_HDMI);
 704 }
 705
 706 static void sunxi_hdmi_mode_set(const struct ctfb_res_modes *mode,
 707                                 int clk_div, int clk_double)
 708 {
 709         struct sunxi_hdmi_reg * const hdmi =
 710                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 711         int x, y;
 712
 713         /* Write clear interrupt status bits */
 714         writel(SUNXI_HDMI_IRQ_STATUS_BITS, &hdmi->irq);
 715
 716         if (sunxi_display.monitor == sunxi_monitor_hdmi)
 717                 sunxi_hdmi_setup_info_frames(mode);
 718
 719         /* Set input sync enable */
 720         writel(SUNXI_HDMI_UNKNOWN_INPUT_SYNC, &hdmi->unknown);
 721
 722         /* Init various registers, select pll3 as clock source */
 723         writel(SUNXI_HDMI_VIDEO_POL_TX_CLK, &hdmi->video_polarity);
 724         writel(SUNXI_HDMI_PAD_CTRL0_RUN, &hdmi->pad_ctrl0);
 725         writel(SUNXI_HDMI_PAD_CTRL1, &hdmi->pad_ctrl1);
 726         writel(SUNXI_HDMI_PLL_CTRL, &hdmi->pll_ctrl);
 727         writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0);
 728
 729         /* Setup clk div and doubler */
 730         clrsetbits_le32(&hdmi->pll_ctrl, SUNXI_HDMI_PLL_CTRL_DIV_MASK,
 731                         SUNXI_HDMI_PLL_CTRL_DIV(clk_div));
 732         if (!clk_double)
 733                 setbits_le32(&hdmi->pad_ctrl1, SUNXI_HDMI_PAD_CTRL1_HALVE);
 734
 735         /* Setup timing registers */
 736         writel(SUNXI_HDMI_Y(mode->yres) | SUNXI_HDMI_X(mode->xres),
 737                &hdmi->video_size);
 738
 739         x = mode->hsync_len + mode->left_margin;
 740         y = mode->vsync_len + mode->upper_margin;
 741         writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_bp);
 742
 743         x = mode->right_margin;
 744         y = mode->lower_margin;
 745         writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_fp);
 746
 747         x = mode->hsync_len;
 748         y = mode->vsync_len;
 749         writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_spw);
 750
 751         if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
 752                 setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_HOR);
 753
 754         if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
 755                 setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_VER);
 756 }
 757
 758 static void sunxi_hdmi_enable(void)
 759 {
 760         struct sunxi_hdmi_reg * const hdmi =
 761                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 762
 763         udelay(100);
 764         setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_ENABLE);
 765 }
 766
 767 #endif /* CONFIG_VIDEO_HDMI */
 768
 769 #ifdef CONFIG_VIDEO_VGA
 770
 771 static void sunxi_vga_mode_set(void)
 772 {
 773         struct sunxi_ccm_reg * const ccm =
 774                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 775         struct sunxi_tve_reg * const tve =
 776                 (struct sunxi_tve_reg *)SUNXI_TVE0_BASE;
 777
 778         /* Clock on */
 779         setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_TVE0);
 780
 781         /* Set TVE in VGA mode */
 782         writel(SUNXI_TVE_GCTRL_DAC_INPUT(0, 1) |
 783                SUNXI_TVE_GCTRL_DAC_INPUT(1, 2) |
 784                SUNXI_TVE_GCTRL_DAC_INPUT(2, 3), &tve->gctrl);
 785         writel(SUNXI_TVE_GCTRL_CFG0_VGA, &tve->cfg0);
 786         writel(SUNXI_TVE_GCTRL_DAC_CFG0_VGA, &tve->dac_cfg0);
 787         writel(SUNXI_TVE_GCTRL_UNKNOWN1_VGA, &tve->unknown1);
 788 }
 789
 790 static void sunxi_vga_enable(void)
 791 {
 792         struct sunxi_tve_reg * const tve =
 793                 (struct sunxi_tve_reg *)SUNXI_TVE0_BASE;
 794
 795         setbits_le32(&tve->gctrl, SUNXI_TVE_GCTRL_ENABLE);
 796 }
 797
 798 #endif /* CONFIG_VIDEO_VGA */
 799
 800 static void sunxi_drc_init(void)
 801 {
 802 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
 803         struct sunxi_ccm_reg * const ccm =
 804                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 805
 806         /* On sun6i the drc must be clocked even when in pass-through mode */
 807         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DRC0);
 808         clock_set_de_mod_clock(&ccm->iep_drc0_clk_cfg, 300000000);
 809 #endif
 810 }
 811
 812 #ifdef CONFIG_VIDEO_VGA_VIA_LCD
 813 static void sunxi_vga_external_dac_enable(void)
 814 {
 815         int pin;
 816
 817         pin = sunxi_name_to_gpio(CONFIG_VIDEO_VGA_EXTERNAL_DAC_EN);
 818         if (pin != -1) {
 819                 gpio_request(pin, "vga_enable");
 820                 gpio_direction_output(pin, 1);
 821         }
 822 }
 823 #endif /* CONFIG_VIDEO_VGA_VIA_LCD */
 824
 825 #ifdef CONFIG_VIDEO_LCD_SSD2828
 826 static int sunxi_ssd2828_init(const struct ctfb_res_modes *mode)
 827 {
 828         struct ssd2828_config cfg = {
 829                 .csx_pin = name_to_gpio(CONFIG_VIDEO_LCD_SPI_CS),
 830                 .sck_pin = name_to_gpio(CONFIG_VIDEO_LCD_SPI_SCLK),
 831                 .sdi_pin = name_to_gpio(CONFIG_VIDEO_LCD_SPI_MOSI),
 832                 .sdo_pin = name_to_gpio(CONFIG_VIDEO_LCD_SPI_MISO),
 833                 .reset_pin = name_to_gpio(CONFIG_VIDEO_LCD_SSD2828_RESET),
 834                 .ssd2828_tx_clk_khz  = CONFIG_VIDEO_LCD_SSD2828_TX_CLK * 1000,
 835                 .ssd2828_color_depth = 24,
 836 #ifdef CONFIG_VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
 837                 .mipi_dsi_number_of_data_lanes           = 4,
 838                 .mipi_dsi_bitrate_per_data_lane_mbps     = 513,
 839                 .mipi_dsi_delay_after_exit_sleep_mode_ms = 100,
 840                 .mipi_dsi_delay_after_set_display_on_ms  = 200
 841 #else
 842 #error MIPI LCD panel needs configuration parameters
 843 #endif
 844         };
 845
 846         if (cfg.csx_pin == -1 || cfg.sck_pin == -1 || cfg.sdi_pin == -1) {
 847                 printf("SSD2828: SPI pins are not properly configured\n");
 848                 return 1;
 849         }
 850         if (cfg.reset_pin == -1) {
 851                 printf("SSD2828: Reset pin is not properly configured\n");
 852                 return 1;
 853         }
 854
 855         return ssd2828_init(&cfg, mode);
 856 }
 857 #endif /* CONFIG_VIDEO_LCD_SSD2828 */
 858
 859 static void sunxi_engines_init(void)
 860 {
 861         sunxi_composer_init();
 862         sunxi_lcdc_init();
 863         sunxi_drc_init();
 864 }
 865
 866 static void sunxi_mode_set(const struct ctfb_res_modes *mode,
 867                            unsigned int address)
 868 {
 869         int __maybe_unused clk_div, clk_double;
 870
 871         switch (sunxi_display.monitor) {
 872         case sunxi_monitor_none:
 873                 break;
 874         case sunxi_monitor_dvi:
 875         case sunxi_monitor_hdmi:
 876 #ifdef CONFIG_VIDEO_HDMI
 877                 sunxi_composer_mode_set(mode, address);
 878                 sunxi_lcdc_tcon1_mode_set(mode, &clk_div, &clk_double, 0);
 879                 sunxi_hdmi_mode_set(mode, clk_div, clk_double);
 880                 sunxi_composer_enable();
 881                 sunxi_lcdc_enable();
 882                 sunxi_hdmi_enable();
 883 #endif
 884                 break;
 885         case sunxi_monitor_lcd:
 886                 sunxi_lcdc_panel_enable();
 887                 sunxi_composer_mode_set(mode, address);
 888                 sunxi_lcdc_tcon0_mode_set(mode);
 889                 sunxi_composer_enable();
 890                 sunxi_lcdc_enable();
 891 #ifdef CONFIG_VIDEO_LCD_SSD2828
 892                 sunxi_ssd2828_init(mode);
 893 #endif
 894                 sunxi_lcdc_backlight_enable();
 895                 break;
 896         case sunxi_monitor_vga:
 897 #ifdef CONFIG_VIDEO_VGA
 898                 sunxi_composer_mode_set(mode, address);
 899                 sunxi_lcdc_tcon1_mode_set(mode, &clk_div, &clk_double, 1);
 900                 sunxi_vga_mode_set();
 901                 sunxi_composer_enable();
 902                 sunxi_lcdc_enable();
 903                 sunxi_vga_enable();
 904 #elif defined CONFIG_VIDEO_VGA_VIA_LCD
 905                 sunxi_composer_mode_set(mode, address);
 906                 sunxi_lcdc_tcon0_mode_set(mode);
 907                 sunxi_composer_enable();
 908                 sunxi_lcdc_enable();
 909                 sunxi_vga_external_dac_enable();
 910 #endif
 911                 break;
 912         }
 913 }
 914
 915 static const char *sunxi_get_mon_desc(enum sunxi_monitor monitor)
 916 {
 917         switch (monitor) {
 918         case sunxi_monitor_none:        return "none";
 919         case sunxi_monitor_dvi:         return "dvi";
 920         case sunxi_monitor_hdmi:        return "hdmi";
 921         case sunxi_monitor_lcd:         return "lcd";
 922         case sunxi_monitor_vga:         return "vga";
 923         }
 924         return NULL; /* never reached */
 925 }
 926
 927 void *video_hw_init(void)
 928 {
 929         static GraphicDevice *graphic_device = &sunxi_display.graphic_device;
 930         const struct ctfb_res_modes *mode;
 931         struct ctfb_res_modes custom;
 932         const char *options;
 933 #ifdef CONFIG_VIDEO_HDMI
 934         int ret, hpd, hpd_delay, edid;
 935 #endif
 936         char mon[16];
 937         char *lcd_mode = CONFIG_VIDEO_LCD_MODE;
 938         int i;
 939
 940         memset(&sunxi_display, 0, sizeof(struct sunxi_display));
 941
 942         printf("Reserved %dkB of RAM for Framebuffer.\n",
 943                CONFIG_SUNXI_FB_SIZE >> 10);
 944         gd->fb_base = gd->ram_top;
 945
 946         video_get_ctfb_res_modes(RES_MODE_1024x768, 24, &mode,
 947                                  &sunxi_display.depth, &options);
 948 #ifdef CONFIG_VIDEO_HDMI
 949         hpd = video_get_option_int(options, "hpd", 1);
 950         hpd_delay = video_get_option_int(options, "hpd_delay", 500);
 951         edid = video_get_option_int(options, "edid", 1);
 952         sunxi_display.monitor = sunxi_monitor_dvi;
 953 #elif defined CONFIG_VIDEO_VGA_VIA_LCD
 954         sunxi_display.monitor = sunxi_monitor_vga;
 955 #else
 956         sunxi_display.monitor = sunxi_monitor_lcd;
 957 #endif
 958         video_get_option_string(options, "monitor", mon, sizeof(mon),
 959                                 sunxi_get_mon_desc(sunxi_display.monitor));
 960         for (i = 0; i <= SUNXI_MONITOR_LAST; i++) {
 961                 if (strcmp(mon, sunxi_get_mon_desc(i)) == 0) {
 962                         sunxi_display.monitor = i;
 963                         break;
 964                 }
 965         }
 966         if (i > SUNXI_MONITOR_LAST)
 967                 printf("Unknown monitor: '%s', falling back to '%s'\n",
 968                        mon, sunxi_get_mon_desc(sunxi_display.monitor));
 969
 970 #ifdef CONFIG_VIDEO_HDMI
 971         /* If HDMI/DVI is selected do HPD & EDID, and handle fallback */
 972         if (sunxi_display.monitor == sunxi_monitor_dvi ||
 973             sunxi_display.monitor == sunxi_monitor_hdmi) {
 974                 /* Always call hdp_detect, as it also enables clocks, etc. */
 975                 ret = sunxi_hdmi_hpd_detect(hpd_delay);
 976                 if (ret) {
 977                         printf("HDMI connected: ");
 978                         if (edid && sunxi_hdmi_edid_get_mode(&custom) == 0)
 979                                 mode = &custom;
 980                 } else if (hpd) {
 981                         sunxi_hdmi_shutdown();
 982                         /* Fallback to lcd / vga / none */
 983                         if (lcd_mode[0]) {
 984                                 sunxi_display.monitor = sunxi_monitor_lcd;
 985                         } else {
 986 #if defined CONFIG_VIDEO_VGA_VIA_LCD || defined CONFIG_VIDEO_VGA
 987                                 sunxi_display.monitor = sunxi_monitor_vga;
 988 #else
 989                                 sunxi_display.monitor = sunxi_monitor_none;
 990 #endif
 991                         }
 992                 } /* else continue with hdmi/dvi without a cable connected */
 993         }
 994 #endif
 995
 996         switch (sunxi_display.monitor) {
 997         case sunxi_monitor_none:
 998                 return NULL;
 999         case sunxi_monitor_dvi:
1000         case sunxi_monitor_hdmi:
1001 #ifdef CONFIG_VIDEO_HDMI
1002                 break;
1003 #else
1004                 printf("HDMI/DVI not supported on this board\n");
1005                 sunxi_display.monitor = sunxi_monitor_none;
1006                 return NULL;
1007 #endif
1008         case sunxi_monitor_lcd:
1009                 if (lcd_mode[0]) {
1010                         sunxi_display.depth = video_get_params(&custom, lcd_mode);
1011                         mode = &custom;
1012                         break;
1013                 }
1014                 printf("LCD not supported on this board\n");
1015                 sunxi_display.monitor = sunxi_monitor_none;
1016                 return NULL;
1017         case sunxi_monitor_vga:
1018 #if defined CONFIG_VIDEO_VGA_VIA_LCD || defined CONFIG_VIDEO_VGA
1019                 sunxi_display.depth = 18;
1020                 break;
1021 #else
1022                 printf("VGA not supported on this board\n");
1023                 sunxi_display.monitor = sunxi_monitor_none;
1024                 return NULL;
1025 #endif
1026         }
1027
1028         if (mode->vmode != FB_VMODE_NONINTERLACED) {
1029                 printf("Only non-interlaced modes supported, falling back to 1024x768\n");
1030                 mode = &res_mode_init[RES_MODE_1024x768];
1031         } else {
1032                 printf("Setting up a %dx%d %s console\n", mode->xres,
1033                        mode->yres, sunxi_get_mon_desc(sunxi_display.monitor));
1034         }
1035
1036         sunxi_engines_init();
1037         sunxi_mode_set(mode, gd->fb_base - CONFIG_SYS_SDRAM_BASE);
1038
1039         /*
1040          * These are the only members of this structure that are used. All the
1041          * others are driver specific. There is nothing to decribe pitch or
1042          * stride, but we are lucky with our hw.
1043          */
1044         graphic_device->frameAdrs = gd->fb_base;
1045         graphic_device->gdfIndex = GDF_32BIT_X888RGB;
1046         graphic_device->gdfBytesPP = 4;
1047         graphic_device->winSizeX = mode->xres;
1048         graphic_device->winSizeY = mode->yres;
1049
1050         return graphic_device;
1051 }
1052
1053 /*
1054  * Simplefb support.
1055  */
1056 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_VIDEO_DT_SIMPLEFB)
1057 int sunxi_simplefb_setup(void *blob)
1058 {
1059         static GraphicDevice *graphic_device = &sunxi_display.graphic_device;
1060         int offset, ret;
1061         const char *pipeline = NULL;
1062
1063         switch (sunxi_display.monitor) {
1064         case sunxi_monitor_none:
1065                 return 0;
1066         case sunxi_monitor_dvi:
1067         case sunxi_monitor_hdmi:
1068                 pipeline = "de_be0-lcd0-hdmi";
1069                 break;
1070         case sunxi_monitor_lcd:
1071                 pipeline = "de_be0-lcd0";
1072                 break;
1073         case sunxi_monitor_vga:
1074 #ifdef CONFIG_VIDEO_VGA
1075                 pipeline = "de_be0-lcd0-tve0";
1076 #elif defined CONFIG_VIDEO_VGA_VIA_LCD
1077                 pipeline = "de_be0-lcd0";
1078 #endif
1079                 break;
1080         }
1081
1082         /* Find a prefilled simpefb node, matching out pipeline config */
1083         offset = fdt_node_offset_by_compatible(blob, -1,
1084                                                "allwinner,simple-framebuffer");
1085         while (offset >= 0) {
1086                 ret = fdt_find_string(blob, offset, "allwinner,pipeline",
1087                                       pipeline);
1088                 if (ret == 0)
1089                         break;
1090                 offset = fdt_node_offset_by_compatible(blob, offset,
1091                                                "allwinner,simple-framebuffer");
1092         }
1093         if (offset < 0) {
1094                 eprintf("Cannot setup simplefb: node not found\n");
1095                 return 0; /* Keep older kernels working */
1096         }
1097
1098         ret = fdt_setup_simplefb_node(blob, offset, gd->fb_base,
1099                         graphic_device->winSizeX, graphic_device->winSizeY,
1100                         graphic_device->winSizeX * graphic_device->gdfBytesPP,
1101                         "x8r8g8b8");
1102         if (ret)
1103                 eprintf("Cannot setup simplefb: Error setting properties\n");
1104
1105         return ret;
1106 }
1107 #endif /* CONFIG_OF_BOARD_SETUP && CONFIG_VIDEO_DT_SIMPLEFB */