drivers/video/sunxi_display.c

   1 /*
   2  * Display driver for Allwinner SoCs.
   3  *
   4  * (C) Copyright 2013-2014 Luc Verhaegen <libv@skynet.be>
   5  * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/display.h>
  14 #include <asm/global_data.h>
  15 #include <asm/io.h>
  16 #include <errno.h>
  17 #include <fdtdec.h>
  18 #include <fdt_support.h>
  19 #include <video_fb.h>
  20 #include "videomodes.h"
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 struct sunxi_display {
  25         GraphicDevice graphic_device;
  26         bool enabled;
  27 } sunxi_display;
  28
  29 /*
  30  * Wait up to 200ms for value to be set in given part of reg.
  31  */
  32 static int await_completion(u32 *reg, u32 mask, u32 val)
  33 {
  34         unsigned long tmo = timer_get_us() + 200000;
  35
  36         while ((readl(reg) & mask) != val) {
  37                 if (timer_get_us() > tmo) {
  38                         printf("DDC: timeout reading EDID\n");
  39                         return -ETIME;
  40                 }
  41         }
  42         return 0;
  43 }
  44
  45 static int sunxi_hdmi_hpd_detect(void)
  46 {
  47         struct sunxi_ccm_reg * const ccm =
  48                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  49         struct sunxi_hdmi_reg * const hdmi =
  50                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
  51
  52         /* Set pll3 to 300MHz */
  53         clock_set_pll3(300000000);
  54
  55         /* Set hdmi parent to pll3 */
  56         clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK,
  57                         CCM_HDMI_CTRL_PLL3);
  58
  59         /* Set ahb gating to pass */
  60 #ifdef CONFIG_MACH_SUN6I
  61         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
  62 #endif
  63         setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
  64
  65         /* Clock on */
  66         setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
  67
  68         writel(SUNXI_HDMI_CTRL_ENABLE, &hdmi->ctrl);
  69         writel(SUNXI_HDMI_PAD_CTRL0_HDP, &hdmi->pad_ctrl0);
  70
  71         udelay(1000);
  72
  73         return (readl(&hdmi->hpd) & SUNXI_HDMI_HPD_DETECT) ? 1 : 0;
  74 }
  75
  76 static void sunxi_hdmi_shutdown(void)
  77 {
  78         struct sunxi_ccm_reg * const ccm =
  79                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  80         struct sunxi_hdmi_reg * const hdmi =
  81                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
  82
  83         clrbits_le32(&hdmi->ctrl, SUNXI_HDMI_CTRL_ENABLE);
  84         clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
  85         clrbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
  86 #ifdef CONFIG_MACH_SUN6I
  87         clrbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
  88 #endif
  89         clock_set_pll3(0);
  90 }
  91
  92 static int sunxi_hdmi_ddc_do_command(u32 cmnd, int offset, int n)
  93 {
  94         struct sunxi_hdmi_reg * const hdmi =
  95                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
  96
  97         setbits_le32(&hdmi->ddc_fifo_ctrl, SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR);
  98         writel(SUNXI_HMDI_DDC_ADDR_EDDC_SEGMENT(offset >> 8) |
  99                SUNXI_HMDI_DDC_ADDR_EDDC_ADDR |
 100                SUNXI_HMDI_DDC_ADDR_OFFSET(offset) |
 101                SUNXI_HMDI_DDC_ADDR_SLAVE_ADDR, &hdmi->ddc_addr);
 102 #ifndef CONFIG_MACH_SUN6I
 103         writel(n, &hdmi->ddc_byte_count);
 104         writel(cmnd, &hdmi->ddc_cmnd);
 105 #else
 106         writel(n << 16 | cmnd, &hdmi->ddc_cmnd);
 107 #endif
 108         setbits_le32(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_START);
 109
 110         return await_completion(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_START, 0);
 111 }
 112
 113 static int sunxi_hdmi_ddc_read(int offset, u8 *buf, int count)
 114 {
 115         struct sunxi_hdmi_reg * const hdmi =
 116                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 117         int i, n;
 118
 119         while (count > 0) {
 120                 if (count > 16)
 121                         n = 16;
 122                 else
 123                         n = count;
 124
 125                 if (sunxi_hdmi_ddc_do_command(
 126                                 SUNXI_HDMI_DDC_CMND_EXPLICIT_EDDC_READ,
 127                                 offset, n))
 128                         return -ETIME;
 129
 130                 for (i = 0; i < n; i++)
 131                         *buf++ = readb(&hdmi->ddc_fifo_data);
 132
 133                 offset += n;
 134                 count -= n;
 135         }
 136
 137         return 0;
 138 }
 139
 140 static int sunxi_hdmi_edid_get_block(int block, u8 *buf)
 141 {
 142         int r, retries = 2;
 143
 144         do {
 145                 r = sunxi_hdmi_ddc_read(block * 128, buf, 128);
 146                 if (r)
 147                         continue;
 148                 r = edid_check_checksum(buf);
 149                 if (r) {
 150                         printf("EDID block %d: checksum error%s\n",
 151                                block, retries ? ", retrying" : "");
 152                 }
 153         } while (r && retries--);
 154
 155         return r;
 156 }
 157
 158 static int sunxi_hdmi_edid_get_mode(struct ctfb_res_modes *mode)
 159 {
 160         struct edid1_info edid1;
 161         struct edid_detailed_timing *t =
 162                 (struct edid_detailed_timing *)edid1.monitor_details.timing;
 163         struct sunxi_hdmi_reg * const hdmi =
 164                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 165         struct sunxi_ccm_reg * const ccm =
 166                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 167         int i, r;
 168
 169         /* SUNXI_HDMI_CTRL_ENABLE & PAD_CTRL0 are already set by hpd_detect */
 170         writel(SUNXI_HDMI_PAD_CTRL1 | SUNXI_HDMI_PAD_CTRL1_HALVE,
 171                &hdmi->pad_ctrl1);
 172         writel(SUNXI_HDMI_PLL_CTRL | SUNXI_HDMI_PLL_CTRL_DIV(15),
 173                &hdmi->pll_ctrl);
 174         writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0);
 175
 176         /* Reset i2c controller */
 177         setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE);
 178         writel(SUNXI_HMDI_DDC_CTRL_ENABLE |
 179                SUNXI_HMDI_DDC_CTRL_SDA_ENABLE |
 180                SUNXI_HMDI_DDC_CTRL_SCL_ENABLE |
 181                SUNXI_HMDI_DDC_CTRL_RESET, &hdmi->ddc_ctrl);
 182         if (await_completion(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_RESET, 0))
 183                 return -EIO;
 184
 185         writel(SUNXI_HDMI_DDC_CLOCK, &hdmi->ddc_clock);
 186 #ifndef CONFIG_MACH_SUN6I
 187         writel(SUNXI_HMDI_DDC_LINE_CTRL_SDA_ENABLE |
 188                SUNXI_HMDI_DDC_LINE_CTRL_SCL_ENABLE, &hdmi->ddc_line_ctrl);
 189 #endif
 190
 191         r = sunxi_hdmi_edid_get_block(0, (u8 *)&edid1);
 192
 193         /* Disable DDC engine, no longer needed */
 194         clrbits_le32(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_ENABLE);
 195         clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE);
 196
 197         if (r)
 198                 return r;
 199
 200         r = edid_check_info(&edid1);
 201         if (r) {
 202                 printf("EDID: invalid EDID data\n");
 203                 return -EINVAL;
 204         }
 205
 206         /* We want version 1.3 or 1.2 with detailed timing info */
 207         if (edid1.version != 1 || (edid1.revision < 3 &&
 208                         !EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(edid1))) {
 209                 printf("EDID: unsupported version %d.%d\n",
 210                        edid1.version, edid1.revision);
 211                 return -EINVAL;
 212         }
 213
 214         /* Take the first usable detailed timing */
 215         for (i = 0; i < 4; i++, t++) {
 216                 r = video_edid_dtd_to_ctfb_res_modes(t, mode);
 217                 if (r == 0)
 218                         break;
 219         }
 220         if (i == 4) {
 221                 printf("EDID: no usable detailed timing found\n");
 222                 return -ENOENT;
 223         }
 224
 225         return 0;
 226 }
 227
 228 /*
 229  * This is the entity that mixes and matches the different layers and inputs.
 230  * Allwinner calls it the back-end, but i like composer better.
 231  */
 232 static void sunxi_composer_init(void)
 233 {
 234         struct sunxi_ccm_reg * const ccm =
 235                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 236         struct sunxi_de_be_reg * const de_be =
 237                 (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
 238         int i;
 239
 240 #ifdef CONFIG_MACH_SUN6I
 241         /* Reset off */
 242         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE_BE0);
 243 #endif
 244
 245         /* Clocks on */
 246         setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE_BE0);
 247         setbits_le32(&ccm->dram_clk_gate, 1 << CCM_DRAM_GATE_OFFSET_DE_BE0);
 248         clock_set_de_mod_clock(&ccm->be0_clk_cfg, 300000000);
 249
 250         /* Engine bug, clear registers after reset */
 251         for (i = 0x0800; i < 0x1000; i += 4)
 252                 writel(0, SUNXI_DE_BE0_BASE + i);
 253
 254         setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_ENABLE);
 255 }
 256
 257 static void sunxi_composer_mode_set(const struct ctfb_res_modes *mode,
 258                                     unsigned int address)
 259 {
 260         struct sunxi_de_be_reg * const de_be =
 261                 (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
 262
 263         writel(SUNXI_DE_BE_HEIGHT(mode->yres) | SUNXI_DE_BE_WIDTH(mode->xres),
 264                &de_be->disp_size);
 265         writel(SUNXI_DE_BE_HEIGHT(mode->yres) | SUNXI_DE_BE_WIDTH(mode->xres),
 266                &de_be->layer0_size);
 267         writel(SUNXI_DE_BE_LAYER_STRIDE(mode->xres), &de_be->layer0_stride);
 268         writel(address << 3, &de_be->layer0_addr_low32b);
 269         writel(address >> 29, &de_be->layer0_addr_high4b);
 270         writel(SUNXI_DE_BE_LAYER_ATTR1_FMT_XRGB8888, &de_be->layer0_attr1_ctrl);
 271
 272         setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_LAYER0_ENABLE);
 273 }
 274
 275 /*
 276  * LCDC, what allwinner calls a CRTC, so timing controller and serializer.
 277  */
 278 static void sunxi_lcdc_pll_set(int dotclock, int *clk_div, int *clk_double)
 279 {
 280         struct sunxi_ccm_reg * const ccm =
 281                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 282         int value, n, m, diff;
 283         int best_n = 0, best_m = 0, best_diff = 0x0FFFFFFF;
 284         int best_double = 0;
 285
 286         /*
 287          * Find the lowest divider resulting in a matching clock, if there
 288          * is no match, pick the closest lower clock, as monitors tend to
 289          * not sync to higher frequencies.
 290          */
 291         for (m = 15; m > 0; m--) {
 292                 n = (m * dotclock) / 3000;
 293
 294                 if ((n >= 9) && (n <= 127)) {
 295                         value = (3000 * n) / m;
 296                         diff = dotclock - value;
 297                         if (diff < best_diff) {
 298                                 best_diff = diff;
 299                                 best_m = m;
 300                                 best_n = n;
 301                                 best_double = 0;
 302                         }
 303                 }
 304
 305                 /* These are just duplicates */
 306                 if (!(m & 1))
 307                         continue;
 308
 309                 n = (m * dotclock) / 6000;
 310                 if ((n >= 9) && (n <= 127)) {
 311                         value = (6000 * n) / m;
 312                         diff = dotclock - value;
 313                         if (diff < best_diff) {
 314                                 best_diff = diff;
 315                                 best_m = m;
 316                                 best_n = n;
 317                                 best_double = 1;
 318                         }
 319                 }
 320         }
 321
 322         debug("dotclock: %dkHz = %dkHz: (%d * 3MHz * %d) / %d\n",
 323               dotclock, (best_double + 1) * 3000 * best_n / best_m,
 324               best_double + 1, best_n, best_m);
 325
 326         clock_set_pll3(best_n * 3000000);
 327
 328         writel(CCM_LCD_CH1_CTRL_GATE |
 329             (best_double ? CCM_LCD_CH1_CTRL_PLL3_2X : CCM_LCD_CH1_CTRL_PLL3) |
 330             CCM_LCD_CH1_CTRL_M(best_m), &ccm->lcd0_ch1_clk_cfg);
 331
 332         *clk_div = best_m;
 333         *clk_double = best_double;
 334 }
 335
 336 static void sunxi_lcdc_init(void)
 337 {
 338         struct sunxi_ccm_reg * const ccm =
 339                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 340         struct sunxi_lcdc_reg * const lcdc =
 341                 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
 342
 343         /* Reset off */
 344 #ifdef CONFIG_MACH_SUN6I
 345         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);
 346 #else
 347         setbits_le32(&ccm->lcd0_ch0_clk_cfg, CCM_LCD_CH0_CTRL_RST);
 348 #endif
 349
 350         /* Clock on */
 351         setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0);
 352
 353         /* Init lcdc */
 354         writel(0, &lcdc->ctrl); /* Disable tcon */
 355         writel(0, &lcdc->int0); /* Disable all interrupts */
 356
 357         /* Disable tcon0 dot clock */
 358         clrbits_le32(&lcdc->tcon0_dclk, SUNXI_LCDC_TCON0_DCLK_ENABLE);
 359
 360         /* Set all io lines to tristate */
 361         writel(0xffffffff, &lcdc->tcon0_io_tristate);
 362         writel(0xffffffff, &lcdc->tcon1_io_tristate);
 363 }
 364
 365 static void sunxi_lcdc_mode_set(const struct ctfb_res_modes *mode,
 366                                 int *clk_div, int *clk_double)
 367 {
 368         struct sunxi_lcdc_reg * const lcdc =
 369                 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
 370         int bp, total;
 371
 372         /* Use tcon1 */
 373         clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
 374                         SUNXI_LCDC_CTRL_IO_MAP_TCON1);
 375
 376         /* Enabled, 0x1e start delay */
 377         writel(SUNXI_LCDC_TCON1_CTRL_ENABLE |
 378                SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(0x1e), &lcdc->tcon1_ctrl);
 379
 380         writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
 381                &lcdc->tcon1_timing_source);
 382         writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
 383                &lcdc->tcon1_timing_scale);
 384         writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
 385                &lcdc->tcon1_timing_out);
 386
 387         bp = mode->hsync_len + mode->left_margin;
 388         total = mode->xres + mode->right_margin + bp;
 389         writel(SUNXI_LCDC_TCON1_TIMING_H_TOTAL(total) |
 390                SUNXI_LCDC_TCON1_TIMING_H_BP(bp), &lcdc->tcon1_timing_h);
 391
 392         bp = mode->vsync_len + mode->upper_margin;
 393         total = mode->yres + mode->lower_margin + bp;
 394         writel(SUNXI_LCDC_TCON1_TIMING_V_TOTAL(total) |
 395                SUNXI_LCDC_TCON1_TIMING_V_BP(bp), &lcdc->tcon1_timing_v);
 396
 397         writel(SUNXI_LCDC_X(mode->hsync_len) | SUNXI_LCDC_Y(mode->vsync_len),
 398                &lcdc->tcon1_timing_sync);
 399
 400         sunxi_lcdc_pll_set(mode->pixclock_khz, clk_div, clk_double);
 401 }
 402
 403 #ifdef CONFIG_MACH_SUN6I
 404 static void sunxi_drc_init(void)
 405 {
 406         struct sunxi_ccm_reg * const ccm =
 407                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 408
 409         /* On sun6i the drc must be clocked even when in pass-through mode */
 410         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DRC0);
 411         clock_set_de_mod_clock(&ccm->iep_drc0_clk_cfg, 300000000);
 412 }
 413 #endif
 414
 415 static void sunxi_hdmi_setup_info_frames(const struct ctfb_res_modes *mode)
 416 {
 417         struct sunxi_hdmi_reg * const hdmi =
 418                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 419         u8 checksum = 0;
 420         u8 avi_info_frame[17] = {
 421                 0x82, 0x02, 0x0d, 0x00, 0x12, 0x00, 0x88, 0x00,
 422                 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 423                 0x00
 424         };
 425         u8 vendor_info_frame[19] = {
 426                 0x81, 0x01, 0x06, 0x29, 0x03, 0x0c, 0x00, 0x40,
 427                 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 428                 0x00, 0x00, 0x00
 429         };
 430         int i;
 431
 432         if (mode->pixclock_khz <= 27000)
 433                 avi_info_frame[5] = 0x40; /* SD-modes, ITU601 colorspace */
 434         else
 435                 avi_info_frame[5] = 0x80; /* HD-modes, ITU709 colorspace */
 436
 437         if (mode->xres * 100 / mode->yres < 156)
 438                 avi_info_frame[5] |= 0x18; /* 4 : 3 */
 439         else
 440                 avi_info_frame[5] |= 0x28; /* 16 : 9 */
 441
 442         for (i = 0; i < ARRAY_SIZE(avi_info_frame); i++)
 443                 checksum += avi_info_frame[i];
 444
 445         avi_info_frame[3] = 0x100 - checksum;
 446
 447         for (i = 0; i < ARRAY_SIZE(avi_info_frame); i++)
 448                 writeb(avi_info_frame[i], &hdmi->avi_info_frame[i]);
 449
 450         writel(SUNXI_HDMI_QCP_PACKET0, &hdmi->qcp_packet0);
 451         writel(SUNXI_HDMI_QCP_PACKET1, &hdmi->qcp_packet1);
 452
 453         for (i = 0; i < ARRAY_SIZE(vendor_info_frame); i++)
 454                 writeb(vendor_info_frame[i], &hdmi->vendor_info_frame[i]);
 455
 456         writel(SUNXI_HDMI_PKT_CTRL0, &hdmi->pkt_ctrl0);
 457         writel(SUNXI_HDMI_PKT_CTRL1, &hdmi->pkt_ctrl1);
 458
 459         setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_HDMI);
 460 }
 461
 462 static void sunxi_hdmi_mode_set(const struct ctfb_res_modes *mode,
 463                                 bool hdmi_mode, int clk_div, int clk_double)
 464 {
 465         struct sunxi_hdmi_reg * const hdmi =
 466                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 467         int x, y;
 468
 469         /* Write clear interrupt status bits */
 470         writel(SUNXI_HDMI_IRQ_STATUS_BITS, &hdmi->irq);
 471
 472         if (hdmi_mode)
 473                 sunxi_hdmi_setup_info_frames(mode);
 474
 475         /* Init various registers, select pll3 as clock source */
 476         writel(SUNXI_HDMI_VIDEO_POL_TX_CLK, &hdmi->video_polarity);
 477         writel(SUNXI_HDMI_PAD_CTRL0_RUN, &hdmi->pad_ctrl0);
 478         writel(SUNXI_HDMI_PAD_CTRL1, &hdmi->pad_ctrl1);
 479         writel(SUNXI_HDMI_PLL_CTRL, &hdmi->pll_ctrl);
 480         writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0);
 481
 482         /* Setup clk div and doubler */
 483         clrsetbits_le32(&hdmi->pll_ctrl, SUNXI_HDMI_PLL_CTRL_DIV_MASK,
 484                         SUNXI_HDMI_PLL_CTRL_DIV(clk_div));
 485         if (!clk_double)
 486                 setbits_le32(&hdmi->pad_ctrl1, SUNXI_HDMI_PAD_CTRL1_HALVE);
 487
 488         /* Setup timing registers */
 489         writel(SUNXI_HDMI_Y(mode->yres) | SUNXI_HDMI_X(mode->xres),
 490                &hdmi->video_size);
 491
 492         x = mode->hsync_len + mode->left_margin;
 493         y = mode->vsync_len + mode->upper_margin;
 494         writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_bp);
 495
 496         x = mode->right_margin;
 497         y = mode->lower_margin;
 498         writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_fp);
 499
 500         x = mode->hsync_len;
 501         y = mode->vsync_len;
 502         writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_spw);
 503
 504         if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
 505                 setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_HOR);
 506
 507         if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
 508                 setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_VER);
 509 }
 510
 511 static void sunxi_engines_init(void)
 512 {
 513         sunxi_composer_init();
 514         sunxi_lcdc_init();
 515 #ifdef CONFIG_MACH_SUN6I
 516         sunxi_drc_init();
 517 #endif
 518 }
 519
 520 static void sunxi_mode_set(const struct ctfb_res_modes *mode, char *monitor,
 521                            unsigned int address)
 522 {
 523         struct sunxi_de_be_reg * const de_be =
 524                 (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
 525         struct sunxi_lcdc_reg * const lcdc =
 526                 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
 527         struct sunxi_hdmi_reg * const hdmi =
 528                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 529         int clk_div, clk_double;
 530         int retries = 3;
 531         bool hdmi_mode = strcmp(monitor, "hdmi") == 0;
 532
 533 retry:
 534         clrbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_ENABLE);
 535         clrbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_TCON_ENABLE);
 536         clrbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_START);
 537
 538         sunxi_composer_mode_set(mode, address);
 539         sunxi_lcdc_mode_set(mode, &clk_div, &clk_double);
 540         sunxi_hdmi_mode_set(mode, hdmi_mode, clk_div, clk_double);
 541
 542         setbits_le32(&de_be->reg_ctrl, SUNXI_DE_BE_REG_CTRL_LOAD_REGS);
 543         setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_START);
 544
 545         udelay(1000000 / mode->refresh + 500);
 546
 547         setbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_TCON_ENABLE);
 548
 549         udelay(1000000 / mode->refresh + 500);
 550
 551         setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_ENABLE);
 552
 553         udelay(1000000 / mode->refresh + 500);
 554
 555         /*
 556          * Sometimes the display pipeline does not sync up properly, if
 557          * this happens the hdmi fifo underrun or overrun bits are set.
 558          */
 559         if (readl(&hdmi->irq) &
 560             (SUNXI_HDMI_IRQ_STATUS_FIFO_UF | SUNXI_HDMI_IRQ_STATUS_FIFO_OF)) {
 561                 if (retries--)
 562                         goto retry;
 563                 printf("HDMI fifo under or overrun\n");
 564         }
 565 }
 566
 567 void *video_hw_init(void)
 568 {
 569         static GraphicDevice *graphic_device = &sunxi_display.graphic_device;
 570         const struct ctfb_res_modes *mode;
 571         struct ctfb_res_modes edid_mode;
 572         const char *options;
 573         unsigned int depth;
 574         int ret, hpd, edid;
 575         char monitor[16];
 576
 577         memset(&sunxi_display, 0, sizeof(struct sunxi_display));
 578
 579         printf("Reserved %dkB of RAM for Framebuffer.\n",
 580                CONFIG_SUNXI_FB_SIZE >> 10);
 581         gd->fb_base = gd->ram_top;
 582
 583         video_get_ctfb_res_modes(RES_MODE_1024x768, 24, &mode, &depth, &options);
 584         hpd = video_get_option_int(options, "hpd", 1);
 585         edid = video_get_option_int(options, "edid", 1);
 586         video_get_option_string(options, "monitor", monitor, sizeof(monitor),
 587                                 "dvi");
 588
 589         /* Always call hdp_detect, as it also enables various clocks, etc. */
 590         ret = sunxi_hdmi_hpd_detect();
 591         if (hpd && !ret) {
 592                 sunxi_hdmi_shutdown();
 593                 return NULL;
 594         }
 595         if (ret)
 596                 printf("HDMI connected: ");
 597
 598         /* Check edid if requested and we've a cable plugged in */
 599         if (edid && ret) {
 600                 if (sunxi_hdmi_edid_get_mode(&edid_mode) == 0)
 601                         mode = &edid_mode;
 602         }
 603
 604         if (mode->vmode != FB_VMODE_NONINTERLACED) {
 605                 printf("Only non-interlaced modes supported, falling back to 1024x768\n");
 606                 mode = &res_mode_init[RES_MODE_1024x768];
 607         } else {
 608                 printf("Setting up a %dx%d %s console\n",
 609                        mode->xres, mode->yres, monitor);
 610         }
 611
 612         sunxi_display.enabled = true;
 613         sunxi_engines_init();
 614         sunxi_mode_set(mode, monitor, gd->fb_base - CONFIG_SYS_SDRAM_BASE);
 615
 616         /*
 617          * These are the only members of this structure that are used. All the
 618          * others are driver specific. There is nothing to decribe pitch or
 619          * stride, but we are lucky with our hw.
 620          */
 621         graphic_device->frameAdrs = gd->fb_base;
 622         graphic_device->gdfIndex = GDF_32BIT_X888RGB;
 623         graphic_device->gdfBytesPP = 4;
 624         graphic_device->winSizeX = mode->xres;
 625         graphic_device->winSizeY = mode->yres;
 626
 627         return graphic_device;
 628 }
 629
 630 /*
 631  * Simplefb support.
 632  */
 633 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_VIDEO_DT_SIMPLEFB)
 634 int sunxi_simplefb_setup(void *blob)
 635 {
 636         static GraphicDevice *graphic_device = &sunxi_display.graphic_device;
 637         int offset, ret;
 638
 639         if (!sunxi_display.enabled)
 640                 return 0;
 641
 642         /* Find a framebuffer node, with pipeline == "de_be0-lcd0-hdmi" */
 643         offset = fdt_node_offset_by_compatible(blob, -1,
 644                                                "allwinner,simple-framebuffer");
 645         while (offset >= 0) {
 646                 ret = fdt_find_string(blob, offset, "allwinner,pipeline",
 647                                       "de_be0-lcd0-hdmi");
 648                 if (ret == 0)
 649                         break;
 650                 offset = fdt_node_offset_by_compatible(blob, offset,
 651                                                "allwinner,simple-framebuffer");
 652         }
 653         if (offset < 0) {
 654                 eprintf("Cannot setup simplefb: node not found\n");
 655                 return 0; /* Keep older kernels working */
 656         }
 657
 658         ret = fdt_setup_simplefb_node(blob, offset, gd->fb_base,
 659                         graphic_device->winSizeX, graphic_device->winSizeY,
 660                         graphic_device->winSizeX * graphic_device->gdfBytesPP,
 661                         "x8r8g8b8");
 662         if (ret)
 663                 eprintf("Cannot setup simplefb: Error setting properties\n");
 664
 665         return ret;
 666 }
 667 #endif /* CONFIG_OF_BOARD_SETUP && CONFIG_VIDEO_DT_SIMPLEFB */