drivers/video/sunxi_display.c

   1 /*
   2  * Display driver for Allwinner SoCs.
   3  *
   4  * (C) Copyright 2013-2014 Luc Verhaegen <libv@skynet.be>
   5  * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/display.h>
  14 #include <asm/global_data.h>
  15 #include <asm/io.h>
  16 #include <errno.h>
  17 #include <fdtdec.h>
  18 #include <fdt_support.h>
  19 #include <video_fb.h>
  20 #include "videomodes.h"
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 enum sunxi_monitor {
  25         sunxi_monitor_none,
  26         sunxi_monitor_dvi,
  27         sunxi_monitor_hdmi,
  28         sunxi_monitor_lcd,
  29         sunxi_monitor_vga,
  30 };
  31 #define SUNXI_MONITOR_LAST sunxi_monitor_vga
  32
  33 struct sunxi_display {
  34         GraphicDevice graphic_device;
  35         bool enabled;
  36         enum sunxi_monitor monitor;
  37 } sunxi_display;
  38
  39 /*
  40  * Wait up to 200ms for value to be set in given part of reg.
  41  */
  42 static int await_completion(u32 *reg, u32 mask, u32 val)
  43 {
  44         unsigned long tmo = timer_get_us() + 200000;
  45
  46         while ((readl(reg) & mask) != val) {
  47                 if (timer_get_us() > tmo) {
  48                         printf("DDC: timeout reading EDID\n");
  49                         return -ETIME;
  50                 }
  51         }
  52         return 0;
  53 }
  54
  55 static int sunxi_hdmi_hpd_detect(void)
  56 {
  57         struct sunxi_ccm_reg * const ccm =
  58                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  59         struct sunxi_hdmi_reg * const hdmi =
  60                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
  61         unsigned long tmo = timer_get_us() + 300000;
  62
  63         /* Set pll3 to 300MHz */
  64         clock_set_pll3(300000000);
  65
  66         /* Set hdmi parent to pll3 */
  67         clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK,
  68                         CCM_HDMI_CTRL_PLL3);
  69
  70         /* Set ahb gating to pass */
  71 #ifdef CONFIG_MACH_SUN6I
  72         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
  73 #endif
  74         setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
  75
  76         /* Clock on */
  77         setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
  78
  79         writel(SUNXI_HDMI_CTRL_ENABLE, &hdmi->ctrl);
  80         writel(SUNXI_HDMI_PAD_CTRL0_HDP, &hdmi->pad_ctrl0);
  81
  82         while (timer_get_us() < tmo) {
  83                 if (readl(&hdmi->hpd) & SUNXI_HDMI_HPD_DETECT)
  84                         return 1;
  85         }
  86
  87         return 0;
  88 }
  89
  90 static void sunxi_hdmi_shutdown(void)
  91 {
  92         struct sunxi_ccm_reg * const ccm =
  93                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  94         struct sunxi_hdmi_reg * const hdmi =
  95                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
  96
  97         clrbits_le32(&hdmi->ctrl, SUNXI_HDMI_CTRL_ENABLE);
  98         clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
  99         clrbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
 100 #ifdef CONFIG_MACH_SUN6I
 101         clrbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
 102 #endif
 103         clock_set_pll3(0);
 104 }
 105
 106 static int sunxi_hdmi_ddc_do_command(u32 cmnd, int offset, int n)
 107 {
 108         struct sunxi_hdmi_reg * const hdmi =
 109                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 110
 111         setbits_le32(&hdmi->ddc_fifo_ctrl, SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR);
 112         writel(SUNXI_HMDI_DDC_ADDR_EDDC_SEGMENT(offset >> 8) |
 113                SUNXI_HMDI_DDC_ADDR_EDDC_ADDR |
 114                SUNXI_HMDI_DDC_ADDR_OFFSET(offset) |
 115                SUNXI_HMDI_DDC_ADDR_SLAVE_ADDR, &hdmi->ddc_addr);
 116 #ifndef CONFIG_MACH_SUN6I
 117         writel(n, &hdmi->ddc_byte_count);
 118         writel(cmnd, &hdmi->ddc_cmnd);
 119 #else
 120         writel(n << 16 | cmnd, &hdmi->ddc_cmnd);
 121 #endif
 122         setbits_le32(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_START);
 123
 124         return await_completion(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_START, 0);
 125 }
 126
 127 static int sunxi_hdmi_ddc_read(int offset, u8 *buf, int count)
 128 {
 129         struct sunxi_hdmi_reg * const hdmi =
 130                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 131         int i, n;
 132
 133         while (count > 0) {
 134                 if (count > 16)
 135                         n = 16;
 136                 else
 137                         n = count;
 138
 139                 if (sunxi_hdmi_ddc_do_command(
 140                                 SUNXI_HDMI_DDC_CMND_EXPLICIT_EDDC_READ,
 141                                 offset, n))
 142                         return -ETIME;
 143
 144                 for (i = 0; i < n; i++)
 145                         *buf++ = readb(&hdmi->ddc_fifo_data);
 146
 147                 offset += n;
 148                 count -= n;
 149         }
 150
 151         return 0;
 152 }
 153
 154 static int sunxi_hdmi_edid_get_block(int block, u8 *buf)
 155 {
 156         int r, retries = 2;
 157
 158         do {
 159                 r = sunxi_hdmi_ddc_read(block * 128, buf, 128);
 160                 if (r)
 161                         continue;
 162                 r = edid_check_checksum(buf);
 163                 if (r) {
 164                         printf("EDID block %d: checksum error%s\n",
 165                                block, retries ? ", retrying" : "");
 166                 }
 167         } while (r && retries--);
 168
 169         return r;
 170 }
 171
 172 static int sunxi_hdmi_edid_get_mode(struct ctfb_res_modes *mode)
 173 {
 174         struct edid1_info edid1;
 175         struct edid_cea861_info cea681[4];
 176         struct edid_detailed_timing *t =
 177                 (struct edid_detailed_timing *)edid1.monitor_details.timing;
 178         struct sunxi_hdmi_reg * const hdmi =
 179                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 180         struct sunxi_ccm_reg * const ccm =
 181                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 182         int i, r, ext_blocks = 0;
 183
 184         /* SUNXI_HDMI_CTRL_ENABLE & PAD_CTRL0 are already set by hpd_detect */
 185         writel(SUNXI_HDMI_PAD_CTRL1 | SUNXI_HDMI_PAD_CTRL1_HALVE,
 186                &hdmi->pad_ctrl1);
 187         writel(SUNXI_HDMI_PLL_CTRL | SUNXI_HDMI_PLL_CTRL_DIV(15),
 188                &hdmi->pll_ctrl);
 189         writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0);
 190
 191         /* Reset i2c controller */
 192         setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE);
 193         writel(SUNXI_HMDI_DDC_CTRL_ENABLE |
 194                SUNXI_HMDI_DDC_CTRL_SDA_ENABLE |
 195                SUNXI_HMDI_DDC_CTRL_SCL_ENABLE |
 196                SUNXI_HMDI_DDC_CTRL_RESET, &hdmi->ddc_ctrl);
 197         if (await_completion(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_RESET, 0))
 198                 return -EIO;
 199
 200         writel(SUNXI_HDMI_DDC_CLOCK, &hdmi->ddc_clock);
 201 #ifndef CONFIG_MACH_SUN6I
 202         writel(SUNXI_HMDI_DDC_LINE_CTRL_SDA_ENABLE |
 203                SUNXI_HMDI_DDC_LINE_CTRL_SCL_ENABLE, &hdmi->ddc_line_ctrl);
 204 #endif
 205
 206         r = sunxi_hdmi_edid_get_block(0, (u8 *)&edid1);
 207         if (r == 0) {
 208                 r = edid_check_info(&edid1);
 209                 if (r) {
 210                         printf("EDID: invalid EDID data\n");
 211                         r = -EINVAL;
 212                 }
 213         }
 214         if (r == 0) {
 215                 ext_blocks = edid1.extension_flag;
 216                 if (ext_blocks > 4)
 217                         ext_blocks = 4;
 218                 for (i = 0; i < ext_blocks; i++) {
 219                         if (sunxi_hdmi_edid_get_block(1 + i,
 220                                                 (u8 *)&cea681[i]) != 0) {
 221                                 ext_blocks = i;
 222                                 break;
 223                         }
 224                 }
 225         }
 226
 227         /* Disable DDC engine, no longer needed */
 228         clrbits_le32(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_ENABLE);
 229         clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE);
 230
 231         if (r)
 232                 return r;
 233
 234         /* We want version 1.3 or 1.2 with detailed timing info */
 235         if (edid1.version != 1 || (edid1.revision < 3 &&
 236                         !EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(edid1))) {
 237                 printf("EDID: unsupported version %d.%d\n",
 238                        edid1.version, edid1.revision);
 239                 return -EINVAL;
 240         }
 241
 242         /* Take the first usable detailed timing */
 243         for (i = 0; i < 4; i++, t++) {
 244                 r = video_edid_dtd_to_ctfb_res_modes(t, mode);
 245                 if (r == 0)
 246                         break;
 247         }
 248         if (i == 4) {
 249                 printf("EDID: no usable detailed timing found\n");
 250                 return -ENOENT;
 251         }
 252
 253         /* Check for basic audio support, if found enable hdmi output */
 254         sunxi_display.monitor = sunxi_monitor_dvi;
 255         for (i = 0; i < ext_blocks; i++) {
 256                 if (cea681[i].extension_tag != EDID_CEA861_EXTENSION_TAG ||
 257                     cea681[i].revision < 2)
 258                         continue;
 259
 260                 if (EDID_CEA861_SUPPORTS_BASIC_AUDIO(cea681[i]))
 261                         sunxi_display.monitor = sunxi_monitor_hdmi;
 262         }
 263
 264         return 0;
 265 }
 266
 267 /*
 268  * This is the entity that mixes and matches the different layers and inputs.
 269  * Allwinner calls it the back-end, but i like composer better.
 270  */
 271 static void sunxi_composer_init(void)
 272 {
 273         struct sunxi_ccm_reg * const ccm =
 274                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 275         struct sunxi_de_be_reg * const de_be =
 276                 (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
 277         int i;
 278
 279 #ifdef CONFIG_MACH_SUN6I
 280         /* Reset off */
 281         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE_BE0);
 282 #endif
 283
 284         /* Clocks on */
 285         setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE_BE0);
 286         setbits_le32(&ccm->dram_clk_gate, 1 << CCM_DRAM_GATE_OFFSET_DE_BE0);
 287         clock_set_de_mod_clock(&ccm->be0_clk_cfg, 300000000);
 288
 289         /* Engine bug, clear registers after reset */
 290         for (i = 0x0800; i < 0x1000; i += 4)
 291                 writel(0, SUNXI_DE_BE0_BASE + i);
 292
 293         setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_ENABLE);
 294 }
 295
 296 static void sunxi_composer_mode_set(const struct ctfb_res_modes *mode,
 297                                     unsigned int address)
 298 {
 299         struct sunxi_de_be_reg * const de_be =
 300                 (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
 301
 302         writel(SUNXI_DE_BE_HEIGHT(mode->yres) | SUNXI_DE_BE_WIDTH(mode->xres),
 303                &de_be->disp_size);
 304         writel(SUNXI_DE_BE_HEIGHT(mode->yres) | SUNXI_DE_BE_WIDTH(mode->xres),
 305                &de_be->layer0_size);
 306         writel(SUNXI_DE_BE_LAYER_STRIDE(mode->xres), &de_be->layer0_stride);
 307         writel(address << 3, &de_be->layer0_addr_low32b);
 308         writel(address >> 29, &de_be->layer0_addr_high4b);
 309         writel(SUNXI_DE_BE_LAYER_ATTR1_FMT_XRGB8888, &de_be->layer0_attr1_ctrl);
 310
 311         setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_LAYER0_ENABLE);
 312 }
 313
 314 /*
 315  * LCDC, what allwinner calls a CRTC, so timing controller and serializer.
 316  */
 317 static void sunxi_lcdc_pll_set(int dotclock, int *clk_div, int *clk_double)
 318 {
 319         struct sunxi_ccm_reg * const ccm =
 320                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 321         int value, n, m, diff;
 322         int best_n = 0, best_m = 0, best_diff = 0x0FFFFFFF;
 323         int best_double = 0;
 324
 325         /*
 326          * Find the lowest divider resulting in a matching clock, if there
 327          * is no match, pick the closest lower clock, as monitors tend to
 328          * not sync to higher frequencies.
 329          */
 330         for (m = 15; m > 0; m--) {
 331                 n = (m * dotclock) / 3000;
 332
 333                 if ((n >= 9) && (n <= 127)) {
 334                         value = (3000 * n) / m;
 335                         diff = dotclock - value;
 336                         if (diff < best_diff) {
 337                                 best_diff = diff;
 338                                 best_m = m;
 339                                 best_n = n;
 340                                 best_double = 0;
 341                         }
 342                 }
 343
 344                 /* These are just duplicates */
 345                 if (!(m & 1))
 346                         continue;
 347
 348                 n = (m * dotclock) / 6000;
 349                 if ((n >= 9) && (n <= 127)) {
 350                         value = (6000 * n) / m;
 351                         diff = dotclock - value;
 352                         if (diff < best_diff) {
 353                                 best_diff = diff;
 354                                 best_m = m;
 355                                 best_n = n;
 356                                 best_double = 1;
 357                         }
 358                 }
 359         }
 360
 361         debug("dotclock: %dkHz = %dkHz: (%d * 3MHz * %d) / %d\n",
 362               dotclock, (best_double + 1) * 3000 * best_n / best_m,
 363               best_double + 1, best_n, best_m);
 364
 365         clock_set_pll3(best_n * 3000000);
 366
 367         writel(CCM_LCD_CH1_CTRL_GATE |
 368             (best_double ? CCM_LCD_CH1_CTRL_PLL3_2X : CCM_LCD_CH1_CTRL_PLL3) |
 369             CCM_LCD_CH1_CTRL_M(best_m), &ccm->lcd0_ch1_clk_cfg);
 370
 371         *clk_div = best_m;
 372         *clk_double = best_double;
 373 }
 374
 375 static void sunxi_lcdc_init(void)
 376 {
 377         struct sunxi_ccm_reg * const ccm =
 378                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 379         struct sunxi_lcdc_reg * const lcdc =
 380                 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
 381
 382         /* Reset off */
 383 #ifdef CONFIG_MACH_SUN6I
 384         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);
 385 #else
 386         setbits_le32(&ccm->lcd0_ch0_clk_cfg, CCM_LCD_CH0_CTRL_RST);
 387 #endif
 388
 389         /* Clock on */
 390         setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0);
 391
 392         /* Init lcdc */
 393         writel(0, &lcdc->ctrl); /* Disable tcon */
 394         writel(0, &lcdc->int0); /* Disable all interrupts */
 395
 396         /* Disable tcon0 dot clock */
 397         clrbits_le32(&lcdc->tcon0_dclk, SUNXI_LCDC_TCON0_DCLK_ENABLE);
 398
 399         /* Set all io lines to tristate */
 400         writel(0xffffffff, &lcdc->tcon0_io_tristate);
 401         writel(0xffffffff, &lcdc->tcon1_io_tristate);
 402 }
 403
 404 static void sunxi_lcdc_mode_set(const struct ctfb_res_modes *mode,
 405                                 int *clk_div, int *clk_double)
 406 {
 407         struct sunxi_lcdc_reg * const lcdc =
 408                 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
 409         int bp, total;
 410
 411         /* Use tcon1 */
 412         clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
 413                         SUNXI_LCDC_CTRL_IO_MAP_TCON1);
 414
 415         /* Enabled, 0x1e start delay */
 416         writel(SUNXI_LCDC_TCON1_CTRL_ENABLE |
 417                SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(0x1e), &lcdc->tcon1_ctrl);
 418
 419         writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
 420                &lcdc->tcon1_timing_source);
 421         writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
 422                &lcdc->tcon1_timing_scale);
 423         writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
 424                &lcdc->tcon1_timing_out);
 425
 426         bp = mode->hsync_len + mode->left_margin;
 427         total = mode->xres + mode->right_margin + bp;
 428         writel(SUNXI_LCDC_TCON1_TIMING_H_TOTAL(total) |
 429                SUNXI_LCDC_TCON1_TIMING_H_BP(bp), &lcdc->tcon1_timing_h);
 430
 431         bp = mode->vsync_len + mode->upper_margin;
 432         total = mode->yres + mode->lower_margin + bp;
 433         writel(SUNXI_LCDC_TCON1_TIMING_V_TOTAL(total) |
 434                SUNXI_LCDC_TCON1_TIMING_V_BP(bp), &lcdc->tcon1_timing_v);
 435
 436         writel(SUNXI_LCDC_X(mode->hsync_len) | SUNXI_LCDC_Y(mode->vsync_len),
 437                &lcdc->tcon1_timing_sync);
 438
 439         sunxi_lcdc_pll_set(mode->pixclock_khz, clk_div, clk_double);
 440 }
 441
 442 #ifdef CONFIG_MACH_SUN6I
 443 static void sunxi_drc_init(void)
 444 {
 445         struct sunxi_ccm_reg * const ccm =
 446                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 447
 448         /* On sun6i the drc must be clocked even when in pass-through mode */
 449         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DRC0);
 450         clock_set_de_mod_clock(&ccm->iep_drc0_clk_cfg, 300000000);
 451 }
 452 #endif
 453
 454 static void sunxi_hdmi_setup_info_frames(const struct ctfb_res_modes *mode)
 455 {
 456         struct sunxi_hdmi_reg * const hdmi =
 457                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 458         u8 checksum = 0;
 459         u8 avi_info_frame[17] = {
 460                 0x82, 0x02, 0x0d, 0x00, 0x12, 0x00, 0x88, 0x00,
 461                 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 462                 0x00
 463         };
 464         u8 vendor_info_frame[19] = {
 465                 0x81, 0x01, 0x06, 0x29, 0x03, 0x0c, 0x00, 0x40,
 466                 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 467                 0x00, 0x00, 0x00
 468         };
 469         int i;
 470
 471         if (mode->pixclock_khz <= 27000)
 472                 avi_info_frame[5] = 0x40; /* SD-modes, ITU601 colorspace */
 473         else
 474                 avi_info_frame[5] = 0x80; /* HD-modes, ITU709 colorspace */
 475
 476         if (mode->xres * 100 / mode->yres < 156)
 477                 avi_info_frame[5] |= 0x18; /* 4 : 3 */
 478         else
 479                 avi_info_frame[5] |= 0x28; /* 16 : 9 */
 480
 481         for (i = 0; i < ARRAY_SIZE(avi_info_frame); i++)
 482                 checksum += avi_info_frame[i];
 483
 484         avi_info_frame[3] = 0x100 - checksum;
 485
 486         for (i = 0; i < ARRAY_SIZE(avi_info_frame); i++)
 487                 writeb(avi_info_frame[i], &hdmi->avi_info_frame[i]);
 488
 489         writel(SUNXI_HDMI_QCP_PACKET0, &hdmi->qcp_packet0);
 490         writel(SUNXI_HDMI_QCP_PACKET1, &hdmi->qcp_packet1);
 491
 492         for (i = 0; i < ARRAY_SIZE(vendor_info_frame); i++)
 493                 writeb(vendor_info_frame[i], &hdmi->vendor_info_frame[i]);
 494
 495         writel(SUNXI_HDMI_PKT_CTRL0, &hdmi->pkt_ctrl0);
 496         writel(SUNXI_HDMI_PKT_CTRL1, &hdmi->pkt_ctrl1);
 497
 498         setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_HDMI);
 499 }
 500
 501 static void sunxi_hdmi_mode_set(const struct ctfb_res_modes *mode,
 502                                 int clk_div, int clk_double)
 503 {
 504         struct sunxi_hdmi_reg * const hdmi =
 505                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 506         int x, y;
 507
 508         /* Write clear interrupt status bits */
 509         writel(SUNXI_HDMI_IRQ_STATUS_BITS, &hdmi->irq);
 510
 511         if (sunxi_display.monitor == sunxi_monitor_hdmi)
 512                 sunxi_hdmi_setup_info_frames(mode);
 513
 514         /* Set input sync enable */
 515         writel(SUNXI_HDMI_UNKNOWN_INPUT_SYNC, &hdmi->unknown);
 516
 517         /* Init various registers, select pll3 as clock source */
 518         writel(SUNXI_HDMI_VIDEO_POL_TX_CLK, &hdmi->video_polarity);
 519         writel(SUNXI_HDMI_PAD_CTRL0_RUN, &hdmi->pad_ctrl0);
 520         writel(SUNXI_HDMI_PAD_CTRL1, &hdmi->pad_ctrl1);
 521         writel(SUNXI_HDMI_PLL_CTRL, &hdmi->pll_ctrl);
 522         writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0);
 523
 524         /* Setup clk div and doubler */
 525         clrsetbits_le32(&hdmi->pll_ctrl, SUNXI_HDMI_PLL_CTRL_DIV_MASK,
 526                         SUNXI_HDMI_PLL_CTRL_DIV(clk_div));
 527         if (!clk_double)
 528                 setbits_le32(&hdmi->pad_ctrl1, SUNXI_HDMI_PAD_CTRL1_HALVE);
 529
 530         /* Setup timing registers */
 531         writel(SUNXI_HDMI_Y(mode->yres) | SUNXI_HDMI_X(mode->xres),
 532                &hdmi->video_size);
 533
 534         x = mode->hsync_len + mode->left_margin;
 535         y = mode->vsync_len + mode->upper_margin;
 536         writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_bp);
 537
 538         x = mode->right_margin;
 539         y = mode->lower_margin;
 540         writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_fp);
 541
 542         x = mode->hsync_len;
 543         y = mode->vsync_len;
 544         writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_spw);
 545
 546         if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
 547                 setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_HOR);
 548
 549         if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
 550                 setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_VER);
 551 }
 552
 553 static void sunxi_engines_init(void)
 554 {
 555         sunxi_composer_init();
 556         sunxi_lcdc_init();
 557 #ifdef CONFIG_MACH_SUN6I
 558         sunxi_drc_init();
 559 #endif
 560 }
 561
 562 static void sunxi_mode_set(const struct ctfb_res_modes *mode,
 563                            unsigned int address)
 564 {
 565         struct sunxi_de_be_reg * const de_be =
 566                 (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
 567         struct sunxi_lcdc_reg * const lcdc =
 568                 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
 569         struct sunxi_hdmi_reg * const hdmi =
 570                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 571         int clk_div, clk_double;
 572
 573         sunxi_composer_mode_set(mode, address);
 574         sunxi_lcdc_mode_set(mode, &clk_div, &clk_double);
 575         sunxi_hdmi_mode_set(mode, clk_div, clk_double);
 576
 577         setbits_le32(&de_be->reg_ctrl, SUNXI_DE_BE_REG_CTRL_LOAD_REGS);
 578         setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_START);
 579         setbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_TCON_ENABLE);
 580
 581         udelay(100);
 582
 583         setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_ENABLE);
 584 }
 585
 586 static const char *sunxi_get_mon_desc(enum sunxi_monitor monitor)
 587 {
 588         switch (monitor) {
 589         case sunxi_monitor_none:        return "none";
 590         case sunxi_monitor_dvi:         return "dvi";
 591         case sunxi_monitor_hdmi:        return "hdmi";
 592         case sunxi_monitor_lcd:         return "lcd";
 593         case sunxi_monitor_vga:         return "vga";
 594         }
 595         return NULL; /* never reached */
 596 }
 597
 598 void *video_hw_init(void)
 599 {
 600         static GraphicDevice *graphic_device = &sunxi_display.graphic_device;
 601         const struct ctfb_res_modes *mode;
 602         struct ctfb_res_modes edid_mode;
 603         const char *options;
 604         unsigned int depth;
 605         int i, ret, hpd, edid;
 606         char mon[16];
 607
 608         memset(&sunxi_display, 0, sizeof(struct sunxi_display));
 609
 610         printf("Reserved %dkB of RAM for Framebuffer.\n",
 611                CONFIG_SUNXI_FB_SIZE >> 10);
 612         gd->fb_base = gd->ram_top;
 613
 614         video_get_ctfb_res_modes(RES_MODE_1024x768, 24, &mode, &depth, &options);
 615         hpd = video_get_option_int(options, "hpd", 1);
 616         edid = video_get_option_int(options, "edid", 1);
 617         sunxi_display.monitor = sunxi_monitor_dvi;
 618         video_get_option_string(options, "monitor", mon, sizeof(mon),
 619                                 sunxi_get_mon_desc(sunxi_display.monitor));
 620         for (i = 0; i <= SUNXI_MONITOR_LAST; i++) {
 621                 if (strcmp(mon, sunxi_get_mon_desc(i)) == 0) {
 622                         sunxi_display.monitor = i;
 623                         break;
 624                 }
 625         }
 626         if (i > SUNXI_MONITOR_LAST)
 627                 printf("Unknown monitor: '%s', falling back to '%s'\n",
 628                        mon, sunxi_get_mon_desc(sunxi_display.monitor));
 629
 630         /* Always call hdp_detect, as it also enables various clocks, etc. */
 631         ret = sunxi_hdmi_hpd_detect();
 632         if (hpd && !ret) {
 633                 sunxi_hdmi_shutdown();
 634                 return NULL;
 635         }
 636         if (ret)
 637                 printf("HDMI connected: ");
 638
 639         /* Check edid if requested and we've a cable plugged in */
 640         if (edid && ret) {
 641                 if (sunxi_hdmi_edid_get_mode(&edid_mode) == 0)
 642                         mode = &edid_mode;
 643         }
 644
 645         if (mode->vmode != FB_VMODE_NONINTERLACED) {
 646                 printf("Only non-interlaced modes supported, falling back to 1024x768\n");
 647                 mode = &res_mode_init[RES_MODE_1024x768];
 648         } else {
 649                 printf("Setting up a %dx%d %s console\n", mode->xres,
 650                        mode->yres, sunxi_get_mon_desc(sunxi_display.monitor));
 651         }
 652
 653         sunxi_display.enabled = true;
 654         sunxi_engines_init();
 655         sunxi_mode_set(mode, gd->fb_base - CONFIG_SYS_SDRAM_BASE);
 656
 657         /*
 658          * These are the only members of this structure that are used. All the
 659          * others are driver specific. There is nothing to decribe pitch or
 660          * stride, but we are lucky with our hw.
 661          */
 662         graphic_device->frameAdrs = gd->fb_base;
 663         graphic_device->gdfIndex = GDF_32BIT_X888RGB;
 664         graphic_device->gdfBytesPP = 4;
 665         graphic_device->winSizeX = mode->xres;
 666         graphic_device->winSizeY = mode->yres;
 667
 668         return graphic_device;
 669 }
 670
 671 /*
 672  * Simplefb support.
 673  */
 674 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_VIDEO_DT_SIMPLEFB)
 675 int sunxi_simplefb_setup(void *blob)
 676 {
 677         static GraphicDevice *graphic_device = &sunxi_display.graphic_device;
 678         int offset, ret;
 679
 680         if (!sunxi_display.enabled)
 681                 return 0;
 682
 683         /* Find a framebuffer node, with pipeline == "de_be0-lcd0-hdmi" */
 684         offset = fdt_node_offset_by_compatible(blob, -1,
 685                                                "allwinner,simple-framebuffer");
 686         while (offset >= 0) {
 687                 ret = fdt_find_string(blob, offset, "allwinner,pipeline",
 688                                       "de_be0-lcd0-hdmi");
 689                 if (ret == 0)
 690                         break;
 691                 offset = fdt_node_offset_by_compatible(blob, offset,
 692                                                "allwinner,simple-framebuffer");
 693         }
 694         if (offset < 0) {
 695                 eprintf("Cannot setup simplefb: node not found\n");
 696                 return 0; /* Keep older kernels working */
 697         }
 698
 699         ret = fdt_setup_simplefb_node(blob, offset, gd->fb_base,
 700                         graphic_device->winSizeX, graphic_device->winSizeY,
 701                         graphic_device->winSizeX * graphic_device->gdfBytesPP,
 702                         "x8r8g8b8");
 703         if (ret)
 704                 eprintf("Cannot setup simplefb: Error setting properties\n");
 705
 706         return ret;
 707 }
 708 #endif /* CONFIG_OF_BOARD_SETUP && CONFIG_VIDEO_DT_SIMPLEFB */