drivers/video/sunxi_display.c

   1 /*
   2  * Display driver for Allwinner SoCs.
   3  *
   4  * (C) Copyright 2013-2014 Luc Verhaegen <libv@skynet.be>
   5  * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/display.h>
  14 #include <asm/global_data.h>
  15 #include <asm/io.h>
  16 #include <errno.h>
  17 #include <fdtdec.h>
  18 #include <fdt_support.h>
  19 #include <video_fb.h>
  20 #include "videomodes.h"
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 struct sunxi_display {
  25         GraphicDevice graphic_device;
  26         bool enabled;
  27 } sunxi_display;
  28
  29 /*
  30  * Wait up to 200ms for value to be set in given part of reg.
  31  */
  32 static int await_completion(u32 *reg, u32 mask, u32 val)
  33 {
  34         unsigned long tmo = timer_get_us() + 200000;
  35
  36         while ((readl(reg) & mask) != val) {
  37                 if (timer_get_us() > tmo) {
  38                         printf("DDC: timeout reading EDID\n");
  39                         return -ETIME;
  40                 }
  41         }
  42         return 0;
  43 }
  44
  45 static int sunxi_hdmi_hpd_detect(void)
  46 {
  47         struct sunxi_ccm_reg * const ccm =
  48                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  49         struct sunxi_hdmi_reg * const hdmi =
  50                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
  51
  52         /* Set pll3 to 300MHz */
  53         clock_set_pll3(300000000);
  54
  55         /* Set hdmi parent to pll3 */
  56         clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK,
  57                         CCM_HDMI_CTRL_PLL3);
  58
  59         /* Set ahb gating to pass */
  60 #ifdef CONFIG_MACH_SUN6I
  61         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
  62 #endif
  63         setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
  64
  65         /* Clock on */
  66         setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
  67
  68         writel(SUNXI_HDMI_CTRL_ENABLE, &hdmi->ctrl);
  69         writel(SUNXI_HDMI_PAD_CTRL0_HDP, &hdmi->pad_ctrl0);
  70
  71         udelay(1000);
  72
  73         return (readl(&hdmi->hpd) & SUNXI_HDMI_HPD_DETECT) ? 1 : 0;
  74 }
  75
  76 static void sunxi_hdmi_shutdown(void)
  77 {
  78         struct sunxi_ccm_reg * const ccm =
  79                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  80         struct sunxi_hdmi_reg * const hdmi =
  81                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
  82
  83         clrbits_le32(&hdmi->ctrl, SUNXI_HDMI_CTRL_ENABLE);
  84         clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
  85         clrbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
  86 #ifdef CONFIG_MACH_SUN6I
  87         clrbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
  88 #endif
  89         clock_set_pll3(0);
  90 }
  91
  92 static int sunxi_hdmi_ddc_do_command(u32 cmnd, int offset, int n)
  93 {
  94         struct sunxi_hdmi_reg * const hdmi =
  95                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
  96
  97         setbits_le32(&hdmi->ddc_fifo_ctrl, SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR);
  98         writel(SUNXI_HMDI_DDC_ADDR_EDDC_SEGMENT(offset >> 8) |
  99                SUNXI_HMDI_DDC_ADDR_EDDC_ADDR |
 100                SUNXI_HMDI_DDC_ADDR_OFFSET(offset) |
 101                SUNXI_HMDI_DDC_ADDR_SLAVE_ADDR, &hdmi->ddc_addr);
 102 #ifndef CONFIG_MACH_SUN6I
 103         writel(n, &hdmi->ddc_byte_count);
 104         writel(cmnd, &hdmi->ddc_cmnd);
 105 #else
 106         writel(n << 16 | cmnd, &hdmi->ddc_cmnd);
 107 #endif
 108         setbits_le32(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_START);
 109
 110         return await_completion(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_START, 0);
 111 }
 112
 113 static int sunxi_hdmi_ddc_read(int offset, u8 *buf, int count)
 114 {
 115         struct sunxi_hdmi_reg * const hdmi =
 116                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 117         int i, n;
 118
 119         while (count > 0) {
 120                 if (count > 16)
 121                         n = 16;
 122                 else
 123                         n = count;
 124
 125                 if (sunxi_hdmi_ddc_do_command(
 126                                 SUNXI_HDMI_DDC_CMND_EXPLICIT_EDDC_READ,
 127                                 offset, n))
 128                         return -ETIME;
 129
 130                 for (i = 0; i < n; i++)
 131                         *buf++ = readb(&hdmi->ddc_fifo_data);
 132
 133                 offset += n;
 134                 count -= n;
 135         }
 136
 137         return 0;
 138 }
 139
 140 static int sunxi_hdmi_edid_get_mode(struct ctfb_res_modes *mode)
 141 {
 142         struct edid1_info edid1;
 143         struct edid_detailed_timing *t =
 144                 (struct edid_detailed_timing *)edid1.monitor_details.timing;
 145         struct sunxi_hdmi_reg * const hdmi =
 146                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 147         struct sunxi_ccm_reg * const ccm =
 148                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 149         int i, r, retries = 2;
 150
 151         /* SUNXI_HDMI_CTRL_ENABLE & PAD_CTRL0 are already set by hpd_detect */
 152         writel(SUNXI_HDMI_PAD_CTRL1 | SUNXI_HDMI_PAD_CTRL1_HALVE,
 153                &hdmi->pad_ctrl1);
 154         writel(SUNXI_HDMI_PLL_CTRL | SUNXI_HDMI_PLL_CTRL_DIV(15),
 155                &hdmi->pll_ctrl);
 156         writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0);
 157
 158         /* Reset i2c controller */
 159         setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE);
 160         writel(SUNXI_HMDI_DDC_CTRL_ENABLE |
 161                SUNXI_HMDI_DDC_CTRL_SDA_ENABLE |
 162                SUNXI_HMDI_DDC_CTRL_SCL_ENABLE |
 163                SUNXI_HMDI_DDC_CTRL_RESET, &hdmi->ddc_ctrl);
 164         if (await_completion(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_RESET, 0))
 165                 return -EIO;
 166
 167         writel(SUNXI_HDMI_DDC_CLOCK, &hdmi->ddc_clock);
 168 #ifndef CONFIG_MACH_SUN6I
 169         writel(SUNXI_HMDI_DDC_LINE_CTRL_SDA_ENABLE |
 170                SUNXI_HMDI_DDC_LINE_CTRL_SCL_ENABLE, &hdmi->ddc_line_ctrl);
 171 #endif
 172
 173         do {
 174                 r = sunxi_hdmi_ddc_read(0, (u8 *)&edid1, 128);
 175                 if (r)
 176                         continue;
 177                 r = edid_check_checksum((u8 *)&edid1);
 178                 if (r) {
 179                         printf("EDID: checksum error%s\n",
 180                                retries ? ", retrying" : "");
 181                 }
 182         } while (r && retries--);
 183
 184         /* Disable DDC engine, no longer needed */
 185         clrbits_le32(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_ENABLE);
 186         clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE);
 187
 188         if (r)
 189                 return r;
 190
 191         r = edid_check_info(&edid1);
 192         if (r) {
 193                 printf("EDID: invalid EDID data\n");
 194                 return -EINVAL;
 195         }
 196
 197         /* We want version 1.3 or 1.2 with detailed timing info */
 198         if (edid1.version != 1 || (edid1.revision < 3 &&
 199                         !EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(edid1))) {
 200                 printf("EDID: unsupported version %d.%d\n",
 201                        edid1.version, edid1.revision);
 202                 return -EINVAL;
 203         }
 204
 205         /* Take the first usable detailed timing */
 206         for (i = 0; i < 4; i++, t++) {
 207                 r = video_edid_dtd_to_ctfb_res_modes(t, mode);
 208                 if (r == 0)
 209                         break;
 210         }
 211         if (i == 4) {
 212                 printf("EDID: no usable detailed timing found\n");
 213                 return -ENOENT;
 214         }
 215
 216         return 0;
 217 }
 218
 219 /*
 220  * This is the entity that mixes and matches the different layers and inputs.
 221  * Allwinner calls it the back-end, but i like composer better.
 222  */
 223 static void sunxi_composer_init(void)
 224 {
 225         struct sunxi_ccm_reg * const ccm =
 226                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 227         struct sunxi_de_be_reg * const de_be =
 228                 (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
 229         int i;
 230
 231 #ifdef CONFIG_MACH_SUN6I
 232         /* Reset off */
 233         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE_BE0);
 234 #endif
 235
 236         /* Clocks on */
 237         setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE_BE0);
 238         setbits_le32(&ccm->dram_clk_gate, 1 << CCM_DRAM_GATE_OFFSET_DE_BE0);
 239         clock_set_de_mod_clock(&ccm->be0_clk_cfg, 300000000);
 240
 241         /* Engine bug, clear registers after reset */
 242         for (i = 0x0800; i < 0x1000; i += 4)
 243                 writel(0, SUNXI_DE_BE0_BASE + i);
 244
 245         setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_ENABLE);
 246 }
 247
 248 static void sunxi_composer_mode_set(const struct ctfb_res_modes *mode,
 249                                     unsigned int address)
 250 {
 251         struct sunxi_de_be_reg * const de_be =
 252                 (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
 253
 254         writel(SUNXI_DE_BE_HEIGHT(mode->yres) | SUNXI_DE_BE_WIDTH(mode->xres),
 255                &de_be->disp_size);
 256         writel(SUNXI_DE_BE_HEIGHT(mode->yres) | SUNXI_DE_BE_WIDTH(mode->xres),
 257                &de_be->layer0_size);
 258         writel(SUNXI_DE_BE_LAYER_STRIDE(mode->xres), &de_be->layer0_stride);
 259         writel(address << 3, &de_be->layer0_addr_low32b);
 260         writel(address >> 29, &de_be->layer0_addr_high4b);
 261         writel(SUNXI_DE_BE_LAYER_ATTR1_FMT_XRGB8888, &de_be->layer0_attr1_ctrl);
 262
 263         setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_LAYER0_ENABLE);
 264 }
 265
 266 /*
 267  * LCDC, what allwinner calls a CRTC, so timing controller and serializer.
 268  */
 269 static void sunxi_lcdc_pll_set(int dotclock, int *clk_div, int *clk_double)
 270 {
 271         struct sunxi_ccm_reg * const ccm =
 272                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 273         int value, n, m, diff;
 274         int best_n = 0, best_m = 0, best_diff = 0x0FFFFFFF;
 275         int best_double = 0;
 276
 277         /*
 278          * Find the lowest divider resulting in a matching clock, if there
 279          * is no match, pick the closest lower clock, as monitors tend to
 280          * not sync to higher frequencies.
 281          */
 282         for (m = 15; m > 0; m--) {
 283                 n = (m * dotclock) / 3000;
 284
 285                 if ((n >= 9) && (n <= 127)) {
 286                         value = (3000 * n) / m;
 287                         diff = dotclock - value;
 288                         if (diff < best_diff) {
 289                                 best_diff = diff;
 290                                 best_m = m;
 291                                 best_n = n;
 292                                 best_double = 0;
 293                         }
 294                 }
 295
 296                 /* These are just duplicates */
 297                 if (!(m & 1))
 298                         continue;
 299
 300                 n = (m * dotclock) / 6000;
 301                 if ((n >= 9) && (n <= 127)) {
 302                         value = (6000 * n) / m;
 303                         diff = dotclock - value;
 304                         if (diff < best_diff) {
 305                                 best_diff = diff;
 306                                 best_m = m;
 307                                 best_n = n;
 308                                 best_double = 1;
 309                         }
 310                 }
 311         }
 312
 313         debug("dotclock: %dkHz = %dkHz: (%d * 3MHz * %d) / %d\n",
 314               dotclock, (best_double + 1) * 3000 * best_n / best_m,
 315               best_double + 1, best_n, best_m);
 316
 317         clock_set_pll3(best_n * 3000000);
 318
 319         writel(CCM_LCD_CH1_CTRL_GATE |
 320             (best_double ? CCM_LCD_CH1_CTRL_PLL3_2X : CCM_LCD_CH1_CTRL_PLL3) |
 321             CCM_LCD_CH1_CTRL_M(best_m), &ccm->lcd0_ch1_clk_cfg);
 322
 323         *clk_div = best_m;
 324         *clk_double = best_double;
 325 }
 326
 327 static void sunxi_lcdc_init(void)
 328 {
 329         struct sunxi_ccm_reg * const ccm =
 330                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 331         struct sunxi_lcdc_reg * const lcdc =
 332                 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
 333
 334         /* Reset off */
 335 #ifdef CONFIG_MACH_SUN6I
 336         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);
 337 #else
 338         setbits_le32(&ccm->lcd0_ch0_clk_cfg, CCM_LCD_CH0_CTRL_RST);
 339 #endif
 340
 341         /* Clock on */
 342         setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0);
 343
 344         /* Init lcdc */
 345         writel(0, &lcdc->ctrl); /* Disable tcon */
 346         writel(0, &lcdc->int0); /* Disable all interrupts */
 347
 348         /* Disable tcon0 dot clock */
 349         clrbits_le32(&lcdc->tcon0_dclk, SUNXI_LCDC_TCON0_DCLK_ENABLE);
 350
 351         /* Set all io lines to tristate */
 352         writel(0xffffffff, &lcdc->tcon0_io_tristate);
 353         writel(0xffffffff, &lcdc->tcon1_io_tristate);
 354 }
 355
 356 static void sunxi_lcdc_mode_set(const struct ctfb_res_modes *mode,
 357                                 int *clk_div, int *clk_double)
 358 {
 359         struct sunxi_lcdc_reg * const lcdc =
 360                 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
 361         int bp, total;
 362
 363         /* Use tcon1 */
 364         clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
 365                         SUNXI_LCDC_CTRL_IO_MAP_TCON1);
 366
 367         /* Enabled, 0x1e start delay */
 368         writel(SUNXI_LCDC_TCON1_CTRL_ENABLE |
 369                SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(0x1e), &lcdc->tcon1_ctrl);
 370
 371         writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
 372                &lcdc->tcon1_timing_source);
 373         writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
 374                &lcdc->tcon1_timing_scale);
 375         writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
 376                &lcdc->tcon1_timing_out);
 377
 378         bp = mode->hsync_len + mode->left_margin;
 379         total = mode->xres + mode->right_margin + bp;
 380         writel(SUNXI_LCDC_TCON1_TIMING_H_TOTAL(total) |
 381                SUNXI_LCDC_TCON1_TIMING_H_BP(bp), &lcdc->tcon1_timing_h);
 382
 383         bp = mode->vsync_len + mode->upper_margin;
 384         total = mode->yres + mode->lower_margin + bp;
 385         writel(SUNXI_LCDC_TCON1_TIMING_V_TOTAL(total) |
 386                SUNXI_LCDC_TCON1_TIMING_V_BP(bp), &lcdc->tcon1_timing_v);
 387
 388         writel(SUNXI_LCDC_X(mode->hsync_len) | SUNXI_LCDC_Y(mode->vsync_len),
 389                &lcdc->tcon1_timing_sync);
 390
 391         sunxi_lcdc_pll_set(mode->pixclock_khz, clk_div, clk_double);
 392 }
 393
 394 #ifdef CONFIG_MACH_SUN6I
 395 static void sunxi_drc_init(void)
 396 {
 397         struct sunxi_ccm_reg * const ccm =
 398                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 399
 400         /* On sun6i the drc must be clocked even when in pass-through mode */
 401         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DRC0);
 402         clock_set_de_mod_clock(&ccm->iep_drc0_clk_cfg, 300000000);
 403 }
 404 #endif
 405
 406 static void sunxi_hdmi_mode_set(const struct ctfb_res_modes *mode,
 407                                 int clk_div, int clk_double)
 408 {
 409         struct sunxi_hdmi_reg * const hdmi =
 410                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 411         int x, y;
 412
 413         /* Write clear interrupt status bits */
 414         writel(SUNXI_HDMI_IRQ_STATUS_BITS, &hdmi->irq);
 415
 416         /* Init various registers, select pll3 as clock source */
 417         writel(SUNXI_HDMI_VIDEO_POL_TX_CLK, &hdmi->video_polarity);
 418         writel(SUNXI_HDMI_PAD_CTRL0_RUN, &hdmi->pad_ctrl0);
 419         writel(SUNXI_HDMI_PAD_CTRL1, &hdmi->pad_ctrl1);
 420         writel(SUNXI_HDMI_PLL_CTRL, &hdmi->pll_ctrl);
 421         writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0);
 422
 423         /* Setup clk div and doubler */
 424         clrsetbits_le32(&hdmi->pll_ctrl, SUNXI_HDMI_PLL_CTRL_DIV_MASK,
 425                         SUNXI_HDMI_PLL_CTRL_DIV(clk_div));
 426         if (!clk_double)
 427                 setbits_le32(&hdmi->pad_ctrl1, SUNXI_HDMI_PAD_CTRL1_HALVE);
 428
 429         /* Setup timing registers */
 430         writel(SUNXI_HDMI_Y(mode->yres) | SUNXI_HDMI_X(mode->xres),
 431                &hdmi->video_size);
 432
 433         x = mode->hsync_len + mode->left_margin;
 434         y = mode->vsync_len + mode->upper_margin;
 435         writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_bp);
 436
 437         x = mode->right_margin;
 438         y = mode->lower_margin;
 439         writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_fp);
 440
 441         x = mode->hsync_len;
 442         y = mode->vsync_len;
 443         writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_spw);
 444
 445         if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
 446                 setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_HOR);
 447
 448         if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
 449                 setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_VER);
 450 }
 451
 452 static void sunxi_engines_init(void)
 453 {
 454         sunxi_composer_init();
 455         sunxi_lcdc_init();
 456 #ifdef CONFIG_MACH_SUN6I
 457         sunxi_drc_init();
 458 #endif
 459 }
 460
 461 static void sunxi_mode_set(const struct ctfb_res_modes *mode, unsigned int address)
 462 {
 463         struct sunxi_de_be_reg * const de_be =
 464                 (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
 465         struct sunxi_lcdc_reg * const lcdc =
 466                 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
 467         struct sunxi_hdmi_reg * const hdmi =
 468                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 469         int clk_div, clk_double;
 470         int retries = 3;
 471
 472 retry:
 473         clrbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_ENABLE);
 474         clrbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_TCON_ENABLE);
 475         clrbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_START);
 476
 477         sunxi_composer_mode_set(mode, address);
 478         sunxi_lcdc_mode_set(mode, &clk_div, &clk_double);
 479         sunxi_hdmi_mode_set(mode, clk_div, clk_double);
 480
 481         setbits_le32(&de_be->reg_ctrl, SUNXI_DE_BE_REG_CTRL_LOAD_REGS);
 482         setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_START);
 483
 484         udelay(1000000 / mode->refresh + 500);
 485
 486         setbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_TCON_ENABLE);
 487
 488         udelay(1000000 / mode->refresh + 500);
 489
 490         setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_ENABLE);
 491
 492         udelay(1000000 / mode->refresh + 500);
 493
 494         /*
 495          * Sometimes the display pipeline does not sync up properly, if
 496          * this happens the hdmi fifo underrun or overrun bits are set.
 497          */
 498         if (readl(&hdmi->irq) &
 499             (SUNXI_HDMI_IRQ_STATUS_FIFO_UF | SUNXI_HDMI_IRQ_STATUS_FIFO_OF)) {
 500                 if (retries--)
 501                         goto retry;
 502                 printf("HDMI fifo under or overrun\n");
 503         }
 504 }
 505
 506 void *video_hw_init(void)
 507 {
 508         static GraphicDevice *graphic_device = &sunxi_display.graphic_device;
 509         const struct ctfb_res_modes *mode;
 510         struct ctfb_res_modes edid_mode;
 511         const char *options;
 512         unsigned int depth;
 513         int ret, hpd, edid;
 514
 515         memset(&sunxi_display, 0, sizeof(struct sunxi_display));
 516
 517         printf("Reserved %dkB of RAM for Framebuffer.\n",
 518                CONFIG_SUNXI_FB_SIZE >> 10);
 519         gd->fb_base = gd->ram_top;
 520
 521         video_get_ctfb_res_modes(RES_MODE_1024x768, 24, &mode, &depth, &options);
 522         hpd = video_get_option_int(options, "hpd", 1);
 523         edid = video_get_option_int(options, "edid", 1);
 524
 525         /* Always call hdp_detect, as it also enables various clocks, etc. */
 526         ret = sunxi_hdmi_hpd_detect();
 527         if (hpd && !ret) {
 528                 sunxi_hdmi_shutdown();
 529                 return NULL;
 530         }
 531         if (ret)
 532                 printf("HDMI connected: ");
 533
 534         /* Check edid if requested and we've a cable plugged in */
 535         if (edid && ret) {
 536                 if (sunxi_hdmi_edid_get_mode(&edid_mode) == 0)
 537                         mode = &edid_mode;
 538         }
 539
 540         if (mode->vmode != FB_VMODE_NONINTERLACED) {
 541                 printf("Only non-interlaced modes supported, falling back to 1024x768\n");
 542                 mode = &res_mode_init[RES_MODE_1024x768];
 543         } else {
 544                 printf("Setting up a %dx%d console\n", mode->xres, mode->yres);
 545         }
 546
 547         sunxi_display.enabled = true;
 548         sunxi_engines_init();
 549         sunxi_mode_set(mode, gd->fb_base - CONFIG_SYS_SDRAM_BASE);
 550
 551         /*
 552          * These are the only members of this structure that are used. All the
 553          * others are driver specific. There is nothing to decribe pitch or
 554          * stride, but we are lucky with our hw.
 555          */
 556         graphic_device->frameAdrs = gd->fb_base;
 557         graphic_device->gdfIndex = GDF_32BIT_X888RGB;
 558         graphic_device->gdfBytesPP = 4;
 559         graphic_device->winSizeX = mode->xres;
 560         graphic_device->winSizeY = mode->yres;
 561
 562         return graphic_device;
 563 }
 564
 565 /*
 566  * Simplefb support.
 567  */
 568 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_VIDEO_DT_SIMPLEFB)
 569 int sunxi_simplefb_setup(void *blob)
 570 {
 571         static GraphicDevice *graphic_device = &sunxi_display.graphic_device;
 572         int offset, ret;
 573
 574         if (!sunxi_display.enabled)
 575                 return 0;
 576
 577         /* Find a framebuffer node, with pipeline == "de_be0-lcd0-hdmi" */
 578         offset = fdt_node_offset_by_compatible(blob, -1,
 579                                                "allwinner,simple-framebuffer");
 580         while (offset >= 0) {
 581                 ret = fdt_find_string(blob, offset, "allwinner,pipeline",
 582                                       "de_be0-lcd0-hdmi");
 583                 if (ret == 0)
 584                         break;
 585                 offset = fdt_node_offset_by_compatible(blob, offset,
 586                                                "allwinner,simple-framebuffer");
 587         }
 588         if (offset < 0) {
 589                 eprintf("Cannot setup simplefb: node not found\n");
 590                 return 0; /* Keep older kernels working */
 591         }
 592
 593         ret = fdt_setup_simplefb_node(blob, offset, gd->fb_base,
 594                         graphic_device->winSizeX, graphic_device->winSizeY,
 595                         graphic_device->winSizeX * graphic_device->gdfBytesPP,
 596                         "x8r8g8b8");
 597         if (ret)
 598                 eprintf("Cannot setup simplefb: Error setting properties\n");
 599
 600         return ret;
 601 }
 602 #endif /* CONFIG_OF_BOARD_SETUP && CONFIG_VIDEO_DT_SIMPLEFB */