drivers/video/tegra.c

   1 /*
   2  * Copyright (c) 2011 The Chromium OS Authors.
   3  * SPDX-License-Identifier:     GPL-2.0+
   4  */
   5
   6 #include <common.h>
   7 #include <dm.h>
   8 #include <fdtdec.h>
   9 #include <panel.h>
  10 #include <pwm.h>
  11 #include <video.h>
  12 #include <asm/system.h>
  13 #include <asm/gpio.h>
  14 #include <asm/io.h>
  15
  16 #include <asm/arch/clock.h>
  17 #include <asm/arch/funcmux.h>
  18 #include <asm/arch/pinmux.h>
  19 #include <asm/arch/pwm.h>
  20 #include <asm/arch/display.h>
  21 #include <asm/arch-tegra/timer.h>
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 enum lcd_cache_t {
  26         FDT_LCD_CACHE_OFF               = 0,
  27         FDT_LCD_CACHE_WRITE_THROUGH     = 1 << 0,
  28         FDT_LCD_CACHE_WRITE_BACK        = 1 << 1,
  29         FDT_LCD_CACHE_FLUSH             = 1 << 2,
  30         FDT_LCD_CACHE_WRITE_BACK_FLUSH  = FDT_LCD_CACHE_WRITE_BACK |
  31                                                 FDT_LCD_CACHE_FLUSH,
  32 };
  33
  34 /* Information about the display controller */
  35 struct tegra_lcd_priv {
  36         int width;                      /* width in pixels */
  37         int height;                     /* height in pixels */
  38         enum video_log2_bpp log2_bpp;   /* colour depth */
  39         struct display_timing timing;
  40         struct udevice *panel;
  41         struct disp_ctlr *disp;         /* Display controller to use */
  42         fdt_addr_t frame_buffer;        /* Address of frame buffer */
  43         unsigned pixel_clock;           /* Pixel clock in Hz */
  44         enum lcd_cache_t cache_type;
  45 };
  46
  47 enum {
  48         /* Maximum LCD size we support */
  49         LCD_MAX_WIDTH           = 1366,
  50         LCD_MAX_HEIGHT          = 768,
  51         LCD_MAX_LOG2_BPP        = VIDEO_BPP16,
  52 };
  53
  54 static void update_window(struct dc_ctlr *dc, struct disp_ctl_win *win)
  55 {
  56         unsigned h_dda, v_dda;
  57         unsigned long val;
  58
  59         val = readl(&dc->cmd.disp_win_header);
  60         val |= WINDOW_A_SELECT;
  61         writel(val, &dc->cmd.disp_win_header);
  62
  63         writel(win->fmt, &dc->win.color_depth);
  64
  65         clrsetbits_le32(&dc->win.byte_swap, BYTE_SWAP_MASK,
  66                         BYTE_SWAP_NOSWAP << BYTE_SWAP_SHIFT);
  67
  68         val = win->out_x << H_POSITION_SHIFT;
  69         val |= win->out_y << V_POSITION_SHIFT;
  70         writel(val, &dc->win.pos);
  71
  72         val = win->out_w << H_SIZE_SHIFT;
  73         val |= win->out_h << V_SIZE_SHIFT;
  74         writel(val, &dc->win.size);
  75
  76         val = (win->w * win->bpp / 8) << H_PRESCALED_SIZE_SHIFT;
  77         val |= win->h << V_PRESCALED_SIZE_SHIFT;
  78         writel(val, &dc->win.prescaled_size);
  79
  80         writel(0, &dc->win.h_initial_dda);
  81         writel(0, &dc->win.v_initial_dda);
  82
  83         h_dda = (win->w * 0x1000) / max(win->out_w - 1, 1U);
  84         v_dda = (win->h * 0x1000) / max(win->out_h - 1, 1U);
  85
  86         val = h_dda << H_DDA_INC_SHIFT;
  87         val |= v_dda << V_DDA_INC_SHIFT;
  88         writel(val, &dc->win.dda_increment);
  89
  90         writel(win->stride, &dc->win.line_stride);
  91         writel(0, &dc->win.buf_stride);
  92
  93         val = WIN_ENABLE;
  94         if (win->bpp < 24)
  95                 val |= COLOR_EXPAND;
  96         writel(val, &dc->win.win_opt);
  97
  98         writel((unsigned long)win->phys_addr, &dc->winbuf.start_addr);
  99         writel(win->x, &dc->winbuf.addr_h_offset);
 100         writel(win->y, &dc->winbuf.addr_v_offset);
 101
 102         writel(0xff00, &dc->win.blend_nokey);
 103         writel(0xff00, &dc->win.blend_1win);
 104
 105         val = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
 106         val |= GENERAL_UPDATE | WIN_A_UPDATE;
 107         writel(val, &dc->cmd.state_ctrl);
 108 }
 109
 110 static int update_display_mode(struct dc_disp_reg *disp,
 111                                struct tegra_lcd_priv *priv)
 112 {
 113         struct display_timing *dt = &priv->timing;
 114         unsigned long val;
 115         unsigned long rate;
 116         unsigned long div;
 117
 118         writel(0x0, &disp->disp_timing_opt);
 119
 120         writel(1 | 1 << 16, &disp->ref_to_sync);
 121         writel(dt->hsync_len.typ | dt->vsync_len.typ << 16, &disp->sync_width);
 122         writel(dt->hback_porch.typ | dt->vback_porch.typ << 16,
 123                &disp->back_porch);
 124         writel((dt->hfront_porch.typ - 1) | (dt->vfront_porch.typ - 1) << 16,
 125                &disp->front_porch);
 126         writel(dt->hactive.typ | (dt->vactive.typ << 16), &disp->disp_active);
 127
 128         val = DE_SELECT_ACTIVE << DE_SELECT_SHIFT;
 129         val |= DE_CONTROL_NORMAL << DE_CONTROL_SHIFT;
 130         writel(val, &disp->data_enable_opt);
 131
 132         val = DATA_FORMAT_DF1P1C << DATA_FORMAT_SHIFT;
 133         val |= DATA_ALIGNMENT_MSB << DATA_ALIGNMENT_SHIFT;
 134         val |= DATA_ORDER_RED_BLUE << DATA_ORDER_SHIFT;
 135         writel(val, &disp->disp_interface_ctrl);
 136
 137         /*
 138          * The pixel clock divider is in 7.1 format (where the bottom bit
 139          * represents 0.5). Here we calculate the divider needed to get from
 140          * the display clock (typically 600MHz) to the pixel clock. We round
 141          * up or down as requried.
 142          */
 143         rate = clock_get_periph_rate(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL);
 144         div = ((rate * 2 + priv->pixel_clock / 2) / priv->pixel_clock) - 2;
 145         debug("Display clock %lu, divider %lu\n", rate, div);
 146
 147         writel(0x00010001, &disp->shift_clk_opt);
 148
 149         val = PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT;
 150         val |= div << SHIFT_CLK_DIVIDER_SHIFT;
 151         writel(val, &disp->disp_clk_ctrl);
 152
 153         return 0;
 154 }
 155
 156 /* Start up the display and turn on power to PWMs */
 157 static void basic_init(struct dc_cmd_reg *cmd)
 158 {
 159         u32 val;
 160
 161         writel(0x00000100, &cmd->gen_incr_syncpt_ctrl);
 162         writel(0x0000011a, &cmd->cont_syncpt_vsync);
 163         writel(0x00000000, &cmd->int_type);
 164         writel(0x00000000, &cmd->int_polarity);
 165         writel(0x00000000, &cmd->int_mask);
 166         writel(0x00000000, &cmd->int_enb);
 167
 168         val = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE;
 169         val |= PW3_ENABLE | PW4_ENABLE | PM0_ENABLE;
 170         val |= PM1_ENABLE;
 171         writel(val, &cmd->disp_pow_ctrl);
 172
 173         val = readl(&cmd->disp_cmd);
 174         val |= CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT;
 175         writel(val, &cmd->disp_cmd);
 176 }
 177
 178 static void basic_init_timer(struct dc_disp_reg *disp)
 179 {
 180         writel(0x00000020, &disp->mem_high_pri);
 181         writel(0x00000001, &disp->mem_high_pri_timer);
 182 }
 183
 184 static const u32 rgb_enb_tab[PIN_REG_COUNT] = {
 185         0x00000000,
 186         0x00000000,
 187         0x00000000,
 188         0x00000000,
 189 };
 190
 191 static const u32 rgb_polarity_tab[PIN_REG_COUNT] = {
 192         0x00000000,
 193         0x01000000,
 194         0x00000000,
 195         0x00000000,
 196 };
 197
 198 static const u32 rgb_data_tab[PIN_REG_COUNT] = {
 199         0x00000000,
 200         0x00000000,
 201         0x00000000,
 202         0x00000000,
 203 };
 204
 205 static const u32 rgb_sel_tab[PIN_OUTPUT_SEL_COUNT] = {
 206         0x00000000,
 207         0x00000000,
 208         0x00000000,
 209         0x00000000,
 210         0x00210222,
 211         0x00002200,
 212         0x00020000,
 213 };
 214
 215 static void rgb_enable(struct dc_com_reg *com)
 216 {
 217         int i;
 218
 219         for (i = 0; i < PIN_REG_COUNT; i++) {
 220                 writel(rgb_enb_tab[i], &com->pin_output_enb[i]);
 221                 writel(rgb_polarity_tab[i], &com->pin_output_polarity[i]);
 222                 writel(rgb_data_tab[i], &com->pin_output_data[i]);
 223         }
 224
 225         for (i = 0; i < PIN_OUTPUT_SEL_COUNT; i++)
 226                 writel(rgb_sel_tab[i], &com->pin_output_sel[i]);
 227 }
 228
 229 static int setup_window(struct disp_ctl_win *win,
 230                         struct tegra_lcd_priv *priv)
 231 {
 232         win->x = 0;
 233         win->y = 0;
 234         win->w = priv->width;
 235         win->h = priv->height;
 236         win->out_x = 0;
 237         win->out_y = 0;
 238         win->out_w = priv->width;
 239         win->out_h = priv->height;
 240         win->phys_addr = priv->frame_buffer;
 241         win->stride = priv->width * (1 << priv->log2_bpp) / 8;
 242         debug("%s: depth = %d\n", __func__, priv->log2_bpp);
 243         switch (priv->log2_bpp) {
 244         case VIDEO_BPP32:
 245                 win->fmt = COLOR_DEPTH_R8G8B8A8;
 246                 win->bpp = 32;
 247                 break;
 248         case VIDEO_BPP16:
 249                 win->fmt = COLOR_DEPTH_B5G6R5;
 250                 win->bpp = 16;
 251                 break;
 252
 253         default:
 254                 debug("Unsupported LCD bit depth");
 255                 return -1;
 256         }
 257
 258         return 0;
 259 }
 260
 261 /**
 262  * Register a new display based on device tree configuration.
 263  *
 264  * The frame buffer can be positioned by U-Boot or overriden by the fdt.
 265  * You should pass in the U-Boot address here, and check the contents of
 266  * struct tegra_lcd_priv to see what was actually chosen.
 267  *
 268  * @param blob                  Device tree blob
 269  * @param priv                  Driver's private data
 270  * @param default_lcd_base      Default address of LCD frame buffer
 271  * @return 0 if ok, -1 on error (unsupported bits per pixel)
 272  */
 273 static int tegra_display_probe(const void *blob, struct tegra_lcd_priv *priv,
 274                                void *default_lcd_base)
 275 {
 276         struct disp_ctl_win window;
 277         struct dc_ctlr *dc;
 278
 279         priv->frame_buffer = (u32)default_lcd_base;
 280
 281         dc = (struct dc_ctlr *)priv->disp;
 282
 283         /*
 284          * A header file for clock constants was NAKed upstream.
 285          * TODO: Put this into the FDT and fdt_lcd struct when we have clock
 286          * support there
 287          */
 288         clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH,
 289                                144 * 1000000);
 290         clock_start_periph_pll(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL,
 291                                600 * 1000000);
 292         basic_init(&dc->cmd);
 293         basic_init_timer(&dc->disp);
 294         rgb_enable(&dc->com);
 295
 296         if (priv->pixel_clock)
 297                 update_display_mode(&dc->disp, priv);
 298
 299         if (setup_window(&window, priv))
 300                 return -1;
 301
 302         update_window(dc, &window);
 303
 304         return 0;
 305 }
 306
 307 static int tegra_lcd_probe(struct udevice *dev)
 308 {
 309         struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
 310         struct video_priv *uc_priv = dev_get_uclass_priv(dev);
 311         struct tegra_lcd_priv *priv = dev_get_priv(dev);
 312         const void *blob = gd->fdt_blob;
 313         int type = DCACHE_OFF;
 314         int ret;
 315
 316         /* Initialize the Tegra display controller */
 317         funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT);
 318         if (tegra_display_probe(blob, priv, (void *)plat->base)) {
 319                 printf("%s: Failed to probe display driver\n", __func__);
 320                 return -1;
 321         }
 322
 323         pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_PWM);
 324         pinmux_tristate_disable(PMUX_PINGRP_GPU);
 325
 326         ret = panel_enable_backlight(priv->panel);
 327         if (ret) {
 328                 debug("%s: Cannot enable backlight, ret=%d\n", __func__, ret);
 329                 return ret;
 330         }
 331
 332         /* Set up the LCD caching as requested */
 333         if (priv->cache_type & FDT_LCD_CACHE_WRITE_THROUGH)
 334                 type = DCACHE_WRITETHROUGH;
 335         else if (priv->cache_type & FDT_LCD_CACHE_WRITE_BACK)
 336                 type = DCACHE_WRITEBACK;
 337         mmu_set_region_dcache_behaviour(priv->frame_buffer, plat->size, type);
 338
 339         /* Enable flushing after LCD writes if requested */
 340         video_set_flush_dcache(dev, priv->cache_type & FDT_LCD_CACHE_FLUSH);
 341
 342         uc_priv->xsize = priv->width;
 343         uc_priv->ysize = priv->height;
 344         uc_priv->bpix = priv->log2_bpp;
 345         debug("LCD frame buffer at %pa, size %x\n", &priv->frame_buffer,
 346               plat->size);
 347
 348         return 0;
 349 }
 350
 351 static int tegra_lcd_ofdata_to_platdata(struct udevice *dev)
 352 {
 353         struct tegra_lcd_priv *priv = dev_get_priv(dev);
 354         const void *blob = gd->fdt_blob;
 355         struct display_timing *timing;
 356         int node = dev->of_offset;
 357         int panel_node;
 358         int rgb;
 359         int ret;
 360
 361         priv->disp = (struct disp_ctlr *)dev_get_addr(dev);
 362         if (!priv->disp) {
 363                 debug("%s: No display controller address\n", __func__);
 364                 return -EINVAL;
 365         }
 366
 367         rgb = fdt_subnode_offset(blob, node, "rgb");
 368         if (rgb < 0) {
 369                 debug("%s: Cannot find rgb subnode for '%s' (ret=%d)\n",
 370                       __func__, dev->name, rgb);
 371                 return -EINVAL;
 372         }
 373
 374         ret = fdtdec_decode_display_timing(blob, rgb, 0, &priv->timing);
 375         if (ret) {
 376                 debug("%s: Cannot read display timing for '%s' (ret=%d)\n",
 377                       __func__, dev->name, ret);
 378                 return -EINVAL;
 379         }
 380         timing = &priv->timing;
 381         priv->width = timing->hactive.typ;
 382         priv->height = timing->vactive.typ;
 383         priv->pixel_clock = timing->pixelclock.typ;
 384         priv->log2_bpp = VIDEO_BPP16;
 385
 386         /*
 387          * Sadly the panel phandle is in an rgb subnode so we cannot use
 388          * uclass_get_device_by_phandle().
 389          */
 390         panel_node = fdtdec_lookup_phandle(blob, rgb, "nvidia,panel");
 391         if (panel_node < 0) {
 392                 debug("%s: Cannot find panel information\n", __func__);
 393                 return -EINVAL;
 394         }
 395         ret = uclass_get_device_by_of_offset(UCLASS_PANEL, panel_node,
 396                                              &priv->panel);
 397         if (ret) {
 398                 debug("%s: Cannot find panel for '%s' (ret=%d)\n", __func__,
 399                       dev->name, ret);
 400                 return ret;
 401         }
 402
 403         return 0;
 404 }
 405
 406 static int tegra_lcd_bind(struct udevice *dev)
 407 {
 408         struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
 409         const void *blob = gd->fdt_blob;
 410         int node = dev->of_offset;
 411         int rgb;
 412
 413         rgb = fdt_subnode_offset(blob, node, "rgb");
 414         if ((rgb < 0) || !fdtdec_get_is_enabled(blob, rgb))
 415                 return -ENODEV;
 416
 417         plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
 418                 (1 << LCD_MAX_LOG2_BPP) / 8;
 419
 420         return 0;
 421 }
 422
 423 static const struct video_ops tegra_lcd_ops = {
 424 };
 425
 426 static const struct udevice_id tegra_lcd_ids[] = {
 427         { .compatible = "nvidia,tegra20-dc" },
 428         { }
 429 };
 430
 431 U_BOOT_DRIVER(tegra_lcd) = {
 432         .name   = "tegra_lcd",
 433         .id     = UCLASS_VIDEO,
 434         .of_match = tegra_lcd_ids,
 435         .ops    = &tegra_lcd_ops,
 436         .bind   = tegra_lcd_bind,
 437         .probe  = tegra_lcd_probe,
 438         .ofdata_to_platdata     = tegra_lcd_ofdata_to_platdata,
 439         .priv_auto_alloc_size   = sizeof(struct tegra_lcd_priv),
 440 };