2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
25 * Figure out an appropriate bytes-per-pixel setting.
27 static int viafb_set_bpp(void __iomem *engine, u8 bpp)
31 /* Preserve the reserved bits */
32 /* Lowest 2 bits to zero gives us no rotation */
33 gemode = readl(engine + VIA_REG_GEMODE) & 0xfffffcfc;
36 gemode |= VIA_GEM_8bpp;
39 gemode |= VIA_GEM_16bpp;
42 gemode |= VIA_GEM_32bpp;
45 printk(KERN_WARNING "viafb_set_bpp: Unsupported bpp %d\n", bpp);
48 writel(gemode, engine + VIA_REG_GEMODE);
53 static int hw_bitblt_1(void __iomem *engine, u8 op, u32 width, u32 height,
54 u8 dst_bpp, u32 dst_addr, u32 dst_pitch, u32 dst_x, u32 dst_y,
55 u32 *src_mem, u32 src_addr, u32 src_pitch, u32 src_x, u32 src_y,
56 u32 fg_color, u32 bg_color, u8 fill_rop)
58 u32 ge_cmd = 0, tmp, i;
62 printk(KERN_WARNING "hw_bitblt_1: Invalid operation: %d\n", op);
66 if (op != VIA_BITBLT_FILL && !src_mem && src_addr == dst_addr) {
79 if (op == VIA_BITBLT_FILL) {
81 case 0x00: /* blackness */
82 case 0x5A: /* pattern inversion */
83 case 0xF0: /* pattern copy */
84 case 0xFF: /* whiteness */
87 printk(KERN_WARNING "hw_bitblt_1: Invalid fill rop: "
93 ret = viafb_set_bpp(engine, dst_bpp);
97 if (op != VIA_BITBLT_FILL) {
98 if (src_x & (op == VIA_BITBLT_MONO ? 0xFFFF8000 : 0xFFFFF000)
99 || src_y & 0xFFFFF000) {
100 printk(KERN_WARNING "hw_bitblt_1: Unsupported source "
101 "x/y %d %d\n", src_x, src_y);
104 tmp = src_x | (src_y << 16);
105 writel(tmp, engine + 0x08);
108 if (dst_x & 0xFFFFF000 || dst_y & 0xFFFFF000) {
109 printk(KERN_WARNING "hw_bitblt_1: Unsupported destination x/y "
110 "%d %d\n", dst_x, dst_y);
113 tmp = dst_x | (dst_y << 16);
114 writel(tmp, engine + 0x0C);
116 if ((width - 1) & 0xFFFFF000 || (height - 1) & 0xFFFFF000) {
117 printk(KERN_WARNING "hw_bitblt_1: Unsupported width/height "
118 "%d %d\n", width, height);
121 tmp = (width - 1) | ((height - 1) << 16);
122 writel(tmp, engine + 0x10);
124 if (op != VIA_BITBLT_COLOR)
125 writel(fg_color, engine + 0x18);
127 if (op == VIA_BITBLT_MONO)
128 writel(bg_color, engine + 0x1C);
130 if (op != VIA_BITBLT_FILL) {
131 tmp = src_mem ? 0 : src_addr;
132 if (dst_addr & 0xE0000007) {
133 printk(KERN_WARNING "hw_bitblt_1: Unsupported source "
134 "address %X\n", tmp);
138 writel(tmp, engine + 0x30);
141 if (dst_addr & 0xE0000007) {
142 printk(KERN_WARNING "hw_bitblt_1: Unsupported destination "
143 "address %X\n", dst_addr);
147 writel(tmp, engine + 0x34);
149 if (op == VIA_BITBLT_FILL)
153 if (tmp & 0xFFFFC007 || dst_pitch & 0xFFFFC007) {
154 printk(KERN_WARNING "hw_bitblt_1: Unsupported pitch %X %X\n",
158 tmp = VIA_PITCH_ENABLE | (tmp >> 3) | (dst_pitch << (16 - 3));
159 writel(tmp, engine + 0x38);
161 if (op == VIA_BITBLT_FILL)
162 ge_cmd |= fill_rop << 24 | 0x00002000 | 0x00000001;
164 ge_cmd |= 0xCC000000; /* ROP=SRCCOPY */
166 ge_cmd |= 0x00000040;
167 if (op == VIA_BITBLT_MONO)
168 ge_cmd |= 0x00000002 | 0x00000100 | 0x00020000;
170 ge_cmd |= 0x00000001;
172 writel(ge_cmd, engine);
174 if (op == VIA_BITBLT_FILL || !src_mem)
177 tmp = (width * height * (op == VIA_BITBLT_MONO ? 1 : (dst_bpp >> 3)) +
180 for (i = 0; i < tmp; i++)
181 writel(src_mem[i], engine + VIA_MMIO_BLTBASE);
186 static int hw_bitblt_2(void __iomem *engine, u8 op, u32 width, u32 height,
187 u8 dst_bpp, u32 dst_addr, u32 dst_pitch, u32 dst_x, u32 dst_y,
188 u32 *src_mem, u32 src_addr, u32 src_pitch, u32 src_x, u32 src_y,
189 u32 fg_color, u32 bg_color, u8 fill_rop)
191 u32 ge_cmd = 0, tmp, i;
195 printk(KERN_WARNING "hw_bitblt_2: Invalid operation: %d\n", op);
199 if (op != VIA_BITBLT_FILL && !src_mem && src_addr == dst_addr) {
201 ge_cmd |= 0x00008000;
206 ge_cmd |= 0x00004000;
212 if (op == VIA_BITBLT_FILL) {
214 case 0x00: /* blackness */
215 case 0x5A: /* pattern inversion */
216 case 0xF0: /* pattern copy */
217 case 0xFF: /* whiteness */
220 printk(KERN_WARNING "hw_bitblt_2: Invalid fill rop: "
226 ret = viafb_set_bpp(engine, dst_bpp);
230 if (op == VIA_BITBLT_FILL)
234 if (tmp & 0xFFFFC007 || dst_pitch & 0xFFFFC007) {
235 printk(KERN_WARNING "hw_bitblt_2: Unsupported pitch %X %X\n",
239 tmp = (tmp >> 3) | (dst_pitch << (16 - 3));
240 writel(tmp, engine + 0x08);
242 if ((width - 1) & 0xFFFFF000 || (height - 1) & 0xFFFFF000) {
243 printk(KERN_WARNING "hw_bitblt_2: Unsupported width/height "
244 "%d %d\n", width, height);
247 tmp = (width - 1) | ((height - 1) << 16);
248 writel(tmp, engine + 0x0C);
250 if (dst_x & 0xFFFFF000 || dst_y & 0xFFFFF000) {
251 printk(KERN_WARNING "hw_bitblt_2: Unsupported destination x/y "
252 "%d %d\n", dst_x, dst_y);
255 tmp = dst_x | (dst_y << 16);
256 writel(tmp, engine + 0x10);
258 if (dst_addr & 0xE0000007) {
259 printk(KERN_WARNING "hw_bitblt_2: Unsupported destination "
260 "address %X\n", dst_addr);
264 writel(tmp, engine + 0x14);
266 if (op != VIA_BITBLT_FILL) {
267 if (src_x & (op == VIA_BITBLT_MONO ? 0xFFFF8000 : 0xFFFFF000)
268 || src_y & 0xFFFFF000) {
269 printk(KERN_WARNING "hw_bitblt_2: Unsupported source "
270 "x/y %d %d\n", src_x, src_y);
273 tmp = src_x | (src_y << 16);
274 writel(tmp, engine + 0x18);
276 tmp = src_mem ? 0 : src_addr;
277 if (dst_addr & 0xE0000007) {
278 printk(KERN_WARNING "hw_bitblt_2: Unsupported source "
279 "address %X\n", tmp);
283 writel(tmp, engine + 0x1C);
286 if (op != VIA_BITBLT_COLOR)
287 writel(fg_color, engine + 0x4C);
289 if (op == VIA_BITBLT_MONO)
290 writel(bg_color, engine + 0x50);
292 if (op == VIA_BITBLT_FILL)
293 ge_cmd |= fill_rop << 24 | 0x00002000 | 0x00000001;
295 ge_cmd |= 0xCC000000; /* ROP=SRCCOPY */
297 ge_cmd |= 0x00000040;
298 if (op == VIA_BITBLT_MONO)
299 ge_cmd |= 0x00000002 | 0x00000100 | 0x00020000;
301 ge_cmd |= 0x00000001;
303 writel(ge_cmd, engine);
305 if (op == VIA_BITBLT_FILL || !src_mem)
308 tmp = (width * height * (op == VIA_BITBLT_MONO ? 1 : (dst_bpp >> 3)) +
311 for (i = 0; i < tmp; i++)
312 writel(src_mem[i], engine + VIA_MMIO_BLTBASE);
317 int viafb_init_engine(struct fb_info *info)
319 struct viafb_par *viapar = info->par;
320 void __iomem *engine;
322 u32 vq_start_addr, vq_end_addr, vq_start_low, vq_end_low, vq_high,
323 vq_len, chip_name = viapar->shared->chip_info.gfx_chip_name;
325 engine = viapar->shared->vdev->engine_mmio;
327 printk(KERN_WARNING "viafb_init_accel: ioremap failed, "
328 "hardware acceleration disabled\n");
332 /* Initialize registers to reset the 2D engine */
333 switch (viapar->shared->chip_info.twod_engine) {
341 for (i = 0; i <= highest_reg; i += 4)
342 writel(0x0, engine + i);
345 case UNICHROME_CLE266:
348 case UNICHROME_PM800:
349 case UNICHROME_CN700:
350 case UNICHROME_CX700:
351 case UNICHROME_CN750:
352 case UNICHROME_K8M890:
353 case UNICHROME_P4M890:
354 case UNICHROME_P4M900:
355 viapar->shared->hw_bitblt = hw_bitblt_1;
357 case UNICHROME_VX800:
358 case UNICHROME_VX855:
359 viapar->shared->hw_bitblt = hw_bitblt_2;
362 viapar->shared->hw_bitblt = NULL;
365 viapar->fbmem_free -= CURSOR_SIZE;
366 viapar->shared->cursor_vram_addr = viapar->fbmem_free;
367 viapar->fbmem_used += CURSOR_SIZE;
369 viapar->fbmem_free -= VQ_SIZE;
370 viapar->shared->vq_vram_addr = viapar->fbmem_free;
371 viapar->fbmem_used += VQ_SIZE;
373 /* Init AGP and VQ regs */
375 case UNICHROME_K8M890:
376 case UNICHROME_P4M900:
377 case UNICHROME_VX800:
378 case UNICHROME_VX855:
379 writel(0x00100000, engine + VIA_REG_CR_TRANSET);
380 writel(0x680A0000, engine + VIA_REG_CR_TRANSPACE);
381 writel(0x02000000, engine + VIA_REG_CR_TRANSPACE);
385 writel(0x00100000, engine + VIA_REG_TRANSET);
386 writel(0x00000000, engine + VIA_REG_TRANSPACE);
387 writel(0x00333004, engine + VIA_REG_TRANSPACE);
388 writel(0x60000000, engine + VIA_REG_TRANSPACE);
389 writel(0x61000000, engine + VIA_REG_TRANSPACE);
390 writel(0x62000000, engine + VIA_REG_TRANSPACE);
391 writel(0x63000000, engine + VIA_REG_TRANSPACE);
392 writel(0x64000000, engine + VIA_REG_TRANSPACE);
393 writel(0x7D000000, engine + VIA_REG_TRANSPACE);
395 writel(0xFE020000, engine + VIA_REG_TRANSET);
396 writel(0x00000000, engine + VIA_REG_TRANSPACE);
401 vq_start_addr = viapar->shared->vq_vram_addr;
402 vq_end_addr = viapar->shared->vq_vram_addr + VQ_SIZE - 1;
404 vq_start_low = 0x50000000 | (vq_start_addr & 0xFFFFFF);
405 vq_end_low = 0x51000000 | (vq_end_addr & 0xFFFFFF);
406 vq_high = 0x52000000 | ((vq_start_addr & 0xFF000000) >> 24) |
407 ((vq_end_addr & 0xFF000000) >> 16);
408 vq_len = 0x53000000 | (VQ_SIZE >> 3);
411 case UNICHROME_K8M890:
412 case UNICHROME_P4M900:
413 case UNICHROME_VX800:
414 case UNICHROME_VX855:
415 vq_start_low |= 0x20000000;
416 vq_end_low |= 0x20000000;
417 vq_high |= 0x20000000;
418 vq_len |= 0x20000000;
420 writel(0x00100000, engine + VIA_REG_CR_TRANSET);
421 writel(vq_high, engine + VIA_REG_CR_TRANSPACE);
422 writel(vq_start_low, engine + VIA_REG_CR_TRANSPACE);
423 writel(vq_end_low, engine + VIA_REG_CR_TRANSPACE);
424 writel(vq_len, engine + VIA_REG_CR_TRANSPACE);
425 writel(0x74301001, engine + VIA_REG_CR_TRANSPACE);
426 writel(0x00000000, engine + VIA_REG_CR_TRANSPACE);
429 writel(0x00FE0000, engine + VIA_REG_TRANSET);
430 writel(0x080003FE, engine + VIA_REG_TRANSPACE);
431 writel(0x0A00027C, engine + VIA_REG_TRANSPACE);
432 writel(0x0B000260, engine + VIA_REG_TRANSPACE);
433 writel(0x0C000274, engine + VIA_REG_TRANSPACE);
434 writel(0x0D000264, engine + VIA_REG_TRANSPACE);
435 writel(0x0E000000, engine + VIA_REG_TRANSPACE);
436 writel(0x0F000020, engine + VIA_REG_TRANSPACE);
437 writel(0x1000027E, engine + VIA_REG_TRANSPACE);
438 writel(0x110002FE, engine + VIA_REG_TRANSPACE);
439 writel(0x200F0060, engine + VIA_REG_TRANSPACE);
441 writel(0x00000006, engine + VIA_REG_TRANSPACE);
442 writel(0x40008C0F, engine + VIA_REG_TRANSPACE);
443 writel(0x44000000, engine + VIA_REG_TRANSPACE);
444 writel(0x45080C04, engine + VIA_REG_TRANSPACE);
445 writel(0x46800408, engine + VIA_REG_TRANSPACE);
447 writel(vq_high, engine + VIA_REG_TRANSPACE);
448 writel(vq_start_low, engine + VIA_REG_TRANSPACE);
449 writel(vq_end_low, engine + VIA_REG_TRANSPACE);
450 writel(vq_len, engine + VIA_REG_TRANSPACE);
454 /* Set Cursor Image Base Address */
455 writel(viapar->shared->cursor_vram_addr, engine + VIA_REG_CURSOR_MODE);
456 writel(0x0, engine + VIA_REG_CURSOR_POS);
457 writel(0x0, engine + VIA_REG_CURSOR_ORG);
458 writel(0x0, engine + VIA_REG_CURSOR_BG);
459 writel(0x0, engine + VIA_REG_CURSOR_FG);
463 void viafb_show_hw_cursor(struct fb_info *info, int Status)
465 struct viafb_par *viapar = info->par;
466 u32 temp, iga_path = viapar->iga_path;
468 temp = readl(viapar->shared->vdev->engine_mmio + VIA_REG_CURSOR_MODE);
485 writel(temp, viapar->shared->vdev->engine_mmio + VIA_REG_CURSOR_MODE);
488 void viafb_wait_engine_idle(struct fb_info *info)
490 struct viafb_par *viapar = info->par;
493 void __iomem *engine = viapar->shared->vdev->engine_mmio;
495 switch (viapar->shared->chip_info.twod_engine) {
498 mask = VIA_CMD_RGTR_BUSY_M1 | VIA_2D_ENG_BUSY_M1 |
502 while (!(readl(engine + VIA_REG_STATUS) &
503 VIA_VR_QUEUE_BUSY) && (loop < MAXLOOP)) {
507 mask = VIA_CMD_RGTR_BUSY | VIA_2D_ENG_BUSY | VIA_3D_ENG_BUSY;
511 while ((readl(engine + VIA_REG_STATUS) & mask) && (loop < MAXLOOP)) {
517 printk(KERN_ERR "viafb_wait_engine_idle: not syncing\n");