2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 * Figure out an appropriate bytes-per-pixel setting.
26 static int viafb_set_bpp(void __iomem *engine, u8 bpp)
30 /* Preserve the reserved bits */
31 /* Lowest 2 bits to zero gives us no rotation */
32 gemode = readl(engine + VIA_REG_GEMODE) & 0xfffffcfc;
35 gemode |= VIA_GEM_8bpp;
38 gemode |= VIA_GEM_16bpp;
41 gemode |= VIA_GEM_32bpp;
44 printk(KERN_WARNING "viafb_set_bpp: Unsupported bpp %d\n", bpp);
47 writel(gemode, engine + VIA_REG_GEMODE);
52 static int hw_bitblt_1(void __iomem *engine, u8 op, u32 width, u32 height,
53 u8 dst_bpp, u32 dst_addr, u32 dst_pitch, u32 dst_x, u32 dst_y,
54 u32 *src_mem, u32 src_addr, u32 src_pitch, u32 src_x, u32 src_y,
55 u32 fg_color, u32 bg_color, u8 fill_rop)
57 u32 ge_cmd = 0, tmp, i;
61 printk(KERN_WARNING "hw_bitblt_1: Invalid operation: %d\n", op);
65 if (op != VIA_BITBLT_FILL && !src_mem && src_addr == dst_addr) {
78 if (op == VIA_BITBLT_FILL) {
80 case 0x00: /* blackness */
81 case 0x5A: /* pattern inversion */
82 case 0xF0: /* pattern copy */
83 case 0xFF: /* whiteness */
86 printk(KERN_WARNING "hw_bitblt_1: Invalid fill rop: "
92 ret = viafb_set_bpp(engine, dst_bpp);
96 if (op != VIA_BITBLT_FILL) {
97 if (src_x & (op == VIA_BITBLT_MONO ? 0xFFFF8000 : 0xFFFFF000)
98 || src_y & 0xFFFFF000) {
99 printk(KERN_WARNING "hw_bitblt_1: Unsupported source "
100 "x/y %d %d\n", src_x, src_y);
103 tmp = src_x | (src_y << 16);
104 writel(tmp, engine + 0x08);
107 if (dst_x & 0xFFFFF000 || dst_y & 0xFFFFF000) {
108 printk(KERN_WARNING "hw_bitblt_1: Unsupported destination x/y "
109 "%d %d\n", dst_x, dst_y);
112 tmp = dst_x | (dst_y << 16);
113 writel(tmp, engine + 0x0C);
115 if ((width - 1) & 0xFFFFF000 || (height - 1) & 0xFFFFF000) {
116 printk(KERN_WARNING "hw_bitblt_1: Unsupported width/height "
117 "%d %d\n", width, height);
120 tmp = (width - 1) | ((height - 1) << 16);
121 writel(tmp, engine + 0x10);
123 if (op != VIA_BITBLT_COLOR)
124 writel(fg_color, engine + 0x18);
126 if (op == VIA_BITBLT_MONO)
127 writel(bg_color, engine + 0x1C);
129 if (op != VIA_BITBLT_FILL) {
130 tmp = src_mem ? 0 : src_addr;
131 if (dst_addr & 0xE0000007) {
132 printk(KERN_WARNING "hw_bitblt_1: Unsupported source "
133 "address %X\n", tmp);
137 writel(tmp, engine + 0x30);
140 if (dst_addr & 0xE0000007) {
141 printk(KERN_WARNING "hw_bitblt_1: Unsupported destination "
142 "address %X\n", dst_addr);
146 writel(tmp, engine + 0x34);
148 if (op == VIA_BITBLT_FILL)
152 if (tmp & 0xFFFFC007 || dst_pitch & 0xFFFFC007) {
153 printk(KERN_WARNING "hw_bitblt_1: Unsupported pitch %X %X\n",
157 tmp = VIA_PITCH_ENABLE | (tmp >> 3) | (dst_pitch << (16 - 3));
158 writel(tmp, engine + 0x38);
160 if (op == VIA_BITBLT_FILL)
161 ge_cmd |= fill_rop << 24 | 0x00002000 | 0x00000001;
163 ge_cmd |= 0xCC000000; /* ROP=SRCCOPY */
165 ge_cmd |= 0x00000040;
166 if (op == VIA_BITBLT_MONO)
167 ge_cmd |= 0x00000002 | 0x00000100 | 0x00020000;
169 ge_cmd |= 0x00000001;
171 writel(ge_cmd, engine);
173 if (op == VIA_BITBLT_FILL || !src_mem)
176 tmp = (width * height * (op == VIA_BITBLT_MONO ? 1 : (dst_bpp >> 3)) +
179 for (i = 0; i < tmp; i++)
180 writel(src_mem[i], engine + VIA_MMIO_BLTBASE);
185 static int hw_bitblt_2(void __iomem *engine, u8 op, u32 width, u32 height,
186 u8 dst_bpp, u32 dst_addr, u32 dst_pitch, u32 dst_x, u32 dst_y,
187 u32 *src_mem, u32 src_addr, u32 src_pitch, u32 src_x, u32 src_y,
188 u32 fg_color, u32 bg_color, u8 fill_rop)
190 u32 ge_cmd = 0, tmp, i;
194 printk(KERN_WARNING "hw_bitblt_2: Invalid operation: %d\n", op);
198 if (op != VIA_BITBLT_FILL && !src_mem && src_addr == dst_addr) {
200 ge_cmd |= 0x00008000;
205 ge_cmd |= 0x00004000;
211 if (op == VIA_BITBLT_FILL) {
213 case 0x00: /* blackness */
214 case 0x5A: /* pattern inversion */
215 case 0xF0: /* pattern copy */
216 case 0xFF: /* whiteness */
219 printk(KERN_WARNING "hw_bitblt_2: Invalid fill rop: "
225 ret = viafb_set_bpp(engine, dst_bpp);
229 if (op == VIA_BITBLT_FILL)
233 if (tmp & 0xFFFFC007 || dst_pitch & 0xFFFFC007) {
234 printk(KERN_WARNING "hw_bitblt_2: Unsupported pitch %X %X\n",
238 tmp = (tmp >> 3) | (dst_pitch << (16 - 3));
239 writel(tmp, engine + 0x08);
241 if ((width - 1) & 0xFFFFF000 || (height - 1) & 0xFFFFF000) {
242 printk(KERN_WARNING "hw_bitblt_2: Unsupported width/height "
243 "%d %d\n", width, height);
246 tmp = (width - 1) | ((height - 1) << 16);
247 writel(tmp, engine + 0x0C);
249 if (dst_x & 0xFFFFF000 || dst_y & 0xFFFFF000) {
250 printk(KERN_WARNING "hw_bitblt_2: Unsupported destination x/y "
251 "%d %d\n", dst_x, dst_y);
254 tmp = dst_x | (dst_y << 16);
255 writel(tmp, engine + 0x10);
257 if (dst_addr & 0xE0000007) {
258 printk(KERN_WARNING "hw_bitblt_2: Unsupported destination "
259 "address %X\n", dst_addr);
263 writel(tmp, engine + 0x14);
265 if (op != VIA_BITBLT_FILL) {
266 if (src_x & (op == VIA_BITBLT_MONO ? 0xFFFF8000 : 0xFFFFF000)
267 || src_y & 0xFFFFF000) {
268 printk(KERN_WARNING "hw_bitblt_2: Unsupported source "
269 "x/y %d %d\n", src_x, src_y);
272 tmp = src_x | (src_y << 16);
273 writel(tmp, engine + 0x18);
275 tmp = src_mem ? 0 : src_addr;
276 if (dst_addr & 0xE0000007) {
277 printk(KERN_WARNING "hw_bitblt_2: Unsupported source "
278 "address %X\n", tmp);
282 writel(tmp, engine + 0x1C);
285 if (op != VIA_BITBLT_COLOR)
286 writel(fg_color, engine + 0x4C);
288 if (op == VIA_BITBLT_MONO)
289 writel(bg_color, engine + 0x50);
291 if (op == VIA_BITBLT_FILL)
292 ge_cmd |= fill_rop << 24 | 0x00002000 | 0x00000001;
294 ge_cmd |= 0xCC000000; /* ROP=SRCCOPY */
296 ge_cmd |= 0x00000040;
297 if (op == VIA_BITBLT_MONO)
298 ge_cmd |= 0x00000002 | 0x00000100 | 0x00020000;
300 ge_cmd |= 0x00000001;
302 writel(ge_cmd, engine);
304 if (op == VIA_BITBLT_FILL || !src_mem)
307 tmp = (width * height * (op == VIA_BITBLT_MONO ? 1 : (dst_bpp >> 3)) +
310 for (i = 0; i < tmp; i++)
311 writel(src_mem[i], engine + VIA_MMIO_BLTBASE);
316 int viafb_init_engine(struct fb_info *info)
318 struct viafb_par *viapar = info->par;
319 void __iomem *engine;
321 u32 vq_start_addr, vq_end_addr, vq_start_low, vq_end_low, vq_high,
322 vq_len, chip_name = viapar->shared->chip_info.gfx_chip_name;
324 engine = ioremap_nocache(info->fix.mmio_start, info->fix.mmio_len);
325 viapar->shared->engine_mmio = engine;
327 printk(KERN_WARNING "viafb_init_accel: ioremap failed, "
328 "hardware acceleration disabled\n");
332 /* Initialize registers to reset the 2D engine */
333 switch (viapar->shared->chip_info.twod_engine) {
341 for (i = 0; i <= highest_reg; i += 4)
342 writel(0x0, engine + i);
345 case UNICHROME_CLE266:
348 case UNICHROME_PM800:
349 case UNICHROME_CN700:
350 case UNICHROME_CX700:
351 case UNICHROME_CN750:
352 case UNICHROME_K8M890:
353 case UNICHROME_P4M890:
354 case UNICHROME_P4M900:
355 viapar->shared->hw_bitblt = hw_bitblt_1;
357 case UNICHROME_VX800:
358 case UNICHROME_VX855:
359 viapar->shared->hw_bitblt = hw_bitblt_2;
362 viapar->shared->hw_bitblt = NULL;
365 viapar->fbmem_free -= CURSOR_SIZE;
366 viapar->shared->cursor_vram_addr = viapar->fbmem_free;
367 viapar->fbmem_used += CURSOR_SIZE;
369 viapar->fbmem_free -= VQ_SIZE;
370 viapar->shared->vq_vram_addr = viapar->fbmem_free;
371 viapar->fbmem_used += VQ_SIZE;
373 /* Init AGP and VQ regs */
375 case UNICHROME_K8M890:
376 case UNICHROME_P4M900:
377 case UNICHROME_VX800:
378 case UNICHROME_VX855:
379 writel(0x00100000, engine + VIA_REG_CR_TRANSET);
380 writel(0x680A0000, engine + VIA_REG_CR_TRANSPACE);
381 writel(0x02000000, engine + VIA_REG_CR_TRANSPACE);
385 writel(0x00100000, engine + VIA_REG_TRANSET);
386 writel(0x00000000, engine + VIA_REG_TRANSPACE);
387 writel(0x00333004, engine + VIA_REG_TRANSPACE);
388 writel(0x60000000, engine + VIA_REG_TRANSPACE);
389 writel(0x61000000, engine + VIA_REG_TRANSPACE);
390 writel(0x62000000, engine + VIA_REG_TRANSPACE);
391 writel(0x63000000, engine + VIA_REG_TRANSPACE);
392 writel(0x64000000, engine + VIA_REG_TRANSPACE);
393 writel(0x7D000000, engine + VIA_REG_TRANSPACE);
395 writel(0xFE020000, engine + VIA_REG_TRANSET);
396 writel(0x00000000, engine + VIA_REG_TRANSPACE);
401 vq_start_addr = viapar->shared->vq_vram_addr;
402 vq_end_addr = viapar->shared->vq_vram_addr + VQ_SIZE - 1;
404 vq_start_low = 0x50000000 | (vq_start_addr & 0xFFFFFF);
405 vq_end_low = 0x51000000 | (vq_end_addr & 0xFFFFFF);
406 vq_high = 0x52000000 | ((vq_start_addr & 0xFF000000) >> 24) |
407 ((vq_end_addr & 0xFF000000) >> 16);
408 vq_len = 0x53000000 | (VQ_SIZE >> 3);
411 case UNICHROME_K8M890:
412 case UNICHROME_P4M900:
413 case UNICHROME_VX800:
414 case UNICHROME_VX855:
415 vq_start_low |= 0x20000000;
416 vq_end_low |= 0x20000000;
417 vq_high |= 0x20000000;
418 vq_len |= 0x20000000;
420 writel(0x00100000, engine + VIA_REG_CR_TRANSET);
421 writel(vq_high, engine + VIA_REG_CR_TRANSPACE);
422 writel(vq_start_low, engine + VIA_REG_CR_TRANSPACE);
423 writel(vq_end_low, engine + VIA_REG_CR_TRANSPACE);
424 writel(vq_len, engine + VIA_REG_CR_TRANSPACE);
425 writel(0x74301001, engine + VIA_REG_CR_TRANSPACE);
426 writel(0x00000000, engine + VIA_REG_CR_TRANSPACE);
429 writel(0x00FE0000, engine + VIA_REG_TRANSET);
430 writel(0x080003FE, engine + VIA_REG_TRANSPACE);
431 writel(0x0A00027C, engine + VIA_REG_TRANSPACE);
432 writel(0x0B000260, engine + VIA_REG_TRANSPACE);
433 writel(0x0C000274, engine + VIA_REG_TRANSPACE);
434 writel(0x0D000264, engine + VIA_REG_TRANSPACE);
435 writel(0x0E000000, engine + VIA_REG_TRANSPACE);
436 writel(0x0F000020, engine + VIA_REG_TRANSPACE);
437 writel(0x1000027E, engine + VIA_REG_TRANSPACE);
438 writel(0x110002FE, engine + VIA_REG_TRANSPACE);
439 writel(0x200F0060, engine + VIA_REG_TRANSPACE);
441 writel(0x00000006, engine + VIA_REG_TRANSPACE);
442 writel(0x40008C0F, engine + VIA_REG_TRANSPACE);
443 writel(0x44000000, engine + VIA_REG_TRANSPACE);
444 writel(0x45080C04, engine + VIA_REG_TRANSPACE);
445 writel(0x46800408, engine + VIA_REG_TRANSPACE);
447 writel(vq_high, engine + VIA_REG_TRANSPACE);
448 writel(vq_start_low, engine + VIA_REG_TRANSPACE);
449 writel(vq_end_low, engine + VIA_REG_TRANSPACE);
450 writel(vq_len, engine + VIA_REG_TRANSPACE);
454 /* Set Cursor Image Base Address */
455 writel(viapar->shared->cursor_vram_addr, engine + VIA_REG_CURSOR_MODE);
456 writel(0x0, engine + VIA_REG_CURSOR_POS);
457 writel(0x0, engine + VIA_REG_CURSOR_ORG);
458 writel(0x0, engine + VIA_REG_CURSOR_BG);
459 writel(0x0, engine + VIA_REG_CURSOR_FG);
463 void viafb_show_hw_cursor(struct fb_info *info, int Status)
465 struct viafb_par *viapar = info->par;
466 u32 temp, iga_path = viapar->iga_path;
468 temp = readl(viapar->shared->engine_mmio + VIA_REG_CURSOR_MODE);
485 writel(temp, viapar->shared->engine_mmio + VIA_REG_CURSOR_MODE);
488 void viafb_wait_engine_idle(struct fb_info *info)
490 struct viafb_par *viapar = info->par;
494 switch (viapar->shared->chip_info.twod_engine) {
497 mask = VIA_CMD_RGTR_BUSY_M1 | VIA_2D_ENG_BUSY_M1 |
501 while (!(readl(viapar->shared->engine_mmio + VIA_REG_STATUS) &
502 VIA_VR_QUEUE_BUSY) && (loop < MAXLOOP)) {
506 mask = VIA_CMD_RGTR_BUSY | VIA_2D_ENG_BUSY | VIA_3D_ENG_BUSY;
510 while ((readl(viapar->shared->engine_mmio + VIA_REG_STATUS) & mask) &&
517 printk(KERN_ERR "viafb_wait_engine_idle: not syncing\n");