2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 #include <linux/via-core.h>
22 #include <linux/via_i2c.h>
25 static void tmds_register_write(int index, u8 data);
26 static int tmds_register_read(int index);
27 static int tmds_register_read_bytes(int index, u8 *buff, int buff_len);
28 static void __devinit dvi_get_panel_size_from_DDCv1(
29 struct tmds_chip_information *tmds_chip,
30 struct tmds_setting_information *tmds_setting);
31 static void __devinit dvi_get_panel_size_from_DDCv2(
32 struct tmds_chip_information *tmds_chip,
33 struct tmds_setting_information *tmds_setting);
34 static int viafb_dvi_query_EDID(void);
36 static int check_tmds_chip(int device_id_subaddr, int device_id)
38 if (tmds_register_read(device_id_subaddr) == device_id)
44 void __devinit viafb_init_dvi_size(struct tmds_chip_information *tmds_chip,
45 struct tmds_setting_information *tmds_setting)
47 DEBUG_MSG(KERN_INFO "viafb_init_dvi_size()\n");
50 switch (viafb_dvi_query_EDID()) {
52 dvi_get_panel_size_from_DDCv1(tmds_chip, tmds_setting);
55 dvi_get_panel_size_from_DDCv2(tmds_chip, tmds_setting);
58 printk(KERN_WARNING "viafb_init_dvi_size: DVI panel size undetected!\n");
65 int __devinit viafb_tmds_trasmitter_identify(void)
67 unsigned char sr2a = 0, sr1e = 0, sr3e = 0;
69 /* Turn on ouputting pad */
70 switch (viaparinfo->chip_info->gfx_chip_name) {
71 case UNICHROME_K8M890:
72 /*=* DFP Low Pad on *=*/
73 sr2a = viafb_read_reg(VIASR, SR2A);
74 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);
77 case UNICHROME_P4M900:
78 case UNICHROME_P4M890:
80 sr2a = viafb_read_reg(VIASR, SR2A);
81 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);
83 sr1e = viafb_read_reg(VIASR, SR1E);
84 viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT6 + BIT7);
88 /* DVP0/DVP1 Pad on */
89 sr1e = viafb_read_reg(VIASR, SR1E);
90 viafb_write_reg_mask(SR1E, VIASR, 0xF0, BIT4 +
92 /* SR3E[1]Multi-function selection:
93 0 = Emulate I2C and DDC bus by GPIO2/3/4. */
94 sr3e = viafb_read_reg(VIASR, SR3E);
95 viafb_write_reg_mask(SR3E, VIASR, 0x0, BIT5);
99 /* Check for VT1632: */
100 viaparinfo->chip_info->tmds_chip_info.tmds_chip_name = VT1632_TMDS;
101 viaparinfo->chip_info->
102 tmds_chip_info.tmds_chip_slave_addr = VT1632_TMDS_I2C_ADDR;
103 viaparinfo->chip_info->tmds_chip_info.i2c_port = VIA_PORT_31;
104 if (check_tmds_chip(VT1632_DEVICE_ID_REG, VT1632_DEVICE_ID) != FAIL) {
106 * Currently only support 12bits,dual edge,add 24bits mode later
108 tmds_register_write(0x08, 0x3b);
110 DEBUG_MSG(KERN_INFO "\n VT1632 TMDS ! \n");
111 DEBUG_MSG(KERN_INFO "\n %2d",
112 viaparinfo->chip_info->tmds_chip_info.tmds_chip_name);
113 DEBUG_MSG(KERN_INFO "\n %2d",
114 viaparinfo->chip_info->tmds_chip_info.i2c_port);
117 viaparinfo->chip_info->tmds_chip_info.i2c_port = VIA_PORT_2C;
118 if (check_tmds_chip(VT1632_DEVICE_ID_REG, VT1632_DEVICE_ID)
120 tmds_register_write(0x08, 0x3b);
121 DEBUG_MSG(KERN_INFO "\n VT1632 TMDS ! \n");
122 DEBUG_MSG(KERN_INFO "\n %2d",
123 viaparinfo->chip_info->
124 tmds_chip_info.tmds_chip_name);
125 DEBUG_MSG(KERN_INFO "\n %2d",
126 viaparinfo->chip_info->
127 tmds_chip_info.i2c_port);
132 viaparinfo->chip_info->tmds_chip_info.tmds_chip_name = INTEGRATED_TMDS;
134 if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) &&
135 ((viafb_display_hardware_layout == HW_LAYOUT_DVI_ONLY) ||
136 (viafb_display_hardware_layout == HW_LAYOUT_LCD_DVI))) {
137 DEBUG_MSG(KERN_INFO "\n Integrated TMDS ! \n");
141 switch (viaparinfo->chip_info->gfx_chip_name) {
142 case UNICHROME_K8M890:
143 viafb_write_reg(SR2A, VIASR, sr2a);
146 case UNICHROME_P4M900:
147 case UNICHROME_P4M890:
148 viafb_write_reg(SR2A, VIASR, sr2a);
149 viafb_write_reg(SR1E, VIASR, sr1e);
153 viafb_write_reg(SR1E, VIASR, sr1e);
154 viafb_write_reg(SR3E, VIASR, sr3e);
158 viaparinfo->chip_info->
159 tmds_chip_info.tmds_chip_name = NON_TMDS_TRANSMITTER;
160 viaparinfo->chip_info->tmds_chip_info.
161 tmds_chip_slave_addr = VT1632_TMDS_I2C_ADDR;
165 static void tmds_register_write(int index, u8 data)
167 viafb_i2c_writebyte(viaparinfo->chip_info->tmds_chip_info.i2c_port,
168 viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr,
172 static int tmds_register_read(int index)
176 viafb_i2c_readbyte(viaparinfo->chip_info->tmds_chip_info.i2c_port,
177 (u8) viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr,
182 static int tmds_register_read_bytes(int index, u8 *buff, int buff_len)
184 viafb_i2c_readbytes(viaparinfo->chip_info->tmds_chip_info.i2c_port,
185 (u8) viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr,
186 (u8) index, buff, buff_len);
191 void viafb_dvi_set_mode(struct VideoModeTable *mode, int mode_bpp,
194 struct VideoModeTable *rb_mode;
195 struct crt_mode_table *pDviTiming;
196 unsigned long desirePixelClock, maxPixelClock;
197 pDviTiming = mode->crtc;
198 desirePixelClock = pDviTiming->clk / 1000000;
199 maxPixelClock = (unsigned long)viaparinfo->
200 tmds_setting_info->max_pixel_clock;
202 DEBUG_MSG(KERN_INFO "\nDVI_set_mode!!\n");
204 if ((maxPixelClock != 0) && (desirePixelClock > maxPixelClock)) {
205 rb_mode = viafb_get_rb_mode(mode->crtc[0].crtc.hor_addr,
206 mode->crtc[0].crtc.ver_addr);
209 pDviTiming = rb_mode->crtc;
212 viafb_fill_crtc_timing(pDviTiming, mode, mode_bpp / 8, set_iga);
215 /* Sense DVI Connector */
216 int viafb_dvi_sense(void)
218 u8 RegSR1E = 0, RegSR3E = 0, RegCR6B = 0, RegCR91 = 0,
219 RegCR93 = 0, RegCR9B = 0, data;
222 DEBUG_MSG(KERN_INFO "viafb_dvi_sense!!\n");
224 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
226 RegSR1E = viafb_read_reg(VIASR, SR1E);
227 viafb_write_reg(SR1E, VIASR, RegSR1E | 0x30);
229 /* CR6B[0]VCK Input Selection: 1 = External clock. */
230 RegCR6B = viafb_read_reg(VIACR, CR6B);
231 viafb_write_reg(CR6B, VIACR, RegCR6B | 0x08);
233 /* CR91[4] VDD On [3] Data On [2] VEE On [1] Back Light Off
234 [0] Software Control Power Sequence */
235 RegCR91 = viafb_read_reg(VIACR, CR91);
236 viafb_write_reg(CR91, VIACR, 0x1D);
238 /* CR93[7] DI1 Data Source Selection: 1 = DSP2.
239 CR93[5] DI1 Clock Source: 1 = internal.
240 CR93[4] DI1 Clock Polarity.
241 CR93[3:1] DI1 Clock Adjust. CR93[0] DI1 enable */
242 RegCR93 = viafb_read_reg(VIACR, CR93);
243 viafb_write_reg(CR93, VIACR, 0x01);
245 /* DVP0/DVP1 Pad on */
246 RegSR1E = viafb_read_reg(VIASR, SR1E);
247 viafb_write_reg(SR1E, VIASR, RegSR1E | 0xF0);
249 /* SR3E[1]Multi-function selection:
250 0 = Emulate I2C and DDC bus by GPIO2/3/4. */
251 RegSR3E = viafb_read_reg(VIASR, SR3E);
252 viafb_write_reg(SR3E, VIASR, RegSR3E & (~0x20));
254 /* CR91[4] VDD On [3] Data On [2] VEE On [1] Back Light Off
255 [0] Software Control Power Sequence */
256 RegCR91 = viafb_read_reg(VIACR, CR91);
257 viafb_write_reg(CR91, VIACR, 0x1D);
259 /*CR9B[4] DVP1 Data Source Selection: 1 = From secondary
260 display.CR9B[2:0] DVP1 Clock Adjust */
261 RegCR9B = viafb_read_reg(VIACR, CR9B);
262 viafb_write_reg(CR9B, VIACR, 0x01);
265 data = (u8) tmds_register_read(0x09);
270 if (viafb_dvi_query_EDID())
275 viafb_write_reg(SR1E, VIASR, RegSR1E);
276 viafb_write_reg(CR91, VIACR, RegCR91);
277 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
278 viafb_write_reg(CR6B, VIACR, RegCR6B);
279 viafb_write_reg(CR93, VIACR, RegCR93);
281 viafb_write_reg(SR3E, VIASR, RegSR3E);
282 viafb_write_reg(CR9B, VIACR, RegCR9B);
288 /* Query Flat Panel's EDID Table Version Through DVI Connector */
289 static int viafb_dvi_query_EDID(void)
294 DEBUG_MSG(KERN_INFO "viafb_dvi_query_EDID!!\n");
296 restore = viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr;
297 viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr = 0xA0;
299 data0 = (u8) tmds_register_read(0x00);
300 data1 = (u8) tmds_register_read(0x01);
301 if ((data0 == 0) && (data1 == 0xFF)) {
302 viaparinfo->chip_info->
303 tmds_chip_info.tmds_chip_slave_addr = restore;
304 return EDID_VERSION_1; /* Found EDID1 Table */
307 data0 = (u8) tmds_register_read(0x00);
308 viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr = restore;
310 return EDID_VERSION_2; /* Found EDID2 Table */
315 /* Get Panel Size Using EDID1 Table */
316 static void __devinit dvi_get_panel_size_from_DDCv1(
317 struct tmds_chip_information *tmds_chip,
318 struct tmds_setting_information *tmds_setting)
320 int i, max_h = 0, tmp, restore;
322 unsigned char EDID_DATA[18];
324 DEBUG_MSG(KERN_INFO "\n dvi_get_panel_size_from_DDCv1 \n");
326 restore = tmds_chip->tmds_chip_slave_addr;
327 tmds_chip->tmds_chip_slave_addr = 0xA0;
329 rData = tmds_register_read(0x23);
337 rData = tmds_register_read(0x24);
345 for (i = 0x25; i < 0x6D; i++) {
355 rData = tmds_register_read(i);
358 /* data = (data + 31) * 8 */
359 tmp = (rData + 31) << 3;
368 tmds_register_read_bytes(i, EDID_DATA, 10);
369 if (!(EDID_DATA[0] || EDID_DATA[1])) {
370 /* The first two byte must be zero. */
371 if (EDID_DATA[3] == 0xFD) {
372 /* To get max pixel clock. */
373 tmds_setting->max_pixel_clock =
384 tmds_setting->max_hres = max_h;
387 tmds_setting->max_vres = 480;
390 tmds_setting->max_vres = 600;
393 tmds_setting->max_vres = 768;
396 tmds_setting->max_vres = 1024;
399 tmds_setting->max_vres = 1050;
402 tmds_setting->max_vres = 1050;
405 tmds_setting->max_vres = 1200;
408 tmds_setting->max_vres = 1080;
411 DEBUG_MSG(KERN_INFO "Unknown panel size max resolution = %d ! "
412 "set default panel size.\n", max_h);
416 DEBUG_MSG(KERN_INFO "DVI max pixelclock = %d\n",
417 tmds_setting->max_pixel_clock);
418 tmds_chip->tmds_chip_slave_addr = restore;
421 /* Get Panel Size Using EDID2 Table */
422 static void __devinit dvi_get_panel_size_from_DDCv2(
423 struct tmds_chip_information *tmds_chip,
424 struct tmds_setting_information *tmds_setting)
427 unsigned char R_Buffer[2];
429 DEBUG_MSG(KERN_INFO "\n dvi_get_panel_size_from_DDCv2 \n");
431 restore = tmds_chip->tmds_chip_slave_addr;
432 tmds_chip->tmds_chip_slave_addr = 0xA2;
434 /* Horizontal: 0x76, 0x77 */
435 tmds_register_read_bytes(0x76, R_Buffer, 2);
436 tmds_setting->max_hres = R_Buffer[0] + (R_Buffer[1] << 8);
438 switch (tmds_setting->max_hres) {
440 tmds_setting->max_vres = 480;
443 tmds_setting->max_vres = 600;
446 tmds_setting->max_vres = 768;
449 tmds_setting->max_vres = 1024;
452 tmds_setting->max_vres = 1050;
455 tmds_setting->max_vres = 1050;
458 tmds_setting->max_vres = 1200;
461 DEBUG_MSG(KERN_INFO "Unknown panel size max resolution = %d! "
462 "set default panel size.\n", tmds_setting->max_hres);
466 tmds_chip->tmds_chip_slave_addr = restore;
469 /* If Disable DVI, turn off pad */
470 void viafb_dvi_disable(void)
472 if (viaparinfo->chip_info->
473 tmds_chip_info.output_interface == INTERFACE_TMDS)
474 /* Turn off TMDS power. */
475 viafb_write_reg(CRD2, VIACR,
476 viafb_read_reg(VIACR, CRD2) | 0x08);
479 static void dvi_patch_skew_dvp0(void)
481 /* Reset data driving first: */
482 viafb_write_reg_mask(SR1B, VIASR, 0, BIT1);
483 viafb_write_reg_mask(SR2A, VIASR, 0, BIT4);
485 switch (viaparinfo->chip_info->gfx_chip_name) {
486 case UNICHROME_P4M890:
488 if ((viaparinfo->tmds_setting_info->h_active == 1600) &&
489 (viaparinfo->tmds_setting_info->v_active ==
491 viafb_write_reg_mask(CR96, VIACR, 0x03,
494 viafb_write_reg_mask(CR96, VIACR, 0x07,
499 case UNICHROME_P4M900:
501 viafb_write_reg_mask(CR96, VIACR, 0x07,
502 BIT0 + BIT1 + BIT2 + BIT3);
503 viafb_write_reg_mask(SR1B, VIASR, 0x02, BIT1);
504 viafb_write_reg_mask(SR2A, VIASR, 0x10, BIT4);
515 static void dvi_patch_skew_dvp_low(void)
517 switch (viaparinfo->chip_info->gfx_chip_name) {
518 case UNICHROME_K8M890:
520 viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1);
524 case UNICHROME_P4M900:
526 viafb_write_reg_mask(CR99, VIACR, 0x08,
527 BIT0 + BIT1 + BIT2 + BIT3);
531 case UNICHROME_P4M890:
533 viafb_write_reg_mask(CR99, VIACR, 0x0F,
534 BIT0 + BIT1 + BIT2 + BIT3);
545 /* If Enable DVI, turn off pad */
546 void viafb_dvi_enable(void)
550 switch (viaparinfo->chip_info->tmds_chip_info.output_interface) {
552 viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0);
553 viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 + BIT5);
554 dvi_patch_skew_dvp0();
555 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
556 tmds_register_write(0x88, 0x3b);
558 /*clear CR91[5] to direct on display period
559 in the secondary diplay path */
560 via_write_reg_mask(VIACR, 0x91, 0x00, 0x20);
564 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
565 viafb_write_reg_mask(CR93, VIACR, 0x21, BIT0 + BIT5);
567 /*fix dvi cann't be enabled with MB VT5718C4 - Al Zhang */
568 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
569 tmds_register_write(0x88, 0x3b);
571 /*clear CR91[5] to direct on display period
572 in the secondary diplay path */
573 via_write_reg_mask(VIACR, 0x91, 0x00, 0x20);
575 /*fix DVI cannot enable on EPIA-M board */
576 if (viafb_platform_epia_dvi == 1) {
577 viafb_write_reg_mask(CR91, VIACR, 0x1f, 0x1f);
578 viafb_write_reg_mask(CR88, VIACR, 0x00, BIT6 + BIT0);
579 if (viafb_bus_width == 24) {
580 if (viafb_device_lcd_dualedge == 1)
584 viafb_i2c_writebyte(viaparinfo->chip_info->
585 tmds_chip_info.i2c_port,
586 viaparinfo->chip_info->
587 tmds_chip_info.tmds_chip_slave_addr,
593 case INTERFACE_DFP_HIGH:
594 if (viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266)
595 via_write_reg_mask(VIACR, CR97, 0x03, 0x03);
597 via_write_reg_mask(VIACR, 0x91, 0x00, 0x20);
600 case INTERFACE_DFP_LOW:
601 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
604 dvi_patch_skew_dvp_low();
605 via_write_reg_mask(VIACR, 0x91, 0x00, 0x20);
609 /* Turn on Display period in the panel path. */
610 viafb_write_reg_mask(CR91, VIACR, 0, BIT7);
612 /* Turn on TMDS power. */
613 viafb_write_reg_mask(CRD2, VIACR, 0, BIT3);
617 if (viaparinfo->tmds_setting_info->iga_path == IGA2) {
618 /* Disable LCD Scaling */
619 viafb_write_reg_mask(CR79, VIACR, 0x00, BIT0);